Electronic device and operating method thereof

Abstract

An electronic device and an operating method thereof are provided. The electronic device is operable to communicate with another electronic device. The operation method comprises the following operations. A forward error correction (FEC) frame to be transmitted via a plurality of enabled channels of a link is retrieved, wherein the FEC frame includes a data block, an error detection block associated with the data block, and an error correction block associated with the data block and the error detection block. The FEC frame is selectively allocated to the plurality of channels of the link in one of a plurality of different channel allocation orders based on a number of enabled channels of the plurality of enabled channels. The FEC frame is transmitted to another electronic device through the plurality of channels of the link.

Description

Technical Field

[0001] The present invention relates to an electronic device and a method thereof, and more particularly to a method for interconnecting a protocol, a controller thereof, and an electronic device such as a host device and a storage device. Background Art

[0002] The Mobile Industry Processor Interface (MIPI) Alliance has developed interconnection protocol technologies, such as the MIPI M-PHY specification related to the physical layer and the MIPI UniPro specification related to the Unified Protocol (UniPro), which are used to interconnect from one chip within a mobile device or affected by a mobile device to another chip to achieve higher transmission speeds and low-power operation. On the other hand, the Joint Electron Device Engineering Council (JEDEC) has launched a high-performance non-volatile memory standard called Universal Flash Storage (UFS) using the MIPI M-PHY specification and the MIPI UniPro specification. The UFS standard achieves high-speed transmission and low-power operation at the gigabit level, and provides the required functionality and scalability for mobile systems (e.g., computing devices such as smartphones, tablets, multimedia devices, and wearable devices) to promote rapid industry adoption.

[0003] A system implemented according to the UFS standard or UniPro specification includes a local host and a remote device, where the local host can be a computing device or chip and the storage device can be a storage device implemented using non-volatile memory or another chip. A bidirectional link is established between the host and the device, and the link can have multiple lanes configured in either direction. The host and device can each be implemented using a physical interface based on the M-PHY specification and a link controller based on the UniPro specification.

[0004] For all M-PHY symbols transmitted on the link, the physical interface is required to apply a specific line coding (or symbol encoding) technique, defined in the M-PHY specification and referred to as "8b10b" or "8b / 10b" encoding, to achieve DC balance. The link controller also utilizes the UniPro-mandated symbol encoding technique for M-PHY. In this well-known 8b10b encoding scheme, each byte is converted to 10 bits, and 8b10b encoding therefore has a 20% overhead. Summary of the Invention

[0005] In the present disclosure, a technique for facilitating an interconnect protocol capable of implementing a line coding scheme to increase an effective data rate and suitable for an electronic device capable of linking to another electronic device based on the interconnect protocol is provided.

[0006] Several embodiments of a method for operating an electronic device are provided, the method comprising: obtaining a forward error correction (FEC) frame to be transmitted via a plurality of enabled lanes of a link, wherein the FEC frame comprises a data block, an error detection block associated with the data block, and an error correction block associated with the data block and the error detection block; selectively allocating the FEC frame to the plurality of lanes of the link in one of a plurality of different lane allocation orders based on a number of enabled lanes of the plurality of enabled lanes; and transmitting the FEC frame to another electronic device via the plurality of lanes of the link.

[0007] Several embodiments of an electronic device are provided, which are configured to communicate with another electronic device. The electronic device includes an interconnect controller comprising physical layer circuitry for signal transmission and a link controller for data transmission, the interconnect controller being coupled to the physical layer circuitry. The interconnect controller is configured to perform a plurality of operations, the plurality of operations comprising: generating a forward error correction (FEC) frame to be transmitted via a plurality of enabled lanes of a link, the FEC frame comprising a data block, an error detection block associated with the data block, and an error correction block associated with the data block and the error detection block; selectively allocating the FEC frame to the plurality of lanes of the link in one of a plurality of different lane allocation orders based on a number of enabled lanes of the plurality of enabled lanes; and transmitting the FEC frame to another electronic device via the plurality of lanes of the link.

[0008] In some embodiments of the above operating method or electronic device, the error correction block is obtained based on an N-way interleaved forward error correction (FEC) scheme, where N is greater than or equal to 3.

[0009] In some embodiments of the above-mentioned operating method or electronic device, multiple data symbols of the FEC frame are divided into N forward error correction (FEC) groups for the N-way interleaved FEC scheme, wherein for at least two channels among the multiple channels, every two adjacent data symbols allocated on the same channel and taken from the FEC frame are associated with two of the N FEC groups.

[0010] In some embodiments of the above-mentioned operating method or electronic device, the multiple data symbols of the FEC frame are divided into N forward error correction (FEC) groups for the N-way interleaved FEC scheme; when the number of enabled channels is a positive multiple of N, the multiple data symbols of the FEC frame are allocated on the multiple channels of the link in a first channel allocation order selected based on the number of enabled channels, wherein, in the first channel allocation order, for each channel among the multiple channels, one data symbol of the multiple data symbols of one of the N FEC groups on one channel of the multiple channels is followed by another data symbol of the multiple data symbols of another group of the N FEC groups on the same channel.

[0011] In some embodiments of the above-mentioned operating method or electronic device, when the number of enabled channels is not a positive multiple of N, the multiple data symbols of the FEC frame are allocated on the multiple channels of the link in a second channel allocation order selected based on the number of enabled channels, wherein, in the second channel allocation order, for each channel among the multiple channels, one data symbol of the multiple data symbols of one of the N FEC groups on one channel among the multiple channels is followed by another data symbol of the multiple data symbols of another group of the N FEC groups on the same channel, wherein the second channel allocation order is different from the first channel allocation order.

[0012] In some embodiments of the above operating method or electronic device, the data block includes data symbols from a data link layer or a physical adapter layer of the electronic device.

[0013] In some embodiments of the above operating method or electronic device, the data symbols from the data link layer or the physical adapter layer of the electronic device are based on a unified protocol (UniPro). BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A block diagram illustrating one embodiment of a communication system capable of communicating according to an interconnection protocol.

[0015] Figure 2 FIG2 is a schematic diagram showing a forward error correction (FEC) frame according to an embodiment of the present disclosure.

[0016] Figure 3 A schematic diagram showing an embodiment of a circuit architecture based on a three-way interleaved forward error correction (FEC) scheme.

[0017] Figure 4 A diagram showing an example of allocating forward error correction (FEC) frames on a two-lane link in a lane allocation order.

[0018] Figure 5 The figure is a diagram showing an example of allocating forward error correction (FEC) frames on a four-lane link in the lane allocation order.

[0019] Figure 6 A diagram showing an example of allocating forward error correction (FEC) frames on a three-lane link in a lane allocation order.

[0020] Figure 7 The diagram is a diagram showing an example of allocating forward error correction (FEC) frames on a three-lane link in another lane allocation order.

[0021] Figure 8 The flowchart shows an embodiment of an operating method of an electronic device.

[0022] Figure 9 FIG. 1 is a flow chart showing an embodiment of step S20 .

[0023] Figure 10 A diagram showing an example of a power consumption mode change request frame.

[0024] Figure 11 A diagram showing an example of allocating forward error correction (FEC) frames in different channel allocation orders before and after a power consumption mode change.

[0025] Figure 12 A diagram showing an example of allocating forward error correction (FEC) frames in the same channel allocation order before and after a power consumption mode change.

[0026] Figure 13 A block diagram showing the circuit architecture for channel allocation.

[0027] Figure 14A A schematic diagram showing an example of a channel allocation sequence.

[0028] Figure 14B A schematic diagram showing an example of a channel allocation sequence.

[0029] Figure 14C A schematic diagram showing an example of a channel allocation sequence.

[0030] Figure 14D A schematic diagram showing an example of a channel allocation sequence.

[0031] Figure 15 A block diagram showing an embodiment of a circuit architecture of a transmission path.

[0032] Figure 16AA block diagram showing an embodiment of a circuit architecture of a receive path.

[0033] Figure 16B FIG. 1 is a block diagram showing one embodiment of an FEC decoder module.

[0034] Figure 17 A flow chart showing an embodiment of a method for an electronic device.

[0035] Figure 18A To display Figure 17 A schematic diagram of an example of the operation of the method.

[0036] Figure 18B To display Figure 17 A schematic diagram of an example of the operation of the method.

[0037] Figure 18C To display Figure 17 A schematic diagram of an example of the operation of the method.

[0038] Figure 18D To display Figure 17 A schematic diagram of an example of the operation of the method.

[0039] Figure 18E To display Figure 17 A schematic diagram of an example of the operation of the method.

[0040] Figure 19A FIG. 1 is a schematic diagram showing a circuit architecture of a storage system for an interconnect protocol with FEC according to an embodiment of the present disclosure.

[0041] Figure 19B To illustrate an embodiment of the present disclosure applicable to Figure 19A Block diagram of the circuit architecture of the controller for the interconnection protocol in .

[0042] Figure 19C To illustrate an embodiment of the present disclosure applicable to Figure 19A Block diagram of the circuit architecture of the controller for the interconnection protocol in .

[0043] Figure 20 for Figure 19A A schematic diagram of an embodiment of a hierarchical structure of a storage system in FIG.

[0044] Description of Reference Numerals

[0045] 10 First Device

[0046] 11 Interconnection Controller

[0047] 20 Second Device

[0048] 21 Interconnection Controller

[0049] 101 Physical Layer Circuit

[0050] 105 Link Controller

[0051] 110 Physical Adapter (PA) Layer

[0052] 120 Data Link (DL) Layer

[0053] 201 Physical Layer Circuit

[0054] 205 Link Controller

[0055] 210 Physical Adapter (PA) Layer

[0056] 220 Data Link (DL) Layer

[0057] 300 Circuit Architecture

[0058] 310 Forward Error Correction Circuit

[0059] 320 Forward Error Correction Circuit

[0060] 330 Forward Error Correction Circuit

[0061] 390 Channel Distribution Module

[0062] 410 Forward Error Correction (FEC) module

[0063] 420 Channel Distribution Module

[0064] 430 Power Mode Change Controller

[0065] 510 Physical Adapter (PA) Arbitrator

[0066] 520 Data Interleaver

[0067] 530 FEC encoder module

[0068] 540 Channel Distribution Module

[0069] 550 Power Mode Change Request Controller

[0070] 560 registers

[0071] 571 Data Scrambler

[0072] 573 Data Scrambler

[0073] 575 Data Scrambler

[0074] 580 physical layer circuit

[0075] 611 Data Descrambler

[0076] 613 Data Descrambler

[0077] 615 Data Descrambler

[0078] 620 Data Merge Module

[0079] 630 FEC decoder module

[0080] 631 Error Correction Code (ECC) Decoder

[0081] 633 ECC decoder

[0082] 635 ECC decoder

[0083] 637 Cyclic Redundancy Check (CRC) Checker

[0084] 640 Data Combination Module

[0085] 650 Physical Adapter (PA) Arbitrator

[0086] 720 physical layer circuit

[0087] 1000 Storage System

[0088] 1010 Host

[0089] 1011 Host Interface

[0090] 1012 Host Controller

[0091] 1016 Application Processor

[0092] 1020 Storage Device

[0093] 1021 Device Interface

[0094] 1022 Device Controller

[0095] 1026 storage modules

[0096] 1013, 1023 hardware protocol engine

[0097] 1014, 1024 processing units

[0098] 1110, 1210 physical layer

[0099] 1111, 1211 transmitters

[0100] 1112, 1212 receivers

[0101] 1130, 1230 Unified Protocol (UniPro) layer

[0102] 1131, 1231 physical adapter layer

[0103] 1132, 1232 data link layer

[0104] 1133, 1233 network layer

[0105] 1134, 1234 transport layer

[0106] 1135, 1235 Device Management Entity (DME)

[0107] Steps S10-S30

[0108] S20A Steps

[0109] Steps S210-S230

[0110] S310-S370 Steps

[0111] Adapt value

[0112] B1 data block

[0113] B2 Error Detection Block

[0114] B3 Error Correction Block

[0115] CCITT CRC-16 CCITT CRC-16

[0116] CLK clock line

[0117] DevID value

[0118] Din data cable

[0119] Dout data cable

[0120] ESC_PA value

[0121] EscParam_PA parameter

[0122] F1 Forward Error Correction (FEC) frame

[0123] Flags value

[0124] PACP_BEGIN value

[0125] PACP_FunctionID field

[0126] PACP_PWR_req value (represents PACP_PWR_req frame)

[0127] PAPowerModeUserData value

[0128] PC1, PC2 protocol controller

[0129] RST reset line

[0130] RxGear Value

[0131] RxLane value

[0132] RxMode value

[0133] SL1, SL2 data channels

[0134] TxGear Value

[0135] TxLane value

[0136] TxMode value DETAILED DESCRIPTION

[0137] To facilitate understanding of the purpose, features, and effects of the present disclosure, a detailed description of multiple embodiments of the present disclosure and the accompanying drawings are provided.

[0138] In the present disclosure, various embodiments of an interconnection protocol having a coding scheme are presented. The coding scheme is herein represented by a 1b / 1b coding scheme having an effective data rate that is greater than the effective data rate of an 8b / 10b coding scheme. Furthermore, to improve data throughput, various embodiments of a data structure for data transmission using the coding scheme are presented for the interconnection protocol, the data structure being referred to as a Forward Error Correction (FEC) frame. Furthermore, a Forward Error Correction (FEC) scheme can be employed in conjunction with an advanced signaling scheme such as n-level pulse amplitude modulation (PAM-n) signaling (where n>2) to reduce retransmission rates.

[0139] The interconnection protocol may be derived from the UFS standard or the UniPro specification. The interconnection protocol may also be considered a proposed or enhanced version of a future UFS standard or UniPro specification. The FEC scheme may be implemented in the interconnection protocol as an advanced operating mode, or high-speed mode, indicating that electronic devices compliant with the interconnection protocol operating in this mode can perform data transmission using the FEC scheme.

[0140] In some embodiments, an advanced signaling scheme for bit transmission that is different from existing signaling schemes available in the current M-PHY specification (e.g., non-return-to-zero (NRZ) or pulse width modulation (PWM)) may be further employed and combined with the FEC scheme to improve overall data transmission throughput. For example, a signaling scheme for bit transmission, such as n-level pulse amplitude modulation (PAM-n, where n>2), may be employed together with the FEC scheme, where n is an integer, such as 3, 4, 5, 6, 8, or 16.

[0141] Various embodiments are provided below for facilitating the interconnection protocol and are applicable to an electronic device capable of communicating with another electronic device according to the interconnection protocol.

[0142] As described above, the interconnection protocol may be derived from the UFS standard or the UniPro specification. For example, an existing UFS system includes a UFS host and a UFS device. The UFS host and the UFS device communicate with each other through their respective UFS Interconnect (UIC) layers, which include UniPro and M-PHY. Therefore, the interconnection protocol can be implemented and derived from the architecture of the existing UFS system by using an adjusted UFS system, which implements an adjusted version of UniPro and an adjusted version of M-PHY. In addition, the interconnection protocol may also be implemented in a communication system including a host and a device, each of which has its own link layer (such as an adjusted version of UniPro) and its own physical layer (such as an adjusted version of M-PHY), both of which are compatible with ALE.

[0143] Furthermore, the present disclosure provides techniques for improving the performance of data frame transmission, and is applicable to an electronic device capable of communicating with another electronic device according to the interconnection protocol. An embodiment of an apparatus and method for facilitating data frame transmission is also provided. By utilizing these techniques, data frame transmission can be performed effectively and efficiently, thereby reducing retransmission rates and improving performance.

[0144] Figure 1 1 is a block diagram showing an embodiment of a communication system capable of communicating according to an interconnection protocol. The interconnection protocol is, for example, based on an adapted UniPro specification, an adapted UFS system, or other related communication protocols or specifications, as appropriate. For example, the communication system includes a first device 10 and a second device 20, which may be a local host and a remote device, respectively, or vice versa. Figure 1In the embodiment, the first device 10 includes a link controller 100 and a physical layer circuit 105 for signal transmission, which can be implemented as an interconnection controller 11. Similarly, the second device 20 includes a link controller 200 and a physical layer circuit 205, which can be implemented as an interconnection controller 21. The link controller 100 of the first device 10, for example, implements the protocol layer (or "link layer" for a physical layer such as M-PHY) of the interconnection protocol, such as a modified UniPro layer including a physical adapter (PA) layer 110, a data link (DL) layer 120, etc.; and similarly, the link controller 200 of the second device 20, for example, also implements the protocol layer (or "link layer"), such as a modified UniPro layer including a physical adapter (PA) layer 210, a data link (DL) layer 220, etc. According to the interconnection protocol, the first device 10 can communicate with the second device 20 via a link, which includes at least one data channel SL1 and at least one data channel SL2, and is bidirectional. For example, the interconnect protocol is applicable to a variety of devices (e.g., with respect to the first device or the second device), such as application processors, coprocessors, modems, storage subsystems including non-volatile memory modules, displays, camera sensors, 3D graphics and multimedia accelerators, chipsets, etc. It is also applicable to different types of data traffic, such as control messages, bulk data transmission, and packetized streams. Where appropriate, other relevant MIPI Alliance specifications or other relevant specifications may also be used for physical layer or application layer implementations.

[0145] The physical layer is referred to as a modified physical layer or modified M-PHY. In some embodiments, the modified physical layer is implemented as an interface circuit to perform bit transmission of the aforementioned "FEC frame" from the modified PA layer in FEC mode, where 8b / 10b encoding is not used or is bypassed. In this manner, the modified PA layer can be configured to implement a line coding scheme to generate FEC frames in FEC mode. For example, the modified M-PHY can be implemented to perform bit transmission using the line coding scheme in addition to bit transmission for traditional 8b / 10b encoding, or to be implemented as a dedicated FEC scheme instead of 8b / 10b encoding. For example, the modified M-PHY can be implemented to perform bit transmission using a specific signaling scheme, such as PAM-n (where n>2, such as PAM-4), which can be used in FEC mode. Additionally, in an implementation of the modified M-PHY, the interface between the modified PA layer and the modified physical layer may be a signaling interface (e.g., based on the Reference M-PHY Module Interface (RMMI)) for an advanced line coding scheme (e.g., an FEC scheme) with a larger bus width (e.g., a bus width of 80 bits, 128 bits, 160 bits, or more).

[0146] Figure 2 A forward error correction (FEC) frame according to one embodiment of the present disclosure is shown. Figure 2 A forward error correction (FEC) frame F1 in the link is transmitted via multiple enabled channels of the link. FEC frame F1 includes a data block B1, an error detection block B2 associated with data block B1, and an error correction block B3 associated with data block B1 and error detection block B2. Data block B1 can include one or more data link layer frames or physical adapter layer frames used in an interconnect protocol. Error detection block B2 can be an error detection code to protect data block B1. The error detection code can be, for example, a cyclic redundancy check (CRC) code. The CRC code is generated using a CRC engine based on a cyclic redundancy check (CRC) calculation (e.g., CRC-16, CRC-32, CRC-64, etc.). The CRC engine can be, for example, a CRC calculation circuit that performs the relevant CRC calculation and includes circuit elements such as shift registers and logic gates. In addition, in some embodiments, error correction block B3 is obtained based on a multi-way (or N-way) interleaved forward error correction (FEC) scheme, where N is greater than or equal to 3. The error correction block B3 may be an error correction code, such as a forward error correction (FEC) code generated by a multi-way interleaved error correction code (ECC) engine based on a multi-way interleaved FEC scheme to protect the data block B1 and the error detection block B2.

[0147] Please refer to Figure 2 and Figure 3 , shows an embodiment of generating FEC frames based on a three-way interleaved forward error correction (FEC) scheme. In this embodiment, each FEC frame has a fixed size of 272 bytes and is based on Figure 2The FEC frame includes a data block (B1) with 258 bytes of data, an error detection block (B2) with an 8-byte error detection code (e.g., CRC), and an error correction block (B3) with a 6-byte error correction code (ECC). The 272-byte FEC frame can be divided into three FEC groups, for example, designated FEC0, FEC1, and FEC2, with widths of 91 bytes, 91 bytes, and 90 bytes, respectively. In this embodiment, each of the three FEC groups is protected by a dedicated set of two ECC bytes within the FEC group. For example, a Reed-Solomon code is used as the ECC code, and each symbol is an 8-bit data symbol. Each of the three FEC groups has single-byte recovery capability. In other words, errors in a data symbol of an FEC group can be corrected by the two ECC bytes of that FEC group if the other data symbols of the FEC group are correct. If an error occurs in two data symbols in an FEC group, the error cannot be corrected by the two ECC bytes of the FEC group. In addition, the CRC code of the FEC frame is only used to detect errors (if any) in the data block, but cannot correct errors.

[0148] like Figure 3 As shown, a circuit architecture 300 based on a three-way interleaved forward error correction (FEC) scheme includes a three-way interleaved FEC circuit 301, which includes three forward error correction (FEC) circuits 310, 320, and 330. The three-way interleaved FEC scheme can be implemented by combining data blocks (e.g., 258 bytes) and their associated error detection blocks (e.g., 8 bytes), such as Figure 3 The "data + CRC" shown in FIG is sequentially applied to FEC circuits 310-330 for execution. For example, each of the FEC circuits 310-330 may be a corresponding ECC encoder having a calculation circuit to generate two ECC bytes for an associated portion of the data in the FEC group based on an associated ECC calculation. Please refer to Figure 3 , the first set of data and its CRC code (e.g., a total of 89 bytes) are applied to the FEC circuit 310 to generate two bytes of ECC bytes (e.g., represented by ECC0[0] and ECC0[1]). The second set of data and its CRC code (e.g., a total of 89 bytes) are applied to the FEC circuit 320 to generate two bytes of ECC bytes (e.g., represented by ECC1[0] and ECC1[1]), and the third set of data and its CRC code (e.g., a total of 88 bytes) are applied to the FEC circuit 330 to generate two bytes of ECC bytes (e.g., represented by ECC2[0] and ECC2[1]).

[0149] like Figure 3As shown, the data blocks, CRC codes, and ECC codes of the three FEC groups of an FEC frame (e.g., 272 bytes) are output to a channel allocation module 390. Channel allocation module 390 allocates the data symbols of the three FEC groups (i.e., FEC frame) to one or more enabled channels in an order referred to as a channel allocation sequence (or sequence). For example, in a first channel allocation sequence, the data symbols of FEC groups FEC0, FEC1, and FEC2 of the FEC frame are allocated byte by byte across multiple enabled channels, alternating between the FEC groups (e.g., FEC0, FEC1, FEC2, FEC0, FEC1, FEC2, etc.). Thus, the receiving end can perform forward error correction on the received FEC frame using the ECC bytes.

[0150] Based on the number of enabled channels and a particular channel assignment order, the channel assignment module 390 may result in the following: Figures 4 to 7 and the different channel allocation scenarios shown in the related figures. Figures 4 to 7 In FIG. 1 , a row (e.g., labeled "Channel 0") is associated with a particular channel (e.g., Channel 0) and represents data symbols allocated over time by channel allocation module 390 on that channel. Furthermore, each data symbol of an FEC frame is displayed as a rectangle with a reference number (e.g., "Data 0," "Data 1," etc.) and a background pattern that indicates the associated FEC group to which the data symbol belongs, based on the 3-way interleaved FEC scheme described above. For example, rectangles with background patterns filled with backslashes, blanks, or dots represent FEC groups FEC0, FEC1, and FEC2, respectively, of the FEC frame.

[0151] Figure 4 An example of allocating FEC frames on a dual-channel link (or two enabled channels of a link) in the above-mentioned first channel allocation order (such as FEC0, FEC1, FEC2, FEC0, FEC1, FEC2, etc.) is shown. Figure 4 As shown, two channels, represented by channel 0 and channel 1, are enabled, and every two adjacent data symbols are associated with two different FEC groups on channel 0 or channel 1. In this way, when an FEC frame is transmitted from one electronic device to another electronic device and two data symbols of the FEC frame on channel 0 (or channel 1) are erroneous, the other electronic device can recover the erroneous data using the two ECC codes of the associated FEC group.

[0152] Figure 5 An example of allocating FEC frames on a four-lane link in the first lane allocation order is shown. Figure 5As shown, four channels, represented by Channel 0, Channel 1, Channel 2, and Channel 3, are enabled, and every two adjacent data symbols on the same channel are associated with two different FEC groups. Thus, when an FEC frame is transmitted from one electronic device to another and an error occurs between two data symbols of the FEC frame on one of Channels 0 to 3, the other electronic device can recover the erroneous data using the two ECC codes of the associated FEC group.

[0153] Figure 6 An example of allocating forward error correction (FEC) frames on a three-lane link in the first lane allocation order is shown. Figure 6 As shown, three channels, represented by Channel 0, Channel 1, and Channel 2, are enabled, and every two adjacent data symbols on the same channel are associated with the same FEC group. In this case, when an FEC frame is transmitted from one electronic device to another and an error occurs between two data symbols of the FEC frame on the same channel (e.g., Channel 0), the other electronic device cannot recover the erroneous data using the two ECC codes of the associated FEC group.

[0154] from Figure 4 and Figure 5 It can be seen that for the three-way interleaved FEC scheme, when the number of enabled channels is not a multiple of three (e.g., two, four, etc.), every two adjacent data symbols allocated on the same channel and taken from the FEC frame are associated with two different FEC groups among the three FEC groups. However, when the number of enabled channels is a multiple of three, every two adjacent data symbols allocated on the same channel and taken from the FEC frame are associated with the same FEC group.

[0155] To solve this problem, according to one embodiment, the channel allocation module 300 may be configured to selectively select one of a plurality of channel allocation orders based on the number of enabled channels. Figure 7 An embodiment of allocating forward error correction (FEC) frames on a three-lane link in a second lane allocation order is shown. In the second lane allocation order, data symbols of FEC groups FEC0, FEC1, and FEC2 of the FEC frame are allocated byte by byte on multiple enabled lanes in an "interleaved" order of the FEC groups, e.g., FEC0, FEC1, FEC2, FEC2, FEC1, FEC0, FEC0, FEC1, FEC2, FEC2, FEC1, FEC0, etc. Figure 7In the clock cycle T0, a synchronization pattern is transmitted from the transmitting end to inform the receiver at the receiving end that a new channel allocation order will start from here. The purpose of transmitting the synchronization pattern is to enable the receiver to synchronize again for certain error recovery situations. In clock cycle T1, "data 0", "data 1", and "data 2" are allocated on channel 0, channel 1, and channel 2, respectively. In clock cycle T2, "data 5", "data 4", and "data 3" are allocated on channel 0, channel 1, and channel 2, respectively. In clock cycle T3, "data 6", "data 7", and "data 8" are allocated on channel 0, channel 1, and channel 2, respectively. In this way, the order shown for clock cycles T1 and T2 can be repeated continuously. On at least two enabled channels, any two adjacent data symbols (for example, "data 0" and "data 5") belong to different FEC groups over time. Therefore, the use of the above-mentioned second channel allocation order can avoid any two adjacent data symbols in the same channel (for example, at least channel 0 and channel 2) being in the same FEC, such as Figure 7 The second channel allocation order can also protect against errors in different channels at the same time. For example, in clock cycle T1, if an error occurs in "Data 1" on channel 1 and "Data 0" on channel 0, the error can be corrected. Figure 7 In another embodiment, in clock cycle T2, "Data 4", "Data 5", "Data 3" or "Data 4", "Data 3", "Data 5" can be allocated to channel 0, channel 1, and channel 2 respectively.

[0156] Figure 8 An embodiment of a method for operating an electronic device is shown. The electronic device is operable to communicate with another electronic device according to an interconnection protocol. The method includes the following steps S10-S30.

[0157] In step S10, a forward error correction (FEC) frame to be transmitted via a plurality of enabled channels of a link is obtained. Figure 2 and Figure 3 The FEC frame includes a data block B1, an error detection block B2 associated with the data block B1, and an error correction block B3 associated with the data block B1 and the error detection block B2. In some embodiments, the error correction block B3 is obtained based on an N-way interleaved forward error correction (FEC) scheme, where N is greater than or equal to 3.

[0158] In step S20, the FEC frames are selectively allocated to the plurality of lanes of the link in one of a plurality of different lane allocation orders based on the enabled lane numbers of the plurality of enabled lanes.

[0159] In step S30 , the FEC frame is transmitted to another electronic device through the multiple lanes of the link.

[0160] In some embodiments, the plurality of data symbols of the FEC frame are divided into N forward error correction (FEC) groups for the N-way interleaved FEC scheme, wherein for at least two or each of the plurality of lanes, every two adjacent data symbols allocated on the same lane and taken from the FEC frame are associated with two of the N FEC groups.

[0161] Figure 9 An embodiment of step S20 is shown. Figure 9 In step S20A, Figure 8 An embodiment of step S20. Step S20A includes the following steps S210 to S230.

[0162] In step S210, it is determined whether the number of enabled channels is a positive multiple of N. If the number of enabled channels is a positive multiple of N, step S220 is executed. If the number of enabled channels is not a positive multiple of N, step S230 is executed.

[0163] In step S220, the number of enabled channels is a positive multiple of N, and the data symbols of the FEC frame are allocated to the plurality of channels of the link according to a first channel allocation order selected based on the number of enabled channels. In the first channel allocation order, for each channel in the plurality of channels, one data symbol of one of the N FEC groups on one of the channels is followed by another data symbol of the plurality of data symbols of another of the N FEC groups on the same channel. For example, if N=3 and the number of enabled channels is 3, then the first data symbol is selected accordingly. Figure 7 Channel assignment order shown.

[0164] In step S230, the number of enabled lanes is not a positive multiple of N, and the data symbols of the FEC frame are allocated to the plurality of lanes of the link according to a second lane allocation order selected based on the number of enabled lanes. In the second lane allocation order, for each lane in the plurality of lanes, one data symbol of one of the plurality of data symbols of the N FEC groups on one lane of the plurality of lanes is followed by another data symbol of the plurality of data symbols of another of the N FEC groups on the same lane, wherein the second lane allocation order is different from the first lane allocation order. For example, if N=3 and the number of enabled lanes is 2 or 4, then select Figure 4 or Figure 5 An alternative channel assignment sequence is shown.

[0165] In some embodiments, the data block includes data symbols from a data link layer or a physical adapter layer of the electronic device.

[0166] In some embodiments, the data symbols from the data link layer or the physical adapter layer of the electronic device are based on the unified protocol (UniPro).

[0167] Below, examples are provided to demonstrate Figure 8 The method can be implemented to apply different channel allocation orders in the interconnection protocol.

[0168] In order to apply a different channel allocation order, a power mode change is required. A power mode change is used when changing the power consumption configuration of a link. Figure 10 An example of a power mode change request frame (as represented by PACP_PWR_req in the UniPro specification) according to the UniPro specification (e.g., UniPro version 2.0) is shown. Figure 10 In the embodiment of the present invention, the two power consumption configuration parameters related to the number of enabled lanes are "TxLane" and "RxLane". "TxLane" represents the number of enabled lanes in the transmit (TX) direction (PA_ActiveTxDataLanes), and "RxLane" represents the number of enabled lanes in the receive (RX) direction (PA_ActiveRxDataLanes). When an electronic device according to the interconnection protocol receives TxLane or RxLane, the power consumption configuration parameters can be used to configure a lane allocation module (e.g., 390) to select a lane allocation order that is appropriate for the power consumption configuration parameters.

[0169] In addition, according to the UniPro specification, each PACP frame of the PA layer contains a series of coded 17-bit symbols. Figure 10 As shown, in the first symbol of the PACP_PWR_req frame (which has 17 bits), the value of bit 16 is 1, indicating that the first symbol is a control symbol; the first symbol includes the value ESC_PA and the parameter EscParam_PA, and the parameter EscParam_PA is set to the value PACP_BEGIN, respectively indicating that the frame is a PA layer frame and the first symbol is the beginning of the PACP frame. In addition, as Figure 10 As shown, in the second symbol (which has 17 bits) of the PACP_PWR_req frame, bit 16 is 0, indicating that the second symbol is a data symbol; the field PACP_FunctionID in the second symbol is set to the value PACP_PWR_req (for example, 0x0306 defined in the UniPro specification), indicating that the frame is a PACP_PWR_req frame associated with power consumption configuration information. In addition, as Figure 10As shown, in the third to last symbols of the PACP_PWR_req frame (each symbol is 17 bits), the value of bit 16 is 0, indicating that these symbols are all data symbols. The third to last symbols respectively include multiple fields, such as DevID, Adapt, Flags, TxMode, TxLane, TxGear, RxMode, RxLane, RxGear, PAPowerModeUserData[0]-PAPowerModeUserData

[11] . The last symbol includes a checksum (e.g., a 16-bit CRC code, such as CCITT CRC-16), where CCITT stands for International Telegraph and Telephone Consultative Committee.

[0170] Figure 11 An example showing the allocation of forward error correction (FEC) frames with different channel allocation orders before and after a power mode change. Figure 11 In the example, a power mode change occurs from two enabled channels to three enabled channels. The channel number configuration changes, so the channel allocation order also changes. Figure 11 As shown in FIG. 1 , after the power mode change, three channels, represented by Channel 0, Channel 1, and Channel 2, are enabled, and each two adjacent data symbols on the same channel are associated with a different FEC group. In this case, when an FEC frame is transmitted from one electronic device to another and an error occurs between two data symbols of the FEC frame on the same channel (e.g., Channel 0), the other electronic device can recover the erroneous data using the two ECC codes of the associated FEC group.

[0171] Figure 12 An example showing the allocation of forward error correction (FEC) frames with the same channel allocation order before and after the power mode change. Figure 12 In the , the number of enabled channels changes from 2 to 3, but the channel allocation order remains unchanged, for example, the general channel allocation order is FEC0, FEC1, FEC2, FEC0, FEC1, FEC2, etc. In some cases, an error occurs between two adjacent data symbols on a channel (for example, channel 0). These two symbol errors exceed the error correction capability of the FEC frame. In this case, a negative acknowledgement control (NAC) frame is required to request the peer to retransmit the FEC frame. In particular, when a PAM-4 signaling scheme with a higher bit error rate is used to transmit an FEC frame to another electronic device through multiple channels of a link, NAC frames are more likely to appear, thereby increasing the retransmission rate. This will significantly degrade performance. In comparison, if Figure 11As shown in or related examples, allocating forward error correction (FEC) frames in different channel allocation orders can reduce retransmission rate and improve efficiency.

[0172] Figure 13 A block diagram showing the circuit architecture for channel allocation is shown in FIG. Figure 13 In the embodiment, the circuit architecture includes an FEC module 410, a channel allocation module 420, and a power mode change controller 430. The FEC module 410 outputs an FEC frame, and the channel allocation module 420 allocates the FEC frame across a plurality of channels. The power mode change controller 430 is a circuit module for processing a power mode change process derived from, for example, the UniPro specification (e.g., UniPro version 2.0, etc.). The power mode change controller 430 may output the number of enabled channels to the channel allocation module 420. The channel allocation module 420 is configured to perform Figure 8 In step S20 , the FEC frame is selectively allocated to the plurality of lanes of the link in one of a plurality of different lane allocation orders based on the enabled lane number (eg, TxLane or RxLane) received from the power consumption mode change controller 430 .

[0173] 14A to 14D Examples showing different channel assignment sequences. 14A to 14D As shown in any one of the figures, three channels represented by channel 0, channel 1, and channel 2 are enabled, and on channel 0, channel 1, or channel 2, every two adjacent data symbols on the channel are associated with two different FEC groups. In this way, when an FEC frame is transmitted from one electronic device to another electronic device, and two data symbols of the FEC frame on channel 0 are erroneous, the other electronic device can recover the erroneous data through the two sets of ECC codes of the associated FEC group. In addition, Figure 6 Compared with the situation shown in 14A to 14D The channel allocation order shown in any one of the above can enable the FEC frame to be corrected when an error occurs between two data symbols of a channel.

[0174] Figure 15 An embodiment of a circuit architecture showing a transmission path. This circuit architecture can be implemented in the PA layer of an electronic device. Figure 15 In FIG. 5 , the circuit architecture 500 of the transmission path includes a physical adapter (PA) arbiter 510 , a data interleaver 520 , an FEC encoder module 530 , a channel allocation module 540 , and data scrambling modules (eg, 571 - 573 ).

[0175] exist Figure 15In the embodiment of the present invention, the power mode change request controller 550 is used to obtain data allocation information (for example, the number of enabled lanes such as "TxLane" and "RxLane" obtained from the power mode change request frame). Thereafter, the number of enabled lanes is written into a register (for example, a register of a physical layer register) for selecting one of the lane allocation orders.

[0176] The data link layer or the PA layer may request permission to use the link from the PA arbiter 510. The PA arbiter 510 receives data link data (e.g., data link layer frames) and PACP data (e.g., PACP frames), grants permission to the DL layer or the PA layer to use the link, selects one of the data link data and the PACP data, and outputs the selected data to the data interleaver 520. The data interleaver 520 interleaves the data and distributes the data to the FEC encoder module 530. For example, the FEC encoder module 530 may be based on Figure 3 The channel allocation module 540 is configured to execute Figure 8 The data symbols of the FEC frame are distributed to the data scramblers 571, 573, and 575 of the data scrambling modules associated with the three enabled channels in step S20. The data scramblers 571 to 575 then output the data to the physical layer circuit 710.

[0177] In one example, the channel allocation module 540 can be implemented based on the pseudo code of the hardware description language described in Table 1.

[0178] Table 1

[0179]

[0180]

[0181] According to Table 1, if the number of enabled channels is 2, for example, two data scramblers 571 and 573 are enabled and used. The inputs of the data scramblers 571 and 573 can be represented by Scrambler_0_input[15:0] and Scrambler_1_input[15:0], respectively, and can be configured by this expression:

[0182] Scrambler_0_input[15:0]={fec_frame[23:16],fec_frame[7:0]}; and

[0183] Scrambler_1_input[15:0]={fec_frame[31:24],fec_frame[15:8]},

[0184] fec_frame[] represents the FEC frame. Therefore, the corresponding channel allocation order is FEC0, FEC1, FEC2, FEC0, FEC1, FEC2, and so on.

[0185] According to Table 1, if the number of enabled channels is 3, for example, three data scramblers 571, 573, and 575 are enabled and used. The inputs of the data scramblers 571, 573, and 575 can be represented by Scrambler_0_input[15:0], Scrambler_1_input[15:0], and Scrambler_2_input[15:0], respectively, and can be configured by the expression:

[0186] Scrambler_0_input[15:0]={fec_frame[47:40],fec_frame[7:0]};

[0187] Scrambler_1_input[15:0]={fec_frame[31:24],fec_frame[15:8]};

[0188] Scrambler_2_input[15:0]={fec_frame[39:32],fec_frame[23:16]};

[0189] fec_frame[] represents the FEC frame. Therefore, the corresponding channel allocation order is FEC0, FEC1, FEC2, FEC2, FEC0, FEC1, FEC0, FEC1, FEC2, and so on.

[0190] Figure 16A An embodiment of a circuit architecture for a receiving path is shown. This circuit architecture can be implemented in the PA layer of an electronic device. Figure 16A In FIG. 6 , the circuit architecture 600 for the receive path includes a data descrambling module (e.g., 611-615), a data merging module 620, an FEC decoder module 630, a data combining module 640, and a PA arbiter 650. The operation of this circuit architecture 600 can be viewed as being composed of Figure 15The circuit architecture 500 of the transmission path shown in FIG. 1 is an inverse operation of the operation performed by the circuit architecture 500 of the transmission path shown. The data descrambling module (e.g., 611-615) receives data from the physical layer circuit 720. After descrambling, the data descrambling module (e.g., 611-615) outputs the data to the data merging module 620. The data merging module 620 performs data merging based on the number of enabled channels. After data merging, the data merging module 620 outputs the merged data to the FEC decoder module 630 for FEC decoding. After FEC decoding, the FEC decoder module 630 outputs the decoded data to the data combining module 640 for data combining. After data combining, the data combining module 640 outputs the combined data to the PA arbiter 650. The PA arbiter 650 determines whether the combined data is DL data or PA data and outputs the combined data accordingly.

[0191] Figure 16B An embodiment of an FEC decoder module is shown. At the receiving end, FEC decoder module 630 includes ECC decoders 631, 633, and 635, which are enabled when a 3-way interleaved FEC scheme is used. FEC decoder module 630 also includes a CRC checker 637. Decoding by ECC decoders 631, 633, and 635 is followed by a CRC check performed by CRC checker 637.

[0192] Figure 17 A flow chart showing an embodiment of a method for an electronic device.

[0193] In step S310 , a power consumption mode change request is executed.

[0194] In step S320 , a power consumption mode changing process is performed.

[0195] In step S330 , the transmission burst (TX burst) is turned off.

[0196] In step S340, the content of the MIB attribute for power consumption mode change is set. Since the transmission burst is turned off, the content of the MIB attribute for power consumption mode change is set.

[0197] In step S350 , it is determined whether the advanced signaling scheme and a specific number of enabled channels are used (eg, the number of enabled channels is 3 or a multiple of 3). If so, step S360 is executed. If not, step S370 is executed.

[0198] In step S360, the first channel allocation sequence is applied. For example, the first channel allocation sequence is as follows: Figure 7 、 14A to 14D One of the channel assignment sequences shown.

[0199] In step S370, the second channel allocation sequence is applied. For example, the second channel allocation sequence is as follows: Figures 4 and 5 Channel assignment order shown.

[0200] refer to Figures 18A-18E , as a schematic diagram Figure 17 Embodiment of the method.

[0201] The power mode change process starts with the power mode change request controller. The user can assign a new power configuration. In this new power configuration, FEC will be enabled after starting this new power configuration. Before starting the new power configuration, the power configuration needs to be transmitted to the peer through a handshake process. For example, a module called the power mode change request controller sends this new power configuration to the peer and ensures that the peer will be consistent with the new power configuration, FEC enablement, and correct data allocation in each channel. Compared with the channel allocation method according to the UniPro specification, in this embodiment, the channel allocation will change to a different channel allocation order based on the number of enabled channels, instead of maintaining the same sequential channel allocation order.

[0202] Please refer to Figure 18A The peer responds with a power mode change from the power mode change response controller. The peer receives the new power configuration. It must respond to this request with agreement. This ensures that the peers reach consensus on the new power configuration and the correct data distribution for the next burst in each channel.

[0203] exist Figure 18B In the present invention, after the power mode change handshake is successful, a new power configuration with several information (such as gear, speed, data allocation and number of channels, etc.) is set and stored in the physical layer registers for the receiver (RX) and transmitter (TX).

[0204] Please refer to Figure 18C The physical adapter layer data controller retrieves this information from the physical layer registers and determines data allocation and FEC activity. For example, it obtains information such as gear, speed, data allocation, number of lanes, and FEC enabled. It then determines the data allocation method and FEC enabled accordingly.

[0205] Please refer to Figure 18D , the link layer (e.g., UniPro's data link layer) transmits the data transmission request to the physical adapter layer data controller. After the physical adapter layer data controller approves the request, the data is transmitted to the FEC module and distributed in the new configuration. Figure 11 In the example shown, the number of channels is changed from two to three, and the data distribution is changed from sequential to interleaved.

[0206] Please refer to Figure 18E , the peer end (e.g., the receiving end) operates according to the new configuration. Since the peer end already knows the new cross-allocation method, it can pass the correct data back to the link layer. Figure 18E As shown, data received from the physical layer is processed using inverse data allocation and then processed by the FEC decoder. As a result, the physical adapter layer data controller outputs correct data to the link layer (eg, data link layer).

[0207] In the above embodiments, for illustrative purposes, a three-way interleaved ECC scheme is employed in the following embodiments. Of course, the implementation of the present disclosure (eg, FEC frame, FEC scheme in FEC frame, etc.) is not limited to the embodiments or examples.

[0208] In addition, it should be noted that the implementation of FEC frames is not limited to Figure 3 The number of data bytes in the data block of the FEC frame, or the number of bytes in the error detection block or the number of bytes in the error correction block can be set to other values. In some embodiments, the FEC frame can be selected from Figure 2 The frames in the FEC frame are derived to include a specific number of data bytes, such as 256 or more. In some embodiments, the number of error detection codes or error correction codes in the FEC frame can also be adjusted when appropriate.

[0209] In addition, in one embodiment, before the FEC frame is transmitted at the physical layer, the bytes of the FEC frame are scrambled so that the receiving end can distinguish the ordered set pattern from the scrambled data.

[0210] Various embodiments for implementing the interconnection protocol are provided below.

[0211] Please refer to Figure 19A , which illustrates a circuit architecture diagram according to an embodiment of the present disclosure. Figure 19A As shown, the storage system 1000 includes a host 1010 and a storage device 1020. The host 1010 and the storage device 1020 communicate with each other through an interconnection protocol, so that the host 1010 can perform data access to the storage device 1020. The interconnection protocol can be based on the above-mentioned Figure 1 Or any one or more of the above embodiments of the transmission FEC frame. Figure 19A The circuit architecture of the above technology is applicable to the first device 10 of one or more embodiments described above, which can communicate with the second device 20 of one or more embodiments described above according to the interconnection protocol, wherein the host 1010 and the storage device 1020 can be used to implement the first device 10 and the second device 20, respectively, or vice versa. Figure 19AIn the circuit architecture of FIG. 1 , the controller in the host 1010 or the storage device 1020 for implementing the interconnection protocol can be implemented in various configurations. Figure 19A As shown, the controller in the host 1010 (e.g., host controller 1012) for implementing the interconnection protocol or the controller in the storage device 1020 (e.g., device controller 1022) for implementing the interconnection protocol can be implemented as a circuit architecture including a hardware protocol engine and a processing unit, wherein the processing unit of the controller is optional. In another example, as Figure 19B As shown, the controller in the host 1010 for implementing the interconnection protocol is called, for example, the protocol controller PC1, which can be configured to include a host interface 1011 and a hardware protocol engine 1013 and be implemented as a single chip, wherein the processing unit 1014 can be regarded as an external circuit of the protocol controller PC1. In addition, similarly, the controller in the storage device 1020 for implementing the interconnection protocol (or referred to as the protocol controller of the storage device 1020) can be configured to include a device interface 1021 and a hardware protocol engine 1023 and be implemented as a single chip, wherein the processing unit 1024 can be regarded as an external circuit of the protocol controller. For another example, as Figure 19C As shown, the controller in the host 1010 for implementing the interconnection protocol, for example, the protocol controller PC2, can be configured to include a host interface 1011, a hardware protocol engine 1013, and a processing unit 1014, and be implemented as a single chip. In addition, similarly, the controller in the storage device 1020 for implementing the interconnection protocol (or referred to as the protocol controller of the storage device 1020) can be configured to include a device interface 1021, a hardware protocol engine 1023, and a processing unit 1024, and be implemented as a single chip. Therefore, according to Figure 19A The circuit architecture in the host 1010 or the storage device 1020 for implementing the interconnection protocol can be considered to include or represent a controller based on Figure 19A 、 Figure 19B or Figure 19C An embodiment of . Figure 19A The description of other related examples also applies to Figure 19A 、 Figure 19B or Figure 19C An embodiment of .

[0212] Figure 19AThe circuit architecture shown is flexible enough to be effectively configured to meet the requirements of different products, thereby adapting to the diverse designs of manufacturers to better develop products. For example, the host 1010 is a computing device, such as a smartphone, a tablet computer, a multimedia device, or other electronic device. The storage device 1020 is, for example, a storage device inside or outside the computing device, and is a storage device such as a non-volatile memory-based storage device. The storage device 1020 can be written with data or provide the written data to the host 1010 under the control of the host 1010. The storage device 1020 can be implemented as an internal storage device, a memory card, a solid-state drive (SSD), etc.; however, the implementation of the present disclosure is not limited to the above examples.

[0213] The host 1010 includes a host interface 1011 , a host controller 1012 , and an application processor 1016 .

[0214] The host interface 1011 implements the physical layer of the interconnect protocol in order to link to the storage device 1020. For example, the host interface 1011 implements an adapted version of the physical (M-PHY) layer as illustrated above.

[0215] The host controller 1012 is coupled between the host interface 1011 and the application processor 1016. When the application processor 1016 needs to access data from the storage device 1020, it outputs corresponding access operation instructions or writes data to the host controller 1012 and communicates with the storage device 1020 via an interconnect protocol, thereby completing data access to the storage device 1020.

[0216] The host controller 1012 includes, for example, a hardware protocol engine 1013 and a processing unit 1014 , wherein the processing unit 1014 is optional.

[0217] The hardware protocol engine 1013 implements the link layer of the interconnection protocol. The link layer can be implemented according to the modified version of UniPro as shown above. The hardware protocol engine 1013 communicates with the host interface 1011 and the processing unit 1014 and performs data conversion according to the specifications of the link layer. In addition, the hardware protocol engine 1013 (or the host controller 1012) can be regarded as Figure 2 An embodiment of a link controller 100 of a first device 10 is shown.

[0218] The processing unit 1014 is coupled to the hardware protocol engine 1013 and communicates with the application processor 1016. The processing unit 1014 can execute one or more firmware. For example, access operation commands or write data output by the operating system, driver, or application program executed by the application processor 1016 are converted by the firmware executed by the processing unit 1014 into a format compatible with the link layer of the interconnection protocol. The command or data is then output to the hardware protocol engine 1013 for processing according to the link layer specifications. Alternatively, read data returned by the storage device 1020 in response to a read command from the host 1010 is returned to the hardware protocol engine 1013 according to the link layer specifications of the interconnection protocol. The corresponding firmware executed by the processing unit 1014 converts the data into a format compatible with the operating system, driver, or application program executed by the application processor 1016, and can then be read. The firmware can be stored, for example, in the internal memory of the processing unit 1014 or in the internal memory of the host controller 1012, where the internal memory may include volatile memory and non-volatile memory. The processing unit 1014 is optional, that is, the tasks of the above firmware can be implemented in the hardware protocol engine 1013 through hardware.

[0219] The storage device 1020 includes a device interface 1021 , a device controller 1022 , and a storage module 1026 .

[0220] The device interface 1021 implements the physical layer of the interconnection protocol to link to the host 1010. For example, the device interface 1021 is used to implement an adjusted version of the physical (M-PHY) layer illustrated above.

[0221] The device controller 1022 is coupled between the device interface 1021 and the storage module 1026. With respect to the interconnection protocol, the device controller 1022 has functions corresponding to or similar to those of the host controller 1012 described above. When the host 1010 issues and transmits access operation commands or write data to the storage device 1020 via the interconnection protocol, the device controller 1022 converts the received data into corresponding access operation commands or write data using the interconnection protocol, facilitating data access by the storage module 1026. Alternatively, the device controller 1022 transmits read data transmitted by the storage device 1020 in response to a read command from the host 1010 back to the host 1010 according to the link layer of the interconnection protocol. The storage module 1026 includes, for example, one or more non-volatile memory chips, such as a flash memory chip. In one example, the storage device 1020 may further include a flash memory controller. The flash memory controller is coupled between the device controller 1022 and the storage module 1026 and can be configured to control write, read, or erase operations of the storage module 1026 and can exchange data with the storage module 1026 via an address bus or a data bus. In another example, the flash memory controller can be further provided in the device controller 1022.

[0222] The device controller 1022 includes, for example, a hardware protocol engine 1023 and a processing unit 1024 , wherein the processing unit 1024 is optional.

[0223] The hardware protocol engine 1023 implements the link layer of the interconnection protocol. The link layer can be implemented according to the modified version of UniPro as illustrated above. The hardware protocol engine 1023 communicates with the device interface 1021 and the processing unit 1024 and performs data conversion according to the specifications of the link layer. In addition, the hardware protocol engine 1023 (or the device controller 1022) can be regarded as Figure 2 An embodiment of a link controller 200 of a second device 20 is shown.

[0224] The processing unit 1024 is coupled to the hardware protocol engine 1023 and communicates with the host 1010 via the device interface 1021. The processing unit 1024 can execute one or more firmware. For example, the processing unit 1024 executes one or more firmware to communicate with the flash memory controller described above, thereby exchanging data between the interconnect protocol and the flash memory controller, such as access operation commands, write data, or read data. The firmware can be stored in, for example, the internal memory of the processing unit 1024, the internal memory of the device controller 1022, or a predetermined storage area of ​​the storage module 1026. The internal memory may include volatile memory and non-volatile memory.

[0225] like Figure 19A As shown, the host interface 1011 can be coupled to the device interface 1021, for example, through data lines Din and Dout for transmitting and receiving data, a reset line RST for transmitting a hardware reset signal, and a clock line CLK for transmitting a clock signal. The data lines Din and Dout can be implemented as multiple pairs, where a pair of data lines Din or a pair of data lines Dout can be referred to as a channel, for example for transmitting differential signals. The host interface 1011 can communicate with the device interface 1021 by using at least one interface protocol, which is based on, for example, an advanced signaling scheme; however, the implementation of the present disclosure is not limited to the above examples. Under the adjusted version of the UFS standard, multiple channels can also be configured between the host 1010 and the storage device 1020 to improve transmission efficiency, wherein one or more channels can be supported in either direction from the host 1010 to the storage device 1020 or from the storage device 1020 to the host 1010, and multiple channels can be selectively set to be enabled or disabled.

[0226] The interconnection protocol is explained by taking an adjusted version of the UFS standard as an example. The UFS standard includes a UFS command set (UCS) layer, a UFS transport (UTP) layer, and a UFS interconnect (UIC) layer. The UIC layer includes a link layer and a physical layer. In the interconnection protocol, the link layer of the UIC layer can be implemented according to an adjusted version of the UniPro specification, and the physical layer of the UIC layer can be implemented according to an adjusted version of the M-PHY specification. Under the interconnection protocol, since the implementation of FEC by the adjusted UniPro and the adjusted M-PHY is hidden from other layers of the UFS standard (such as the UCS and UTP layers), the complexity of the implementation of the interconnection protocol is reduced.

[0227] Please refer to Figure 20 , which displays the data according to the UFS standard and Figure 1 of Figure 19A Since the UFS standard is based on the MIPI UniPro layer and the MIPI M-PHY layer, Figure 19A The host interface 1011 and the hardware protocol engine 1013 of the host 1010 shown in FIG are used to implement Figure 20 The adjusted physical layer 1110 and the adjusted UniPro layer 1130. In addition, Figure 19A The device interface 1021 and the hardware protocol engine 1023 of the storage device 1020 are used to implement Figure 20 The adjusted physical layer 1210 and the adjusted UniPro layer 1230 in.

[0228] like Figure 20 As shown, the adjusted UniPro layer 1130 (or 1230) may include an adjusted physical adapter (PA) layer 1131 (or 1231), a data link (DL) layer 1132 (or 1232), a network layer 1133 (or 1233), and a transport layer 1134 (or 1234). The various layers in the adjusted UniPro layer 1230 of the storage device 1020 may also operate and be implemented similarly.

[0229] The adapted physical adapter layer (1131 or 1231) couples the adapted physical layer (1110 or 1210) to the data link layer (1132 or 1232). The adapted physical adapter layer (1131 or 1231) can perform bandwidth control and power management between the adapted physical layer (1110 or 1210) and the data link layer (1132 or 1232). In implementation, the adapted physical layer 1110 of the host 1010 includes a transmitter (TX) 1111 and a receiver (RX) 1112, while the adapted physical layer 1210 of the storage device 1020 includes a transmitter (TX) 1211 and a receiver (RX) 1212, thereby establishing data channels SL1 and SL2 for full-duplex communication. The adapted UniPro specification can support multiple data channels for each transmission direction (e.g., forward or reverse) of the link.

[0230] The data link layer (1132 or 1232) can perform flow control for data transmission between the host 1010 and the storage device 1020. According to one or more of the above embodiments, the data link layer can perform error detection and retransmit frames if errors occur.

[0231] The network layer (1133 or 1233) is used to select a routing function for a transmission path of a packet received from the transport layer (1134 or 1234).

[0232] The transport layer (1134 or 1234) can use the command received from the UFS application layer to configure a data segment suitable for the protocol and transmit the data segment to the network layer (1133 or 1233), or can extract the command from the packet received from the network layer (1133 or 1233) and transmit the command to the UFS application layer.

[0233] In addition, the adjusted UniPro layer (1130 or 1230) can further implement a device management entity (DME) (1135 or 1235), which can communicate with the adjusted physical layer (1110 or 1210) and each layer in the adjusted UniPro layer (1130 or 1230), for example, the adjusted physical adapter layer (1131 or 1231), the data link layer (1132 or 1232), the network layer (1133 or 1233) and the transport layer (1134 or 1234), so as to communicate with the UFS application layer, thereby implementing the overall functions of the adjusted unified protocol (UniPro), such as control or configuration functions, including power on, power off, reset and power consumption mode changes.

[0234] Whenever appropriate, Figure 19A 、 Figure 19B 、 Figure 19C or Figure 20 The circuit architecture in can be configured to perform Figure 8 or Figure 9 Operations of one or more of the multiple embodiments or related examples.

[0235] Whenever appropriate, Figure 15 、 Figure 16A 、 Figure 16B The circuit architecture in this paper can be applied to Figure 19A 、 Figure 19B 、 Figure 19C or Figure 20 The controller in the Figure 8 or Figure 9 The operations of one or more of the above-mentioned multiple embodiments or related examples.

[0236] Furthermore, in the aforementioned embodiments related to a host and a storage device, the hardware protocol engine in the host controller or device controller can be designed based on a hardware description language (HDL) such as Verilog or any other digital circuit design method commonly known to those skilled in the art, and can be implemented by one or more circuits based on, for example, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a complex programmable logic device (CPLD), or by a dedicated circuit or module. The host controller or device controller (or the processing unit or hardware protocol engine therein) can also be based on a microcontroller, a processor, or a digital signal processor (DSP).

[0237] The present disclosure is described using the above-described multiple embodiments. Those skilled in the art will appreciate that these embodiments are intended solely to illustrate the present disclosure and should not be construed as limiting the scope of the present disclosure. It should be noted that all equivalent modifications, substitutions, and replacements made to the embodiments are intended to be within the scope of the present disclosure. Therefore, the scope of protection of the present disclosure should be consistent with the broadest interpretation of the appended claims.

Claims

1. A method for operating an electronic device, the method comprising: obtaining a forward error correction (FEC) frame to be transmitted via a plurality of enabled channels of a link, the FEC frame comprising a data block, an error detection block associated with the data block, and an error correction block associated with the data block and the error detection block; selectively allocating the FEC frames to the plurality of lanes of the link in one of a plurality of different lane allocation orders based on enabled lane quantities of the plurality of enabled lanes; as well as The FEC frame is transmitted to another electronic device through the plurality of lanes of the link.

2. The operating method according to claim 1, wherein: The error correction block is obtained based on an N-way interleaved forward error correction (FEC) scheme, where N is greater than or equal to 3.

3. The operating method according to claim 2, wherein: A plurality of data symbols of the FEC frame are divided into N forward error correction (FEC) groups for the N-way interleaved FEC scheme, wherein for at least two channels among the plurality of channels, every two adjacent data symbols allocated on the same channel and taken from the FEC frame are associated with two of the N FEC groups.

4. The operating method according to claim 2, wherein: The plurality of data symbols of the FEC frame are divided into N forward error correction (FEC) groups for the N-way interleaved FEC scheme; when the number of enabled channels is a positive multiple of N, the plurality of data symbols of the FEC frame are allocated on the plurality of channels of the link in a first channel allocation order selected based on the number of enabled channels, wherein, in the first channel allocation order, for each channel among the plurality of channels, one data symbol of the plurality of data symbols of one of the N FEC groups on one channel among the plurality of channels is followed by another data symbol of the plurality of data symbols of another group of the N FEC groups on the same channel.

5. The operating method according to claim 4, wherein: When the number of enabled lanes is not a positive multiple of N, the plurality of data symbols of the FEC frame are allocated across the plurality of lanes of the link in a second lane allocation order selected based on the number of enabled lanes, wherein, in the second lane allocation order, for respective lanes of the plurality of lanes, one data symbol of the plurality of data symbols of one of the N FEC groups on one of the plurality of lanes is followed by another data symbol of the plurality of data symbols of another of the N FEC groups on the same lane, wherein the second lane allocation order is different from the first lane allocation order. The operating method according to claim 1 , wherein the data block comprises data symbols from a data link layer or a physical adapter layer of the electronic device. 7 . The operating method according to claim 6 , wherein the data symbols from the data link layer or the physical adapter layer of the electronic device are based on a unified protocol UniPro.

8. An electronic device configured to communicate with another electronic device, the electronic device comprising: Interconnect controller, including: Physical layer circuits, used for signal transmission; and A link controller for data transmission coupled to the physical layer circuit, wherein the interconnect controller is configured to perform a plurality of operations, the plurality of operations comprising: generating a forward error correction (FEC) frame to be transmitted via a plurality of enabled channels of a link, the FEC frame comprising a data block, an error detection block associated with the data block, and an error correction block associated with the data block and the error detection block; selectively allocating the FEC frames to the plurality of lanes of the link in one of a plurality of different lane allocation orders based on enabled lane quantities of the plurality of enabled lanes; and The FEC frame is transmitted to another electronic device through the plurality of lanes of the link.

9. The electronic device according to claim 8, wherein: The error correction block is obtained based on an N-way interleaved forward error correction (FEC) scheme, where N is greater than or equal to 3.

10. The electronic device according to claim 9, wherein: A plurality of data symbols of the FEC frame are divided into N forward error correction (FEC) groups for the N-way interleaved FEC scheme, wherein for at least two channels among the plurality of channels, every two adjacent data symbols allocated on the same channel and taken from the FEC frame are associated with two of the N FEC groups.

11. The electronic device according to claim 9, wherein: The plurality of data symbols of the FEC frame are divided into N forward error correction (FEC) groups for the N-way interleaved FEC scheme; when the number of enabled channels is a positive multiple of N, the plurality of data symbols of the FEC frame are allocated on the plurality of channels of the link in a first channel allocation order selected based on the number of enabled channels, wherein, in the first channel allocation order, for each channel among the plurality of channels, one data symbol of the plurality of data symbols of one of the N FEC groups on one channel among the plurality of channels is followed by another data symbol of the plurality of data symbols of another group of the N FEC groups on the same channel.

12. The electronic device according to claim 11, wherein: When the number of enabled lanes is not a positive multiple of N, the plurality of data symbols of the FEC frame are allocated across the plurality of lanes of the link in a second lane allocation order selected based on the number of enabled lanes, wherein, in the second lane allocation order, for respective lanes of the plurality of lanes, one data symbol of the plurality of data symbols of one of the N FEC groups on one of the plurality of lanes is followed by another data symbol of the plurality of data symbols of another of the N FEC groups on the same lane, wherein the second lane allocation order is different from the first lane allocation order.

13. The electronic device of claim 8, wherein the data block comprises data symbols from a data link layer or a physical adapter layer of the electronic device. 14 . The electronic device of claim 13 , wherein the data symbols from the data link layer or the physical adapter layer of the electronic device are based on a unified protocol UniPro.

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