Electric energy quality detector and detection method based on ARM and double DSP chips

Abstract

The invention provides an electric energy quality detector and detection method based on an ARM and double DSP chips, and relates to the technical field of electric energy quality detection, the electric energy quality detector comprises a heterogeneous communication module, a dynamic task scheduling module and a fault-tolerant self-healing module which are connected in sequence; the heterogeneous communication module comprises a dedicated DMA channel and a multi-level priority message queue. Through multi-aspect deep optimization of a heterogeneous communication channel, the stability, rate and flexibility of data transmission reach a new level, more complex and diversified power quality data transmission scenes can be dealt with, and compared with the prior art, qualitative leap in communication performance is realized, and the efficient processing requirement of the system on massive and high-frequency data is effectively supported.

Description

Technical Field

[0001] The present invention relates to the field of power monitoring technology, and specifically to a power quality detector based on an ARM and dual-DSP chip combination architecture. The instrument achieves efficient data processing and real-time optimization through an innovative inter-chip communication protocol and a dynamic task coordination mechanism. Background Art

[0002] Existing power quality detectors mostly use single-core or simple multi-core architectures, which have many problems: 1. Communication bottleneck: Inter-core data transmission relies on shared memory or traditional buses, resulting in significant latency when transmitting high-sampling data (e.g., above 10kHz). As power systems demand higher precision in power quality monitoring, efficient transmission of high-sampling-frequency data has become a critical issue, and traditional communication methods are unable to meet this requirement. In a combination of ARM-based and dual-DSP chips, using traditional communication methods would severely hinder inter-chip data exchange.

[0003] 2. Load imbalance: Fixed task allocation leads to overloading of some chips (for example, FFT calculations often overburden one chip), while other chips remain idle. This results in low overall system resource utilization and prevents the full performance advantage of the ARM and dual DSP chip combination.

[0004] 3. Insufficient real-time performance: Critical tasks (such as transient event capture) may be blocked by routine tasks. In power systems, transient events have a significant impact on power quality. Real-time capture and processing of these events is crucial, but existing systems struggle to ensure this. Similar issues can arise if this chip combination architecture is not properly scheduled.

[0005] 4. Poor fault tolerance: A single chip failure can cause system failure. Power monitoring requires a highly reliable system, but the fault tolerance of existing systems cannot meet the requirements of actual application scenarios. For an ARM and dual-DSP chip combination, a single chip failure could affect the entire system, clearly failing to meet these requirements. Summary of the Invention

[0006] The purpose of the present invention is to solve the technical problems raised in the above background technology.

[0007] In order to solve the above technical problems, the technical solutions included in the present invention are as follows: This invention provides a heterogeneous communication channel design for ARM and dual DSP chips. This design utilizes an independent direct memory access (DMA) channel to meet the transmission requirements of high-frequency sampled data (such as 1kHz-100kHz sampling of voltage and current signals) in power quality monitoring. This channel enables direct transmission between the analog-to-digital conversion (ADC) module and the ARM or DSP chip, completely bypassing the universal bus. Based on the combined architecture of the ARM and dual DSP chips, this design significantly improves data transmission rates. For example, compared to traditional transmission methods that rely on shared memory or traditional buses, data transmission latency is reduced by over 30%. This enables fast and stable data exchange between chips at high sampling frequencies, fully leveraging the data processing capabilities of the ARM and dual DSP chip combination and providing an efficient data input foundation for subsequent data analysis and processing.

[0008] Preferably, a multi-level priority message queue mechanism is constructed. Non-real-time tasks, such as historical energy data storage, are placed in a low-priority queue for transmission. However, tasks with extremely high real-time requirements, such as alarm signals for overvoltage alarms and voltage sags, are transmitted via high-priority interrupt-driven channels. When transferring tasks between different chips, this mechanism ensures that real-time tasks are prioritized and avoid being blocked by non-real-time tasks, thereby ensuring the system's rapid response to critical events. For example, when an overvoltage alarm is detected, the alarm signal is quickly transmitted to the corresponding chip via a high-priority channel for processing, greatly improving the system's ability to respond to emergencies. Furthermore, the data processing and transmission module includes a data acquisition card, a microprocessor, and a wireless transmission module. The data acquisition card uses a high-speed ADC chip with a sampling frequency of no less than 1.2 MSPS to acquire and process the processed Barkhausen signals. The microprocessor uses a high-performance ARM chip to analyze and process the acquired data. The wireless transmission module uses a Wi-Fi module supporting the 2.4 GHz frequency band to transmit the processed data to an external host computer for further analysis.

[0009] Optimally, the ARM and dual-DSP chips report their resource utilization, including key information such as CPU usage and memory utilization, to the scheduler in real time. The scheduler uses lightweight machine learning models, such as linear regression, to predict the workload for the next cycle based on historical task loads and each chip's resource usage. Based on these predictions, the scheduler dynamically allocates tasks to idle or lightly loaded chips. For example, when a large number of Fast Fourier Transform (FFT) calculation tasks are predicted, the scheduler allocates these tasks to the least loaded chip based on the current load of the ARM and dual-DSP chips. This maximizes system resources and avoids situations where some chips are overloaded and others idle due to fixed task allocation. This improves load balancing between the ARM and dual-DSP chips to over 90%, significantly enhancing overall system efficiency.

[0010] Preferably, a task preemption and migration strategy is established. When the system detects a critical event, such as a transient event in the power system (voltage sag, current surge, etc.), a high-priority task can immediately preempt the currently executing low-priority task. At the same time, the interrupted low-priority task is migrated to other chips for continued execution. Under the multi-core architecture of ARM and dual DSP chips, this mechanism ensures that critical tasks can obtain sufficient computing resources for processing in a timely manner, fully utilizing the advantages of multi-core and effectively improving the real-time performance of the system. For example, when a voltage sag event is detected, the system can quickly preempt the currently executing low-priority logging task, concentrating the resources of the ARM and dual DSP chips to analyze and process the transient event, ensuring the power quality detection system's rapid response to critical events.

[0011] Optimally, heartbeat monitoring and hot backup are enhanced: A distributed heartbeat monitoring architecture is employed, with slave chips regularly sending heartbeat signals to the master chip and other slave chips, forming a mutually monitoring network. If a chip detects an abnormal heartbeat in another chip, it immediately conducts a secondary confirmation via redundant communication links, avoiding misjudgments caused by a single link failure. Furthermore, during the task takeover process of the backup chip, a dynamic task priority adjustment strategy is introduced to prioritize the resumption of critical tasks, ensuring that the system can quickly restore core functions after a fault is resolved.

[0012] Preferably, data verification redundancy is enhanced: in addition to the existing dual-core parallel computing combined with CRC verification and error correction code technology, version management and differential backup technology of data copies are adopted. Different copies of key data are version-tagged, and the difference information of each data update is recorded. When data needs to be restored, it is quickly restored to the correct data version at the specified time point based on the version information and differential backup. In addition, a distributed consensus mechanism for data verification is established, and consensus verification of data verification results is performed among multiple chips to improve the credibility and anti-attack capability of data verification. Compared with the existing technology, the significant advantages of the present invention are: 1. Excellent communication capabilities: Through in-depth optimization of various aspects of heterogeneous communication channels, the stability, speed, and flexibility of data transmission have reached new heights. It can cope with more complex and diverse power quality data transmission scenarios. Compared with existing technologies, it has achieved a qualitative leap in communication performance and effectively supports the system's demand for efficient processing of massive and high-frequency data.

[0013] 2. Intelligent and Precise Task Collaboration: Further improvements to the dynamic task coordination mechanism enable more accurate prediction of task loads, more scientific and rational task scheduling, and enhanced risk mitigation capabilities. This enables optimal chip resource allocation and efficient task execution under complex and changing operating conditions, significantly improving the system's overall operational efficiency and real-time responsiveness, overcoming the limitations of existing task scheduling technologies.

[0014] 3. Superior fault tolerance and self-healing capabilities: Comprehensively enhanced fault tolerance and self-healing mechanisms, from more reliable fault monitoring and faster backup takeover to more efficient data recovery and verification, comprehensively improve the system's fault tolerance and data reliability. Even in the face of complex chip failures and data security threats, it can ensure stable system operation and accurate and complete data, far exceeding the reliability level of existing technologies and meeting the extremely high reliability requirements of power monitoring.

[0015] 4. Advanced and Efficient Power Management: Innovative improvements to the power supply module enable energy recycling, convenient wireless charging, and accurate health status assessment, improving energy efficiency and the stability and convenience of system power supply. Compared to existing technologies, power management is more intelligent, efficient, and reliable, providing a solid guarantee for the long-term stable operation of the probe. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the multi-core architecture and communication channels based on the combined architecture of ARM and dual DSP chips provided by the present invention. DETAILED DESCRIPTION

[0017] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described below in conjunction with the accompanying drawings and embodiments. It should be noted that the embodiments of the present application and the features therein can be combined with each other without conflict.

[0018] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways than those described herein. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0019] Example 1 See also Figure 1 The present invention provides a design for heterogeneous communication channels between ARM and dual DSP chips, and carefully designs an independent direct memory access (DMA) channel to meet the transmission requirements of high-frequency sampling data (such as 1kHz-100kHz sampling of voltage and current signals) in power quality detection. This channel realizes direct transmission between the analog-to-digital conversion (ADC) module and the ARM or DSP chip, completely bypassing the universal bus. Under the combined architecture based on ARM and dual DSP chips, this design greatly improves the data transmission rate. For example, compared with the traditional transmission method that relies on shared memory or traditional bus, the data transmission delay is reduced by more than 30%. This enables fast and stable data exchange between chips at high sampling frequencies, fully leveraging the data processing capabilities of the combination of ARM and dual DSP chips, and providing an efficient data input basis for subsequent data analysis and processing.

[0020] Preferably, a multi-level priority message queue mechanism is constructed. Non-real-time tasks, such as historical energy data storage, are placed in a low-priority queue for transmission. However, tasks with extremely high real-time requirements, such as alarm signals for overvoltage alarms and voltage sags, are transmitted via high-priority interrupt-driven channels. When transferring tasks between different chips, this mechanism ensures that real-time tasks are prioritized and avoid being blocked by non-real-time tasks, thereby ensuring the system's rapid response to critical events. For example, when an overvoltage alarm is detected, the alarm signal is quickly transmitted to the corresponding chip via a high-priority channel for processing, greatly improving the system's ability to respond to emergencies. Furthermore, the data processing and transmission module includes a data acquisition card, a microprocessor, and a wireless transmission module. The data acquisition card uses a high-speed ADC chip with a sampling frequency of no less than 1.2 MSPS to acquire and process the processed Barkhausen signals. The microprocessor uses a high-performance ARM chip to analyze and process the acquired data. The wireless transmission module uses a Wi-Fi module supporting the 2.4 GHz frequency band to transmit the processed data to an external host computer for further analysis.

[0021] Optimally, the ARM and dual-DSP chips report their resource utilization, including key information such as CPU usage and memory utilization, to the scheduler in real time. The scheduler uses lightweight machine learning models, such as linear regression, to predict the workload for the next cycle based on historical task loads and each chip's resource usage. Based on these predictions, the scheduler dynamically allocates tasks to idle or lightly loaded chips. For example, when a large number of Fast Fourier Transform (FFT) calculation tasks are predicted, the scheduler allocates these tasks to the least loaded chip based on the current load of the ARM and dual-DSP chips. This maximizes system resources and avoids situations where some chips are overloaded and others idle due to fixed task allocation. This improves load balancing between the ARM and dual-DSP chips to over 90%, significantly enhancing overall system efficiency.

[0022] Preferably, a task preemption and migration strategy is established. When the system detects a critical event, such as a transient event in the power system (voltage sag, current surge, etc.), a high-priority task can immediately preempt the currently executing low-priority task. At the same time, the interrupted low-priority task is migrated to other chips for continued execution. Under the multi-core architecture of ARM and dual DSP chips, this mechanism ensures that critical tasks can obtain sufficient computing resources for processing in a timely manner, fully utilizing the advantages of multi-core and effectively improving the real-time performance of the system. For example, when a voltage sag event is detected, the system can quickly preempt the currently executing low-priority logging task, concentrating the resources of the ARM and dual DSP chips to analyze and process the transient event, ensuring the power quality detection system's rapid response to critical events.

[0023] Optimally, heartbeat monitoring and hot backup are enhanced: A distributed heartbeat monitoring architecture is employed, with slave chips regularly sending heartbeat signals to the master chip and other slave chips, forming a mutually monitoring network. If a chip detects an abnormal heartbeat in another chip, it immediately conducts a secondary confirmation via redundant communication links, avoiding misjudgments caused by a single link failure. Furthermore, during the task takeover process of the backup chip, a dynamic task priority adjustment strategy is introduced to prioritize the resumption of critical tasks, ensuring that the system can quickly restore core functions after a fault is resolved.

[0024] Optimally, data verification redundancy is enhanced: In addition to the existing dual-core parallel computing combined with CRC and error-correcting code technology, data replica version management and differential backup technology are employed. Different copies of critical data are version-stamped, recording the difference information for each data update. When data recovery is needed, the correct data version at the specified time point can be quickly restored based on the version information and differential backups. Furthermore, a distributed consensus mechanism for data verification is established, verifying data verification results across multiple chips, improving the reliability and attack resistance of data verification. Through comprehensive optimization of heterogeneous communication channels, data transmission stability, speed, and flexibility have reached new heights, enabling it to handle more complex and diverse power quality data transmission scenarios. This represents a qualitative leap in communication performance compared to existing technologies, effectively supporting the system's demand for efficient processing of massive, high-frequency data. Further improvements to the dynamic task coordination mechanism enable more accurate task load prediction, more scientific and reasonable task scheduling, and enhanced risk mitigation capabilities. This system can achieve optimal chip resource allocation and efficient task execution under complex and changing operating conditions, significantly improving the system's overall operational efficiency and real-time responsiveness, overcoming the limitations of existing task scheduling. Comprehensive enhancements to the fault-tolerance and self-healing mechanisms, from more reliable fault monitoring and faster backup takeover to more efficient data recovery and verification, comprehensively improve the system's fault tolerance and data reliability. Even in the face of complex chip failures and data security threats, the system can ensure stable operation and accurate and complete data, far exceeding the reliability level of existing technologies and meeting the extremely high reliability requirements of power monitoring. Innovative improvements to the power supply module enable energy recycling, convenient wireless charging, and accurate health status assessment, improving energy efficiency and the stability and convenience of system power supply. Compared to existing technologies, power management is more intelligent, efficient, and reliable, providing a solid guarantee for the long-term stable operation of the probe.

[0025] The above description is merely a preferred embodiment of the present invention and does not constitute any other form of limitation to the present invention. Any person skilled in the art may utilize the technical contents disclosed above to change or modify them into equivalent embodiments with equivalent changes for application in other fields. However, any simple modification, equivalent change, and modification of the above embodiments made in accordance with the technical essence of the present invention without departing from the technical solution of the present invention shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A power quality detector based on ARM and dual DSP chips, characterized in that: It includes a heterogeneous communication module, a dynamic task scheduling module, and a fault-tolerant self-healing module that are connected in sequence; the heterogeneous communication module includes a dedicated DMA channel and a multi-level priority message queue.

2. The power quality detector based on ARM and dual DSP chips according to claim 1, characterized in that: The dynamic task scheduling module adopts a load prediction model to dynamically allocate computing resources according to historical task volume and reasonably allocate tasks between ARM and dual DSP chips.

3. The power quality detector based on ARM and dual DSP chips according to claim 1, characterized in that: The fault-tolerant self-healing module quickly realizes seamless migration of faulty chip tasks through heartbeat detection and context.

4. The detection method of the power quality detector based on ARM and dual DSP chips according to claim 1, characterized in that: The steps include: (1) The ADC module transfers the sampled data to the local cache of the designated chip through a dedicated DMA channel. After the chip pre-processes the data, it sends a real-time alarm signal through a high-priority interrupt and distributes the analyzed data to other chips through a message queue. (2) The scheduler dynamically assigns tasks to the chip with the lowest load based on the load of the ARM and dual DSP chips. When a critical event is detected, it preempts low-priority tasks and concentrates multi-core resources for processing. (3) The master chip periodically sends heartbeat packets to detect the status of the slave chip. When the slave chip fails, the backup chip loads the context snapshot of the failed chip, takes over the task queue and reallocates unfinished tasks.

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