Display panel, preparation method of display panel and electronic equipment

Abstract

The embodiment of the invention provides a display panel, a preparation method of the display panel and electronic equipment, and relates to the technical field of display. The isolation structure and the electrode wires are located on the same layer of one side of the array substrate, the isolation structure is insulated from the adjacent electrode wires, and at least part of the electrode wires comprise first touch electrodes and second touch electrodes; one of the first touch electrodes and the second touch electrodes is configured to access a touch driving signal, and the other one of the first touch electrodes and the second touch electrodes is configured to output a touch sensing signal. According to the display panel, an isolation structure does not need to be reused, mutual capacitance touch control of the display panel can be completed through the first touch control electrode and the second touch control electrode, the cost of the display panel can be reduced, the thickness of the display panel can be reduced, and the purpose that the display panel is light and thin is achieved more easily.

Description

Technical Field

[0001] The present application relates to the field of display technology, and more specifically, to a display panel, a method for manufacturing a display panel, and an electronic device. Background Art

[0002] Organic Light Emitting Diode (OLED) and flat panel display devices based on technologies such as Light Emitting Diode (LED) have been widely used in various consumer electronic products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display panels.

[0003] However, there are still some problems with display panels that need to be solved urgently. Summary of the Invention

[0004] In order to overcome the technical problems mentioned in the above technical background, an embodiment of the present application provides a display panel, wherein the display panel includes:

[0005] array substrate;

[0006] An isolation structure and electrode traces are provided on the same layer on one side of the array substrate, wherein the isolation unit is insulated from adjacent electrode traces, and at least part of the electrode traces include a first touch electrode and a second touch electrode;

[0007] One of the first touch electrode and the second touch electrode is configured to receive a touch driving signal, and the other of the first touch electrode and the second touch electrode is configured to output a touch sensing signal.

[0008] In some possible implementations, the isolation structure includes a plurality of isolation units spaced apart from each other, adjacent isolation units being electrically connected along a first direction via first connecting traces, the first touch electrodes and the second touch electrodes being spaced apart from each other, and orthographic projections of at least some of the first connecting traces on the array substrate being located between orthographic projections of the spaced-apart first touch electrodes and the second touch electrodes on the array substrate;

[0009] Preferably, along the second direction, at least some of the adjacent isolation units are electrically connected via a second connecting wire;

[0010] Preferably, the orthographic projection of the second connecting wire on the array substrate is located between the orthographic projections of the first touch electrode and the second touch electrode on the array substrate that are spaced apart;

[0011] Preferably, the first connecting line and the isolation unit are arranged on the same layer;

[0012] Preferably, the second connecting line is provided on the same layer as the isolation unit;

[0013] Preferably, along the second direction, the distance between the first touch electrode and the second touch electrode ranges from 5 μm to 10 μm;

[0014] Preferably, along the second direction, the width of the orthographic projection of the first connecting trace on the array substrate is in a range of 3 μm to 10 μm;

[0015] Preferably, along the first direction, the width of the orthographic projection of the second connecting trace on the array substrate is in a range of 3 μm to 10 μm.

[0016] In some possible embodiments, at least some of the first touch electrodes include first touch trace segments extending along a first direction, at least some of the first touch trace segments are arranged at intervals, and two adjacent first touch trace segments arranged at intervals along the first direction are electrically connected via a jumper trace, the jumper trace and the first touch trace segments are located in different film layers in the display panel, and the orthographic projection of the jumper trace on the array substrate at least partially overlaps with the orthographic projection of some of the second touch electrodes on the array substrate; and / or

[0017] At least some of the second touch electrodes include second touch trace segments extending along a second direction, at least some of the second touch trace segments are arranged at intervals, and two adjacent second touch trace segments arranged at intervals along the second direction are electrically connected via a jumper trace, the jumper trace and the second touch trace segments are located in different film layers of the display panel, an orthographic projection of the jumper trace on the array substrate at least partially overlaps with an orthographic projection of some of the first touch electrodes on the array substrate, and the second direction intersects the first direction;

[0018] Preferably, at least part of the first touch electrodes include a third touch trace segment extending along the second direction, and the third touch trace segment is electrically connected to the first touch trace segment;

[0019] Preferably, along the second direction, the width of the orthographic projection of the first touch sensing trace segment on the array substrate is in a range of 5 μm to 15 μm;

[0020] Preferably, the isolation structure includes a plurality of isolation units arranged at intervals, and a minimum distance between an orthographic projection of a side of the first touch trace segment close to the isolation unit on the array substrate and an orthographic projection of the isolation unit on the array substrate is 10 μm-30 μm;

[0021] Preferably, along the first direction, the width of the orthographic projection of the second touch sensing trace segment on the array substrate is in a range of 5 μm to 15 μm;

[0022] Preferably, the isolation structure includes a plurality of isolation units arranged at intervals, and a minimum distance between an orthographic projection of a side of the second touch trace segment close to the isolation unit on the array substrate and an orthographic projection of the isolation unit on the array substrate is 10 μm-30 μm;

[0023] Preferably, the second direction is perpendicular to the first direction.

[0024] In some possible embodiments, the isolation structure includes a plurality of isolation units spaced apart, at least some of the adjacent isolation units are electrically connected along a first direction via jumper traces, at least some of the first touch electrodes include third touch trace segments extending along a second direction, the jumper traces and the isolation units are located in different film layers in the display panel, and an orthographic projection of the third touch trace segment on the array substrate at least partially overlaps with an orthographic projection of some of the jumper traces on the array substrate; and / or

[0025] At least some of the first touch electrodes include third touch trace segments extending along the second direction, at least some of the third touch trace segments are spaced apart, and two adjacent third touch trace segments spaced apart along the second direction are electrically connected via a jumper trace; at least some of the adjacent isolation units along the first direction are electrically connected via a first connecting trace, the jumper trace and the third touch trace segments are located in different film layers of the display panel, and an orthographic projection of the jumper trace on the array substrate at least partially overlaps with an orthographic projection of the first connecting trace on the array substrate;

[0026] Preferably, the display panel further includes a third connecting wire extending along the second direction, wherein the third connecting wire is electrically connected to the isolation units arranged along the second direction;

[0027] Preferably, along the first direction, the width of the orthographic projection of the third touch sensing trace segment on the array substrate is in a range of 5 μm to 15 μm;

[0028] Preferably, a minimum distance between an orthographic projection of a side of the third touch sensing trace segment close to the isolation unit on the array substrate and an orthographic projection of the isolation unit on the array substrate is 10 μm-30 μm.

[0029] In some possible embodiments, the isolation structure includes a plurality of isolation units spaced apart, at least some of the adjacent isolation units are electrically connected along a first direction via jumper traces, at least some of the second touch electrodes include second touch trace segments extending along a second direction, the jumper traces and the isolation units are located in different film layers in the display panel, and an orthographic projection of the second touch trace segments on the array substrate at least partially overlaps with an orthographic projection of the jumper trace on the array substrate; and / or

[0030] At least some of the second touch electrodes include second touch trace segments extending along the second direction, at least some of the second touch trace segments are spaced apart, and two adjacent second touch trace segments spaced apart along the second direction are electrically connected via a jumper trace; at least some of the adjacent isolation units along the first direction are electrically connected via a first connecting trace, the jumper trace and the second touch trace segments are located in different film layers in the display panel, and an orthographic projection of the jumper trace on the array substrate at least partially overlaps with an orthographic projection of the first connecting trace on the array substrate;

[0031] Preferably, at least part of the second touch electrodes include a fourth touch trace segment extending along the first direction, and the fourth touch trace segment is electrically connected to the second touch trace segment;

[0032] Preferably, along the second direction, the width of the orthographic projection of the fourth touch trace segment on the array substrate is in a range of 5 μm to 15 μm;

[0033] Preferably, a minimum distance between an orthographic projection of a side of the fourth touch trace segment close to the isolation unit on the array substrate and an orthographic projection of the isolation unit on the array substrate is 10 μm-30 μm.

[0034] In some possible implementations, at least some of the first touch electrodes include first touch trace segments extending along a first direction, and along the first direction, a distance between at least some of the first touch trace segments and the second touch electrodes ranges from 20 μm to 50 μm.

[0035] In some possible implementations, the first touch electrode includes a plurality of first touch sub-electrodes, the second touch electrode includes a plurality of second touch sub-electrodes, and the first touch sub-electrodes and the second touch sub-electrodes are arranged alternately;

[0036] Preferably, the first touch electrode and the second touch electrode are engaged with each other;

[0037] Preferably, the orthographic projections of the first touch electrodes and / or the second touch electrodes on the array substrate are in a mesh structure.

[0038] In some possible implementations, the display panel further includes a pixel group located on one side of the array substrate, and orthographic projections of at least part of the first touch electrodes and / or at least part of the second touch electrodes on the array substrate surround the orthographic projection of the pixel group on the array substrate;

[0039] Preferably, the pixel group includes at least one light-emitting sub-pixel;

[0040] Preferably, the light-emitting sub-pixel includes a red light-emitting sub-pixel, a blue light-emitting sub-pixel, or a green light-emitting sub-pixel.

[0041] In some possible implementations, the array substrate includes a substrate and a conductive layer located on one side of the substrate;

[0042] Preferably, the jumper wire is located in the conductive layer, and / or the display panel further includes a first electrode layer located on one side of the array substrate, and the jumper wire is located in the first electrode layer.

[0043] In some possible implementations, the display panel further includes a first electrode layer, a light-emitting functional layer, and a second electrode layer, which are located on one side of the array substrate and are sequentially stacked in a direction away from the array substrate, and the second electrode layer is electrically connected to the isolation unit;

[0044] Preferably, the isolation structure encloses an isolation opening, the first electrode layer includes a first electrode at least partially located within the isolation opening, the light-emitting functional layer includes a light-emitting portion located within the isolation opening, and the second electrode layer includes a second electrode at least partially located within the isolation opening, and the second electrode is electrically connected to the isolation unit;

[0045] Preferably, the display panel further comprises a pixel defining layer located on one side of the array substrate, the conductive isolation layer is located on a side of the pixel defining layer away from the array substrate, the pixel defining layer comprises a pixel opening exposing at least a portion of the first electrode, the orthographic projection of the isolation unit on the array substrate is located between the orthographic projections of two adjacent pixel openings on the array substrate, and the orthographic projection of the pixel opening on the array substrate is located within the orthographic projection of the isolation opening on the array substrate;

[0046] Preferably, the first electrode comprises an anode;

[0047] Preferably, the second electrode comprises a cathode.

[0048] In some possible implementations, the display panel further includes a first encapsulation layer located on a side of the second electrode layer away from the array substrate, the first encapsulation layer including a plurality of encapsulation units spaced apart from each other, the encapsulation units extending from a side of the isolation unit to a side of the isolation unit away from the array substrate;

[0049] Preferably, the first encapsulation layer is an inorganic encapsulation layer.

[0050] In some possible embodiments, the isolation unit includes a first isolation portion and a second isolation portion stacked in sequence in a direction away from the array substrate, and the orthographic projection of the first isolation portion on the array substrate is located within the orthographic projection of the second isolation portion on the array substrate.

[0051] In some possible implementations, the second electrode is electrically connected to the first isolation portion; and / or the isolation unit further includes a third isolation portion located on a side of the first isolation portion facing the array substrate, and the second electrode is electrically connected to the third isolation portion;

[0052] Preferably, the material of the third isolation portion includes molybdenum metal; and / or the material of the first isolation portion includes aluminum metal; and / or the material of the second isolation portion includes a titanium metal layer.

[0053] In some possible implementations, the present application further provides another display panel, comprising:

[0054] array substrate;

[0055] a pixel group located on one side of the array substrate;

[0056] Electrode traces located on a side of the pixel group away from the array substrate, at least part of the electrode traces including first touch electrodes and second touch electrodes, orthographic projections of at least part of the first touch traces and / or at least part of the second touch traces on the array substrate surrounding the orthographic projection of the pixel group on the array substrate;

[0057] One of the first touch electrode and the second touch electrode is configured to receive a touch driving signal, and the other of the first touch electrode and the second touch electrode is configured to output a touch sensing signal.

[0058] In some possible implementations, the present application further provides a method for preparing a display panel, the method comprising:

[0059] providing an array substrate;

[0060] A conductive isolation layer is formed on one side of the array substrate, the conductive isolation layer including an isolation structure and electrode traces provided on the same layer, the isolation structure being insulated from adjacent electrode traces, and at least some of the electrode traces including first touch electrodes and second touch electrodes;

[0061] One of the first touch electrode and the second touch electrode is configured to receive a touch driving signal, and the other of the first touch electrode and the second touch electrode is configured to output a touch sensing signal.

[0062] Compared with the prior art, this application has the following beneficial effects:

[0063] The present application provides a display panel, a method for manufacturing a display panel, and an electronic device. By disposing an isolation structure, a first touch electrode, and a second touch electrode in the same layer on one side of an array substrate, the display panel can achieve mutual capacitive touch control through the first and second touch electrodes without reusing the isolation structure. This reduces both the cost and thickness of the display panel, further facilitating the goal of thinner and lighter display panels. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0065] Figure 1 A schematic cross-sectional view of a display panel in the related art provided in an embodiment of the present application;

[0066] Figure 2 A schematic top view of a conductive isolation layer provided in an embodiment of the present application;

[0067] Figure 3 This is one of the cross-sectional schematic diagrams of a display panel provided in an embodiment of the present application;

[0068] Figure 4 Provided in the embodiments of this application Figure 2 A magnified schematic diagram of point A in the middle;

[0069] Figure 5 Provided in the embodiments of this application Figure 2 A magnified schematic diagram of point B in the middle;

[0070] Figure 6 The second cross-sectional schematic diagram of the display panel provided in the embodiment of the present application;

[0071] Figure 7 Provided in the embodiments of this application Figure 5 One of the cross-sectional diagrams at AA in the middle;

[0072] Figure 8 Provided in the embodiments of this application Figure 5 The second cross-sectional diagram at AA in the middle;

[0073] Figure 9 Provided in the embodiments of this application Figure 5 The third cross-sectional diagram at AA in the middle;

[0074] Figure 10 Provided in the embodiments of this application Figure 5 The fourth cross-sectional diagram at AA in the middle;

[0075] Figure 11 Provided in the embodiments of this application Figure 5 The fifth cross-sectional diagram at AA in the middle;

[0076] Figure 12 Provided in the embodiments of this application Figure 2 The enlarged schematic diagram of point C in the middle;

[0077] Figure 13 Provided in the embodiments of this application Figure 12 One of the cross-sectional diagrams at the middle BB;

[0078] Figure 14 Provided in the embodiments of this application Figure 12 The second cross-sectional diagram at the middle BB;

[0079] Figure 15 Provided in the embodiments of this application Figure 12 The third cross-sectional diagram at the middle BB;

[0080] Figure 16 Provided in the embodiments of this application Figure 12 The fourth cross-sectional diagram at the middle BB;

[0081] Figure 17 Provided in the embodiments of this application Figure 12 The fifth cross-sectional diagram at the middle BB;

[0082] Figure 18 Provided in the embodiments of this application Figure 2 The enlarged schematic diagram of point D in the middle;

[0083] Figure 19 Provided in the embodiments of this application Figure 18 One of the cross-sectional diagrams at CC;

[0084] Figure 20Provided in the embodiments of this application Figure 18 The second cross-sectional diagram at CC;

[0085] Figure 21 Provided in the embodiments of this application Figure 18 The third cross-sectional diagram at CC;

[0086] Figure 22 Provided in the embodiments of this application Figure 18 The fourth cross-sectional diagram at CC;

[0087] Figure 23 Provided in the embodiments of this application Figure 18 Sectional diagram of CC in the middle part 5;

[0088] Figure 24 Provided in the embodiments of this application Figure 2 The enlarged schematic diagram of point E in the middle;

[0089] Figure 25 Provided in the embodiments of this application Figure 24 One of the cross-sectional diagrams at DD in the middle;

[0090] Figure 26 Provided in the embodiments of this application Figure 24 The second cross-sectional diagram at DD in the middle;

[0091] Figure 27 Provided in the embodiments of this application Figure 24 The third cross-sectional diagram at DD in the middle;

[0092] Figure 28 Provided in the embodiments of this application Figure 24 The fourth cross-sectional diagram at DD in the middle;

[0093] Figure 29 Provided in the embodiments of this application Figure 24 The fifth cross-sectional diagram at DD in the middle;

[0094] Figure 30 Provided in the embodiments of this application Figure 2 The enlarged schematic diagram of point F in the middle;

[0095] Figure 31 Provided in the embodiments of this application Figure 30 One of the cross-sectional diagrams at EE in the middle;

[0096] Figure 32 Provided in the embodiments of this application Figure 30 The second cross-sectional diagram at EE in the middle;

[0097] Figure 33 Provided in the embodiments of this application Figure 30The third cross-sectional diagram at EE;

[0098] Figure 34 Provided in the embodiments of this application Figure 30 The fourth cross-sectional diagram at EE in the middle;

[0099] Figure 35 Provided in the embodiments of this application Figure 30 The fifth cross-sectional diagram at EE in the middle;

[0100] Figure 36 Provided in the embodiments of this application Figure 2 Enlarged schematic diagram of point G in the middle;

[0101] Figure 37 Provided in the embodiments of this application Figure 36 One of the cross-sectional diagrams at FF in the middle;

[0102] Figure 38 Provided in the embodiments of this application Figure 36 The second cross-sectional diagram at FF in the middle;

[0103] Figure 39 Provided in the embodiments of this application Figure 36 The third cross-sectional diagram at FF in the middle;

[0104] Figure 40 Provided in the embodiments of this application Figure 36 The fourth cross-sectional diagram at FF in the middle;

[0105] Figure 41 Provided in the embodiments of this application Figure 36 The fifth cross-sectional diagram at FF in the middle;

[0106] Figure 42 A schematic top view of a first touch electrode and a second touch electrode provided in an embodiment of the present application;

[0107] Figure 43 A schematic flow chart of a method for manufacturing a display panel provided in an embodiment of the present application.

[0108] Reference numerals: 1, array substrate; 101, substrate; 102, buffer layer; 103, gate insulating layer; 104, capacitor dielectric layer; 105, interlayer insulating layer; 106, first planarization layer; 107, second planarization layer; 108, semiconductor layer; 109, first metal layer; 110, second metal layer; 111, third metal layer; 112, fourth metal layer; 2, touch emitting electrode; 3, touch receiving electrode; 4, touch insulating layer; 5, optical adhesive layer; 6, conductive isolation layer; 7, isolation unit; 71, first isolation portion; 72, second isolation portion; 73, third isolation portion; 8, first touch Electrode; 801, first touch sub-electrode; 81, first touch routing segment; 82, third touch routing segment; 9, second touch electrode; 901, second touch sub-electrode; 91, second touch routing segment; 92, fourth touch routing segment; 10, jumper routing; 11, light-emitting sub-pixel; 12, first connecting routing; 13, third connecting routing; 14, first electrode layer; 15, light-emitting portion; 16, second electrode; 17, isolation opening; 18, pixel opening; 19, pixel defining layer; 20, via; 21, first packaging layer; 211, packaging unit; 22, second connecting routing; 23, isolation structure. DETAILED DESCRIPTION

[0109] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0110] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without making any creative efforts shall fall within the scope of protection of the present application.

[0111] The terms "first", "second", "third", etc. are only used for distinction and description and should not be understood as indicating or implying relative importance.

[0112] It should be noted that, in the absence of conflict, different features in the embodiments of the present application can be combined with each other.

[0113] See Figure 1The display panel in the related art includes an array substrate 1, an encapsulation layer located on one side of the array substrate 1, a touch emitting electrode 2 located on the side of the encapsulation layer away from the array substrate 1, a touch insulating layer 4 located on the side of the touch emitting electrode 2 away from the array substrate 1, a touch receiving electrode 3 located on the side of the touch insulating layer 4 away from the array substrate 1, and an optical adhesive layer 5 located on the side of the touch receiving electrode 3 away from the array substrate 1. Forming the touch emitting electrode 2, the touch insulating layer 4, the touch receiving electrode 3, and the optical adhesive layer 5 each requires a mask. Therefore, at least four masks are required to form the touch film layer of the display panel. This not only increases the cost of the display panel but also makes it thicker, making it difficult to achieve the goal of making the display panel thinner and lighter.

[0114] In view of this, this embodiment provides a solution that can improve the reliability of the display panel. The solution provided by this embodiment is described in detail below.

[0115] See Figure 2-Figure 3 This embodiment provides a display panel, which includes an array substrate 1, an isolation structure 23 and electrode wiring.

[0116] The array substrate 1 may include a substrate and multiple drive units located on one side of the substrate. Each drive unit may include one or more semiconductor switching devices. The semiconductor switching devices may be formed by the cooperation of multiple film layers in the array substrate 1. For example, the semiconductor switching devices may be thin film transistors formed by the cooperation of multiple film layers.

[0117] The isolation structure 23 and the electrode traces are arranged in the same layer. The isolation structure 23 and the adjacent electrode traces are insulated. At least part of the electrode traces include the first touch electrode 8 and the second touch electrode 9. The isolation structure 23 and the electrode traces form a conductive isolation layer 6.

[0118] One of the first touch electrode 8 and the second touch electrode 9 is configured to receive a touch driving signal, and the other of the first touch electrode 8 and the second touch electrode 9 is configured to output a touch sensing signal.

[0119] The composition, preparation, etc. of the isolation structure 23 are further described in patents PCT / CN2023 / 134518, 202310759370.2, 202310740412.8, 202310707209.0, and 202311346196.5 for reference.

[0120] When the isolation structure 23 is formed, a first touch electrode 8 and a second touch electrode 9 are formed. When the first touch electrode 8 is configured to receive a touch drive signal, the second touch electrode 9 is configured to output a touch sensing signal; when the second touch electrode 9 is configured to receive a touch drive signal, the first touch electrode 8 is configured to output a touch sensing signal. Thus, compared to the related art solution that requires at least four masks to set up a touch film layer, the number of masks for setting up the touch film layer can be reduced in this embodiment, thereby reducing the manufacturing cost of the display panel. Furthermore, compared to the related art solution in which the touch electrodes are located on different layers and a touch insulating layer 4 is required to separate the touch electrodes on different layers, resulting in a relatively thick display panel in the related art, the first touch electrode 8 and the second touch electrode 9 are set up on the same layer in this embodiment, thereby significantly reducing the thickness of the display panel.

[0121] Furthermore, compared to a low self-capacitance approach, the mutual capacitance between the first touch electrode 8 and the second touch electrode 9 in this embodiment provides a greater capacitance, resulting in a better touch experience. Furthermore, the isolation structure 23 is not required for time-division multiplexing, making the display panel easier to drive and coordinate timing.

[0122] Based on the above design, in this embodiment, an isolation structure 23, first touch electrodes 8, and second touch electrodes 9 are provided in the same layer on one side of the array substrate 1. This eliminates the need to reuse the isolation structure 23, and mutual capacitive touch control of the display panel can be achieved through the first touch electrodes 8 and the second touch electrodes 9. This not only reduces the cost of the display panel, but also reduces the thickness of the display panel, further facilitating the goal of making the display panel thinner and lighter.

[0123] For some possible implementations, see again Figure 2 The display panel further includes a pixel group located on one side of the array substrate 1. The pixel group includes at least one light-emitting sub-pixel 11. The light-emitting sub-pixel 11 includes a red light-emitting sub-pixel, a blue light-emitting sub-pixel, or a green light-emitting sub-pixel. For example, Figure 2 A pixel group includes a red light-emitting sub-pixel, a blue light-emitting sub-pixel, and a green light-emitting sub-pixel.

[0124] For some possible implementations, see again Figure 3The isolation structure 23 includes a plurality of isolation units 7 arranged at intervals. The display panel also includes a first electrode layer 14, a light-emitting functional layer, and a second electrode layer located on one side of the array substrate 1 and stacked in sequence in a direction away from the array substrate 1. The second electrode layer is electrically connected to the isolation structure 23. The isolation units 7 enclose an isolation opening 17. The first electrode layer 14 includes a first electrode at least partially located in the isolation opening 17. The light-emitting functional layer includes a light-emitting portion 15 located in the isolation opening 17. The second electrode layer includes a second electrode 16 at least partially located in the isolation opening 17. The second electrode 16 is electrically connected to the isolation unit 7.

[0125] The display panel also includes a pixel defining layer 19 located on one side of the array substrate 1, the conductive isolation layer 6 is located on the side of the pixel defining layer 19 away from the array substrate 1, the pixel defining layer 19 includes a pixel opening 18 exposing at least part of the first electrode, the orthographic projection of the isolation unit 7 on the array substrate 1 is located between the orthographic projections of two adjacent pixel openings 18 on the array substrate 1, and the orthographic projection of the pixel opening 18 on the array substrate 1 is located within the orthographic projection of the isolation opening 17 on the array substrate 1.

[0126] When forming the first electrode layer 14, the first electrode layer 14 is separated by the isolation unit 7 to form a plurality of spaced first electrodes. When forming the light-emitting functional layer, the light-emitting functional layer is separated by the isolation unit 7 to form a plurality of spaced light-emitting portions 15. When forming the second electrode layer, the second electrode layer is separated by the isolation unit 7 to form a plurality of spaced second electrodes 16. The isolation unit 7 includes a conductive material, and the second electrode 16 is electrically connected to the isolation unit 7. One first electrode, one light-emitting portion 15, and one second electrode 16 form one light-emitting sub-pixel 11. The first electrode is an anode, and the second electrode 16 is a cathode.

[0127] Please see again Figure 2 Along the first direction X, adjacent isolation units 7 can be electrically connected via first connecting traces 12. The first connecting traces 12 are provided on the same layer as the isolation units 7 and can be formed simultaneously with the formation of the isolation units 7. The display panel also includes third connecting traces 13 extending along the second direction Y. The third connecting traces 13 electrically connect the isolation units 7 arranged along the second direction Y. In this way, the second electrodes 16 between the light-emitting sub-pixels 11 can be electrically connected via the first connecting traces 12 and the third connecting traces 13, thereby facilitating uniform application of voltage signals to the second electrodes 16 of the display panel.

[0128] Preferably, see again Figure 2, along the second direction Y, at least some adjacent isolation units 7 are electrically connected through the second connecting trace 22; the orthographic projection of the second connecting trace 22 on the array substrate 1 is located between the orthographic projections of the first touch electrodes 8 and the second touch electrodes 9 arranged at intervals on the array substrate 1, and the second connecting trace 22 is arranged on the same layer as the isolation unit 7.

[0129] For some possible implementations, see Figure 4 , Figure 4 for Figure 3 Enlarged schematic diagram of point A in the middle. First touch electrodes 8 and second touch electrodes 9 are spaced apart, and adjacent isolation units 7 are electrically connected via first connecting traces 12. The orthographic projections of at least some first connecting traces 12 on the array substrate 1 are located between the orthographic projections of the spaced-apart first touch electrodes 8 and second touch electrodes 9 on the array substrate 1.

[0130] At the junction of the first touch electrode 8 and the second touch electrode 9, the first touch electrode 8 and the second touch electrode 9 are spaced apart. Adjacent isolation units 7 are electrically connected in the first direction X via first connecting traces 12; and in the second direction Y, adjacent isolation units 7 are electrically connected via second connecting traces 22. This allows for better electrical connection of the isolation units 7. The first direction X is perpendicular to the second direction Y. For example, the first direction X can be the row direction of the pixel group, and the second direction Y can be the column direction of the pixel group.

[0131] Preferably, see again Figure 4 Along the second direction Y, the spacing L1 between the first touch electrode 8 and the second touch electrode 9 ranges from 5 μm to 10 μm. For example, the spacing L1 can be 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm. Properly setting the spacing L1 not only facilitates the first connecting traces 12 to electrically connect adjacent isolation units 7, but also increases the capacitance between the first touch electrode 8 and the second touch electrode 9, thereby improving the touch accuracy of the display panel.

[0132] Preferably, see again Figure 4 The width W1 of the orthographic projection of the first connecting trace 12 on the array substrate 1 ranges from 3 μm to 10 μm. Width W1 can be 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm, etc. If width W1 is set too large, it will affect the area occupied by the first touch electrode 8 and the second touch electrode 9. If width W1 is set too small, it may affect the reliability of the electrical connection between adjacent isolation units 7. Therefore, a reasonable setting of W1 will not affect the area occupied by the first touch electrode 8 and the second touch electrode 9, but can also improve the reliability of the electrical connection between adjacent isolation units 7.

[0133] Preferably, see again Figure 2 The width W6 of the orthographic projection of the second connecting trace 22 on the array substrate 1 ranges from 3 μm to 10 μm. Width W6 can be 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm, etc. If width W6 is set too large, it will affect the area occupied by the first touch electrodes 8 and the second touch electrodes 9. If width W6 is set too small, it may affect the reliability of the electrical connection between adjacent isolation units 7. Therefore, a reasonable setting of W6 will not affect the area occupied by the first touch electrodes 8 and the second touch electrodes 9, but can also improve the reliability of the electrical connection between adjacent isolation units 7.

[0134] For some possible implementations, see again Figure 2 At the overlapping position of the first touch electrode 8 and the second touch electrode 9, the first touch electrode 8 and / or the second touch electrode 9 are electrically connected through the jumper line 10 to avoid a short circuit between the first touch electrode 8 and the second touch electrode 9.

[0135] In one implementation, see Figure 5 , Figure 5 for Figure 2 Enlarged schematic diagram at point B in the middle. At least some of the first touch electrodes 8 include first touch trace segments 81 extending along the first direction X. At least some of the first touch trace segments 81 are spaced apart. Two adjacent first touch trace segments 81 spaced apart along the first direction X are electrically connected via a jumper trace 10. The jumper trace 10 and the first touch trace segments 81 are located in different film layers of the display panel. The orthographic projection of the jumper trace 10 on the array substrate 1 at least partially overlaps with the orthographic projection of some of the second touch electrodes 9 on the array substrate 1.

[0136] At the overlapping position of the first touch electrode 8 and the second touch electrode 9, the first touch electrode 8 includes first touch trace segments 81 that are oppositely arranged and extend along the first direction X. The first touch trace segments 81 that are oppositely arranged along the first direction X are electrically connected via a jumper trace 10. The jumper trace 10 and the first touch electrode 8 and the second touch electrode 9 are located in different film layers. Therefore, the first touch electrode 8 can avoid the second touch electrode 9.

[0137] See Figure 6 The array substrate 1 includes a substrate 101 and a conductive layer located on one side of the substrate 101 , wherein the conductive layer includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially arranged in a direction away from the substrate 101 .

[0138] The first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer are all metal layers. The array substrate 1 also includes a buffer layer 102 located on one side of the substrate 101 and a semiconductor layer 108 located on the side of the buffer layer 102 away from the substrate 101. The semiconductor layer 108 includes a source region, a drain region and a channel region. The first metal layer 109 includes a gate and a first capacitor plate. The second metal layer 110 includes a second capacitor plate. The first capacitor plate and the second capacitor plate form a capacitor. The third metal layer 111 includes a drain and a source. The drain is electrically connected to the drain region, and the source is electrically connected to the source region. The gate, source and drain form a switching device. The metal wiring of the fourth metal layer 112 is connected to the drain, and the metal wiring of the fourth metal layer 112 is further electrically connected to the first electrode.

[0139] Preferably, see again Figure 6 , an insulating layer is provided between the first conductive layer and the second conductive layer, between the second conductive layer and the third conductive layer, and between the third conductive layer and the fourth conductive layer;

[0140] The insulating layer includes a gate insulating layer 103, a capacitor dielectric layer 104, an interlayer insulating layer 105 and a first planarizing layer 106. The gate insulating layer 103 is located between the buffer layer 102 and the first metal layer 109, the capacitor dielectric layer 104 is located between the first metal layer 109 and the second metal layer 110, the interlayer insulating layer 105 is located between the second metal layer 110 and the third metal layer 111, the first planarizing layer 106 is located between the third metal layer 111 and the fourth metal layer 112, the semiconductor layer 108 is located between the buffer layer 102 and the gate insulating layer 103, and a second planarizing layer 107 is also provided between the fourth metal layer 112 and the anode.

[0141] Preferably, the jumper trace 10 is located in the same film layer or different film layers in the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the first electrode layer, respectively. A via 20 is opened on the insulating layer in the direction away from the substrate 101, and at least part of the jumper trace 10 is located in the via 20.

[0142] In the first example, see Figure 7 The first metal layer 109 includes a jumper trace 10. When forming the first metal layer 109, the jumper trace 10 is formed. Vias 20 are sequentially opened in the pixel definition layer 19, the second planarization layer 107, the first planarization layer 106, the interlayer insulating layer 105, and the capacitor dielectric layer 104. Oppositely disposed first touch sensing trace segments 81 are electrically connected via the jumper trace 10 located in the first metal layer 109. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of installing the jumper traces 10.

[0143] In the second embodiment, see Figure 8The second metal layer 110 includes a jumper trace 10. When forming the second metal layer 110, the jumper trace 10 is formed. Vias 20 are sequentially opened in the pixel definition layer 19, the second planarization layer 107, the first planarization layer 106, and the interlayer insulating layer 105. Oppositely disposed first touch sensing trace segments 81 are electrically connected via the jumper trace 10 located in the second metal layer 110. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of installing the jumper traces 10.

[0144] In the third embodiment, see Figure 9 The third metal layer 111 includes a jumper trace 10. When forming the third metal layer 111, the jumper trace 10 is formed. Vias 20 are sequentially opened in the pixel definition layer 19, the second planarization layer 107, and the first planarization layer 106. Oppositely located first touch trace segments 81 are electrically connected via the jumper trace 10 located in the third metal layer 111. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of installing the jumper traces 10.

[0145] In the fourth embodiment, see Figure 10 The fourth metal layer 112 includes a jumper trace 10. When forming the fourth metal layer 112, the jumper trace 10 is formed, and vias 20 are sequentially opened in the pixel definition layer 19 and the second planarization layer 107. Oppositely disposed first touch trace segments 81 are electrically connected via the jumper trace 10 located in the fourth metal layer 112. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of installing the jumper traces 10.

[0146] In the fifth embodiment, see Figure 11 The first electrode layer 14 includes a jumper trace 10. When forming the first electrode layer 14, the jumper trace 10 is formed, and vias 20 are opened in the pixel definition layer 19. Oppositely disposed first touch trace segments 81 are electrically connected via the jumper trace 10 located in the first electrode layer 14. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of providing the jumper traces 10.

[0147] In another implementation, see Figure 12 , Figure 12 for Figure 2 Enlarged schematic diagram at point C in the middle. At least some of the second touch electrodes 9 include second touch trace segments 91 extending along the second direction Y. At least some of the second touch trace segments 91 are spaced apart. Two adjacent second touch trace segments 91 spaced apart along the second direction Y are electrically connected via a jumper trace 10. The jumper trace 10 and the second touch trace segments 91 are located in different film layers of the display panel. The orthographic projection of the jumper trace 10 on the array substrate 1 at least partially overlaps with the orthographic projection of some of the first touch electrodes 8 on the array substrate 1. The first direction X intersects the second direction Y.

[0148] Preferably, the orthographic projections of at least some of the first touch electrodes 8 and / or at least some of the second touch electrodes 9 on the array substrate 1 surround the orthographic projections of the pixel group on the array substrate 1. In this way, with a pixel group as the minimum division unit, the first touch trace segment 81 and / or at least some of the second touch trace segment 91 surround the pixel group.

[0149] In the first example, see Figure 13 The first metal layer 109 includes a jumper trace 10. When forming the first metal layer 109, the jumper trace 10 is formed. Vias 20 are sequentially opened in the pixel definition layer 19, the second planarization layer 107, the first planarization layer 106, the interlayer insulating layer 105, and the capacitor dielectric layer 104. Oppositely disposed second touch sensing trace segments 91 are electrically connected via the jumper trace 10 located in the first metal layer 109. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of installing the jumper traces 10.

[0150] In the second embodiment, see Figure 14 The second metal layer 110 includes a jumper trace 10. When forming the second metal layer 110, the jumper trace 10 is formed. Vias 20 are sequentially opened in the pixel definition layer 19, the second planarization layer 107, the first planarization layer 106, and the interlayer insulating layer 105. Oppositely disposed second touch sensing trace segments 91 are electrically connected via the jumper trace 10 located in the second metal layer 110. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of installing the jumper traces 10.

[0151] In the third embodiment, see Figure 15 The third metal layer 111 includes a jumper trace 10. When forming the third metal layer 111, the jumper trace 10 is formed. Vias 20 are sequentially opened in the pixel definition layer 19, the second planarization layer 107, and the first planarization layer 106. Oppositely located second touch trace segments 91 are electrically connected via the jumper trace 10 located in the third metal layer 111. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of installing the jumper traces 10.

[0152] In the fourth embodiment, see Figure 16 The fourth metal layer 112 includes a jumper trace 10. When forming the fourth metal layer 112, the jumper trace 10 is formed, and vias 20 are sequentially opened in the pixel definition layer 19 and the second planarization layer 107. The oppositely disposed second touch trace segments 91 are electrically connected via the jumper trace 10 located in the fourth metal layer 112. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of installing the jumper traces 10.

[0153] In the fifth embodiment, see Figure 17 The first electrode layer 14 includes a jumper trace 10. When forming the first electrode layer 14, the jumper trace 10 is formed, and vias 20 are opened in the pixel definition layer 19. Oppositely disposed second touch trace segments 91 are electrically connected via the jumper trace 10 located in the first electrode layer 14. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of providing the jumper traces 10.

[0154] Preferably, see again Figure 2 At least some of the first touch electrodes 8 include third touch trace segments 82 extending along the second direction Y. The third touch trace segments 82 are electrically connected to the first touch trace segments 81. This increases the area occupied by the first touch electrodes 8, thereby further improving the touch accuracy of the display panel.

[0155] Preferably, see again Figure 12 Along the second direction Y, the width W2 of the orthographic projection of the first touch trace segment 81 on the array substrate 1 ranges from 5μm to 15μm. For example, the width W2 can be 5μm, 7μm, 10μm, 12μm, 14μm, or 15μm. If the width W2 is set too large, the spacing between the first touch trace segment 81 and the isolation unit 7 will be reduced, thereby increasing the difficulty of etching the first touch trace segment 81 and the isolation unit 7. If the width W2 is set too small, the touch sensitivity of the display panel will be reduced. Therefore, a reasonable setting of the width W2 can make it easier to etch the first touch trace segment 81 from the conductive isolation layer 6 without affecting the touch sensitivity of the display panel.

[0156] Preferably, see again Figure 12 The minimum distance D2 between the orthographic projection of the side of the first touch trace segment 81 closest to the isolation unit 7 on the array substrate 1 and the orthographic projection of the isolation unit 7 on the array substrate 1 is 10μm-30μm. For example, the minimum distance D2 can be 10μm, 12μm, 15μm, 20μm, 25μm, 28μm, or 30μm. If the minimum distance D2 is set too small, it will increase the difficulty of etching the first touch trace segment 81 and even increase the risk of short circuiting between the first touch trace segment 81 and the isolation unit 7. If the minimum distance D2 is set too small, the area of ​​the first touch trace segment 81 will be reduced, thereby reducing the touch sensitivity of the display panel. Therefore, a reasonable setting of the minimum distance D2 can make it easier to etch the first touch trace segment 81 from the conductive isolation layer 6 without affecting the touch sensitivity of the display panel.

[0157] For some possible implementations, see again Figure 2At the overlapping position of the first touch electrode 8 and the isolation unit 7 , the first touch electrode 8 and / or the isolation unit 7 are electrically connected via a jumper line 10 to avoid a short circuit between the first touch electrode 8 and the isolation unit 7 .

[0158] In one implementation, see Figure 18 , Figure 18 for Figure 2 An enlarged schematic diagram of point D in the middle. Along a first direction X, at least some adjacent isolation units 7 are electrically connected via jumper traces 10. At least some first touch electrodes 8 include third touch trace segments 82 extending along a second direction Y. The jumper traces 10 and the isolation units 7 are located in different film layers within the display panel. The orthographic projection of the third touch trace segment 82 on the array substrate 1 at least partially overlaps with the orthographic projection of some of the jumper traces 10 on the array substrate 1. In this implementation, the first touch electrode 8 is located on the side of the jumper trace 10 away from the substrate 101. The potential of the second electrode 16 is less likely to absorb the ground electric field of the first touch electrode 8, which helps increase the coupling capacitance between the first touch electrode 8 and the second touch electrode 9, thereby improving the touch performance of the display panel.

[0159] In the first example, see Figure 19 The first metal layer 109 includes jumper traces 10. When forming the first metal layer 109, the jumper traces 10 are formed. Vias 20 are then sequentially opened in the pixel definition layer 19, the second planarization layer 107, the first planarization layer 106, the interlayer insulating layer 105, and the capacitor dielectric layer 104. Adjacent isolation units 7 are electrically connected via the jumper traces 10 located in the first metal layer 109. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of providing jumper traces 10.

[0160] In the second embodiment, see Figure 20 The second metal layer 110 includes jumper traces 10. When forming the second metal layer 110, the jumper traces 10 are formed, and vias 20 are sequentially opened in the pixel definition layer 19, the second planarization layer 107, the first planarization layer 106, and the interlayer insulating layer 105. Adjacent isolation units 7 are electrically connected via the jumper traces 10 located in the second metal layer 110. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of providing jumper traces 10.

[0161] In the third embodiment, see Figure 21The third metal layer 111 includes a jumper trace 10. When forming the third metal layer 111, the jumper trace 10 is formed. Vias 20 are then sequentially opened in the pixel definition layer 19, the second planarization layer 107, and the first planarization layer 106. Adjacent isolation units 7 are electrically connected via the jumper trace 10 located in the third metal layer 111. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of providing jumper traces 10.

[0162] In the fourth embodiment, see Figure 22 The fourth metal layer 112 includes a jumper trace 10. When forming the fourth metal layer 112, the jumper trace 10 is formed, and vias 20 are sequentially opened in the pixel definition layer 19 and the second planarization layer 107. Adjacent isolation units 7 are electrically connected via the jumper trace 10 located in the fourth metal layer 112. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of providing jumper traces 10.

[0163] In the fifth embodiment, see Figure 23 The first electrode layer 14 includes jumper traces 10. When forming the first electrode layer 14, the jumper traces 10 are formed, and vias 20 are opened in the pixel defining layer 19. Adjacent isolation units 7 are electrically connected via the jumper traces 10 located in the first electrode layer 14. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of providing the jumper traces 10.

[0164] In another implementation, see Figure 24 , Figure 24 for Figure 2 Enlarged schematic diagram at point E in the middle. At least some of the first touch electrodes 8 include third touch trace segments 82 extending along the second direction Y. At least some of the third touch trace segments 82 are spaced apart, and two adjacent third touch trace segments 82 spaced apart along the second direction Y are electrically connected via a jumper trace 10. At least some adjacent isolation units 7 along the first direction X are electrically connected via a first connecting trace 12. The jumper trace 10 and the third touch trace segments 82 are located in different film layers of the display panel, and the orthographic projection of the jumper trace 10 on the array substrate 1 at least partially overlaps with the orthographic projection of some first connecting traces 12 on the array substrate 1.

[0165] In the first example, see Figure 25The first metal layer 109 includes a jumper trace 10. When forming the first metal layer 109, the jumper trace 10 is formed. Vias 20 are sequentially opened in the pixel definition layer 19, the second planarization layer 107, the first planarization layer 106, the interlayer insulating layer 105, and the capacitor dielectric layer 104. The opposing third touch lines are electrically connected via the jumper trace 10 located in the first metal layer 109. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of installing the jumper traces 10.

[0166] In the second embodiment, see Figure 26 The second metal layer 110 includes a jumper trace 10. When forming the second metal layer 110, the jumper trace 10 is formed. Vias 20 are sequentially opened in the pixel definition layer 19, the second planarization layer 107, the first planarization layer 106, and the interlayer insulating layer 105. The opposing third touch lines are electrically connected via the jumper trace 10 located in the second metal layer 110. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of installing the jumper traces 10.

[0167] In the third embodiment, see Figure 27 The third metal layer 111 includes a jumper trace 10. When forming the third metal layer 111, the jumper trace 10 is formed. Vias 20 are sequentially opened in the pixel definition layer 19, the second planarization layer 107, and the first planarization layer 106. Oppositely located third touch lines are electrically connected via the jumper trace 10 located in the third metal layer 111. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of installing the jumper traces 10.

[0168] In the fourth embodiment, see Figure 28 The fourth metal layer 112 includes a jumper trace 10. When forming the fourth metal layer 112, the jumper trace 10 is formed, and vias 20 are sequentially opened in the pixel definition layer 19 and the second planarization layer 107. The opposing third touch lines are electrically connected via the jumper trace 10 located in the fourth metal layer 112. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of installing the jumper traces 10.

[0169] In the fifth embodiment, see Figure 29 The first electrode layer 14 includes a jumper trace 10. When forming the first electrode layer 14, the jumper trace 10 is formed, and vias 20 are opened in the pixel definition layer 19. Oppositely located third touch lines are electrically connected via the jumper trace 10 located in the first electrode layer 14. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of installing the jumper traces 10.

[0170] Preferably, see again Figure 18Along the first direction X, the width W3 of the orthographic projection of the third touch trace segment 82 on the array substrate 1 ranges from 5μm to 15μm. For example, the width W3 can be 5μm, 7μm, 10μm, 12μm, 14μm, or 15μm. If the width W3 is set too large, the spacing between the third touch trace segment 82 and the isolation unit 7 will be reduced, thereby increasing the difficulty of etching the third touch trace segment 82 and the isolation unit 7. If the width W3 is set too small, the touch sensitivity of the display panel will be reduced. Therefore, a reasonable setting of the width W3 can make it easier to etch the third touch trace segment 82 from the conductive isolation layer 6 without affecting the touch sensitivity of the display panel.

[0171] Preferably, the minimum distance D3 between the orthographic projection of the side of the third touch trace segment 82 closest to the isolation unit 7 on the array substrate 1 and the orthographic projection of the isolation unit 7 on the array substrate 1 is 10 μm-30 μm. For example, the minimum distance D3 can be 10 μm, 12 μm, 15 μm, 20 μm, 25 μm, 28 μm, or 30 μm. If the minimum distance D3 is set too small, the difficulty of etching the third touch trace segment 82 will increase, and there may even be a risk of short circuiting between the third touch trace segment 82 and the isolation unit 7. If the minimum distance D3 is set too small, the area of ​​the third touch trace segment 82 will be reduced, thereby reducing the touch sensitivity of the display panel. Therefore, a reasonable setting of the minimum distance D3 can make it easier to etch the third touch trace segment 82 from the conductive isolation layer 6 without affecting the touch sensitivity of the display panel.

[0172] For some possible implementations, see again Figure 2 At the overlapping position of the second touch electrode 9 and the isolation unit 7 , the second touch electrode 9 and / or the isolation unit 7 are electrically connected via a jumper line 10 to avoid a short circuit between the second touch electrode 9 and the isolation unit 7 .

[0173] In one implementation, see Figure 30 , Figure 30 for Figure 2 Enlarged schematic diagram at point F. Along the first direction X, at least some adjacent isolation units 7 are electrically connected via jumper traces 10. At least some second touch electrodes 9 include second touch trace segments 91 extending along the second direction Y. The jumper traces 10 and the isolation units 7 are located in different film layers of the display panel. The orthographic projections of the second touch trace segments 91 on the array substrate 1 at least partially overlap with the orthographic projections of some jumper traces 10 on the array substrate 1. In this implementation, the second touch electrodes 9 are located on the side of the jumper traces 10 away from the substrate 101. The potential of the second electrode 16 is less likely to absorb the ground electric field of the second touch electrodes 9, which helps increase the coupling capacitance between the first touch electrodes 8 and the second touch electrodes 9, thereby improving the touch performance of the display panel.

[0174] In the first example, see Figure 31 The first metal layer 109 includes jumper traces 10. When forming the first metal layer 109, the jumper traces 10 are formed. Vias 20 are then sequentially opened in the pixel definition layer 19, the second planarization layer 107, the first planarization layer 106, the interlayer insulating layer 105, and the capacitor dielectric layer 104. Adjacent isolation units 7 are electrically connected via the jumper traces 10 located in the first metal layer 109. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of providing jumper traces 10.

[0175] In the second embodiment, see Figure 32 The second metal layer 110 includes jumper traces 10. When forming the second metal layer 110, the jumper traces 10 are formed, and vias 20 are sequentially opened in the pixel definition layer 19, the second planarization layer 107, the first planarization layer 106, and the interlayer insulating layer 105. Adjacent isolation units 7 are electrically connected via the jumper traces 10 located in the second metal layer 110. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of providing jumper traces 10.

[0176] In the third embodiment, see Figure 33 The third metal layer 111 includes a jumper trace 10. When forming the third metal layer 111, the jumper trace 10 is formed. Vias 20 are then sequentially opened in the pixel definition layer 19, the second planarization layer 107, and the first planarization layer 106. Adjacent isolation units 7 are electrically connected via the jumper trace 10 located in the third metal layer 111. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of providing jumper traces 10.

[0177] In the fourth embodiment, see Figure 34 The fourth metal layer 112 includes a jumper trace 10. When forming the fourth metal layer 112, the jumper trace 10 is formed, and vias 20 are sequentially opened in the pixel definition layer 19 and the second planarization layer 107. Adjacent isolation units 7 are electrically connected via the jumper trace 10 located in the fourth metal layer 112. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of providing jumper traces 10.

[0178] In the fifth embodiment, see Figure 35 The first electrode layer 14 includes jumper traces 10. When forming the first electrode layer 14, the jumper traces 10 are formed, and vias 20 are opened in the pixel defining layer 19. Adjacent isolation units 7 are electrically connected via the jumper traces 10 located in the first electrode layer 14. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of providing the jumper traces 10.

[0179] In another implementation, see Figure 36 , Figure 36 for Figure 2 Enlarged schematic diagram at point G in the middle. At least some of the second touch electrodes 9 include second touch trace segments 91 extending along the second direction Y. At least some of the second touch trace segments 91 are spaced apart, and two adjacent second touch trace segments 91 spaced apart along the second direction Y are electrically connected via a jumper trace 10. At least some adjacent isolation units 7 along the first direction X are electrically connected via a first connecting trace 12. The jumper trace 10 and the second touch trace segments 91 are located in different film layers of the display panel, and the orthographic projection of the jumper trace 10 on the array substrate 1 at least partially overlaps with the orthographic projection of the first connecting trace 12 on the array substrate 1.

[0180] In the first example, see Figure 37 The first metal layer 109 includes a jumper trace 10. When forming the first metal layer 109, the jumper trace 10 is formed. Vias 20 are sequentially opened in the pixel definition layer 19, the second planarization layer 107, the first planarization layer 106, the interlayer insulating layer 105, and the capacitor dielectric layer 104. Oppositely disposed second touch lines are electrically connected via the jumper trace 10 located in the first metal layer 109. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of installing the jumper traces 10.

[0181] In the second embodiment, see Figure 38 The second metal layer 110 includes a jumper trace 10. When forming the second metal layer 110, the jumper trace 10 is formed. Vias 20 are sequentially opened in the pixel definition layer 19, the second planarization layer 107, the first planarization layer 106, and the interlayer insulating layer 105. Oppositely disposed second touch lines are electrically connected via the jumper trace 10 located in the second metal layer 110. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of installing the jumper traces 10.

[0182] In the third embodiment, see Figure 39 The third metal layer 111 includes a jumper trace 10. When forming the third metal layer 111, the jumper trace 10 is formed. Vias 20 are then sequentially opened in the pixel definition layer 19, the second planarization layer 107, and the first planarization layer 106. The oppositely disposed second touch lines are electrically connected via the jumper trace 10 located in the third metal layer 111. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of installing the jumper traces 10.

[0183] In the fourth embodiment, see Figure 40The fourth metal layer 112 includes a jumper trace 10. When forming the fourth metal layer 112, the jumper trace 10 is formed. Vias 20 are then opened in the pixel definition layer 19 and the second planarization layer 107. The opposing second touch lines are electrically connected via the jumper trace 10 located in the fourth metal layer 112. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of installing the jumper trace 10.

[0184] In the fifth embodiment, see Figure 41 The first electrode layer 14 includes a jumper trace 10. When forming the first electrode layer 14, the jumper trace 10 is formed, and vias 20 are opened in the pixel definition layer 19. Oppositely located third touch lines are electrically connected via the jumper trace 10 located in the first electrode layer 14. This eliminates the need for dedicated jumper traces 10, thereby reducing the cost of installing the jumper traces 10.

[0185] Preferably, see again Figure 30 Along the first direction X, the width W4 of the orthographic projection of the second touch trace segment 91 on the array substrate 1 ranges from 5μm to 15μm. For example, the width W4 can be 5μm, 7μm, 10μm, 12μm, 14μm, or 15μm. If the width W4 is set too large, the spacing between the second touch trace segment 91 and the isolation unit 7 will be reduced, thereby increasing the difficulty of etching the second touch trace segment 91 and the isolation unit 7. If the width W4 is set too small, the touch sensitivity of the display panel will be reduced. Therefore, a reasonable setting of the width W4 can make it easier to etch the second touch trace segment 91 from the conductive isolation layer 6 without affecting the touch sensitivity of the display panel.

[0186] Preferably, see again Figure 30 The minimum distance D4 between the orthographic projection of the side of the second touch trace segment 91 closest to the isolation unit 7 on the array substrate 1 and the orthographic projection of the isolation unit 7 on the array substrate 1 is 10μm-30μm. For example, the minimum distance D3 can be 10μm, 12μm, 15μm, 20μm, 25μm, 28μm, or 30μm. If the minimum distance D4 is set too small, it will increase the difficulty of etching the second touch trace segment 91 and even increase the risk of short circuiting between the second touch trace segment 91 and the isolation unit 7. If the minimum distance D4 is set too small, the area of ​​the second touch trace segment 91 will be reduced, thereby reducing the touch sensitivity of the display panel. Therefore, a reasonable setting of the minimum distance D4 can make it easier to etch the second touch trace segment 91 from the conductive isolation layer 6 without affecting the touch sensitivity of the display panel.

[0187] Preferably, see again Figure 2At least some of the second touch electrodes 9 include a fourth touch trace segment 92 extending along the first direction X. The fourth touch trace segment 92 is electrically connected to the second touch trace segment 91. In this way, the area of ​​the second touch electrodes 9 can be increased, thereby further improving the touch accuracy of the display panel.

[0188] Preferably, along the second direction Y, the width W5 of the orthographic projection of the fourth touch trace segment 92 on the array substrate 1 is in the range of 5μm-15μm. For example, the width W5 can be 5μm, 7μm, 10μm, 12μm, 14μm or 15μm, etc. If the width W5 is set too large, the spacing between the fourth touch trace segment 92 and the isolation unit 7 will be reduced, thereby increasing the difficulty of etching the fourth touch trace segment 92 and the isolation unit 7; if the width W5 is set too small, the touch sensitivity of the display panel will be reduced. Therefore, a reasonable setting of the width W5 can make it easier to etch the fourth touch trace segment 92 from the conductive isolation layer 6 without affecting the touch sensitivity of the display panel.

[0189] Preferably, the minimum distance D5 between the orthographic projection of the side of the fourth touch trace segment 92 closest to the isolation unit 7 on the array substrate 1 and the orthographic projection of the isolation unit 7 on the array substrate 1 is 10 μm-30 μm. For example, the minimum distance D5 can be 10 μm, 12 μm, 15 μm, 20 μm, 25 μm, 28 μm, or 30 μm. If the minimum distance D5 is set too small, the difficulty of etching the fourth touch trace segment 92 will increase, and there may even be a risk of short circuiting between the fourth touch trace segment 92 and the isolation unit 7. If the minimum distance D5 is set too small, the area of ​​the fourth touch trace segment 92 will be reduced, thereby reducing the touch sensitivity of the display panel. Therefore, a reasonable setting of the minimum distance D5 can make it easier to etch the fourth touch trace segment 92 from the conductive isolation layer 6 without affecting the touch sensitivity of the display panel.

[0190] For some possible implementations, see again Figure 2 At least some of the first touch electrodes 8 include first touch trace segments 81 extending along the first direction X. Along the first direction X, the spacing H between at least some of the first touch trace segments 81 and the second touch electrodes 9 ranges from 20 μm to 50 μm. For example, the spacing H can be 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, or 50 μm. Thus, by reasonably increasing the spacing between the first touch trace segments 81 and the second touch electrodes 9 at the junction between the first touch electrodes 8 and the second touch electrodes 9, the overlapping area between the first touch trace segments 81 and the traces in the array substrate 1 can be reduced, thereby reducing coupling between the first touch trace segments 81 and the traces in the array substrate 1, thereby further improving the touch quality of the display panel.

[0191] For some possible implementations, see Figure 42 The first touch electrodes 8 and the second touch electrodes 9 are interlaced. Furthermore, the first touch electrode 8 includes multiple first touch sub-electrodes 801, and the second touch electrode 9 includes multiple second touch sub-electrodes 901. The first touch sub-electrodes 801 and the second touch sub-electrodes 901 intermesh with each other. This further increases the interaction area between the first touch electrodes 8 and the second touch electrodes 9, thereby further increasing the mutual capacitance between the first touch electrodes 8 and the second touch electrodes 9. Parameters such as the capacitance between the first touch electrodes 8 and the second touch electrodes 9 can be adjusted according to actual needs, providing greater flexibility.

[0192] Preferably, see again Figure 42 The orthographic projections of the first touch electrodes 8 and / or the second touch electrodes 9 on the array substrate 1 are in a mesh structure. In this way, the interaction area between the first touch electrodes 8 and the second touch electrodes 9 can be further increased.

[0193] For some possible implementations, see again Figure 35 The display panel further includes a first encapsulation layer 21 located on a side of the second electrode layer away from the array substrate 1. The first encapsulation layer 21 includes a plurality of spaced-apart encapsulation units 211. The encapsulation units 211 extend from the side of the isolation unit 7 to the side of the isolation unit 7 away from the array substrate 1. The first encapsulation layer 21 is an inorganic encapsulation layer. The encapsulation units 211 can independently encapsulate the light-emitting sub-pixels 11, thereby improving the display characteristics of the display panel.

[0194] For some possible implementations, see again Figure 34 The isolation unit 7 includes a first isolation portion 71 and a second isolation portion 72 stacked in sequence in a direction away from the array substrate 1 , and the orthographic projection of the first isolation portion 71 on the array substrate 1 is located within the orthographic projection of the second isolation portion 72 on the array substrate 1 .

[0195] Because the second isolation portion 72 is located on the side of the first isolation portion 71 away from the array substrate 1, and the lateral width of the second isolation portion 72 is greater than the lateral width of the first isolation portion 71, the second isolation portion 72 disconnects the light-emitting functional layer and the second electrode layer at the isolation unit 7. In this way, the isolation unit 7 formed by the first isolation portion 71 and the second isolation portion 72 can more easily enable each light-emitting sub-pixel 11 to be independently packaged.

[0196] For some possible implementations, see again Figure 34 , the second electrode 16 is electrically connected to the first isolation portion 71; see again Figure 35, and / or the isolation unit 7 further includes a third isolation portion 73 located on the side of the first isolation portion 71 facing the array substrate 1, and the second electrode 16 is electrically connected to the third isolation portion 73; the third isolation portion 73 is made of molybdenum; and / or the first isolation portion 71 is made of aluminum; and / or the second isolation portion 72 is made of a titanium layer. In this way, when the isolation unit 7 separates the second electrode layer into the second electrode 16, the second electrode 16 is more easily electrically connected to the first isolation portion 71 and / or the third isolation portion 73.

[0197] In some possible implementations, the present application further provides another display panel, which includes an array substrate 1, a pixel group, and electrode wiring.

[0198] The pixel group is located on one side of the array substrate 1; the electrode routing is located on the side of the pixel group away from the array substrate 1, at least part of the electrode routing includes a first touch electrode 8 and a second touch electrode 9, and the orthographic projections of at least part of the first touch electrodes 8 and / or at least part of the second touch electrodes 9 on the array substrate surround the orthographic projection of the pixel group on the array substrate.

[0199] One of the first touch electrode and the second touch electrode is configured to receive a touch driving signal, and the other of the first touch electrode and the second touch electrode is configured to output a touch sensing signal.

[0200] The pixel group includes at least one light-emitting sub-pixel 11, and the light-emitting sub-pixel 11 includes a red light-emitting sub-pixel, a blue light-emitting sub-pixel, or a green light-emitting sub-pixel. For example, Figure 2 A pixel group includes a red light-emitting sub-pixel, a blue light-emitting sub-pixel, and a green light-emitting sub-pixel.

[0201] This embodiment enables mutual capacitive touch control of the display panel through the first touch electrodes 8 and the second touch electrodes 9, making it easier to achieve the goal of a thinner and lighter display panel. By arranging the orthographic projections of at least a portion of the first touch electrodes 8 and / or at least a portion of the second touch electrodes 9 on the array substrate to surround the orthographic projections of the pixel groups on the array substrate, the first touch trace segments 81 and / or at least a portion of the second touch trace segments 91 can surround the pixel groups, with a pixel group as the minimum division unit.

[0202] In summary, in the present application, multiple isolation units 7 and first touch electrodes 8 and second touch electrodes 9 are provided on one side of the array substrate 1. This eliminates the need to reuse the isolation units 7, and mutual capacitive touch control of the display panel can be achieved through the first touch electrodes 8 and the second touch electrodes 9. This not only reduces the cost of the display panel, but also reduces the thickness of the display panel, thereby making it easier to achieve the goal of making the display panel thinner and lighter.

[0203] For some possible implementations, see Figure 1-43 , the present application also provides a method for preparing a display panel, the method comprising:

[0204] S10: providing an array substrate 1.

[0205] The array substrate 1 may include a substrate 101 and multiple driving units located on one side of the substrate 101. Each driving unit may include one or more semiconductor switching devices. The semiconductor switching devices may be formed by the cooperation of multiple film layers in the array substrate 1. For example, the semiconductor switching devices may be thin film transistors formed by the cooperation of multiple film layers.

[0206] S11: A conductive isolation layer 6 is formed on one side of the array substrate 1, and the conductive isolation layer 6 includes an isolation structure 23 and electrode traces arranged on the same layer. The isolation structure 23 is insulated from adjacent electrode traces, and at least part of the electrode traces includes a first touch electrode 8 and a second touch electrode 9; one of the first touch electrode 8 and the second touch electrode 9 is configured to receive a touch drive signal, and the other of the first touch electrode 8 and the second touch electrode 9 is configured to output a touch sensing signal.

[0207] When the isolation structure 23 is formed, a first touch electrode 8 and a second touch electrode 9 are formed. When the first touch electrode 8 is used to receive a touch drive signal, the second touch electrode 9 is used to output a touch sensing signal; when the second touch electrode 9 is used to receive a touch drive signal, the first touch electrode 8 is used to output a touch sensing signal. Thus, compared to the related art solution that requires at least four masks to set up a touch film layer, the number of masks for setting up the touch film layer can be reduced in this embodiment, thereby reducing the manufacturing cost of the display panel. In addition, compared to the related art solution in which the touch electrodes are located on different layers and a touch insulation layer 4 is required to separate the touch electrodes on different layers, resulting in a relatively thick display panel in the related art, the first touch electrode 8 and the second touch electrode 9 are set up on the same layer in this embodiment, thereby greatly reducing the thickness of the display panel.

[0208] Furthermore, compared to a low self-capacitance approach, in this embodiment, the first touch electrodes 8 and the second touch electrodes 9 form a mutual capacitance touch approach. The capacitance between the first touch electrodes 8 and the second touch electrodes 9 is greater, resulting in a better touch experience. Furthermore, the isolation structure 23 is not required for time-division multiplexing, making the display panel easier to drive and coordinate timing.

[0209] In some possible implementations, the present application further provides an electronic device including the display panel described herein. The electronic device may include a device with image processing capabilities, such as a server, a personal computer, or a laptop computer. Because the electronic device includes the display panel described herein, the electronic device has higher reliability.

[0210] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0211] The above embodiments merely illustrate several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make various modifications and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A display panel, characterized in that: The display panel includes: array substrate; An isolation structure and electrode traces are provided on the same layer on one side of the array substrate, wherein the isolation structure is insulated from adjacent electrode traces, and at least part of the electrode traces include a first touch electrode and a second touch electrode; One of the first touch electrode and the second touch electrode is configured to receive a touch driving signal, and the other of the first touch electrode and the second touch electrode is configured to output a touch sensing signal.

2. The display panel according to claim 1, wherein: The isolation structure includes a plurality of isolation units spaced apart, wherein adjacent isolation units are electrically connected along a first direction via first connecting traces; the first touch electrodes and the second touch electrodes are spaced apart, and orthographic projections of at least some of the first connecting traces on the array substrate are located between orthographic projections of the first touch electrodes and the second touch electrodes spaced apart on the array substrate; Preferably, along the second direction, at least some of the adjacent isolation units are electrically connected via a second connecting wire; Preferably, the orthographic projection of the second connecting wire on the array substrate is located between the orthographic projections of the first touch electrode and the second touch electrode on the array substrate that are spaced apart; Preferably, the first connecting line and the isolation unit are arranged on the same layer; Preferably, the second connecting line is provided on the same layer as the isolation unit; Preferably, along the second direction, the distance between the first touch electrode and the second touch electrode ranges from 5 μm to 10 μm; Preferably, along the second direction, the width of the orthographic projection of the first connecting trace on the array substrate is in a range of 3 μm to 10 μm; Preferably, along the first direction, the width of the orthographic projection of the second connecting trace on the array substrate is in a range of 3 μm to 10 μm.

3. The display panel according to claim 1, wherein: At least some of the first touch electrodes include first touch trace segments extending along a first direction, at least some of the first touch trace segments are arranged at intervals, and two adjacent first touch trace segments arranged at intervals along the first direction are electrically connected via a jumper trace, the jumper trace and the first touch trace segments are located in different film layers of the display panel, and an orthographic projection of the jumper trace on the array substrate at least partially overlaps with an orthographic projection of some of the second touch electrodes on the array substrate; and / or At least some of the second touch electrodes include second touch trace segments extending along a second direction, at least some of the second touch trace segments are arranged at intervals, and two adjacent second touch trace segments arranged at intervals along the second direction are electrically connected via a jumper trace, the jumper trace and the second touch trace segments are located in different film layers of the display panel, an orthographic projection of the jumper trace on the array substrate at least partially overlaps with an orthographic projection of some of the first touch electrodes on the array substrate, and the second direction intersects the first direction; Preferably, at least part of the first touch electrodes include a third touch trace segment extending along the second direction, and the third touch trace segment is electrically connected to the first touch trace segment; Preferably, along the second direction, the width of the orthographic projection of the first touch sensing trace segment on the array substrate is in a range of 5 μm to 15 μm; Preferably, the isolation structure includes a plurality of isolation units arranged at intervals, and a minimum distance between an orthographic projection of a side of the first touch trace segment close to the isolation unit on the array substrate and an orthographic projection of the isolation unit on the array substrate is 10 μm-30 μm; Preferably, along the first direction, the width of the orthographic projection of the second touch sensing trace segment on the array substrate is in a range of 5 μm to 15 μm; Preferably, the isolation structure includes a plurality of isolation units arranged at intervals, and a minimum distance between an orthographic projection of a side of the second touch trace segment close to the isolation unit on the array substrate and an orthographic projection of the isolation unit on the array substrate is 10 μm-30 μm; Preferably, the second direction is perpendicular to the first direction.

4. The display panel according to claim 1, wherein: The isolation structure includes a plurality of isolation units arranged at intervals, at least some of the adjacent isolation units are electrically connected along a first direction via jumper traces, at least some of the first touch electrodes include third touch trace segments extending along a second direction, the jumper traces and the isolation units are located in different film layers in the display panel, and an orthographic projection of the third touch trace segment on the array substrate at least partially overlaps with an orthographic projection of some of the jumper traces on the array substrate; and / or At least some of the first touch electrodes include third touch trace segments extending along the second direction, at least some of the third touch trace segments are spaced apart, and two adjacent third touch trace segments spaced apart along the second direction are electrically connected via a jumper trace; at least some of the adjacent isolation units along the first direction are electrically connected via a first connecting trace, the jumper trace and the third touch trace segments are located in different film layers of the display panel, and an orthographic projection of the jumper trace on the array substrate at least partially overlaps with an orthographic projection of some of the first connecting traces on the array substrate; Preferably, the display panel further includes a third connecting wire extending along the second direction, wherein the third connecting wire is electrically connected to the isolation units arranged along the second direction; Preferably, along the first direction, the width of the orthographic projection of the third touch sensing trace segment on the array substrate is in a range of 5 μm to 15 μm; Preferably, a minimum distance between an orthographic projection of a side of the third touch sensing trace segment close to the isolation unit on the array substrate and an orthographic projection of the isolation unit on the array substrate is 10 μm-30 μm.

5. The display panel according to claim 1, wherein: The isolation structure includes a plurality of isolation units arranged at intervals, at least some of the adjacent isolation units are electrically connected along a first direction via jumper traces, at least some of the second touch electrodes include second touch trace segments extending along a second direction, the jumper traces and the isolation units are located in different film layers in the display panel, and an orthographic projection of the second touch trace segments on the array substrate at least partially overlaps with an orthographic projection of the jumper trace on the array substrate; and / or At least some of the second touch electrodes include second touch trace segments extending along the second direction, at least some of the second touch trace segments are arranged at intervals, and two adjacent second touch trace segments arranged at intervals along the second direction are electrically connected via a jumper trace; Along a first direction, at least some of the adjacent isolation units are electrically connected via a first connecting wire, the jumper wire and the second touch sensing wire segment are located in different film layers of the display panel, and an orthographic projection of the jumper wire on the array substrate at least partially overlaps with an orthographic projection of the first connecting wire on the array substrate; Preferably, at least part of the second touch electrodes include a fourth touch trace segment extending along the first direction, and the fourth touch trace segment is electrically connected to the second touch trace segment; Preferably, along the second direction, the width of the orthographic projection of the fourth touch trace segment on the array substrate is in a range of 5 μm to 15 μm; Preferably, a minimum distance between an orthographic projection of a side of the fourth touch trace segment close to the isolation unit on the array substrate and an orthographic projection of the isolation unit on the array substrate is 10 μm-30 μm.

6. The display panel according to claim 1, wherein: At least part of the first touch electrodes include first touch trace segments extending along a first direction. Along the first direction, a distance between at least part of the first touch trace segments and the second touch electrodes ranges from 20 μm to 50 μm.

7. The display panel according to claim 1, wherein: The first touch electrodes and the second touch electrodes are arranged alternately; Preferably, the first touch electrode includes a plurality of first touch sub-electrodes, the second touch electrode includes a plurality of second touch sub-electrodes, and the first touch sub-electrodes and the second touch sub-electrodes are engaged with each other; Preferably, the orthographic projections of the first touch electrodes and / or the second touch electrodes on the array substrate are in a mesh structure.

8. The display panel according to claim 1, wherein: The display panel further includes a pixel group located on one side of the array substrate, and orthographic projections of at least part of the first touch electrodes and / or at least part of the second touch electrodes on the array substrate surround the orthographic projection of the pixel group on the array substrate; Preferably, the pixel group includes at least one light-emitting sub-pixel; Preferably, the light-emitting sub-pixel unit includes red light-emitting sub-pixels and / or blue light-emitting sub-pixels and / or green light-emitting sub-pixels.

9. The display panel according to any one of claims 3 to 5, characterized in that: The array substrate includes a substrate and a conductive layer located on one side of the substrate; The jumper wire is located in the conductive layer, and / or the display panel further includes a first electrode layer located on one side of the array substrate, and the jumper wire is located in the first electrode layer.

10. The display panel according to claim 4 or 5, characterized in that: The display panel further includes a first electrode layer, a light-emitting functional layer, and a second electrode layer located on one side of the array substrate and stacked in sequence in a direction away from the array substrate, wherein the second electrode layer is electrically connected to the isolation unit; Preferably, the isolation structure encloses an isolation opening, the first electrode layer includes a first electrode at least partially located within the isolation opening, the light-emitting functional layer includes a light-emitting portion located within the isolation opening, and the second electrode layer includes a second electrode at least partially located within the isolation opening, and the second electrode is electrically connected to the isolation unit; Preferably, the display panel further comprises a pixel defining layer located on one side of the array substrate, the conductive isolation layer is located on a side of the pixel defining layer away from the array substrate, the pixel defining layer comprises a pixel opening exposing at least a portion of the first electrode, the orthographic projection of the isolation unit on the array substrate is located between the orthographic projections of two adjacent pixel openings on the array substrate, and the orthographic projection of the pixel opening on the array substrate is located within the orthographic projection of the isolation opening on the array substrate; Preferably, the display panel further comprises a first encapsulation layer located on a side of the second electrode layer away from the array substrate, the first encapsulation layer comprising a plurality of encapsulation units arranged at intervals, the encapsulation units extending from a side of the isolation unit to a side of the isolation unit away from the array substrate; Preferably, the first encapsulation layer is an inorganic encapsulation layer; Preferably, the first electrode comprises an anode; Preferably, the second electrode comprises a cathode.

11. The display panel according to claim 10, wherein: The isolation unit includes a first isolation portion and a second isolation portion stacked in sequence in a direction away from the array substrate, wherein an orthographic projection of the first isolation portion on the array substrate is located within an orthographic projection of the second isolation portion on the array substrate.

12. The display panel according to claim 11, wherein: The second electrode is electrically connected to the first isolation portion; and / or the isolation unit further includes a third isolation portion located on a side of the first isolation portion facing the array substrate, and the second electrode is electrically connected to the third isolation portion; Preferably, the material of the third isolation portion includes molybdenum metal; and / or the material of the first isolation portion includes aluminum metal; and / or the material of the second isolation portion includes a titanium metal layer.

13. A display panel, characterized in that: The display panel includes: array substrate; a pixel group located on one side of the array substrate; Electrode traces located on a side of the pixel group away from the array substrate, at least part of the electrode traces including first touch electrodes and second touch electrodes, orthographic projections of at least part of the first touch traces and / or at least part of the second touch traces on the array substrate surrounding the orthographic projection of the pixel group on the array substrate; One of the first touch electrode and the second touch electrode is configured to receive a touch driving signal, and the other of the first touch electrode and the second touch electrode is configured to output a touch sensing signal.

14. A method for preparing a display panel, characterized in that: The method comprises: providing an array substrate; An isolation structure and electrode traces are formed on one side of the array substrate and are arranged in the same layer, wherein the isolation structure is insulated from adjacent electrode traces, and at least part of the electrode traces includes a first touch electrode and a second touch electrode; One of the first touch electrode and the second touch electrode is configured to receive a touch driving signal, and the other of the first touch electrode and the second touch electrode is configured to output a touch sensing signal.

15. An electronic device, characterized in that: The electronic device comprises the display panel according to any one of claims 1 to 13.

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