Double-read verification method and device for OTP (One Time Programmable)

Abstract

The invention relates to an OTP double-read verification method and device, and the method comprises the steps: generating a power-on reset signal based on a power voltage, carrying out the signal response, and obtaining a periodic reading signal and a verification control signal; carrying out OTP primary reading on the OTP read-write system according to the first period of the periodic read signal and the verification control signal, and storing the OTP read-write system in a static random access memory to obtain reference data; performing OTP secondary reading according to a second period of the periodic reading signal in combination with the verification control signal, and comparing with the reference data to obtain a verification result; and carrying out closed-loop detection on the verification result to obtain an OTP verification result. According to the invention, the risk of data misreading caused by transient fluctuation of the power supply can be effectively avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of OTP verification, and in particular to an OTP dual-reading verification method and device. Background Art

[0002] One-time programmable memory (OTP) is the core carrier for firmware storage and security key configuration. The reliability of its data reading directly affects the overall stability of the system. The current mainstream single-read solution has systemic defects in the operation process: the traditional method directly reads the storage unit during the power-on reset phase, but transient fluctuations during the power supply voltage ramp-up process can easily cause data misjudgment; the redundant design or verification algorithm adopted to improve fault tolerance often requires a significant increase in hardware resource overhead, making it difficult for cost-sensitive devices to bear; at the same time, the asynchronous clock control mechanism is prone to triggering sampling deviations during the phase where the timing is unstable, resulting in systematic data distortion. More seriously, the existing solution lacks an effective on-chip real-time error correction mechanism. When an error is detected, it relies on the intervention of an external processing unit, resulting in error recovery delays far exceeding the timeliness requirements of safety-critical scenarios. Summary of the Invention

[0003] The main purpose of the present invention is to provide an OTP dual-read verification method and device, which can effectively avoid the risk of data misreading caused by transient power fluctuations and significantly improve the integrity protection capability of stored information.

[0004] To achieve the above object, the present invention provides an OTP dual-read verification method, comprising: Generate a power-on reset signal based on the power supply voltage, perform a signal response, and obtain a periodic read signal and a verification control signal; Performing an OTP read once on the OTP read / write system according to the first cycle of the periodic read signal and the verification control signal, and storing the OTP in a static random access memory to obtain reference data; According to the second cycle of the periodic read signal, the OTP is read again in combination with the verification control signal, and compared with the reference data to obtain a verification result; Perform closed-loop detection on the verification result to obtain an OTP verification result.

[0005] Furthermore, the generating of a power-on reset signal based on the power supply voltage and performing a signal response to obtain a periodic read signal and a verification control signal includes: Performing voltage detection and threshold comparison on the power supply voltage to generate a power-on reset signal; Acquire a periodic read signal generated by the OTP read / write system based on the power-on reset signal; Perform OTP control activation based on the power-on reset signal to obtain an OTP read-write control enable signal; The OTP read-write control enable signal is state-machine converted according to the periodic read signal to obtain a verification control signal.

[0006] Furthermore, the OTP read / write system is subjected to an OTP read once according to the first cycle of the periodic read signal and the verification control signal, and stored in a static random access memory to obtain reference data, including: Performing high-level interval detection on the first cycle to obtain an operation window signal; Reading the level state of the verification control signal according to the one-time operation window signal to obtain a first level state; According to the first level state, the address pointer of the OTP read-write system is incremented and triggered to obtain a first read address; Perform storage array selection on the OTP read / write system according to the first read address to obtain a target storage cell row; Performing bit-selection conduction reading on the target memory cell row and outputting first signal data; The first signal data is input into the static random access memory for latching processing to obtain the reference data.

[0007] Furthermore, the step of inputting the first signal data into the static random access memory for latching to obtain the reference data includes: Performing switch control signal generation on the check control signal to obtain a bit selection control signal; Performing differential conversion on the first signal data to obtain an in-phase data signal and an inverted data signal; Performing a first input path gate drive on the in-phase data signal according to the bit selection control signal to obtain a first node voltage; Performing a second input path gate drive on the inverted data signal according to the bit selection control signal to obtain a second node voltage; performing cross-coupling inverter latching on the first node voltage and the second node voltage to obtain a stable node voltage pair; Output buffering is performed on the stable node voltage pair to obtain reference data.

[0008] Furthermore, the second period of the periodic reading signal is combined with the verification control signal to perform an OTP secondary reading, and compare it with the reference data to obtain a verification result, including: Identifying a high-level interval of the second period to obtain a secondary operation window signal; Performing state switching detection on the verification control signal according to the secondary operation window signal to obtain a low-level state signal; performing output path multiplexing control on the static random access memory and activating a readback path according to the low-level state signal to extract the reference data; Triggering the OTP read / write system to increment the address pointer according to the secondary operation window signal to obtain a second read address; Performing target unit reading on the OTP read / write system according to the second read address to obtain second signal data; Perform a real-time XOR comparison on the second signal data and the reference data to obtain the verification result.

[0009] Furthermore, performing a real-time XOR comparison on the second signal data and the reference data to obtain the verification result includes: performing signal buffering on the reference data to obtain an enhanced driving reference signal; performing level conversion on the second signal data to obtain a full-swing data signal; Performing an XOR logic gate operation on the enhanced driving reference signal and the full-swing data signal to obtain original verification data; An edge-triggered check is performed on the original check data according to the periodic read signal to obtain the check result.

[0010] Furthermore, performing closed-loop detection on the verification result to obtain an OTP test result includes: Performing status analysis on the verification result to obtain a verification status identification signal; Performing decision branch identification on the verification status identification signal to obtain an operation mode; When the operation mode is data output mode: Perform tri-state gating activation on the OTP read / write system according to the verification status identification signal to obtain a data output channel; enhancing the driving capability of the second signal data through the data output channel to obtain bus-compatible data; The bus compatible data is packaged and outputted according to the protocol to obtain the OTP test result.

[0011] Furthermore, when the operation mode is the error handling trigger mode: Performing reset pulse width modulation on the verification status identification signal to obtain a reset control pulse; Asynchronously clearing the address pointer according to the reset control pulse to obtain a reset addressing state; Discharging node charges of the static random access memory according to the reset control pulse to obtain a residual data clearing signal; Resetting the signal generation state of the reset control pulse according to the reset addressing state and the residual data clearing signal to obtain a reset signal generation state; reinitialize the check control signal according to the reset signal generation state to obtain a restart check signal; The dual-read verification process is restarted according to the restart verification signal to obtain restart process information.

[0012] The present invention further provides an OTP dual-reading verification device, which is applied to any of the above-mentioned OTP dual-reading verification methods, comprising: A power-on reset and address generation module, configured to generate a power-on reset signal based on a power supply voltage, perform a signal response, and obtain a periodic read signal and a verification control signal; A reading module, wherein the reading module is used to read the OTP once from the OTP reading and writing system according to the first cycle of the periodic reading signal and the verification control signal, and store the OTP in a static random access memory to obtain reference data; a comparison module configured to perform a second OTP read according to the second period of the periodic read signal in combination with the verification control signal, and compare the read result with the reference data to obtain a verification result; The processing module is used to perform closed-loop detection on the verification result to obtain an OTP verification result.

[0013] The present invention provides an OTP dual-reading verification method and device, which has the following beneficial effects: By coordinating the timing of periodic read signals and verification control signals, a baseline data is established during the first read phase and instantaneously latched in the static random access memory (SRAM). Combined with a real-time comparison structure during the second read, this effectively mitigates the risk of data misreading caused by power supply transients, significantly improving the integrity of critical stored information. By innovatively reusing the physical input / output paths of the SRAM, the baseline data establishment and verification readback functions are integrated into the same hardware unit. This enables dual-channel verification while eliminating the storage resource consumption of traditional triple-module redundancy, providing a resource-efficient and reliable solution for cost-sensitive devices. A synchronous timing control system, based on periodic read signals, precisely triggers data sampling points during the second read window, completely avoiding asynchronous clock setup conflicts and ensuring timing consistency between the storage unit and the verification logic. If the verification result is abnormal, a closed-loop detection mechanism automatically triggers an address pointer reset and a memory state refresh. This reset of the signal generation state enables self-contained error recovery, achieving millisecond-level error correction response at the hardware level. This dual-cycle check architecture reduces physical resource usage while enhancing timing robustness, meeting the stringent requirements of zero-fault tolerance scenarios in functional safety standards and providing a storage access paradigm that is both economical and secure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 The present invention provides a flow chart of a dual-read verification method for an OTP; Figure 2 The present invention provides a structural diagram of an OTP read-write control system in an OTP dual-read verification device; Figure 3 This is a circuit diagram of a static random access memory used in an embodiment of the present invention; Figure 4 Schematic diagram of word selection and bit selection control in an embodiment of the present invention; Figure 5 It is a signal timing diagram of an embodiment of the present invention; Figure 6 The present invention provides a structural diagram of an OTP dual-reading verification device.

[0015] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0016] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0017] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0018] Reference Figure 1-5 As shown, the present invention provides an OTP dual-read verification method, comprising: Step S1: generating a power-on reset signal based on the power supply voltage, performing a signal response, and obtaining a periodic read signal and a verification control signal; Step S1: performing an OTP read operation on the OTP read / write system according to the first cycle of the periodic read signal and the check control signal, and storing the OTP data in the static random access memory to obtain reference data; Step S3: performing a second OTP read according to the second cycle of the periodic reading signal in combination with the verification control signal, and comparing the result with the reference data to obtain a verification result; Step S4: Perform closed-loop detection on the verification result to obtain the OTP test result.

[0019] Based on the above steps, the detailed process is as follows: Step S1: Based on power supply voltage detection, the power-on reset signal module generates a power-on reset signal (POR_OK), triggering activation of the OTP read / write control system. A periodic read signal (READ) is generated through clock division and pulse-width modulation. Its fixed period and high-level pulse width match the access timing requirements of the OTP memory cell array. A synchronously generated check control signal (READ_CHECK) implements level switching control through a state machine transition mechanism: it outputs a high level during the first period of the periodic read signal (READ) and switches to a low level in subsequent periods. The signal coordination relationship is that the rising edge of the periodic read signal (READ) drives the address counter, and the level state of the check control signal (READ_CHECK) controls the path mode switching of the static random access memory (SRAM).

[0020] Step S2: During the first high cycle of the periodic read signal (READ), the POR_OK signal is high, activating the addressing operation of the OTP read / write system. When either the POR_OK signal or the CHECK_QN signal is low, RSTN is low, resetting the OTP read / write control system. The address pointer generation module outputs the current addressing location and locates the target memory cell array using the word select signal (WL) for word select decoding and the bit select signal (BL) for bit select control. Switch S1 is opened, transmitting the first data signal read via the static random access memory (SRAM) input path. The check control signal (READ_CHECK) controls switch S1, and the bit select control signal (BL) turns on the NM1 / NM4 input transistors, writing the data into the cross-coupled inverter latch structure. The inverter pairs formed by PM1 / NM2 and PM2 / NM3 use a positive feedback loop to stably store the data at the L1 / L2 nodes, forming the baseline data that is maintained until the next operation phase.

[0021] Step S3: During the second high-level cycle of the periodic read signal (READ), the check control signal (READ_CHECK) switches to a low-level state. Switch S1 is disconnected, and the bit select control signal (BL) turns on the NM1 / NM4 input transistors, multiplexing the in-phase terminal (INP_SRAM) and the inverting terminal (INN_SRAM). , so that the reference data is read back to the comparison unit. The OTP read-write system performs a second read on the same storage unit address and outputs a second data signal. Figure 3 The XOR1 of the reference data is compared with the second data signal in real time to generate the original verification level. The synchronous sampling clock signal (CLK_CK) is triggered before the falling edge of the periodic read signal (READ) to synchronize the sampling pulse ( Figure 5 The check result is captured and latched into a digital signal: a low level is output when the data is consistent and a high level is output when it is inconsistent. The check result signal (CHECK) is converted into a check status indicator through decision logic.

[0022] Step S4: The verification status identification signal drives the dual-mode decision branch: when the identification signal indicates that the data is consistent, the three-state gate circuit is activated to conduct the data output channel. After the second data signal is level-converted and driven, it is encapsulated in the frame header according to the AMBA bus protocol, and the OTP verification result is generated and output to the system bus. When the identification signal indicates that the data is inconsistent, a 200ns low-level reset control signal (RSTN) is generated. This pulse synchronously triggers three operations: asynchronous clearing of the address counter, charge discharge of the static random access memory (SRAM) node ( Figure 3The NM5 transistor is turned on, forcing L2 to ground. The timing control state machine is reset. After the reset, the signal generation module restarts the process of generating the periodic read signal (READ) and the check control signal (READ_CHECK), and returns to step S2 to perform baseline data reconstruction, forming a self-correction closed loop.

[0023] Among them, PM1 / NM2 and PM2 / NM3 (cross-coupled inverters): PM1 / NM2 and PM2 / NM3 constitute the data latch unit of static random access memory (SRAM): PM1 and NM2 form the first inverter, with the input connected to the L1 node and the output connected to the L2 node.

[0024] PM2 and NM3 form the second inverter, with the input connected to the L2 node and the output connected to the L1 node.

[0025] Cross-coupling forms a positive feedback loop (L1-Inverter 2-L2-Inverter 1-L1) to achieve stable data latching. When the input path is activated, the differential signal between the input signal's positive terminal (INP_SRAM) and the input signal's negative terminal (INN_SRAM) drives the node voltage, completing data write and retention while the check control signal (READ_CHECK) is high.

[0026] NM1 / NM4 (input pathway gated tube): NM1 and NM4 are the input path control switches of static random access memory (SRAM): NM1: Connects the non-inverting end of the input signal (INP_SRAM) and the L1 node, and is directly controlled by the bit select signal (BL).

[0027] NM4: Connects the inverting terminal of the input signal (INN_SRAM) to the L2 node and is directly controlled by the bit select signal (BL).

[0028] When the check control signal (READ_CHECK) is high, the bit select signal (BL) turns on NM1 / NM4, allowing the differential input signal to be written into the latch unit. This design achieves hardware-level path isolation through cascaded MOS transistors, ensuring no crosstalk during data writing.

[0029] NM5 (reset bleed pipe): NM5 is the charge discharge control transistor of the static random access memory (SRAM), and its gate is connected to the reset signal (RST). When the verification fails and the reset control signal (RSTN) is generated: The RSTN low level is converted into a high level signal (RST) through inverter INV1.

[0030] The high level of RST drives NM5 to turn on.

[0031] The L2 node is forced to ground, the L1 node voltage is pulled high, and the output buffer INV2 outputs a low level. This enables millisecond-level rapid discharge of stored charge, eliminating interference from residual data on the restart process.

[0032] The L1 node is the first node (Node L1): Connection Location: The input of inverter 1 (PM1 / NM2), the output of inverter 2 (PM2 / NM3), and the input of the output buffer (INV2) directly determine the output value (OUT_SRAM) through the voltage state.

[0033] The L2 node is the second node (Node L2): Connection Location: The output end of inverter 1 (PM1 / NM2), the input end of inverter 2 (PM2 / NM3), and the drain end of reset tube (NM5) always have a voltage state complementary to the first node (L1).

[0034] The present invention provides an OTP dual-read verification method. Through the timing coordination mechanism of periodic read signals and verification control signals, the method establishes reference data during the first read phase and achieves instantaneous latching through static random access memory. Combined with the real-time comparison structure of the second read, it effectively avoids the risk of data misreading caused by transient power supply fluctuations and significantly improves the integrity protection capability of critical storage information. The method innovatively reuses the input / output physical paths of the static random access memory, integrating the reference data establishment and verification readback functions into the same hardware unit. While achieving dual-channel verification functions, it eliminates the storage resource consumption of traditional triple-module redundancy and provides a resource-efficient and reliable solution for cost-sensitive devices. The synchronous timing control system constructed based on the periodic read signal accurately triggers the data sampling point in the second read window, completely avoiding the problem of asynchronous clock establishment time conflicts and ensuring the timing consistency between the storage cell array and the verification logic. When the verification result is abnormal, the closed-loop detection mechanism automatically triggers the address pointer reset and the memory state refresh. By resetting the signal generation state, self-contained error recovery is achieved, and millisecond-level error correction response is completed at the hardware level. This dual-cycle check architecture reduces physical resource usage while enhancing timing robustness, meeting the stringent requirements of zero-fault tolerance scenarios in functional safety standards and providing a storage access paradigm that is both economical and secure.

[0035] Reference Figure 2-5 As shown, in one embodiment, a power-on reset signal is generated based on a power supply voltage, and a signal response is performed to obtain a periodic read signal and a verification control signal, including: The power supply voltage is monitored in real time by a voltage detection circuit consisting of a voltage-divider sampling network and a hysteresis comparator. The sampling network captures the instantaneous power supply value and outputs a proportional voltage to the comparator's non-inverting input. A reference voltage provides a threshold voltage connected to the inverting input. When the power supply voltage continues to rise and exceeds the preset threshold, the hysteresis comparator output flips, generating a high-level power-on reset signal (POR_OK). This signal's trip point strictly corresponds to the power supply's stable state, eliminating ringing artifacts during voltage ramps. The power-on reset signal serves as a system startup signal, directly activating subsequent control modules.

[0036] The power-on reset signal (POR_OK) is connected to the enable port of the OTP read / write control system, triggering the internal state machine to switch from sleep mode to active mode. This state machine outputs the OTP read / write control enable signal. A high level unlocks the clock gating circuit and address generation unit. The control enable signal acts as a hardware-level switch, freezing all read / write operations when low and releasing the divider and pulse-width modulation modules when high. This design ensures that OTP access is initiated only after the power supply is fully stable, mitigating the risk of false triggering at voltage thresholds.

[0037] The OTP read / write control enable signal activates the divider chain, dividing the system master clock by an integer. This generates a square wave signal with a fixed 50% duty cycle. The period of this square wave is fixed at 100ns, and the high level lasts for 50ns, forming a periodic read signal (READ). The rising edge of the signal accurately triggers the address counter to increment, and the high level window ensures stable data transmission and strict matching. Figure 5 Timing specifications are shown.

[0038] The periodic read signal (READ) drives the finite state machine transition.

[0039] The state machine output directly controls the path mode of the static random access memory (SRAM): when the high level is high, the input path gating tube (NM1 / NM4 tube) is activated and the output path multiplexing is enabled (enable Figure 3 The OUT_SRAM port in the memory is connected to the OUT_SRAM port in the memory. This prevents output signal inversion from affecting the internal L1 and L2 nodes through the output buffer (INV2). During the store phase, data flows from the inverting port (INN_SRAM) and the non-inverting port (INP_SRAM) to the L1 and L2 nodes. During the verify phase, the data latched in the L1 and L2 nodes is inverted and written to the inverting port (INN_SRAM) and the non-inverting port (INP_SRAM), respectively. This conversion mechanism enables seamless switching between the store and verify phases.

[0040] This embodiment generates a power-on reset signal by comparing voltage detection with a threshold value. This accurately identifies the stable state of the power supply and eliminates ringing interference during the power ramp-up phase, thereby ensuring the reliability of the system startup timing. The OTP control module is activated based on the power-on reset signal, generating a read / write control enable signal to ensure that OTP access operations are only performed after the power supply stabilizes, thereby avoiding the risk of false triggering at critical voltages. By periodically reading the signal to drive the state machine transition, the dual-mode verification control signal is automatically output, achieving seamless switching between the storage phase and the verification phase, thereby providing a precise timing control foundation for static random access memory path mode switching.

[0041] Reference Figure 2-5 As shown, in one embodiment, the OTP read / write system performs an OTP read once according to the first cycle of the periodic read signal and the check control signal, and stores the OTP in a static random access memory (SRAM) to obtain the benchmark data, including: The first read cycle of the periodic read signal (READ) is accurately identified by activating the OTP read circuit at a high level. This detection process utilizes hysteresis voltage characteristics to effectively eliminate the risk of false triggering caused by signal edge jitter. The generated one-shot window signal strictly defines the valid period for the first read operation, ensuring that the operation window fully matches the electrical characteristics and timing requirements of the memory cell. The high state of the one-shot window signal serves as the enable reference for subsequent operations, providing time boundary constraints for the entire read process.

[0042] During the high-level duration of the single-operation window signal, the check control signal (READ_CHECK) controls control switch S1. It outputs a stable first-level state: a high level indicates the initial activation of the read mode, while a low level indicates an abnormal state. This state signal directly drives the enable control of the addressing module, establishing the operation mode for memory array access. The level reading process is strictly synchronized with the window signal, and the risk of metastability is eliminated through the setup time margin design.

[0043] The high-level output of the first level state enables the trigger function of the address pointer generation module. The address counter responds to the trigger signal on the rising edge of the periodic read signal (READ) and performs a step-up operation. The counter uses ordinary binary coding or Gray code encoding scheme to output the first read address in binary format. The address bit width fully matches the physical structure of the memory array and supports from 0 to 2 N-1 The address generation process is subject to both window signal and level constraints, ensuring that each increment is executed only within the valid operation window. The generated first read address is transmitted to the word select decoder via a low-latency bus.

[0044] The first read address is input to the word select decoding logic unit. The decoding process prioritizes the most significant address bit (MSB) and generates a word select signal (WL) corresponding to the target memory cell row. The activated word select signal turns on the access transistors (RTSs) in the specific row of the memory array, connecting the stored charge to the bit line. Decoding latency is strictly controlled within 3ns, ensuring that the row selection operation is completed early in the high-level window of the periodic read signal (READ).

[0045] The bit select decoder generates a bit select signal (BL) based on the least significant bit (LSB) of the first read address. This bit select signal turns on the column select transistor of the target memory cell, outputting the bit line charge to the sense amplifier. The sense amplifier uses a differential structure to convert the microcurrent signal into a full-swing 1.8V voltage. The output signal is shaped by the driver circuit to eliminate ringing overshoot, resulting in a stable first signal data. The bit select read operation covers all columns of the memory array and supports M-bit parallel data output.

[0046] The first signal data is transmitted to the static random access memory (SRAM) via the differential line pair (INP_SRAM / INN_SRAM). The check control signal (READ_CHECK) controls switch S1, and the bit select control signal (BL) turns on the NM1 / NM4 input transistors. After data is loaded into the L1 / L2 nodes, the cross-coupled inverters latch the charge through a positive feedback loop: the PM1 / NM2 inverters maintain the L1 node voltage level, and the PM2 / NM3 inverters maintain the L2 node voltage level. The latching process is completed before the periodic read signal (READ) reaches a high level. The node voltage is maintained in a stable state by the output buffer, forming a reference data that persists until the check phase.

[0047] This embodiment ensures that address pointer increments are executed only during valid periods by reading the level of the verification control signal through an operation window signal, thereby eliminating the risk of addressing deviation caused by asynchronous timing. The coordinated operation of address pointer increment and memory array word select decoding enables precise row and column positioning of the target memory cell, thus overcoming data distortion caused by charge crosstalk between adjacent cells. High-quality signal data is output through a bit-select conduction read mechanism, combined with the differential latch structure of the static random access memory to form zero-attenuation benchmark data, enabling a stable and reliable comparison benchmark in the secondary verification phase.

[0048] Reference Figure 2-5 As shown, in one embodiment, the first signal data is input into a static random access memory (SRAM) for latching to obtain the reference data, including: The check control signal (READ_CHECK) is input to the switch control logic circuit, which controls the signal path for signal conditioning and driver enhancement. This circuit utilizes a three-stage architecture for reliable conversion. The primary level shifter adapts the input signal's voltage amplitude to the MOS transistor drive requirements, using a hysteresis comparison mechanism to ensure output stability during power supply fluctuations. The secondary filter suppresses high-frequency noise interference and employs an RC low-pass network to attenuate power supply ripple. The final push-pull amplifier enhances current drive capability to meet the requirements of multiple parallel loads. When the check control signal (READ_CHECK) is high, a high bit select control signal (BL) is output after a reasonable delay. Its rise time is optimized to match the memory cell response characteristics. When the check control signal (READ_CHECK) transitions low, a preset low static voltage is output. Tolerance compensation is incorporated into the signal generation process, and the voltage threshold settings include reasonable margins to ensure functional correctness despite process corner variations. The bit select control signal is connected to the static random access memory (SRAM) gate transistor array via matched impedance transmission lines. The transmission path layout mitigates crosstalk risks.

[0049] The first signal data input is processed by the fully differential conversion module. This module is based on a folded cascode operational amplifier structure. The non-inverting input receives a single-ended input signal through a precision resistor network, and the inverting input is connected to a high-stability bandgap reference voltage source. The conversion mechanism dynamically calibrates the output operating point through an active common-mode feedback loop to eliminate DC offset caused by process variations. The in-phase data signal maintains the phase and amplitude characteristics of the original signal, while the inverted data signal generates a precise complementary voltage waveform. The swing range of both is strictly constrained within the device operating range. The differential signal output stage uses a symmetrical drive structure, and the transmission path implements an equal-length wiring design to ensure transmission delay matching between the two signals. Common-mode rejection performance is enhanced by the circuit topology, effectively suppressing power supply noise and substrate coupling interference.

[0050] The high state of the bit select control signal (BL) turns on the NMOS gate transistor in the first input path. The in-phase data signal is transmitted via a source-follower architecture consisting of a gate drive amplifier and an active load current mirror, enabling high-precision voltage transmission. During the gate transistor's on-time, the signal is loaded via a low-impedance path to the L1 node of the static random-access memory (SRAM). A precharge circuit neutralizes the node's parasitic capacitance, and a ramp control technique is used during the voltage buildup process to optimize transient response. The final value of the first node voltage is stabilized within the target range via a negative feedback mechanism, with a deviation range that meets the input sensitivity requirements of the cross-coupled inverter. Temperature compatibility of the driver circuit is achieved through adaptive bias current adjustment, covering the full temperature range specified in the device data sheet.

[0051] A high level on the bit select control signal (BL) synchronously activates the gate driver circuitry of the second input path. The inverted data signal is loaded into the L2 node of the static random access memory (SRAM) via a mirror-symmetrical transmission architecture. Charge compensation technology is employed during the gate transistor's on-time to precisely offset switching transients by injecting an equal amount of reverse charge. The signal transmission path utilizes a cascode structure, maintaining a stable voltage gain near unity and keeping phase offset within a reasonable range. The voltage at the L2 node maintains a complementary relationship with the L1 node, and the differential voltage swing covers the entire operating range of the memory cell. Dynamic substrate biasing technology adjusts the backgate potential in real time, significantly suppressing the effects of subthreshold leakage current. A slope control mechanism is incorporated into the voltage buildup process to optimize signal edge characteristics and eliminate the risk of high-frequency oscillation. The voltage accuracy of the second node is maintained through closed-loop calibration, meeting the input tolerance requirements of the cross-coupled inverter.

[0052] Step 5: Perform cross-coupling inverter latching on the first node voltage and the second node voltage to obtain a stable node voltage pair.

[0053] The first and second nodes are connected to a cross-coupled inverter latch structure. Inverter 1 (PM1 / NM2) and inverter 2 (PM2 / NM3) form a positive feedback loop: Node 1 drives the input of Inverter 1 and is simultaneously connected to the output of Inverter 2; Node 2 drives the input of Inverter 2 and is simultaneously connected to the output of Inverter 1. The positive feedback coefficients are optimized to ensure that the voltages at Node 1 and Node 2 lock quickly within a reasonable time. The latching process enhances noise tolerance through the negative resistance effect, significantly improving the ability to suppress power supply fluctuations. Static power consumption is minimized during data retention, and charge retention time meets the requirements for a full verification cycle. Soft error immunity is achieved through circuit topology optimization, providing inherent immunity to interference such as particle bombardment, ultimately outputting a stable node voltage pair.

[0054] Stabilizing node voltages reconstructs signals driving three cascaded output buffers. The first-stage source follower provides a high input impedance interface, blocking interference from subsequent loads. The second-stage differential amplifier achieves precise voltage gain, compensating for process variations. The third-stage Class AB output stage enhances current drive capability to support capacitive bus loads. The buffer's frequency response is optimized with phase margin to eliminate ringing and overshoot. Reference data is reconstructed into rail-to-rail digital levels, and hysteresis is incorporated into the logic thresholds to enhance noise immunity. The output stage's quiescent current automatically drops to microamperes in the hold state, significantly optimizing power efficiency. Drive capability is tailored to standard bus load characteristics, ensuring signal integrity meets high-speed interface specifications. Reference data continues to be output until the secondary verification phase is complete.

[0055] This embodiment achieves reliable switching of static random access memory path modes through a precise generation mechanism of switch control signals, thereby time-sharing input and output functions within a single hardware unit, significantly reducing chip area overhead. Strictly complementary in-phase and anti-phase signals are generated through differential conversion technology, effectively suppressing common-mode noise interference, thereby ensuring signal integrity during the benchmark data establishment process. Through the synergistic effect of gated drive and cross-coupled inverters, the node voltage is locked at a stable dual operating point, thereby forming a benchmark data retention capability that is resistant to power supply fluctuations and temperature drift. Through impedance conversion and drive enhancement of the output buffer, a bus-compatible benchmark data signal is generated, thereby providing a high-reliability comparison benchmark for secondary verification.

[0056] Reference Figure 2-5 As shown, in one embodiment, according to the second cycle of the periodic read signal, the OTP is read twice in combination with the verification control signal, and compared with the reference data to obtain the verification result, including: The second high-level cycle of the periodic read signal (READ) is accurately identified by a timing detection circuit. This detection mechanism employs a window comparator structure to capture the complete 50ns high-level interval of the READ signal, from the rising edge to the falling edge. The identification process leverages the hysteresis characteristics of the Schmitt trigger to effectively eliminate the risk of false triggering caused by signal edge jitter. The generated secondary operation window signal is limited to the execution period of the second read operation, ensuring that the operation window precisely matches the electrical characteristics of the memory cell. The high-level state of the secondary operation window signal serves as the enabling reference for subsequent operations, providing clear time boundary constraints for the secondary read process and ensuring the timing reliability of data capture.

[0057] During the high-level duration of the secondary operation window signal, the state detection circuit determines the level state to identify the check result signal (CHECK). The detection circuit uses a bistable latch structure and triggers state sampling on the rising edge of the window signal. Directly read the physical level status of the check control signal (READ_CHECK): When READ_CHECK is stable and presents a low level, it is determined that the verification mode is activated; When a high level appears during the first read cycle, the switch (S1) is closed and the data is written into the static random access memory (SRAM).

[0058] The state switching detection process establishes a time margin design to eliminate the risk of metastability. The low-level state signal serves as the trigger reference for the channel multiplexing control and provides a mode identifier for the output channel activation of the static random access memory.

[0059] When verification mode is active, the path multiplexing control logic is driven to generate an output enable signal (OE). This signal activates the output path multiplexing switch of the SRAM, enabling the transmission path from the output buffer (INV2) to the data bus while simultaneously disabling the input path gate. The multiplexing control circuit utilizes a complementary switch design to eliminate charge injection effects during path switching. When the readback path is activated, the reference data stored in the cross-coupled inverters is output to the data bus via the SRAM output port (OUT_SRAM port). A timing synchronization mechanism is incorporated into the data extraction process to ensure stable transmission of the reference data within the secondary read window, providing reliable input for real-time comparison.

[0060] During the high-level period of the secondary operation window signal, the address pointer generation module triggers in response to the rising edge of the READ signal. The address counter uses a Gray code encoding mechanism and increments on each triggering edge. The counter outputs the second read address in binary format, with an address bit width that precisely matches the physical structure of the memory array. The address generation process is strictly constrained by the window signal, ensuring that addressing operations are performed only within the valid period. During this period, the check control signal (READ_CHECK) remains low, indicating that the system is in secondary read mode. The address pointer points to the same memory cell location as the initial read. The address transmission path utilizes a low-latency bus design.

[0061] The second read address is input to the memory array access interface. The word select decoder interprets the high-order bits of the address, activating the word select signal (WL) for the target cell row. The bit select decoder interprets the low-order bits and generates a bit select signal (BL) to activate the target column. The bit select control signal (BL) activates the NM1 / NM4 input transistors, multiplexing the positive-inverting terminal (INP_SRAM) and the negative-inverting terminal (INN_SRAM), allowing the reference data to be read back to the comparison cell.

[0062] The memory cell charge is converted into a voltage signal by a sense amplifier and then shaped into a full-swing digital level by a driver circuit. The read process is completed synchronously within the READ high-level window, with a data setup time margin exceeding the timing specification. The second signal data is output while the check control signal (READ_CHECK) remains low, ensuring that the SRAM is in output path multiplexing mode and preventing accidental writing of the currently read data.

[0063] The second signal data and the readback reference data are input in parallel to the XOR logic unit. This unit utilizes a current-mode logic architecture and performs real-time comparison within the READ high-level window: it outputs a low level when the data bits are identical and a high level when there are differences. A timing alignment circuit is incorporated into the comparison process to eliminate transmission path delay variations. The check result signal (CHECK) is latched as a stable output by the synchronous sampling clock (CLK_CK) before the falling edge of READ. During this time, the low state of the check control signal (READ_CHECK) maintains the output path active, ensuring a continuous supply of reference data. The check result immediately drives the subsequent decision-making process, forming a complete closed-loop verification chain.

[0064] This embodiment uses a collaborative mechanism of high-level interval identification and state switching detection to accurately define the reliable time window of the secondary read operation and verify the low-level state of the verification control signal, thereby ensuring the timing stability and mode correctness of the verification process. The low-level state of the verification control signal drives the multiplexing control of the static random access memory output path to achieve seamless readback extraction of the reference data, thereby reusing the same storage unit to complete the data storage and verification output functions, significantly reducing hardware resource overhead. The synchronous operation of the address pointer increment trigger and the target unit read is used to ensure that the secondary read address is strictly consistent with the first addressing position, thereby avoiding the risk of data comparison distortion caused by bit offset. The hardware-level verification of the second signal data and the reference data is completed within the operation window through the real-time XOR comparison mechanism to generate the verification results required for the decision closed loop, thereby achieving high-reliability error detection within a single clock cycle.

[0065] Reference Figure 2-5 As shown, in one embodiment, performing a real-time XOR comparison on the second signal data and the reference data to obtain a verification result includes: The reference data is fed into the driver enhancement circuit for signal conditioning. This circuit utilizes a current-multiplexing push-pull amplifier structure, consisting of a symmetrically arranged array of PMOS pull-up transistors and an array of NMOS pull-down transistors. The input stage uses source-follower circuits to isolate the load effect, achieving high input impedance. The reference data voltage drives the push-pull output stage, generating a full-swing output signal between the power rails. The voltage slew rate is optimized to meet the requirements of driving high capacitive loads. The enhanced drive reduces the output impedance of the reference signal to below 200Ω, adapting the drive capability to the bus transmission load while eliminating signal ringing. Internal phase compensation is incorporated into the buffering process to ensure full-band stability and mitigate the risk of oscillation caused by capacitive loads. Impedance matching is implemented in the enhanced signal transmission path to ensure monotonic signal edges.

[0066] The second signal data is processed by the level conversion module. This module utilizes a latched level converter architecture. The low-voltage input port receives the original signal via a level shifter, and the high-voltage output port is connected to a dual-power supply system. The conversion mechanism uses a cross-coupled inverter pair to expand the signal amplitude, generating a full-swing output that meets the target logic level requirements. The high and low levels of the full-swing data signal are strictly constrained within the power supply rails, and the threshold hysteresis is controlled within 200mV. The conversion process settling time matches the high-level window of the periodic read signal, and the delay deviation is maintained within an accuracy range of ±1ns. The output stage is equipped with an electrostatic protection structure to improve interface reliability.

[0067] The enhanced drive reference signal and the full-swing data signal are input in parallel to the XOR logic gate. The logic gate utilizes a complementary transmission gate design: the P-type network comprises a series-connected PMOS transistor and a parallel-connected NMOS transistor as the input path, while the N-type network is arranged in a mirror-image configuration. When the two input signals are at opposite levels, the logic gate outputs a high state; when the input signals are in phase, the output is a low state. The result of the operation is reconstructed into digital logic levels by the output buffer stage, forming the raw verification data. The logic gate propagation delay is strictly controlled within 3ns, meeting the timing constraints of real-time comparison. Power supply noise suppression is achieved through substrate isolation and independent power supply pins, with a voltage fluctuation tolerance of ±10%. An integrated glitch filter is included at the raw verification data output to eliminate the risk of metastability.

[0068] The raw check data is input into an edge-triggered verification circuit for processing. The core of this circuit is the synchronous sampling clock (CLK_CK) generation module, whose trigger source is the falling edge of the periodic read signal (READ). When the periodic read signal (READ) transitions from a high to a low level, the clock generator is triggered to output a 5ns sampling pulse. The verification circuit utilizes a master-slave D-type flip-flop architecture: the master latch captures the raw check data level on the rising edge of the synchronous sampling clock (CLK_CK), while the slave latch outputs a stable synchronous check result on the falling edge of the synchronous sampling clock (CLK_CK). A setup time design ensures data stability before the sampling window, maintaining time constraints and eliminating the risk of metastability. Timing skew control is implemented through a delay-locked loop (DLL), achieving phase alignment accuracy of ±0.5ns. A temperature compensation circuit maintains timing stability across the full operating temperature range, ensuring sampling reliability under extreme operating conditions.

[0069] The synchronous verification results are connected to a bistable latch for state solidification. The latch utilizes a cross-coupled NOR gate architecture: the first NOR gate input receives the verification data signal, and the output is connected to the second NOR gate input; the second NOR gate output is fed back to the first NOR gate input. The locking process completes steady-state establishment within 3ns through a positive feedback loop, and the noise margin enhancement design enhances noise immunity. The latch output stage integrates three-state control logic: the output drive is enabled when the periodic read signal (READ) is low, and switches to a high-impedance state when high. The verification result is latched as a stable digital signal: a low level indicates data consistency verification has been passed, while a high level indicates data anomaly. The static power optimization design controls leakage current to the nanoampere level, and the data retention time covers the full decision cycle requirements.

[0070] The latched check result drives the decision state machine to execute branching operations: When the check result is low, the enable port of the tri-state output buffer is activated, enabling the OTP data bus transmission channel. When the check result is high, a 200ns-wide negative pulse is generated on the reset control signal (RSTN). The RSTN pulse synchronously triggers three linked operations: the address counter is asynchronously cleared to reset the address pointer; the static random access memory charge dump module forces the first and second nodes to be initialized (by turning on transistor NM5 to ground); and the timing control state machine resets the generation process of the periodic read signal (READ) and check control signal (READ_CHECK). The linked response latency is controlled within 10ns, and the hardware state machine implements autonomous error correction without software intervention. The check result is also input into a 32-bit error counter, which triggers a fuse protection mechanism when the accumulated number of anomalies exceeds a preset threshold.

[0071] This embodiment uses an edge-triggered verification mechanism to precisely trigger the sampling clock using the falling edge of the periodic read signal, thereby achieving synchronous capture of the verification data and completely eliminating the risk of metastable states caused by asynchronous sampling. Through the result latching technology, a cross-coupled bistable structure is used to solidify the verification state, thereby significantly improving the noise tolerance and anti-interference capability. Through the closed-loop feedback linkage design, the verification results directly drive the collaborative operation of multiple modules, thereby completing error detection and system reset within a single clock cycle. Through the coordinated processing of level conversion and signal buffering, the voltage domain and drive characteristics of the data signal are unified, thereby ensuring the electrical compatibility of the comparison operation. Through hardware-level real-time XOR operation, data consistency verification is completed within the read window, thereby avoiding the millisecond-level delay of traditional software verification. Through the three-state control and error counting mechanism, a hierarchical response strategy is implemented, thereby providing cumulative protection while ensuring core functions.

[0072] Reference Figure 2-5 As shown, in one embodiment, closed-loop detection is performed on the verification result to obtain the OTP verification result, including: The check result signal is input into the state analysis circuit for processing. This circuit uses a window comparator architecture with set high and low level thresholds: values ​​below 0.3V are considered a logic low, and values ​​above 1.5V are considered a logic high. The level detection result is transmitted to the encoding logic unit, which maps the single-bit check state into a two-bit binary code: 00 indicates standby state, 01 indicates data consistency, and 10 indicates data exception state. When 01 indicates data consistency, the reference readback data line (DR) is 101, and the real-time read data line (DL) is 101. When 10 indicates a data exception state, the reference readback data line (DR) is 101, and the real-time read data line (DL) is 111.

[0073] The status flag signal output stage is equipped with an electrostatic protection network and an RC low-pass filter to eliminate high-frequency noise interference and electrostatic discharge risks. The signal transmission path utilizes differential balanced routing, with path delay deviation controlled within ±5ps. The total latency of the analysis process is strictly constrained to within 3ns. The falling edge of the synchronous sampling clock (CLK_CK) triggers the output latch, and the status flag signal is aligned with the falling edge of the periodic read signal (READ). The verified status flag signal is transmitted to the decision module via a low-impedance bus. Buffer repeaters are inserted in the transmission path to ensure signal integrity.

[0074] The check state flag signal is fed into the decision state machine for pattern recognition. This state machine utilizes a synchronous finite state machine architecture, with its clock source tied to the falling edge of the periodic read signal (READ). The state transition logic strictly adheres to the encoding definition: when the flag signal is 01, the system switches to the data output branch, outputting an active-high "data output mode" enable signal; when the flag signal is 10, the system switches to the error handling branch, outputting an "error handling mode" trigger pulse. The state transition process incorporates an integrated protection mechanism: an illegal encoding state (00 or 11) triggers a watchdog timer, forcing the state machine to reset to its initial state within 10ns. The operating mode output signal is maintained stable via a master-slave latch. The latch enable terminal is connected to the synchronous sampling clock (CLK_CK), maintaining a constant level throughout the periodic read signal (READ). The signal transmission path utilizes equal-length serpentine routing to minimize multipath transmission delay variations. The operating mode signal serves as the core control variable, directly driving the activation timing of subsequent tri-state gating and data output processes.

[0075] When the verification status indicator signal reaches the data consistency state (code 01), the operation mode switches to data output mode. The verification status indicator signal, code 01, is input to the tri-state gating circuit to generate a drive signal. This signal turns on the output-stage PMOS / NMOS transistor array, forming a low-impedance path, while simultaneously blocking the input buffer circuit to prevent signal conflicts. The gate activation process is tied to the low-level window of the periodic read signal (READ) in the timing sequence, completing channel establishment within 5ns of the falling edge of the synchronous sampling clock (CLK_CK). The output channel integrates a dynamic impedance matching network to eliminate waveform distortion caused by signal reflections, ensuring return loss compliance with high-speed bus transmission standards. At this stage, the reference readback data line (DR) has completed its verification mission, and the real-time read data line (DL) carries the secondary signal data, becoming the core processing target.

[0076] After the data output channel is activated, the secondary signal data undergoes physical layer enhancement via a three-stage driver architecture. A current-mode pre-driver stage optimizes the signal slew rate to 200V / μs, eliminating propagation delay variations. A push-pull output stage extends the current drive capability to a 10mA threshold, supporting multi-node parallel loads. Active termination circuitry compensates for impedance fluctuations in real time to suppress intersymbol interference. The driver process reconstructs the DL signal into a full-swing digital level from 0V to 1.8V, with rise / fall times symmetrically controlled within 1.5ns ± 0.1ns and overshoot limited to 5% of the voltage swing. The electrical characteristics of the bus-compatible data fully match the AMBA bus specification, with setup / hold time margins meeting the most stringent timing constraints.

[0077] The bus-compatible data input protocol encapsulation engine performs structured processing: a hexadecimal synchronization header (55AAh) is added to mark the start of the data frame, with a duty cycle tolerance of ±0.1%. A CRC8 checksum is inserted to verify transmission integrity, using an industry-standard generator polynomial. A 24-bit timestamp is appended to record the operation time with nanosecond accuracy. The encapsulation process utilizes a four-stage pipeline architecture, with each processing stage strictly aligned to the 10MHz system clock. The resulting OTP checksum is structured into a standard bus data packet: [2-byte synchronization header] - [2-byte length field] - [N-byte payload] - [1-byte CRC8] - [3-byte timestamp]. The frame structure utilizes pre-emphasis to optimize signal integrity. Output timing parameters meet the 2ns setup time / 1ns hold time requirements. A flow control mechanism dynamically adjusts data throughput to avoid bus bandwidth overload.

[0078] The data output process establishes a physical path through tri-state gating, driver enhancement ensures signal quality, and protocol encapsulation achieves bus standardization, forming a complete conversion chain from verification results to application-layer data. The entire process adheres to timing requirements: tri-state activation is completed early in the low-level window of the periodic read signal (READ), driver enhancement is performed mid-way through the window, and protocol encapsulation is output late in the window, with a timing boundary accuracy of ±0.5ns. The value of this technology lies in the seamless integration of physical layer signals and protocol layer specifications, enabling OTP stored data to be directly integrated into the automotive control system bus architecture.

[0079] This embodiment precisely drives tri-state gates through the verification state identification signal, activating the output channel only when data is consistent, thereby eliminating the risk of erroneous data contaminating the system bus. A multi-level driver enhancement architecture optimizes the physical layer of the secondary signal data, enhancing signal integrity and load drive capability, thereby ensuring data transmission reliability in highly capacitive bus environments. The protocol encapsulation engine's triple protection mechanism of frame header synchronization, check bytes, and timestamp tags supports plug-and-play system integration and highly reliable data exchange.

[0080] Reference Figure 2-5 As shown, in one embodiment, it further includes, when the operation mode is the error handling trigger mode: When the verification status flag signal indicates a data anomaly (code 10), the reset pulse generation circuit is triggered to perform width modulation. This circuit utilizes a voltage-controlled oscillator (VCO) and a duty-cycle controller: the oscillator frequency dynamically adjusts based on the supply voltage, while the duty-cycle controller sets a fixed 20% duty cycle. The modulation process stabilizes the pulse characteristics through a feedback loop, and temperature drift compensation maintains output consistency. The generated reset control pulse (RSTN) exhibits a 200ns active-low pulse with a falling edge delay controlled within 5ns and a rising edge with a gradual slope to mitigate electromagnetic interference. The pulse width tolerance is ±10%, and the voltage swing covers the full 0V to 1.8V supply range, providing sufficient drive capability for multiple modules connected in parallel. Pulse parameters strictly match system reset timing requirements, eliminating the risk of cascaded reset conflicts.

[0081] The active-low edge of the reset control pulse directly drives the address pointer clear circuit. This circuit comprises an asynchronous reset logic gate and a counter array. The falling edge of the reset pulse triggers the RS latch to output a clear enable signal, which is directly connected to the asynchronous reset port of the address counter. All memory cells in the counter are forced to zero within 10ns, outputting an all-zero binary-coded address. The clear process operates independently of the system clock, with response latency within the timing constraint. The reset addressing state is verified by a status detection circuit: when the address bus is stable at all-zero levels, an active-high status flag is output. The status flag signal is transmitted to the reset pulse modulation module, forming a closed-loop verification chain. The address pointer reset mechanism ensures that the memory array access location returns to its initial state.

[0082] The low state of the reset control pulse activates the charge dump control circuit. This circuit generates a dump enable signal to drive the NMOS dump transistor array within the static random access memory. The enable signal turns on the NM5 transistor, forcing the second node to ground. It also simultaneously activates a chain of inverters to pull the voltage of the first node to the supply rail. The charge dump process resets the node voltage within 50ns, with the peak dump current limited to 5mA. The completion of the dump is detected by a voltage comparator. This signal, indicating that the memory cell has returned to zero charge, is fed back to the reset control module via metal layer routing. The dump operation eliminates any interference from residual charge on the restart process.

[0083] The reset addressing state and residual data clear signals are input into the reset state machine in parallel for collaborative verification. When the reset addressing state flag is high (address bus all zeros) and the residual data clear signal remains valid high, the state machine outputs a reset confirmation instruction. This instruction drives the reset control pulse generation module to perform a state reset operation: first, it shuts down the voltage-controlled oscillator power supply, then clears the internal registers of the duty cycle controller, and finally, it switches the output stage to a high-impedance state. The reset process releases residual energy in the energy storage element through the charge discharge circuit, and the reset completion flag transitions high within 20ns. The reset signal generation state indicates that the pulse generation circuit has returned to its initial standby state, reducing quiescent current to microamperes, providing a clean initialization environment for the restart process. An interlock mechanism is integrated into the state transition process to ensure that the signal generation module is not reset until the address and memory reset are complete, thus avoiding the risk of timing conflicts.

[0084] An active-high flag that resets the signal generation state triggers the reinitialization of the check control signal. The initialization sequence is controlled by a state machine: first, the check control signal (READ_CHECK) is loaded to its default high state, then the timing divider phase is reset to its reference position, and finally, the clock gating enable is synchronously released. The restart check signal is output via a push-pull driver with a rising edge delay controlled within 5ns and a voltage swing strictly constrained to the 0V-1.8V range. Signal characteristics verified by a calibration circuit demonstrate a frequency tolerance of ±100ppm, a duty cycle deviation of ≤2%, and a phase jitter of 50ps peak-to-peak. An overshoot suppression network is configured at the restart check signal output to eliminate high-frequency harmonic interference and ensure signal edge monotonicity. This signal serves as the core timing reference for system restart, directly driving the subsequent activation of the dual-read check process.

[0085] The rising edge of the restart check signal triggers the restart of the dual read check process. The process controller executes a four-level startup sequence: 1. The address pointer generation module is released from reset. 2. The static random access memory input path is enabled. 3. The periodic read signal generator is synchronously activated. 4. The verification decision state machine returns to its initial standby state.

[0086] The restart process is tracked in real time by monitoring circuitry: the address counter stepping serves as an addressing resume indicator, the static random access memory latch node voltage buildup serves as a memory-ready indicator, and the first rising edge of the periodic read signal (READ) serves as a timing reference. When all monitored indicators reach steady state, an active-high restart process signal is output. This signal indicates that the system has fully returned to its initial state, allowing the "power-on reset signal generation based on the power supply voltage" startup process to be re-executed. Restart response latency is compressed to within 100ns, and peak power consumption is limited to 120% of normal operating mode.

[0087] This embodiment uses a reset pulse width modulation mechanism to generate precisely timed reset control pulses, enabling rapid response to error states and accelerating hardware-level recovery. By asynchronously clearing the address pointer and simultaneously draining the memory node charge, the core module state is reset, eliminating the risk of residual data interfering with the restart process. A dual verification mechanism for the reset state and clear signal ensures reset operation integrity and timing coordination, thus avoiding logic conflicts caused by cascaded resets.

[0088] Reference Figure 6 As shown, the present invention provides an OTP dual-reading verification device, which is applied to any of the above-mentioned OTP dual-reading verification methods, including: A power-on reset and address generation module, which is used to generate a power-on reset signal based on the power supply voltage, perform signal response, and obtain a periodic read signal and a verification control signal; The reading module is used to read the OTP once from the OTP reading and writing system according to the first cycle of the periodic reading signal and the verification control signal, and store the OTP into the static random access memory to obtain the reference data; The comparison module is used to perform a second OTP reading based on the second cycle of the periodic reading signal in combination with the verification control signal, and compare the result with the reference data to obtain the verification result; The processing module is used to perform closed-loop detection on the verification result to obtain the OTP verification result.

[0089] The present invention provides an OTP dual-read verification device. Through a timing coordination mechanism between a periodic read signal and a verification control signal, it establishes reference data during the first read phase and achieves instantaneous latching via a static random access memory (SRAM). Combined with a real-time comparison structure for the second read, this effectively avoids the risk of data misreading caused by transient power supply fluctuations, significantly improving the integrity assurance capability of critical stored information. By innovatively reusing the input / output physical pathways of the SRAM, the reference data establishment and verification readback functions are integrated into the same hardware unit. This eliminates the storage resource consumption of traditional triple-module redundancy while implementing dual-channel verification, providing a resource-efficient and reliable solution for cost-sensitive devices. A synchronous timing control system, built on periodic read signals, precisely triggers data sampling points during the second read window, completely avoiding the issue of asynchronous clock establishment time conflicts and ensuring timing consistency between the storage unit and the verification logic. When the verification result is abnormal, a closed-loop detection mechanism automatically triggers an address pointer reset and a memory state refresh, achieving self-contained error recovery by resetting the signal generation state, and completing millisecond-level error correction response at the hardware level. This dual-cycle check architecture reduces physical resource usage while enhancing timing robustness, meeting the stringent requirements of zero-fault tolerance scenarios in functional safety standards and providing a storage access paradigm that is both economical and secure.

[0090] It should be noted that, those skilled in the art will clearly understand that, for the sake of convenience and brevity of description, the specific working processes of the above-described system and each module can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0091] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A dual-read verification method for OTP, characterized in that: include: Generate a power-on reset signal based on the power supply voltage, perform a signal response, and obtain a periodic read signal and a verification control signal; Performing an OTP read once on the OTP read / write system according to the first cycle of the periodic read signal and the verification control signal, and storing the OTP in a static random access memory to obtain reference data; According to the second cycle of the periodic read signal, the OTP is read again in combination with the verification control signal, and compared with the reference data to obtain a verification result; Perform closed-loop detection on the verification result to obtain an OTP verification result.

2. The dual-read verification method of OTP according to claim 1, wherein: The generating of a power-on reset signal based on the power supply voltage and performing a signal response to obtain a periodic read signal and a verification control signal includes: Performing voltage detection and threshold comparison on the power supply voltage to generate a power-on reset signal; Acquire a periodic read signal generated by the OTP read / write system based on the power-on reset signal; Perform OTP control activation based on the power-on reset signal to obtain an OTP read-write control enable signal; The OTP read-write control enable signal is state-machine converted according to the periodic read signal to obtain a verification control signal.

3. The dual-read verification method of OTP according to claim 1, wherein: The OTP read / write system is subjected to an OTP read operation according to the first cycle of the periodic read signal and the verification control signal, and stored in a static random access memory to obtain reference data, including: Performing high-level interval detection on the first cycle to obtain an operation window signal; Reading the level state of the verification control signal according to the one-time operation window signal to obtain a first level state; According to the first level state, the address pointer of the OTP read-write system is incremented and triggered to obtain a first read address; Perform storage array selection on the OTP read / write system according to the first read address to obtain a target storage cell row; Performing bit-selection conduction reading on the target memory cell row and outputting first signal data; The first signal data is input into the static random access memory for latching processing to obtain the reference data.

4. The dual-read verification method of OTP according to claim 3, wherein: The step of inputting the first signal data into the static random access memory for latching to obtain the reference data includes: Performing switch control signal generation on the check control signal to obtain a bit selection control signal; Performing differential conversion on the first signal data to obtain an in-phase data signal and an inverted data signal; Performing a first input path gate drive on the in-phase data signal according to the bit selection control signal to obtain a first node voltage; Performing a second input path gate drive on the inverted data signal according to the bit selection control signal to obtain a second node voltage; performing cross-coupling inverter latching on the first node voltage and the second node voltage to obtain a stable node voltage pair; Output buffering is performed on the stable node voltage pair to obtain reference data.

5. The dual-read verification method of OTP according to claim 1, wherein: The performing of a second OTP reading according to the second cycle of the periodic reading signal in combination with the verification control signal, and comparing the OTP reading with the reference data to obtain a verification result, includes: Identifying a high-level interval of the second period to obtain a secondary operation window signal; Performing state switching detection on the verification control signal according to the secondary operation window signal to obtain a low-level state signal; performing output path multiplexing control on the static random access memory and activating a readback path according to the low-level state signal to extract the reference data; Triggering the OTP read / write system to increment the address pointer according to the secondary operation window signal to obtain a second read address; Performing target unit reading on the OTP read / write system according to the second read address to obtain second signal data; Perform a real-time XOR comparison on the second signal data and the reference data to obtain the verification result.

6. The OTP dual-reading verification method according to claim 1, wherein: Performing a real-time XOR comparison on the second signal data and the reference data to obtain the verification result includes: performing signal buffering on the reference data to obtain an enhanced driving reference signal; performing level conversion on the second signal data to obtain a full-swing data signal; Performing an XOR logic gate operation on the enhanced driving reference signal and the full-swing data signal to obtain original verification data; An edge-triggered check is performed on the original check data according to the periodic read signal to obtain the check result.

7. The dual-read verification method of OTP according to claim 1, characterized in that: The performing closed-loop detection on the verification result to obtain the OTP test result includes: Performing status analysis on the verification result to obtain a verification status identification signal; Performing decision branch identification on the verification status identification signal to obtain an operation mode; When the operation mode is data output mode: Perform tri-state gating activation on the OTP read / write system according to the verification status identification signal to obtain a data output channel; enhancing the driving capability of the second signal data through the data output channel to obtain bus-compatible data; The bus compatible data is packaged and outputted according to the protocol to obtain the OTP test result.

8. The OTP dual-reading verification method according to claim 7, wherein: Also included, when the operation mode is the error handling trigger mode: Performing reset pulse width modulation on the verification status identification signal to obtain a reset control pulse; Asynchronously clearing the address pointer according to the reset control pulse to obtain a reset addressing state; Discharging node charges of the static random access memory according to the reset control pulse to obtain a residual data clearing signal; Resetting the signal generation state of the reset control pulse according to the reset addressing state and the residual data clearing signal to obtain a reset signal generation state; reinitialize the check control signal according to the reset signal generation state to obtain a restart check signal; The dual-read verification process is restarted according to the restart verification signal to obtain restart process information.

9. An OTP dual-reading verification device, characterized in that: The dual-read verification method for an OTP according to any one of claims 1 to 8 comprises: A power-on reset and address generation module, configured to generate a power-on reset signal based on a power supply voltage, perform a signal response, and obtain a periodic read signal and a verification control signal; A reading module, wherein the reading module is used to read the OTP once from the OTP reading and writing system according to the first cycle of the periodic reading signal and the verification control signal, and store the OTP in a static random access memory to obtain reference data; a comparison module configured to perform a second OTP read according to the second period of the periodic read signal in combination with the verification control signal, and compare the read result with the reference data to obtain a verification result; The processing module is used to perform closed-loop detection on the verification result to obtain an OTP verification result.

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