Superconducting quantum chip wiring path optimization method and device based on line segment line-of-sight algorithm

Abstract

The embodiment of the invention discloses a superconducting quantum chip wiring path optimization method and device based on a line segment sight line algorithm. A specific implementation mode of the method comprises the following steps: starting from a current path point, backwards extending along an original path to construct a straight line segment; determining the shortest distance between the straight line segment and each obstacle polygon, and determining whether the shortest distance is greater than or equal to a preset cache distance; in response to determining that the shortest distance is greater than or equal to the preset cache distance, determining that the straight-line segment is safe; according to a preset cache distance, the obstacle polygon corresponding to the shortest distance is expanded outwards, and a buffer area is generated; performing simplification processing on the initial wiring path from the current path point by adopting a forward jump greedy algorithm to generate a simplified wiring path; and performing multi-objective optimization processing on the simplified wiring path according to the parameterized weight tuning function to generate an optimized wiring path. According to the implementation mode, through iterative collinear point elimination, the curvature change rate smoothness of a wiring path is improved, and the requirement for low-impedance connection between superconducting quantum bits is met.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of superconducting quantum chip wiring path optimization, and more particularly to a method and apparatus for superconducting quantum chip wiring path optimization based on a line-segment line-of-sight algorithm. Background Art

[0002] In the field of superconducting quantum chip wiring technology, existing research has not yet paid sufficient attention to the critical impact of path geometry on the performance of quantum devices. Traditional wiring schemes mostly follow the path planning ideas of classical integrated circuits, with only physical connectivity as the design goal, and no dedicated optimization model is established for the unique electromagnetic sensitivity of superconducting quantum systems. This technological gap leads to unnecessary topological twists in the wiring path, and the parasitic inductance effect caused by it will significantly reduce the coherence time of the quantum bit, while the local electromagnetic radiation interference at the turning point of the path is more likely to destroy the stability of adjacent quantum states. Especially in the wiring of multi-qubit arrays, unoptimized redundant path structures will aggravate microwave signal crosstalk, resulting in a decrease in the fidelity of quantum gate operations. The current technology system lacks a systematic method to couple path geometry smoothness, electromagnetic compatibility and superconducting material properties. It is difficult to simultaneously meet the multi-dimensional requirements of low-loss transmission, enhanced anti-interference and process manufacturability under complex wiring constraints. This has become a core bottleneck problem restricting the performance improvement of large-scale superconducting quantum chips. Summary of the Invention

[0003] The content of this disclosure is used to briefly introduce concepts that will be described in detail in the detailed description section below. The content of this disclosure is not intended to identify key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0004] Some embodiments of the present disclosure propose a superconducting quantum chip wiring path optimization method, device, electronic device and computer-readable medium based on a line-segment line-of-sight algorithm to solve the technical problems mentioned in the above background technology section.

[0005] In a first aspect, some embodiments of the present disclosure provide a superconducting quantum chip wiring path optimization method based on a line segment line of sight algorithm, the method comprising: converting a list of obstacle polygon vertices corresponding to a superconducting quantum chip wiring diagram into geometric objects in a target library; establishing a query mechanism for each converted obstacle polygon using a spatial index result; starting from a current path point, extending backward along an original path to construct a straight line segment, wherein the original path is an initial wiring path corresponding to the superconducting quantum chip wiring diagram; determining the shortest distance between the straight line segment and each obstacle polygon, and determining whether the shortest distance is greater than or equal to a preset cache distance; in response to determining that the shortest distance is greater than or equal to the preset cache distance, determining that the straight line segment is safe; expanding the obstacle polygon corresponding to the shortest distance outward according to the preset cache distance to generate a buffer zone; detecting whether there is an intersection between the straight line segment and the buffer zone, and in response to determining that there is no intersection between the straight line segment and the buffer zone, simplifying the initial wiring path starting from the current path point using a forward skipping greedy algorithm to generate a simplified wiring path; and performing multi-objective optimization on the simplified wiring path according to a parameterized weight tuning function to generate an optimized wiring path.

[0006] In a second aspect, some embodiments of the present disclosure provide a superconducting quantum chip wiring path optimization device based on a line segment sight algorithm, the device comprising: a conversion unit configured to convert a list of obstacle polygon vertices corresponding to a superconducting quantum chip wiring diagram into a geometric object of a target library; a creation unit configured to use a spatial index result to establish a query mechanism for each converted obstacle polygon; an extension unit configured to start from a current path point and extend backward along the original path to construct a straight line segment, wherein the original path is the initial wiring path corresponding to the superconducting quantum chip wiring diagram; a first determination unit configured to determine the shortest distance between the above straight line segment and each obstacle polygon, and to determine whether the shortest distance is greater than or equal to the maximum value. is equal to a preset cache distance; a second determining unit is configured to, in response to determining that the shortest distance is greater than or equal to the preset cache distance, determine that the straight line segment is safe; a generating unit is configured to, based on the preset cache distance, expand the obstacle polygon corresponding to the shortest distance outward to generate a buffer zone; a simplification unit is configured to detect whether there is an intersection between the straight line segment and the buffer zone, and in response to determining that there is no intersection between the straight line segment and the buffer zone, adopt a forward jumping greedy algorithm to simplify the initial routing path starting from the current path point to generate a simplified routing path; an optimizing unit is configured to perform multi-objective optimization on the simplified routing path according to a parameterized weight tuning function to generate an optimized routing path.

[0007] In a third aspect, some embodiments of the present disclosure provide an electronic device comprising: one or more processors; a storage device on which one or more programs are stored, and when the one or more programs are executed by one or more processors, the one or more processors implement the method described in any implementation of the first aspect above.

[0008] In a fourth aspect, some embodiments of the present disclosure provide a computer-readable medium having a computer program stored thereon, wherein when the program is executed by a processor, the method described in any implementation of the first aspect is implemented.

[0009] The above-mentioned embodiments of the present disclosure have the following beneficial effects: Through the superconducting quantum chip wiring path optimization method based on the line-segment line-of-sight algorithm in some embodiments of the present disclosure, the number of path turning points is reduced while maintaining the wiring spacing constraint through a multi-stage post-processing collaborative mechanism; redundant turning points that cause parasitic inductance effects are eliminated through dynamic angle threshold control, thereby reducing microwave signal transmission loss; intermediate points close to collinearity (angles close to 180 degrees) are dynamically eliminated. Local safety reviews are performed on necessary turning points to ensure that the path after collinearity optimization still meets the full-segment obstacle avoidance constraint; and through iterative collinear point elimination, the curvature change rate of the wiring path is smoothed, meeting the low-impedance connection requirements between superconducting quantum bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that components and elements are not necessarily drawn to scale.

[0011] Figure 1 is a flow chart of some embodiments of a superconducting quantum chip wiring path optimization method based on a line segment sight algorithm according to the present disclosure; Figure 2 This is a schematic diagram of an initial wiring path in a superconducting quantum chip wiring path optimization method based on a line segment sight algorithm in some embodiments of the present disclosure; Figure 3 This is a schematic diagram of optimizing a wiring path in a superconducting quantum chip wiring path optimization method based on a line segment sight algorithm in some embodiments of the present disclosure; Figure 4 Schematic diagram of the structure of some embodiments of the superconducting quantum chip wiring path optimization device based on the line segment line of sight algorithm according to the present disclosure; Figure 5 It is a structural diagram of an electronic device suitable for implementing some embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0013] It should also be noted that, for ease of description, only the parts related to the invention are shown in the drawings. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0014] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0015] It should be noted that the modifications of "one" and "multiple" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, they should be understood as "one or more".

[0016] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0017] The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0018] Figure 1 This is a process 100 of some embodiments of a superconducting quantum chip wiring path optimization method based on a line segment line of sight algorithm in some embodiments of the present disclosure. The superconducting quantum chip wiring path optimization method based on a line segment line of sight algorithm includes the following steps: Step 101: Convert the obstacle polygon vertex list corresponding to the superconducting quantum chip wiring diagram into geometric objects in the target library.

[0019] In some embodiments, an execution subject (e.g., a computing device) of the superconducting quantum chip wiring path optimization method based on a line segment sight algorithm may convert a list of obstacle polygon vertices corresponding to a superconducting quantum chip wiring diagram into geometric objects of a target library.

[0020] The parameter configurations of the paths, obstacles, and safety distances after wiring the superconducting quantum chip are shown in Table 1 below: Table 1 Field Name Data Type illustrate path List Redundant polyline paths, including multiple intermediate points polygons List Obstacles are a list of regions consisting of polygonal vertices buffer_distance Float Safe distance to prevent wiring signal interference The initial wiring path of the superconducting quantum chip before wiring path optimization is as follows Figure 2 As shown, Figure 2 The blue lines shown in the example are the initial routing paths.

[0021] The target library may refer to a Shapely library, and the geometric object may refer to a Polygon geometric object.

[0022] For invalid obstacle polygons that are self-intersecting or unclosed, polygon.buffer(0) is used for topological repair. The mathematical expression is: .

[0023] The steps to convert the obstacle polygon vertex list into a Shapely library Polygon object and handle invalid polygons are as follows: 1. First check whether the number of points is greater than or equal to 3 (a polygon requires at least 3 points); 2. Use Shapely's Polygon constructor to create a geometric object; 3. For invalid obstacle polygons (such as self-intersection), use buffer(0) technology to fix topological errors; 4. If the repaired obstacle polygon is valid and non-empty, it is added to the processed list.

[0024] Step 102: Using the spatial index result, a query mechanism is established for each transformed obstacle polygon.

[0025] In some embodiments, the execution entity can use the spatial index results to establish a query mechanism for each converted obstacle polygon. For example, a spatial index structure (such as STRtree) can be used to establish a fast query mechanism for polygons. This index hierarchically organizes the minimum bounding rectangles (MBRs) of polygons, reducing the time complexity of collision detection from linear search (O(n)) to logarithmic O(log n).

[0026] Among them, the relationship between the spatial index and the obstacle polygon is: 1. Spatial indexes (such as STRtree) organize the minimum bounding rectangle (MBR) of polygons into a tree structure; 2. When you need to check whether a line segment intersects a polygon, first check whether the line segment intersects the polygon's MBR; 3. Only when MBRs intersect, more complex and precise geometric calculations are performed; 4. This reduces the time complexity of collision detection from O(n) (traversing all polygons) to O(log n).

[0027] Step 103: Starting from the current path point, extend backward along the original path to construct a straight line segment.

[0028] In some embodiments, the execution subject can start from the current path point and extend backward along the original path to construct a straight line segment. The original path is the initial wiring path corresponding to the superconducting quantum chip wiring diagram. For example, the line of sight dynamic detection starts from the current path point P i Start from the original path and extend it backward to construct the straight line segment L(P i , P j ).

[0029] Step 104 : determining the shortest distance between the straight line segment and each obstacle polygon, and determining whether the shortest distance is greater than or equal to a preset cache distance.

[0030] In some embodiments, the execution entity may determine the shortest distance between the straight line segment and each obstacle polygon, and determine whether the shortest distance is greater than or equal to a preset buffer distance. Specifically, the perpendicular distance between the straight line segment and each obstacle polygon is determined, and then the shortest distance among these perpendicular distances is determined as the shortest distance. The preset buffer distance may be represented by buffer_distance.

[0031] For example, the shortest distance between the above straight line segment and each obstacle polygon can be determined by the following formula: .

[0032] in, represents the k-th obstacle polygon.

[0033] Step 105 : In response to determining that the shortest distance is greater than or equal to the preset cache distance, determining that the straight line segment is safe.

[0034] In some embodiments, the execution entity can determine that the line segment is safe in response to determining that the shortest distance is greater than or equal to the preset cache distance. Starting from the current path node, the line segment (LineString) is extended backward point by point along the path sequence. Shapely's distance method is used to calculate the shortest distance between the line segment and all obstacle polygons in real time. If the entire distance is greater than the buffer threshold, it is marked as a visible point P. j , otherwise the detection is terminated.

[0035] Step 106 : According to the preset cache distance, the obstacle polygon corresponding to the shortest distance is expanded outward to generate a buffer zone.

[0036] In some embodiments, the execution entity may expand the obstacle polygon corresponding to the shortest distance outward according to a preset cache distance to generate a buffer zone.

[0037] For example, the buffer distance buffer_distance can be adaptively checked to block the obstacle polygon P k Expand outward to generate buffer P k ' =P k buffer (buffer_distance).

[0038] Step 107 , detecting whether there is an intersection between the straight line segment and the buffer zone, and in response to determining that there is no intersection between the straight line segment and the buffer zone, using a forward skipping greedy algorithm, starting from the current path point, simplifying the initial routing path to generate a simplified routing path.

[0039] In some embodiments, the execution subject may detect whether there is an intersection between the straight line segment and the buffer zone, and in response to determining that there is no intersection between the straight line segment and the buffer zone, adopt a forward skipping greedy algorithm to simplify the initial routing path starting from the current path point to generate a simplified routing path. By detecting whether the straight line segment L has an intersection L∩(⋃ N k=1 P k ' ) = ∅, dynamically avoiding potential collision risks. This mechanism supports micron-level precision adjustment, for example, allocating a larger buffer distance for microwave signal lines in quantum chips to suppress electromagnetic crosstalk.

[0040] In practice, the path search strategy adopts the forward jumping greedy algorithm, starting from the current point P i Start by checking P backwards (i+2) , click P (i+3) ,…, point P (n-1) Visibility, directly skipping the intermediate redundant points (for example, point P (i+2) , click P (i+3) Once an invisible point is found, the current round of detection is terminated and the farthest visible point P is selected. jmax as the next node.

[0041] In practice, the above execution entity can simplify the initial wiring path through the following steps: The first step is to start from the original path starting point P0 and set the current point index i=0.

[0042] The second step is to use the current path point P i As a benchmark, detect point P in reverse order (from far end to near end). (i+2) , click P (i+3) ,…, point P (n-1) visibility.

[0043] In the third step, in response to the detection of point P jIf it is not visible, stop detecting subsequent points and record the farthest visible point P that can be reached. jmax , the farthest visible point P jmax Join the smooth path and update the current point index i=jmax.

[0044] Loop iteration: Repeat steps 2-3 until the end of the path is reached.

[0045] The fourth step is to check whether the end point P is included at the end of the smooth path. end To ensure the physical connectivity of the path, the endpoint mandatory inclusion mechanism verifies whether the endpoint P is included at the end of the smooth path. end If the end point is detected to be missing, it is directly appended to the end of the path, that is: .

[0046] Step 5: If the endpoint P is detected end If missing, append to the end of the smoothed path.

[0047] This mechanism further eliminates the risk of path interruption caused by complex obstacle layouts through reverse collision detection (backtracking from the end point).

[0048] Step 108 : performing multi-objective optimization processing on the simplified wiring path according to the parameterized weight tuning function to generate an optimized wiring path.

[0049] In some embodiments, the execution entity may perform multi-objective optimization processing on the simplified routing path according to a parameterized weight tuning function to generate an optimized routing path.

[0050] In practice, the above execution entity can perform multi-objective optimization on the above simplified wiring path through the following parameterized weight tuning function: , in, represents the control path length weight, Represents the adjusted collision risk cost (the inverse of the distance from the point to the obstacle 1 / d min Related), for highly sensitive signal lines (such as flux lines), set ≫ , to prioritize security; for paths with low latency requirements, increase To shorten the overall length, Indicates the current path point P i The corresponding shortest distance.

[0051] As an example, optimizing routing paths such as Figure 3 The example given.

[0052] Further references Figure 4 As an implementation of the methods shown in the above figures, the present disclosure provides some embodiments of a superconducting quantum chip wiring path optimization device based on a line segment line algorithm. These device embodiments are similar to Figure 1 Corresponding to the method embodiments shown, the superconducting quantum chip wiring path optimization device based on the line segment line of sight algorithm can be specifically applied to various electronic devices.

[0053] like Figure 4 As shown, some embodiments of the superconducting quantum chip wiring path optimization device 400 based on the line segment line algorithm include: a conversion unit 401, an establishment unit 402, an extension unit 403, a first determination unit 404, a second determination unit 405, a generation unit 406, a simplification unit 407 and an optimization unit 408. The conversion unit 401 is configured to convert the list of obstacle polygon vertices corresponding to the superconducting quantum chip wiring diagram into geometric objects of the target library; the establishment unit 402 is configured to use the spatial index result to establish a query mechanism for each obstacle polygon after conversion; the extension unit 403 is configured to start from the current path point and extend backward along the original path to construct a straight line segment, wherein the original path is the initial wiring path corresponding to the superconducting quantum chip wiring diagram; the first determination unit 404 is configured to determine the shortest distance between the above straight line segment and each obstacle polygon, and determine whether the shortest distance is greater than or equal to the preset cache distance; the second determination unit 405 is configured In response to determining that the shortest distance is greater than or equal to the preset cache distance, it is determined that the straight line segment is safe; the generation unit 406 is configured to expand the obstacle polygon corresponding to the shortest distance outward according to the preset cache distance to generate a buffer zone; the simplification unit 407 is configured to detect whether there is an intersection between the straight line segment and the buffer zone, and in response to determining that there is no intersection between the straight line segment and the buffer zone, adopt a forward jumping greedy algorithm to simplify the initial routing path starting from the current path point to generate a simplified routing path; the optimization unit 408 is configured to perform multi-objective optimization on the above-mentioned simplified routing path according to the parameterized weight tuning function to generate an optimized routing path.

[0054] It is understandable that the various units recorded in the superconducting quantum chip wiring path optimization device 400 based on the line segment line algorithm are the same as those in the reference Figure 1 Therefore, the operations, features and beneficial effects described above for the method are also applicable to the superconducting quantum chip wiring path optimization device 400 based on the line segment line of sight algorithm and the units included therein, and will not be repeated here.

[0055] Reference below Figure 5 , which shows a schematic structural diagram of an electronic device (such as a computing device) suitable for implementing some embodiments of the present disclosure. Figure 5The electronic device shown is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure. Figure 5 As shown, the computer device includes a processor, a memory and a network interface connected via a system bus, wherein the memory may include a non-volatile storage medium and an internal memory. The non-volatile storage medium can store an operating system and a computer program. The computer program includes program instructions, which, when executed, can enable the processor to execute any method for optimizing the wiring path of a superconducting quantum chip based on a line-segment line-of-sight algorithm. The processor is used to provide computing and control capabilities to support the operation of the entire computer device. The internal memory provides an environment for the operation of the computer program in the non-volatile storage medium, which, when executed by the processor, can enable the processor to execute any method for optimizing the wiring path of a superconducting quantum chip based on a line-segment line-of-sight algorithm. The network interface is used for network communication, such as sending assigned tasks, etc. Those skilled in the art will understand that Figure 5 The structure shown in the figure is only a block diagram of a part of the structure related to the scheme of the present disclosure, and does not constitute a limitation on the computer device to which the scheme of the present disclosure is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0056] It should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0057] In one embodiment, the processor is configured to execute a computer program stored in a memory to implement the following steps: converting a list of obstacle polygon vertices corresponding to a superconducting quantum chip wiring diagram into geometric objects in a target library; establishing a query mechanism for each of the converted obstacle polygons using a spatial index result; starting from a current path point, extending backward along an original path to construct a straight line segment, wherein the original path is an initial wiring path corresponding to the superconducting quantum chip wiring diagram; determining the shortest distance between the straight line segment and each obstacle polygon, and determining whether the shortest distance is greater than or equal to a preset cache distance; determining that the straight line segment is safe in response to determining that the shortest distance is greater than or equal to the preset cache distance; expanding the obstacle polygon corresponding to the shortest distance outward according to the preset cache distance to generate a buffer zone; detecting whether there is an intersection between the straight line segment and the buffer zone, and in response to determining that there is no intersection between the straight line segment and the buffer zone, simplifying the initial wiring path starting from the current path point using a forward-leaping greedy algorithm to generate a simplified wiring path; and performing multi-objective optimization on the simplified wiring path according to a parameterized weight tuning function to generate an optimized wiring path.

[0058] An embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored. The computer program includes program instructions. The method implemented when the program instructions are executed can refer to the various embodiments of the superconducting quantum chip wiring path optimization method based on the line segment line algorithm disclosed in the present disclosure.

[0059] The computer-readable storage medium may be an internal storage unit of the computer device described in the aforementioned embodiment, such as a hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, a SmartMedia Card (SMC), a Secure Digital (SD) card, a flash memory card, etc., provided on the computer device.

[0060] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or system comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or system. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or system comprising the element.

[0061] The above descriptions are merely some preferred embodiments of the present disclosure and illustrate the underlying technical principles. Those skilled in the art should understand that the scope of the invention encompassed by the embodiments of the present disclosure is not limited to technical solutions formed by specific combinations of the aforementioned technical features. It also encompasses other technical solutions formed by any combination of the aforementioned technical features or their equivalents, without departing from the aforementioned inventive concept. For example, a technical solution formed by replacing the aforementioned features with (but not limited to) technical features with similar functions disclosed in the embodiments of the present disclosure.

Claims

1. A superconducting quantum chip wiring path optimization method based on line segment line of sight algorithm, characterized in that: include: Convert the obstacle polygon vertex list corresponding to the superconducting quantum chip wiring diagram into a geometric object in the target library; Using the spatial index results, a query mechanism is established for each transformed obstacle polygon; Starting from the current path point, extend backward along the original path to construct a straight line segment, where the original path is the initial wiring path corresponding to the superconducting quantum chip wiring diagram; Determining the shortest distance between the straight line segment and each obstacle polygon, and determining whether the shortest distance is greater than or equal to a preset cache distance; In response to determining that the shortest distance is greater than or equal to the preset cache distance, determining that the straight line segment is safe; According to the preset cache distance, the obstacle polygon corresponding to the shortest distance is expanded outward to generate a buffer zone; detecting whether there is an intersection between the straight line segment and the buffer zone, and in response to determining that there is no intersection between the straight line segment and the buffer zone, simplifying the initial routing path starting from the current path point using a forward skipping greedy algorithm to generate a simplified routing path; According to the parameterized weight tuning function, a multi-objective optimization process is performed on the simplified wiring path to generate an optimized wiring path.

2. The method according to claim 1, characterized in that The forward skipping greedy algorithm is used to simplify the initial routing path starting from the current path point to generate a simplified routing path, including: Starting from the original path starting point P0, set the current point index i=0; Take the current path point P i As a benchmark, detect point P according to the reverse priority principle (i+2) , click P (i+3) ,…, point P (n-1) visibility; In response to detecting point P j If it is not visible, stop detecting subsequent points and record the farthest visible point P that can be reached. jmax , the farthest visible point P jmax Join the smooth path and update the current point index i=jmax.

3. The method according to claim 2, characterized in that The method adopts a forward skipping greedy algorithm to simplify the initial routing path starting from the current path point to generate a simplified routing path, and further includes: At the end of the smooth path, check whether the end point P is included. end ; If the endpoint P is detected end If missing, append to the end of the smoothed path.

4. The method according to claim 3, characterized in that The multi-objective optimization process is performed on the simplified wiring path according to the parameterized weight tuning function to generate an optimized wiring path, including: The simplified routing path is subjected to multi-objective optimization through the following parameterized weight tuning function: ， in, represents the control path length weight, Indicates the adjustment of collision risk cost. For highly sensitive signal lines, set ≫ , to prioritize security; for paths with low latency requirements, increase To shorten the overall length, Indicates the current path point P i The corresponding shortest distance.

5. A superconducting quantum chip wiring path optimization device based on line segment line of sight algorithm, characterized in that: include: a conversion unit configured to convert a list of obstacle polygon vertices corresponding to the superconducting quantum chip wiring diagram into a geometric object of a target library; An establishment unit is configured to establish a query mechanism for each transformed obstacle polygon using the spatial index result; an extension unit configured to extend backward along an original path starting from a current path point to construct a straight line segment, wherein the original path is an initial wiring path corresponding to the wiring diagram of the superconducting quantum chip; a first determining unit configured to determine the shortest distance between the straight line segment and each obstacle polygon, and determine whether the shortest distance is greater than or equal to a preset cache distance; a second determining unit configured to determine that the straight line segment is safe in response to determining that the shortest distance is greater than or equal to a preset cache distance; A generating unit is configured to expand the obstacle polygon corresponding to the shortest distance outward according to a preset cache distance to generate a buffer zone; a simplification unit configured to detect whether there is an intersection between the straight line segment and the buffer zone, and in response to determining that there is no intersection between the straight line segment and the buffer zone, simplify the initial routing path starting from the current path point using a forward skipping greedy algorithm to generate a simplified routing path; The optimization unit is configured to perform multi-objective optimization processing on the simplified routing path according to a parameterized weight tuning function to generate an optimized routing path.

6. An electronic device, characterized in that: include: one or more processors; a storage device having one or more programs stored thereon; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 4.

7. A computer-readable medium, characterized in that A computer program is stored thereon, wherein when the computer program is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

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