Superconducting quantum chip wiring path optimization method and device based on RDP algorithm

Abstract

The embodiment of the invention discloses a superconducting quantum chip wiring path optimization method and device based on an RDP algorithm. A specific embodiment of the method comprises the following steps: simplifying an initial wiring path in a superconducting quantum chip wiring diagram through an RDP recursive algorithm to obtain a simplified wiring path; carrying out collinear point identification on the simplified wiring path, and optimizing the simplified wiring path; for each line segment in the optimized wiring path, executing the following processing steps: in response to determining that a global minimum distance corresponding to the line segment is greater than or equal to a preset safety buffer distance, determining the line segment as a compliant line segment; and performing line segment safety verification on the optimized wiring path, and determining the optimized wiring path as a target optimized wiring path in response to the fact that the optimized wiring path passes the safety verification. According to the implementation mode, through iterative collinear point elimination, the curvature change rate smoothness of a wiring path is improved, and the requirement for low-impedance connection between superconducting quantum bits is met.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of superconducting quantum chip wiring path optimization, and more particularly to a method and apparatus for superconducting quantum chip wiring path optimization based on the RDP algorithm. Background Art

[0002] In the field of superconducting quantum chip wiring technology, existing research has not yet paid sufficient attention to the critical impact of path geometry on the performance of quantum devices. Traditional wiring schemes mostly follow the path planning ideas of classical integrated circuits, with only physical connectivity as the design goal, and no dedicated optimization model is established for the unique electromagnetic sensitivity of superconducting quantum systems. This technological gap leads to unnecessary topological twists in the wiring path, and the parasitic inductance effect caused by it will significantly reduce the coherence time of the quantum bit, while the local electromagnetic radiation interference at the turning point of the path is more likely to destroy the stability of adjacent quantum states. Especially in the wiring of multi-qubit arrays, unoptimized redundant path structures will aggravate microwave signal crosstalk, resulting in a decrease in the fidelity of quantum gate operations. The current technology system lacks a systematic method to couple path geometry smoothness, electromagnetic compatibility and superconducting material properties. It is difficult to simultaneously meet the multi-dimensional requirements of low-loss transmission, enhanced anti-interference and process manufacturability under complex wiring constraints. This has become a core bottleneck problem restricting the performance improvement of large-scale superconducting quantum chips. Summary of the Invention

[0003] The content of this disclosure is used to briefly introduce concepts that will be described in detail in the detailed description section below. The content of this disclosure is not intended to identify key features or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0004] Some embodiments of the present disclosure propose a superconducting quantum chip wiring path optimization method, device, electronic device and computer-readable medium based on the RDP algorithm to solve the technical problems mentioned in the above background technology section.

[0005] In a first aspect, some embodiments of the present disclosure provide a superconducting quantum chip wiring path optimization method based on an RDP algorithm, the method comprising: pre-processing obstacle polygons in a superconducting quantum chip wiring diagram to obtain a set of valid obstacle polygons; simplifying an initial wiring path in the superconducting quantum chip wiring diagram using an RDP recursive algorithm to obtain a simplified wiring path; identifying collinear points on the simplified wiring path based on vector angle analysis, and optimizing the simplified wiring path to obtain an optimized wiring path; performing the following processing steps for each line segment in the optimized wiring path: determining a minimum distance between the line segment and each valid obstacle polygon in the set of valid obstacle polygons; determining the line segment as a compliant line segment in response to determining that the global minimum distance corresponding to the line segment is greater than or equal to a preset safety buffer distance; determining the line segment as a noncompliant line segment in response to determining that the global minimum distance corresponding to the line segment is less than the preset safety buffer distance; performing line segment security verification on the optimized wiring path, and determining the optimized wiring path as a target optimized wiring path in response to the optimized wiring path passing the security verification.

[0006] In a second aspect, some embodiments of the present disclosure provide a superconducting quantum chip wiring path optimization device based on the RDP algorithm, the device comprising: a preprocessing unit configured to identify and preprocess obstacle polygons in a superconducting quantum chip wiring diagram to obtain a set of valid obstacle polygons; a simplification unit configured to simplify the initial wiring path in the superconducting quantum chip wiring diagram using the RDP recursive algorithm to obtain a simplified wiring path; an optimization unit configured to identify collinear points on the simplified wiring path based on vector angle analysis, and optimize the simplified wiring path to obtain an optimized wiring path; a line segment determination unit , configured to perform the following processing steps for each line segment in the optimized routing path: determining the minimum distance between the line segment and each valid obstacle polygon in the set of valid obstacle polygons; in response to determining that the global minimum distance corresponding to the line segment is greater than or equal to a preset safety buffer distance, determining the line segment as a compliant line segment; in response to determining that the global minimum distance corresponding to the line segment is less than a preset safety buffer distance, determining the line segment as an illegal line segment; a verification unit, configured to perform line segment security verification on the optimized routing path, and in response to the optimized routing path passing the security verification, determining the optimized routing path as a target optimized routing path.

[0007] In a third aspect, some embodiments of the present disclosure provide an electronic device comprising: one or more processors; a storage device on which one or more programs are stored, and when the one or more programs are executed by one or more processors, the one or more processors implement the method described in any implementation of the first aspect above.

[0008] In a fourth aspect, some embodiments of the present disclosure provide a computer-readable medium having a computer program stored thereon, wherein when the program is executed by a processor, the method described in any implementation of the first aspect is implemented.

[0009] The above-mentioned embodiments of the present disclosure have the following beneficial effects: Through the RDP algorithm-based superconducting quantum chip wiring path optimization method of some embodiments of the present disclosure, the RDP algorithm and multi-stage post-processing collaborative mechanism are used to reduce the density of path turning points while maintaining the quantum safety distance constraint; a correlation model between path geometry and quantum state stability is established, and redundant turning points that cause parasitic inductance effects are eliminated through dynamic angle threshold control, thereby reducing microwave signal transmission loss; intermediate points close to collinearity (angles close to 180 degrees) are dynamically eliminated. Local safety reviews are performed on necessary turning points to ensure that the path after collinearity optimization still meets the full-segment obstacle avoidance constraint; and through iterative collinear point elimination, the curvature change rate of the wiring path is smoothed, meeting the low-impedance connection requirements between superconducting quantum bits. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features, advantages, and aspects of the various embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and that components and elements are not necessarily drawn to scale.

[0011] Figure 1 is a flowchart of some embodiments of a superconducting quantum chip wiring path optimization method based on the RDP algorithm according to the present disclosure; Figure 2 This is a schematic diagram of an initial wiring path in a superconducting quantum chip wiring path optimization method based on an RDP algorithm in some embodiments of the present disclosure; Figure 3 This is a schematic diagram of a target optimized wiring path in a superconducting quantum chip wiring path optimization method based on an RDP algorithm in some embodiments of the present disclosure; Figure 4 Schematic diagram of the structure of some embodiments of the superconducting quantum chip wiring path optimization device based on the RDP algorithm according to the present disclosure; Figure 5 It is a structural diagram of an electronic device suitable for implementing some embodiments of the present disclosure. DETAILED DESCRIPTION

[0012] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein. On the contrary, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0013] It should also be noted that, for ease of description, only the parts related to the invention are shown in the drawings. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0014] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0015] It should be noted that the modifications of "one" and "multiple" mentioned in the present disclosure are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, they should be understood as "one or more".

[0016] The names of the messages or information exchanged between multiple devices in the embodiments of the present disclosure are only used for illustrative purposes and are not used to limit the scope of these messages or information.

[0017] The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0018] Figure 1 This is a process 100 of some embodiments of the method for optimizing the wiring path of a superconducting quantum chip based on the RDP algorithm in some embodiments of the present disclosure. The method for optimizing the wiring path of a superconducting quantum chip based on the RDP algorithm includes the following steps: Step 101: perform identification preprocessing on obstacle polygons in the superconducting quantum chip wiring diagram to obtain a set of valid obstacle polygons.

[0019] In some embodiments, the execution subject (e.g., a computing device) of the superconducting quantum chip wiring path optimization method based on the RDP algorithm can identify and preprocess the obstacle polygons in the superconducting quantum chip wiring diagram to obtain a set of valid obstacle polygons. As an example, the input obstacle polygons are preprocessed. First, polygons containing at least three vertices are screened out and then converted into standard geometric objects. For invalid geometric shapes (such as self-intersecting polygons) found during the conversion process, a buffer technology (buffer(0)) is applied for automatic repair. If the geometry is still invalid or empty after repair, the obstacle is removed from the processing list. Finally, a set containing all valid polygons is established to provide a basis for subsequent distance calculations and spatial queries.

[0020] The parameter configurations of the paths, obstacles, and safety distances after wiring the superconducting quantum chip are shown in Table 1 below: Table 1 Field Name Data Type illustrate path List Redundant polyline paths, including multiple intermediate points polygons List Obstacles are a list of regions consisting of polygonal vertices buffer_distance Float Safe distance to prevent wiring signal interference Step 102: Simplify the initial wiring path in the superconducting quantum chip wiring diagram using an RDP recursive algorithm to obtain a simplified wiring path.

[0021] In some embodiments, the execution subject can simplify the initial wiring path in the superconducting quantum chip wiring diagram through the RDP recursive algorithm to obtain a simplified wiring path. Figure 2 As shown, Figure 2 The blue line in the example is the initial routing path. The RDP recursive algorithm may refer to a recursive RDP (Ramer-Douglas-Peucker) algorithm.

[0022] The initial routing path is usually a series of consecutive points generated by a path planning algorithm (such as A* search) to form a line from the starting point to the end point. The path contains multiple points: the starting point, the end point, and several intermediate points.

[0023] The relationship between the path and polygons (obstacles) is: 1. The path needs to avoid all obstacles; 2. The path should maintain a certain safe distance (buffer_distance) from obstacles; 3. The goal of path optimization is to reduce inflection points while ensuring the safe distance constraint.

[0024] In practice, the execution entity may simplify the initial wiring path in the superconducting quantum chip wiring diagram by the following steps: The first step is to connect the starting point and the end point of the initial wiring path to obtain a connecting straight line.

[0025] The second step is to determine the vertical distance from each intermediate point in the initial wiring path to the connecting straight line.

[0026] In a third step, in response to determining that the vertical distances from all the intermediate points to the connecting straight line are less than a preset threshold, the connecting straight line is determined as a simplified wiring path.

[0027] In the fourth step, in response to determining that there is a vertical distance greater than a preset threshold among the vertical distances from all intermediate points to the connecting straight line, the point corresponding to the maximum vertical distance among the vertical distances is determined as a split point to split the initial wiring path into two segments, and the two segments are simplified by the RDP recursive algorithm to obtain a simplified wiring path.

[0028] As an example, the simplification intensity is controlled by setting a distance threshold, epsilon. This RDP recursive algorithm first connects the start and end points of a path (the initial routing path) to form a straight line, then calculates the perpendicular distance from each intermediate point on the path to the straight line. If the distance from all points to the straight line is less than the threshold, epsilon, the original path segment is directly replaced by the straight line. Otherwise, the point with the largest distance is selected as the split point, dividing the path into two segments, and recursively applying the same simplification process to each segment. This method can preserve the key feature points in the path while significantly reducing redundant intermediate points.

[0029] Step 103 : Based on vector angle analysis, identify collinear points on the simplified routing path, and optimize the simplified routing path to obtain an optimized routing path.

[0030] In some embodiments, the execution entity may identify collinear points on the simplified routing path based on vector angle analysis, and optimize the simplified routing path to obtain an optimized routing path.

[0031] Vector angle analysis can mean calculating the angle between vector V1 (P1→P2) and vector V2 (P2→P3) for any three consecutive points P1, P2, and P3. The angle calculation formula is: θ = arccos((V1·V2) / (|V1|·|V2|)), where V1·V2 represents the vector dot product, and |V1| and |V2| represent the vector moduli. The result is converted to an angle for subsequent collinearity determination. When the angle between two vectors approaches 180 degrees, the three points are nearly collinear, and the middle point may be redundant.

[0032] In practice, the execution entity may identify collinear points on the simplified wiring path through the following steps: In the first step, for any three consecutive points in the simplified routing path, the angle between the first vector and the second vector is calculated. The three consecutive points include: point P1, point P2, point P3, the first vector is: P1→P2, and the second vector is: P2→P3.

[0033] In the second step, in response to the angle between the two vectors formed by any three consecutive points in the simplified routing path being greater than an angle threshold, the three consecutive points are determined to be collinear points. In response to the distance between the first and last points of the three consecutive points being greater than a safe distance, the middle point of the three consecutive points is removed. As an example, an angle threshold (such as 170 degrees) is set. When the angle between the two vectors formed by the three consecutive points is greater than the threshold, the points are determined to be approximately collinear. In the case of collinearity, further verification is performed to determine whether directly connecting the first and last points meets the safety distance requirement. If so, the middle point is removed; if not, it is retained to ensure path safety. This step can effectively eliminate unnecessary inflection points in the path, making the path smoother and more natural.

[0034] Step 104: For each line segment in the optimized routing path, perform the following processing steps: Step 1041: Determine the minimum distance between the line segment and each valid obstacle polygon in the valid obstacle polygon set.

[0035] In some embodiments, the execution entity may determine the minimum distance between the line segment and each valid obstacle polygon in the set of valid obstacle polygons. For example, the Shapely library may be used to calculate the shortest Euclidean distance between a LineString (a line segment of a path) and a Polygon (an obstacle polygon).

[0036] Step 1042 : In response to determining that the global minimum distance corresponding to the line segment is greater than or equal to a preset safety buffer distance, the line segment is determined to be a compliant line segment.

[0037] In some embodiments, the execution entity may determine the line segment as a compliant line segment in response to determining that the global minimum distance corresponding to the line segment is greater than or equal to a preset safety buffer distance. The global minimum distance may be the minimum value of the minimum distances corresponding to the line segment.

[0038] Step 1043 : In response to determining that the global minimum distance corresponding to the line segment is less than the preset safety buffer distance, the line segment is determined as a violation line segment.

[0039] In some embodiments, the execution entity may determine the line segment as a violation line segment in response to determining that the global minimum distance corresponding to the line segment is less than a preset safety buffer distance.

[0040] Step 105 : performing line segment security verification on the optimized routing path, and in response to the optimized routing path passing the security verification, determining the optimized routing path as a target optimized routing path.

[0041] In some embodiments, the execution entity may perform line segment security verification on the optimized routing path, and in response to the optimized routing path passing the security verification, determine the optimized routing path as a target optimized routing path.

[0042] In practice, the execution entity may perform line segment security verification on the optimized wiring path through the following steps: The first step is to determine whether there is any illegal line segment among the line segments included in the optimized routing path.

[0043] In the second step, in response to the existence of the illegal line segment, the simplified routing path is used as the optimized routing path and security verification is performed again.

[0044] Optionally, in response to the re-security verification failing, the initial wiring path is simplified again.

[0045] As an example, the optimized path undergoes full safety verification. If verification passes, the optimized path is directly adopted as the final output. If a safety distance violation is detected, an adaptive fallback mechanism is activated. The fallback mechanism first attempts a path constructed using key feature points simplified by the RDP algorithm after line-of-sight verification. If this result still does not meet safety requirements, it further falls back to the original path. This multi-level fallback strategy ensures the algorithm's robustness in various complex environments, consistently outputting a path solution that meets safety requirements.

[0046] Optionally, a quantitative evaluation mechanism for path smoothing effectiveness can be established, including metrics such as point reduction rate, minimum safe clearance, and path length change. By comparing the differences between the original and optimized paths on these metrics, the smoothing effect can be quantitatively evaluated. Detailed processing feedback is also provided, including point changes at each optimization stage, safe clearance status, and whether the fallback mechanism was triggered, to help users understand the algorithm's working process and effectiveness.

[0047] As an example, suppose the original path has 20 points and after optimization: 1. Point reduction: from 20 points to 8 points (point reduction rate of 60%); 2. Minimum safety clearance: The minimum clearance of the original path was 4.5 units, and after optimization it was 4.3 units (larger than the safety distance requirement of 4.0 units); 3. Path length: The original path length was 150 units, and after optimization it was 148 units (a decrease of approximately 1.3%). Output feedback information example: Path optimization successful: reduced from 20 points to 8 points; minimum gap: 4.30>=4.00; path length change: 150.0→148.0 (reduced by 2.0 units); If the fallback mechanism is triggered, the possible output is: Warning: The smoothed path does not meet the safety distance requirement (minimum clearance: 3.75 < 4.00) Falling back to RDP result: 12 points, minimum gap: 4.15.

[0048] Optionally, improve the algorithm's boundary condition handling mechanism to ensure stable operation under various extreme conditions. For paths with too few points (e.g., containing only two points or fewer), simply return to the original path without further processing. For abnormal conditions that may arise during geometric calculations, such as division by zero errors and failed geometric object creation, implement a reasonable exception capture and handling strategy to ensure that the algorithm does not completely crash due to local failures.

[0049] Optionally, an adaptive adjustment mechanism for key parameters is implemented so that the algorithm can automatically adjust its working mode according to the specific scene characteristics. The main parameters include the epsilon threshold of the RDP algorithm, the angle threshold for collinearity determination, the safety distance buffer value, etc. By analyzing factors such as the complexity of the path, the density of obstacle distribution, and the requirements of the application scenario, these parameters are dynamically adjusted to achieve the best smoothing effect while ensuring safety. After the optimization is completed, Figure 3 shown.

[0050] Further references Figure 4 As an implementation of the methods shown in the above figures, the present disclosure provides some embodiments of a superconducting quantum chip wiring path optimization device based on the RDP algorithm. These device embodiments are similar to Figure 1 Corresponding to the method embodiments shown, the superconducting quantum chip wiring path optimization device based on the RDP algorithm can be specifically applied to various electronic devices.

[0051] like Figure 4As shown, in some embodiments, a superconducting quantum chip wiring path optimization device 400 based on the RDP algorithm includes: a preprocessing unit 401, a simplification unit 402, an optimization unit 403, a line segment determination unit 404, and a verification unit 405. The preprocessing unit 401 is configured to identify and preprocess obstacle polygons in the superconducting quantum chip wiring diagram to obtain a set of valid obstacle polygons; the simplification unit 402 is configured to simplify the initial wiring path in the superconducting quantum chip wiring diagram using the RDP recursive algorithm to obtain a simplified wiring path; the optimization unit 403 is configured to identify collinear points on the simplified wiring path based on vector angle analysis, and optimize the simplified wiring path to obtain an optimized wiring path; the line segment determination unit 404 is configured to identify collinear points in the optimized wiring path. For each line segment, the following processing steps are performed: determining the minimum distance between the line segment and each valid obstacle polygon in the set of valid obstacle polygons; in response to determining that the global minimum distance corresponding to the line segment is greater than or equal to the preset safety buffer distance, determining the line segment as a compliant line segment; in response to determining that the global minimum distance corresponding to the line segment is less than the preset safety buffer distance, determining the line segment as an illegal line segment; the verification unit 405 is configured to perform line segment security verification on the optimized routing path, and in response to the optimized routing path passing the security verification, determining the optimized routing path as the target optimized routing path.

[0052] It is understandable that the various units recorded in the superconducting quantum chip wiring path optimization device 400 based on the RDP algorithm are similar to those in the reference Figure 1 Therefore, the operations, features and beneficial effects described above for the method are also applicable to the superconducting quantum chip wiring path optimization device 400 based on the RDP algorithm and the units included therein, and will not be repeated here.

[0053] Reference below Figure 5 , which shows a schematic structural diagram of an electronic device (such as a computing device) suitable for implementing some embodiments of the present disclosure. Figure 5 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure. Figure 5As shown, the computer device includes a processor, a memory and a network interface connected via a system bus, wherein the memory may include a non-volatile storage medium and an internal memory. The non-volatile storage medium can store an operating system and a computer program. The computer program includes program instructions, which, when executed, can enable the processor to execute any method for optimizing the wiring path of a superconducting quantum chip based on the RDP algorithm. The processor is used to provide computing and control capabilities to support the operation of the entire computer device. The internal memory provides an environment for the operation of the computer program in the non-volatile storage medium, which, when executed by the processor, can enable the processor to execute any method for optimizing the wiring path of a superconducting quantum chip based on the RDP algorithm. The network interface is used for network communication, such as sending assigned tasks, etc. Those skilled in the art will understand that Figure 5 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present disclosure, and does not constitute a limitation on the computer device to which the solution of the present disclosure is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0054] It should be understood that the processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0055] In one embodiment, the processor is configured to execute a computer program stored in a memory to implement the following steps: performing identification preprocessing on obstacle polygons in a superconducting quantum chip wiring diagram to obtain a set of valid obstacle polygons; simplifying an initial wiring path in the superconducting quantum chip wiring diagram using an RDP recursive algorithm to obtain a simplified wiring path; identifying collinear points on the simplified wiring path based on vector angle analysis, and optimizing the simplified wiring path to obtain an optimized wiring path; and performing the following processing steps for each line segment in the optimized wiring path: determining a minimum distance between the line segment and each valid obstacle polygon in the set of valid obstacle polygons; determining the line segment as a compliant line segment in response to determining that the global minimum distance corresponding to the line segment is greater than or equal to a preset safety buffer distance; determining the line segment as a noncompliant line segment in response to determining that the global minimum distance corresponding to the line segment is less than the preset safety buffer distance; performing line segment security verification on the optimized wiring path, and determining the optimized wiring path as a target optimized wiring path in response to the optimized wiring path passing the security verification.

[0056] An embodiment of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored. The computer program includes program instructions. The method implemented when the program instructions are executed can refer to the various embodiments of the superconducting quantum chip wiring path optimization method based on the RDP algorithm disclosed in the present disclosure.

[0057] The computer-readable storage medium may be an internal storage unit of the computer device described in the aforementioned embodiment, such as a hard disk or memory of the computer device. The computer-readable storage medium may also be an external storage device of the computer device, such as a plug-in hard disk, a SmartMedia Card (SMC), a Secure Digital (SD) card, a flash memory card, etc., provided on the computer device.

[0058] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or system comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or system. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or system comprising the element.

[0059] The above descriptions are merely some preferred embodiments of the present disclosure and illustrate the underlying technical principles. Those skilled in the art should understand that the scope of the invention encompassed by the embodiments of the present disclosure is not limited to technical solutions formed by specific combinations of the aforementioned technical features. It also encompasses other technical solutions formed by any combination of the aforementioned technical features or their equivalents, without departing from the aforementioned inventive concept. For example, a technical solution formed by replacing the aforementioned features with (but not limited to) technical features with similar functions disclosed in the embodiments of the present disclosure.

Claims

1. A superconducting quantum chip wiring path optimization method based on the RDP algorithm, characterized in that: include: Perform identification and preprocessing on obstacle polygons in the wiring diagram of the superconducting quantum chip to obtain a set of valid obstacle polygons; Simplifying the initial wiring path in the superconducting quantum chip wiring diagram using an RDP recursive algorithm to obtain a simplified wiring path; Based on vector angle analysis, collinearity points are identified on the simplified wiring path, and the simplified wiring path is optimized to obtain an optimized wiring path; For each line segment in the optimized routing path, the following processing steps are performed: Determining the minimum distance between the line segment and each valid obstacle polygon in the set of valid obstacle polygons; In response to determining that the global minimum distance corresponding to the line segment is greater than or equal to the preset safety buffer distance, determining the line segment as a compliant line segment; In response to determining that the global minimum distance corresponding to the line segment is less than a preset safety buffer distance, determining the line segment as a violation line segment; A line segment safety verification is performed on the optimized routing path, and in response to the optimized routing path passing the safety verification, the optimized routing path is determined as a target optimized routing path.

2. The method according to claim 1, characterized in that The performing line segment security verification on the optimized wiring path includes: Determining whether there are any illegal line segments among the line segments included in the optimized routing path; In response to the presence of a violation line segment, the simplified routing path is used as the optimized routing path and safety verification is performed again.

3. The method according to claim 2, characterized in that The method further comprises: In response to the re-security verification failing, the initial wiring path is simplified again.

4. The method according to claim 3, characterized in that The method of simplifying the initial wiring path in the superconducting quantum chip wiring diagram by using the RDP recursive algorithm to obtain a simplified wiring path includes: Connecting the starting point and the end point of the initial wiring path to obtain a connecting straight line; Determining the vertical distance from each intermediate point in the initial wiring path to the connecting straight line; In response to determining that the vertical distances from all the intermediate points to the connecting straight line are less than a preset threshold, determining the connecting straight line as a simplified wiring path; In response to determining that there is a vertical distance greater than a preset threshold among the vertical distances from all the intermediate points to the connecting straight line, the point corresponding to the maximum vertical distance among the vertical distances is determined as a split point to split the initial wiring path into two segments, and the two segments are simplified by the RDP recursive algorithm to obtain a simplified wiring path.

5. The method according to claim 4, characterized in that The identifying of collinear points on the simplified wiring path based on vector angle analysis includes: For any three consecutive points in the simplified routing path, calculate the angle between the first vector and the second vector, wherein the three consecutive points include: point P1, point P2, point P3, the first vector is: P1→P2, and the second vector is: P2→P3; In response to the angle between two vectors formed by any three consecutive points in the simplified wiring path being greater than an angle threshold, the three consecutive points are determined as collinear points, and in response to the distance between the first and last points of the three consecutive points being greater than a safety distance, the middle point of the three consecutive points is removed.

6. A superconducting quantum chip wiring path optimization device based on the RDP algorithm, characterized in that: include: a preprocessing unit configured to perform identification preprocessing on obstacle polygons in the superconducting quantum chip wiring diagram to obtain a valid obstacle polygon set; A simplification unit is configured to simplify an initial wiring path in the superconducting quantum chip wiring diagram by using an RDP recursive algorithm to obtain a simplified wiring path; an optimization unit configured to identify collinear points on the simplified routing path based on vector angle analysis, and optimize the simplified routing path to obtain an optimized routing path; The line segment determination unit is configured to perform the following processing steps for each line segment in the optimized routing path: determining the minimum distance between the line segment and each valid obstacle polygon in the set of valid obstacle polygons; in response to determining that the global minimum distance corresponding to the line segment is greater than or equal to a preset safety buffer distance, determining the line segment as a compliant line segment; In response to determining that the global minimum distance corresponding to the line segment is less than a preset safety buffer distance, determining the line segment as a violation line segment; The verification unit is configured to perform line segment security verification on the optimized routing path, and in response to the optimized routing path passing the security verification, determine the optimized routing path as a target optimized routing path.

7. An electronic device, characterized in that: include: one or more processors; a storage device having one or more programs stored thereon; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 5.

8. A computer-readable medium, characterized in that A computer program is stored thereon, wherein when the computer program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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