Display panel, driving method thereof and display device

Abstract

The invention provides a display panel, a driving method thereof and a display device, and belongs to the technical field of display. The display panel has a first display mode and a second display mode. The refresh frequency of the display panel in the first display mode is smaller than that in the second display mode; the display panel comprises N shift registers and N rows of pixel units arranged in an array. The shift register is configured to provide a gate drive signal for a row of pixel units. The display panel further comprises a time schedule controller and N clock signal lines. The timing controller is configured to provide a clock signal to the shift register through the clock signal line. In the second display mode, the time schedule controller is configured to provide M clock signals for the N clock signal lines, and the difference of the rising starting time of the effective level of the M clock signals is 1H in sequence; m is smaller than N, and M and N are positive integers; wherein the clock signals received by at least part of the clock signal lines are the same.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display panel and a driving method thereof, and a display device. Background Art

[0002] The resolution of existing display panels is a fixed value, and the refresh rate can be adjusted within a certain range. However, due to the response rate limitations of the graphics card and timing controller (Tcon), the maximum refresh rate that a panel with a fixed resolution can achieve is fixed. However, customers currently have different demands for display panels. For example, when watching movies, a higher resolution is required to improve image quality, and the refresh rate is not required to be high; when playing games, a higher refresh rate is required to improve game smoothness, and the resolution is not required to be high. Based on the above problems, the inventors propose a display panel with multiple display modes, each with a different resolution and refresh rate, which users can choose according to their needs. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art and provides a display panel and a driving method thereof, and a display device.

[0004] In a first aspect, the present disclosure provides a display panel having a first display mode and a second display mode; the refresh frequency of the display panel in the first display mode is lower than the refresh frequency in the second display mode; the display panel includes a gate drive circuit and pixel units arranged in an array; the gate drive circuit includes N shift registers; the shift registers are configured to provide gate drive signals for a row of the pixel units;

[0005] The display panel further includes a timing controller and N clock signal lines; the timing controller is configured to provide a clock signal to the shift register through the clock signal lines, and the starting time of the effective level of each clock signal is sequentially different by 1H, where H is a unit scanning time;

[0006] In the second display mode, the timing controller is configured to provide M clock signals for the N clock signal lines, and the starting time of the rise of the effective levels of the M clock signals differs by 1H respectively; M is less than N, and M and N are both positive integers; wherein, the clock signals received by at least some of the clock signal lines are the same.

[0007] In some embodiments, in the first display mode, the timing controller is configured to provide N clock signals corresponding to each of the N clock signal lines, and the starting time of the rising effective levels of the N clock signals differs by 1H, where H is the unit scanning time.

[0008] In some embodiments, the gate drive circuit includes at least one gate drive sub-circuit; the gate drive sub-circuit includes 6n cascaded shift registers, where n is a positive integer; the 6n shift registers in each gate drive sub-circuit are connected to the 6n clock signal lines in a one-to-one correspondence;

[0009] For the gate driving circuit, the i-th shift register and the i+6n-th shift register are connected to the same clock signal line; i is N-6n.

[0010] In some embodiments, in the second display mode, for the gate driving sub-circuit, the timing controller is configured to provide 4n clock signals to the 6n clock signal lines, and the starting times of the effective levels of the 4n clock signals are sequentially different by 1H, where H is a unit scanning time;

[0011] The clock signal received by the i-th clock signal line and the (i+1)-th clock signal line is the same; i=3j-2, j is a positive integer.

[0012] In some embodiments, in the second display mode, for the gate driving sub-circuit, the timing controller is configured to provide 3n clock signals to the 6n clock signal lines, and the starting times of the effective levels of the 3n clock signals are sequentially different by 1H, where H is a unit scanning time;

[0013] The clock signal received by the i-th clock signal line and the (i+1)-th clock signal line is the same; i=2j-1, j is a positive integer.

[0014] In some embodiments, for the 6n shift registers in the gate drive subcircuit, the signal input ends of the 1st to 3nth shift registers are connected to the clock signal line that transmits the frame start signal; the signal output end of the ath shift register is connected to the signal input end of the a+3nth shift register; the reset signal end of the ath shift register is connected to the signal output end of the a+3nth shift register; 1≤a≤3n, and a is an integer.

[0015] In some embodiments, the gate drive subcircuit includes a first shift register group and a second shift register group that are alternately cascaded; one of the first shift register group and the second shift register group includes the odd-numbered shift registers, and the other includes the even-numbered shift registers.

[0016] In some embodiments, the display panel further includes a signal generator; the signal generator is configured to send a first control signal to the timing controller when the user selects the first display mode, and to send a second control signal to the timing controller when the user selects the second display mode.

[0017] In some embodiments, the duty cycle of the clock signal is 50%.

[0018] In a second aspect, the present disclosure provides a method for driving a display panel, wherein the display panel has a first display mode and a second display mode; the refresh frequency of the display panel in the first display mode is lower than the refresh frequency in the second display mode; the display panel includes a gate drive circuit and pixel units arranged in an array; the gate drive circuit includes N shift registers; the shift registers are configured to provide gate drive signals for a row of the pixel units;

[0019] The display panel further includes a timing controller and N clock signal lines; the timing controller is configured to provide a clock signal to the shift register through the clock signal lines, and the starting time of the effective level of each clock signal is sequentially different by 1H, where H is a unit scanning time;

[0020] The driving method includes: in the second display mode, the timing controller provides M clock signals for the N clock signal lines, and the starting times of the rising effective levels of the M clock signals differ by 1H respectively; M is less than N, and M and N are both positive integers; wherein, the clock signals received by at least some of the clock signal lines are the same.

[0021] In a third aspect, the present disclosure provides a display device comprising the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A schematic diagram of the structure of the shift register provided by the present disclosure;

[0023] Figure 2 for Figure 1 Timing diagram of the shift register;

[0024] Figures 3a-3c A circuit cascade diagram of a gate drive sub-circuit provided by the present disclosure;

[0025] Figure 4a This is a timing signal diagram provided by the timing controller of the present disclosure for the 6clk circuit in the first display mode;

[0026] Figure 4b A timing signal diagram provided by the timing controller of the present disclosure for the 6clk circuit in the second display mode;

[0027] Figure 5a This is a timing signal diagram provided by the timing controller of the present disclosure for the 12clk circuit in the first display mode;

[0028] Figure 5b A timing signal diagram provided by the timing controller of the present disclosure for the 12clk circuit in the second display mode;

[0029] Figure 5c This is another timing signal diagram provided by the timing controller of the present disclosure for the 12clk circuit in the second display mode. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0031] Unless otherwise defined, the technical or scientific terms used in this application should have the ordinary meaning understood by a person of ordinary skill in the technical field to which this application belongs. The words "one", "a", "the" and the like used in this application do not indicate a limit on quantity and may indicate the singular or plural. The terms "include", "comprise", "have" and any variations thereof used in this application are intended to cover non-exclusive inclusions; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units that are not listed, or may also include other steps or units that are inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The word "multiple" used in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates an "or" relationship between the preceding and following objects. The terms "first," "second," and "third" used in this application merely distinguish similar objects and do not represent a specific ordering of the objects. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships. If the absolute position of the described objects changes, the relative positional relationship may also change accordingly.

[0032] Display panels have a crucial parameter: bandwidth, which represents their overall display capabilities. The formula for calculating display panel bandwidth is: Bandwidth = Resolution × Refresh Rate. Given a given bandwidth, you can lower the resolution to achieve a higher refresh rate, resulting in a smoother experience. Alternatively, you can lower the refresh rate to achieve a higher resolution, resulting in a more detailed image and a better viewing experience. Existing technologies use a fixed resolution for display panels, and the refresh rate adjustment range is very limited, making them unsuitable for a variety of scenarios.

[0033] Based on the above problems, in the first aspect, the present disclosure provides a display panel having a first display mode and a second display mode, wherein the refresh frequency of the second display mode is greater than the refresh frequency of the first display mode, and the resolution of the second display mode is less than the resolution of the first display mode. The display panel includes a timing controller, a plurality of clock signal lines, a gate drive circuit, and a plurality of pixel units arranged in an array, the timing controller is configured to provide a frame start signal and a plurality of clock signals to the gate drive circuit through the clock signal line, and the starting time of the effective level of each clock signal differs by 1H in sequence, where H is the unit scanning time; the gate drive circuit is configured to provide a gate drive signal to the pixel unit array. The gate drive circuit includes a plurality of cascaded shift registers. Each shift register is configured to provide a gate drive signal for a row of pixel units, and the structure of the shift register is specifically as follows. Figure 1 shown.

[0034] Reference Figure 1 The shift register includes: an input module 10, an output module 20, a pull-down module 30, a reset module 40, a pull-up module 50, a pull-down control module 60 and an output control module 70.

[0035] Specifically, the input module 10 may include: a first switch element M1 , a control end of which receives an input signal, a first end of which receives a first power signal VDD, and a second end of which is connected to a pull-up node PU.

[0036] The output module 20 may include: a fourth switch element M4 , a control end of which is connected to the pull-up node PU, a first end of which receives the clock signal CLK, and a second end of which is connected to the signal output end Output.

[0037] The pull-down module 30 may include: a fifth switch element M5, whose control end is connected to the pull-down node PD, a first end receives the second power signal VGL, and a second end is connected to the signal output end Output; a sixth switch element M6, whose control end is connected to the pull-down node PD, a first end receives the second power signal VGL, and a second end is connected to the pull-up node PU.

[0038] The reset module 40 may include: a seventh switch element M7 , a control terminal of which is connected to the reset signal, a first terminal of which receives the first power signal VSS, and a second terminal of which is connected to the pull-up node PU.

[0039] The pull-up module 50 may specifically include: an eighth switch element M8, whose control end is connected to the pull-up node PU, a first end receives the second power signal VGL, and a second end is connected to the second end of the tenth switch element M10, so as to be connected to the pull-down node PD through the tenth switch element and the eleventh switch element; a ninth switch element M9, whose control end is connected to the pull-up node PU, a first end receives the second power signal VGL, and a second end is connected to the pull-down node PD.

[0040] The pull-down control module 60 may specifically include: a tenth switch element M10, whose control end and first end both receive the first voltage signal GCH, the second end is connected to the pull-down node PD, connected to the second end of the eighth switch element, and at the same time connected to the control end of the third switch element M3, so as to be connected to the pull-down node PD through the eleventh switch element; a third switch element M3, whose control end is connected to the second end of the tenth switch element, the first end receives the first voltage signal GCH, and the second end is connected to the pull-down node PD.

[0041] The output control module 70 may specifically include: a second switch element M2 , a control end of which receives the second voltage signal GCL, a first end of which receives the second power signal VGL, and a second end of which is connected to the signal output end Output.

[0042] Figure 2 for Figure 1 The timing diagram of the shift register is shown below. Figure 2 The working principle of the shift register unit that controls the timing operation to each stage is described in detail, wherein the first power signal VDD is a high-level signal, the second power signal VGL / VSS is a low-level signal, the first voltage signal GCH is a high-level signal, and the second voltage signal GCL is a low-level signal.

[0043] First, it should be noted that the first voltage signal GCH is always a high-level signal, so the tenth and eleventh switching elements remain on, and the pull-down node PD remains high, thereby keeping the fifth and sixth switching elements on.

[0044] Phase 1 t1: The input signal is a high-level signal, and the first switch element M1 is turned on under the action of the high-level input signal; when the clock signal CLK is a low-level signal, the level of the pull-up node PU is pulled up by the high-level signal at the signal input end, thereby charging the storage capacitor C1.

[0045] In the second phase t2, the input signal is low, switching element M1 is off, and pull-up node PU remains high due to the action of storage capacitor C1. Fourth switching element M4 remains on. Clock signal CLK is high, and the voltage on pull-up node PU is amplified by the bootstrap effect, ultimately transmitting the gate drive signal to the output terminal.

[0046] In the third stage t3, the reset signal is at a high level. Under the control of the high level of the reset signal, M7 is turned on, and the second power supply signal VSS is transmitted to the pull-up node PU through it. M4 is turned off. Since the first voltage signal GCH is always at a high level, the first voltage signal GCH is transmitted to the pull-down node PD through the tenth switch element M10 and the third switch element M3, thereby turning on the fifth switch element M5 and the sixth switch element M6 to transmit the second power supply signal VGL to the signal output terminal Output, so as to ensure stable output of the signal.

[0047] In the fourth stage t4, since GCH is always at a high potential and the pull-up node PU and the signal output terminal Output have been discharged through M7 in the second stage, M9 is in a closed state at this time, so the pull-down node PD will not be discharged; since GCH is at a high potential, M10 and M2 are turned on, and the potential of the pull-down node PD is pulled up, thereby turning on the discharge tubes M5 and M6 to discharge the noise of the pull-up node PU and the signal output terminal Output, so that the coupling noise voltage generated by CLK can be eliminated, thereby ensuring low-voltage output and signal output stability.

[0048] Based on the above description of the shift register's operation, it can be seen that the start time of the effective level rise of the gate drive signal output by the shift register (i.e., the time when the high-level signal output begins in the second stage t2) depends on the start time of the effective level rise of the clock signal CLK. Therefore, by controlling the clock signal CLK input to the shift register, the gate drive signal output by the shift register can be controlled. For example, by inputting the same clock signal to two cascaded shift registers, they can be controlled to output the same gate drive signal.

[0049] It should be noted that the display panel includes N rows of pixel units and N shift registers, with one shift register driving each row of pixel units. The display panel also includes a timing controller and N clock signal lines. The timing controller provides clock signals via the N clock signal lines to the N shift registers, which are connected one-to-one to the clock signal lines. To achieve switching between different display modes, the timing controller in the display panel of the present disclosure has different configurations in different display modes.

[0050] Specifically, in the first display mode, the timing controller is configured to provide N clock signals corresponding to each other for N clock signal lines, and the starting time of the rise of the effective level of the N clock signals differs by 1H in sequence; in the second display mode, the timing controller is configured to provide M clock signals for N clock signal lines, and the starting time of the rise of the effective level of the M clock signals differs by 1H in sequence. Wherein, M is less than N, and both M and N are positive integers. In particular, in the display panel in the second display mode, at least some of the clock signal lines receive the same clock signal, that is, in the second display mode, at least some of the shift registers output the same gate drive signal, so that in the display panel in the second display mode, some pixel rows can be turned on and displayed at the same time. For large-size display panels, the simultaneous display of some pixel rows means that the number of pixel rows that need to be scanned within one frame time is reduced (that is, the resolution is reduced), so the refresh frequency of the display panel can be increased to achieve the display of the second display mode (i.e., high refresh rate mode).

[0051] In some embodiments, the gate drive circuit can be divided into at least one gate drive sub-circuit, each gate drive sub-circuit includes 6n shift register units, where n is an integer. Among them, the gate drive sub-circuit can be divided into a first shift register group and a second shift register group, and the two shift register groups are respectively connected to different initial gate scan signals. Specifically, the first shift register may include 3n odd-numbered shift registers, such as the 1st shift register, the 3rd shift register, the 5th shift register unit... the 6n-1th shift register unit, and accordingly, the second shift register group includes 3n even-numbered shift register units, such as the 2nd shift register unit, the 4th shift register unit, the 6th shift register unit... the 6nth shift register unit. Of course, the first shift register group may also include even-numbered shift register units, and the second shift register group may include odd-numbered shift register units, which are not limited here.

[0052] Furthermore, the gate drive circuit includes at least one gate drive sub-circuit, each gate drive sub-circuit includes 6n cascaded shift registers, and the 6n shift registers are connected to 6n clock signal lines in a one-to-one correspondence. Preferably, the duty cycle of the clock signal is 50%. For the entire gate drive circuit, the i-th shift register and the i+6n-th shift register are connected to the same clock signal line; i is N-6n. For example, the gate drive circuit includes two gate drive sub-circuits, each gate drive sub-circuit includes 6 shift registers (i.e., n=1), that is, the gate drive circuit includes 12 cascaded shift registers. The first shift register and the seventh shift register are both connected to the first clock signal line, the second shift register and the eighth shift register are both connected to the second clock signal line, the third shift register and the ninth shift register are both connected to the third clock signal line, and so on.

[0053] In order to facilitate the description of the configuration of the timing controller after the display panel switches the display mode in the present disclosure, the following only takes one gate drive sub-circuit in the gate drive circuit as an example for explanation. It should be understood that the clock signal lines connected to different gate drive sub-circuits are the same, and the gate drive signals generated are also the same. For example, for the 12clk circuit in the above example, the 1st to 6th shift registers are respectively connected to the 1st to 6th clock signal lines, and the 7th to 12th shift registers are also respectively connected to the 1st to 6th clock signal lines. Therefore, the driving process and output drive signals of the two gate drive sub-circuits are the same, and will not be repeated below.

[0054] Figure 3a is the cascade diagram of the gate drive sub-circuit, such as Figure 3a As shown, the gate drive sub-circuit includes 6n cascaded shift registers, wherein the signal input terminals INPUT of the 1st to 3nth shift registers are connected to the clock signal line transmitting the frame start signal STV0. In response to the frame start signal STV0, the signal output terminal OUTPUT of the ath shift register is connected to the signal input terminal INPUT of the a+3nth shift register, and the reset signal terminal RESET of the ath shift register is connected to the signal output terminal OUTPUT of the a+3nth shift register, where a is an integer from 1 to 3n. In other words, for the 4th to 6nth shift registers, they respond to the output signal of the previous stage shift register, and the output signal of the current stage shift register serves as the reset signal of the corresponding previous stage shift register.

[0055] For example, when n=1, the gate drive circuit includes 6 shift registers. Figure 3bAs shown, the signal input terminals INPUT of the first to third shift registers GOA3 are connected to the clock signal line for transmitting the frame start signal; the signal output terminal OUTPUT of the first shift register GOA1 is connected to the signal input terminal INPUT of the fourth shift register GOA4, and the signal output terminal OUTPUT of the fourth shift register GOA4 is connected to the reset signal terminal RESET of the first shift register GOA1; the signal output terminal OUTPUT of the second shift register GOA2 is connected to the signal input terminal INPUT of the fifth shift register GOA5, and the signal output terminal OUTPUT of the fifth shift register GOA5 is connected to the reset signal terminal RESET of the second shift register GOA2; the signal output terminal OUTPUT of the third shift register GOA3 is connected to the signal input terminal INPUT of the sixth shift register GOA6, and the signal output terminal OUTPUT of the sixth shift register GOA6 is connected to the reset signal terminal RESET of the third shift register GOA3.

[0056] For example, when n=2, the gate drive circuit includes 12 shift registers. Figure 3cAs shown, the signal input terminals INPUT of the first to sixth shift registers GOA6 are connected to the clock signal line of the transmission frame start signal; the signal output terminal OUTPUT of the first shift register GOA1 is connected to the signal input terminal INPUT of the seventh shift register GOA7, and the signal output terminal OUTPUT of the seventh shift register GOA7 is connected to the reset signal terminal RESET of the first shift register GOA1; the signal output terminal OUTPUT of the second shift register GOA2 is connected to the signal input terminal INPUT of the eighth shift register GOA8, and the signal output terminal OUTPUT of the eighth shift register GOA8 is connected to the reset signal terminal RESET of the second shift register GOA2; the signal output terminal OUTPUT of the third shift register GOA3 is connected to the signal input terminal INPUT of the ninth shift register GOA9, and the signal output terminal OUTPUT of the ninth shift register GOA9 is connected to the signal input terminal INPUT of the third shift register GOA1. The signal output terminal OUTPUT of the fourth shift register GOA4 is connected to the signal input terminal INPUT of the tenth shift register GOA10, and the signal output terminal OUTPUT of the tenth shift register GOA10 is connected to the reset signal terminal RESET of the fourth shift register GOA4; the signal output terminal OUTPUT of the fifth shift register GOA5 is connected to the signal input terminal INPUT of the eleventh shift register GOA11, and the signal output terminal OUTPUT of the eleventh shift register GOA11 is connected to the reset signal terminal RESET of the fifth shift register GOA5; the signal output terminal OUTPUT of the sixth shift register GOA6 is connected to the signal input terminal INPUT of the twelfth shift register GOA12, and the signal output terminal OUTPUT of the twelfth shift register GOA12 is connected to the reset signal terminal RESET of the sixth shift register GOA6.

[0057] Based on the cascade structure of the above-mentioned gate driving sub-circuit, the following describes the configuration of the timing controller of the display panel in different display modes.

[0058] For a gate drive subcircuit, it includes 6n cascaded shift registers, and correspondingly connected to 6n clock signal lines. In some embodiments, in the first display mode, the timing controller is configured to provide N clock signals corresponding to each of the N clock signal lines, and the starting time of the rise of the effective level of the N clock signals is 1H apart; when the display mode is switched to the second display mode (high refresh rate), the timing controller is configured to provide 4n clock signals for the 6n clock signal lines, and the starting time of the effective level of the 4n clock signals is 1H apart. Among them, the clock signal received by the i-th clock signal line and the i+1-th clock signal line is the same; i=3j-2, j is a positive integer.

[0059] For example, when n=1, the gate drive subcircuit includes 6 cascaded shift registers and is connected to 6 clock signal lines. Figure 3b In the first display mode, the timing controller is configured to provide 6 clock signals corresponding to each of the 6 clock signal lines, and the starting time of the rise of the effective level of the 6 clock signals differs by 1H in sequence. Figure 4a Specifically, the first clock signal line CLK1 receives the first clock signal, and the first shift register GOA1 outputs the first gate drive signal G1 in response to the first clock signal, and turns on the first row of pixel units in the first unit scanning time (the first 1H); the second clock signal line CLK2 receives the second clock signal, and the second shift register GOA2 outputs the second gate drive signal G2 in response to the second clock signal, and turns on the second row of pixels in the second unit scanning time (the second 1H), and so on, until 6 gate drive signals G1 to G6 are output in sequence to turn on 6 rows of pixels in sequence.

[0060] When the display mode is switched to the second display mode, the timing controller is configured to provide 4 clock signals for 6 clock signal lines, namely the first clock signal, the second clock signal, the third clock signal and the fourth clock signal, and the starting time of the effective level of the 4 clock signals is 1H apart in sequence, referring to Figure 4b. Among them, the first clock signal line CLK1 and the second clock signal line CLK2 both receive the first clock signal, the third clock signal line CLK3 receives the second clock signal, the fourth clock signal line CLK4 and the fifth clock signal line CLK5 both receive the third clock signal, and the sixth clock signal line CLK6 receives the fourth clock signal. Correspondingly, the first shift register GOA1 and the second shift register GOA2 both output the first gate drive signal in response to the first clock signal, and turn on the first row of pixel units and the second row of pixel units in the first unit scan time (within the first 1H); the third shift register GOA3 outputs the second gate drive signal in response to the second clock signal, and turns on the third row of pixel units in the second unit scan time; the fourth shift register GOA4 and the fifth shift register GOA5 both output the third gate drive signal in response to the third clock signal, and turn on the fourth and fifth rows of pixel units in the third unit scan time; the sixth shift register GOA6 outputs the fourth gate drive signal in response to the fourth clock signal, and turns on the sixth row of pixel units in the fourth unit scan time. Compared to the first display mode, the second display mode takes two-thirds of the time to open the same number of pixel rows. Therefore, in a single frame, the refresh rate of the first display mode is 1.5 times that of the second display mode. For example, the refresh rate of the first display mode is 240Hz, and the refresh rate of the second display mode is 360Hz. It is understandable that in the above driving process, the period of the clock signal in the first display mode is 6H, and the period of the clock signal in the second display mode is 4H.

[0061] For another example, when n=2, the gate drive sub-circuit includes 12 cascaded shift registers, and correspondingly connected to 12 clock signal lines, refer to Figure 3c In the first display mode, the timing controller is configured to provide 12 clock signals corresponding to each of the 12 clock signal lines, and the starting time of the rise of the effective level of the 12 clock signals differs by 1H in sequence. Figure 5a Specifically, the first clock signal line CLK1 receives the first clock signal, and the first shift register GOA1 outputs the first gate drive signal G1 in response to the first clock signal, and turns on the first row of pixel units in the first unit scanning time (the first 1H); the second clock signal line CLK2 receives the second clock signal, and the second shift register GOA2 outputs the second gate drive signal G2 in response to the second clock signal, and turns on the second row of pixels in the second unit scanning time (the second 1H), and so on, until 12 gate drive signals are output in sequence to turn on 12 rows of pixels.

[0062] When the display mode is switched to the second display mode, the timing controller is configured to provide 8 clock signals for 12 clock signal lines, namely the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, the fifth clock signal, the sixth clock signal, the seventh clock signal and the eighth clock signal, and the starting time of the effective level of the 8 clock signals differs by 1H in sequence, referring to Figure 5bAmong them, the first clock signal line CLK1 and the second clock signal line CLK2 both receive the first clock signal, the third clock signal line CLK3 receives the second clock signal, the fourth clock signal line CLK4 and the fifth clock signal line CLK5 both receive the third clock signal, the sixth clock signal line CLK6 receives the fourth clock signal, the seventh shift register GOA7 and the eighth shift register GOA8 both receive the fifth clock signal, the ninth clock signal line CLK9 receives the sixth clock signal, the tenth clock signal line CLK10 and the eleventh clock signal line CLK11 both receive the seventh clock signal, and the twelfth clock signal line CLK12 receives the eighth clock signal. Correspondingly, the first shift register GOA1 and the second shift register GOA2 both output the first gate drive signal G1 in response to the first clock signal, and open the first row of pixel units and the second row of pixel units in the first unit scan time (within the first 1H); the third shift register GOA3 outputs the second gate drive signal G2 in response to the second clock signal, and opens the third row of pixel units in the second unit scan time; the fourth shift register GOA4 and the fifth shift register GOA5 both output the third gate drive signal G3 in response to the third clock signal, and open the fourth and fifth rows of pixel units in the third unit scan time; the sixth shift register GOA6 outputs the fourth gate drive signal G4 in response to the fourth clock signal, and opens the sixth row of pixel units in the fourth unit scan time; The seventh shift register GOA7 and the eighth shift register GOA8 both output the fifth gate drive signal G5 in response to the fifth clock signal, and turn on the seventh row of pixel units and the eighth row of pixel units in the fifth unit scan time (within the fifth 1H); the ninth shift register GOA9 outputs the sixth gate drive signal G6 in response to the sixth clock signal, and turns on the ninth row of pixel units in the sixth unit scan time; the tenth shift register GOA10 and the eleventh shift register GOA11 both output the seventh gate drive signal G7 in response to the seventh clock signal, and turn on the tenth row and the eleventh row of pixel units in the seventh unit scan time; the twelfth shift register GOA12 outputs the eighth gate drive signal G8 in response to the eighth clock signal, and turns on the twelfth row of pixel units in the eighth unit scan time. It can be understood that in the above driving process, the period of the clock signal in the first display mode is 12H, and the period of the clock signal in the second display mode is 8H.

[0063] In other embodiments, in the first display mode, the timing controller is configured to provide N clock signals corresponding to each of the N clock signal lines, and the starting times of the rise of the effective levels of the N clock signals are sequentially different by 1 hour; when the display mode is switched to the second display mode (high refresh rate), the timing controller is configured to provide 3n clock signals to the 6n clock signal lines, and the starting times of the effective levels of the 3n clock signals are sequentially different by 1 hour. The clock signal received by the i-th clock signal line and the i+1-th clock signal line is the same; i=2j-1, where j is a positive integer.

[0064] For example, when n=2, the gate drive subcircuit includes 12 cascaded shift registers, and correspondingly connected to 12 clock signal lines, refer to Figure 3c In the first display mode, the timing controller is configured to provide 12 clock signals corresponding to each of the 12 clock signal lines, and the starting time of the rise of the effective level of the 12 clock signals differs by 1H in sequence. Figure 5a Specifically, the first clock signal line CLK1 receives the first clock signal, and the first shift register GOA1 outputs the first gate drive signal G1 in response to the first clock signal, and turns on the first row of pixel units in the first unit scanning time (the first 1H); the second clock signal line CLK2 receives the second clock signal, and the second shift register GOA2 outputs the second gate drive signal G2 in response to the second clock signal, and turns on the second row of pixels in the second unit scanning time (the second 1H), and so on, until 12 gate drive signals are output in sequence to turn on 12 rows of pixels.

[0065] When the display mode is switched to the second display mode, the timing controller is configured to provide 6 clock signals for the 12 clock signal lines, namely the first clock signal, the second clock signal, the third clock signal, the fourth clock signal, the fifth clock signal and the sixth clock signal, and the starting time of the effective level of the 6 clock signals is 1H apart in sequence, referring to Figure 5cAmong them, the first clock signal line CLK1 and the second clock signal line CLK2 both receive the first clock signal, the third clock signal line CLK3 and the fourth clock signal line CLK4 both receive the second clock signal, the fifth clock signal line CLK5 and the sixth clock signal line CLK6 both receive the third clock signal, the seventh clock signal line CLK7 and the eighth clock signal line CLK8 both receive the fourth clock signal, the ninth shift register GOA9 and the tenth shift register GOA10 both receive the fifth clock signal, and the eleventh clock signal line CLK11 and the twelfth clock signal line CLK12 both receive the sixth clock signal. Correspondingly, the first shift register GOA1 and the second shift register GOA2 both output the first gate drive signal G1 in response to the first clock signal, and turn on the first row of pixel units and the second row of pixel units in the first unit scan time (within the first 1H); the third shift register GOA3 and the fourth shift register GOA4 output the second gate drive signal G2 in response to the second clock signal, and turn on the third row of pixel units and the fourth row of pixel units in the second unit scan time; the fifth shift register GOA5 and the sixth shift register GOA6 both output the third gate drive signal G3 in response to the third clock signal, and turn on the fifth row and the sixth row of pixel units in the third unit scan time; The seventh shift register GOA7 and the eighth shift register GOA8 both output the fourth gate drive signal G4 in response to the fourth clock signal and turn on the seventh and eighth rows of pixel units within the fourth unit scan time; the ninth shift register GOA9 and the tenth shift register GOA10 both output the fifth gate drive signal G5 in response to the fifth clock signal and turn on the ninth and tenth rows of pixel units within the fifth unit scan time (within the fifth 1H); the eleventh shift register GOA11 and the twelfth shift register GOA12 both output the sixth gate drive signal G6 in response to the sixth clock signal and turn on the eleventh and twelfth rows of pixel units within the sixth unit scan time. Compared with the first display mode, the second display mode takes half the time to turn on the same number of pixel rows. Therefore, in one frame, the refresh rate of the former is twice that of the latter. For example, the refresh rate of the first display mode is 240Hz, and the refresh rate of the second display mode is 480Hz. It can be understood that, in the above driving process, the period of the clock signal in the first display mode is 12H, and the period of the clock signal in the second display mode is 6H.

[0066] In some examples, the display panel further includes a signal generator configured to send a first control signal to the timing controller when the user selects the first display mode, and to send a second control signal to the timing controller when the user selects the second display mode.

[0067] In a second aspect, the present disclosure further provides a method for driving a display panel, wherein the display panel may be the display panel in any of the above embodiments. The driving method may specifically include:

[0068] S1. When the user selects the first display mode, the signal generator sends a first control signal to the timing controller, and the timing controller provides N clock signals corresponding to each of the N clock signal lines, and the starting time of the rising of the effective levels of the N clock signals differs by 1H in sequence, where H is the unit scanning time.

[0069] S2. When the user selects the second display mode, the signal generator sends a second control signal to the timing controller, and the timing controller provides M clock signals for N clock signal lines, and the starting times of the rising effective levels of the M clock signals differ by 1H respectively; M is less than N, and M and N are both positive integers; wherein the clock signals received by at least some of the clock signal lines are the same.

[0070] It should be noted that there is no sequential relationship between S1 and S2, and the display panel can be switched from the first display mode to the second display mode, or from the second display mode to the first display mode.

[0071] In a third aspect, the present disclosure further provides a display device comprising the display panel of the aforementioned embodiment. The display device can be any device, such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, or navigation system, or any combination of electronic devices and hardware, without limitation in the embodiments of the present disclosure.

[0072] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display panel having a first display mode and a second display mode; the refresh frequency of the display panel in the first display mode is lower than the refresh frequency in the second display mode; the display panel comprises a gate drive circuit and pixel units arranged in an array; the gate drive circuit comprises N shift registers; the shift registers are configured to provide gate drive signals for a row of the pixel units; The display panel further includes a timing controller and N clock signal lines; the timing controller is configured to provide a clock signal to the shift register through the clock signal lines, and the starting time of the effective level of each clock signal is sequentially different by 1H, where H is a unit scanning time; In the second display mode, the timing controller is configured to provide M clock signals for the N clock signal lines, and the starting times of the rising effective levels of the M clock signals differ by 1H; M is less than N, and both M and N are positive integers; wherein, The clock signals received by at least some of the clock signal lines are identical.

2. The display panel according to claim 1, wherein In the first display mode, the timing controller is configured to provide N clock signals corresponding to each of the N clock signal lines, and the starting time of the rising of the effective levels of the N clock signals differs by 1H, where H is the unit scanning time.

3. The display panel according to claim 1, wherein: The gate drive circuit includes at least one gate drive sub-circuit; the gate drive sub-circuit includes 6n cascaded shift registers, where n is a positive integer; the 6n shift registers in each gate drive sub-circuit are connected to the 6n clock signal lines in a one-to-one correspondence; For the gate driving circuit, the i-th shift register and the i+6n-th shift register are connected to the same clock signal line; i is N-6n.

4. The display panel according to claim 3, wherein: In the second display mode, for the gate driving sub-circuit, the timing controller is configured to provide 4n clock signals to the 6n clock signal lines, and the starting times of the effective levels of the 4n clock signals are sequentially different by 1H, where H is a unit scanning time; The clock signal received by the i-th clock signal line and the (i+1)-th clock signal line is the same; i=3j-2, j is a positive integer.

5. The display panel according to claim 3, wherein: In the second display mode, for the gate driving sub-circuit, the timing controller is configured to provide 3n clock signals to the 6n clock signal lines, and the starting times of the effective levels of the 3n clock signals are sequentially different by 1H, where H is a unit scanning time; The clock signal received by the i-th clock signal line and the (i+1)-th clock signal line is the same; i=2j-1, j is a positive integer. The display panel according to claim 3 , wherein: For the 6n shift registers in the gate drive subcircuit, the signal input ends of the 1st to 3nth shift registers are connected to the clock signal line that transmits the frame start signal; the signal output end of the ath shift register is connected to the signal input end of the a+3nth shift register; the reset signal end of the ath shift register is connected to the signal output end of the a+3nth shift register; 1≤a≤3n, and a is an integer.

7. The display panel according to claim 3, wherein: The gate driving sub-circuit includes a first shift register group and a second shift register group that are alternately cascaded; one of the first shift register group and the second shift register group includes the odd-numbered shift registers, and the other includes the even-numbered shift registers.

8. The display panel according to claim 1, wherein: The display panel further includes a signal generator; the signal generator is configured to send a first control signal to the timing controller when a user selects a first display mode, and to send a second control signal to the timing controller when a user selects a second display mode.

9. The display panel according to claim 1, wherein: The duty cycle of the clock signal is 50%.

10. A method for driving a display panel, the display panel having a first display mode and a second display mode; the refresh frequency of the display panel in the first display mode is lower than the refresh frequency in the second display mode; the display panel comprises a gate drive circuit and pixel units arranged in an array; the gate drive circuit comprises N shift registers; the shift registers are configured to provide gate drive signals for a row of the pixel units; The display panel further includes a timing controller and N clock signal lines; the timing controller is configured to provide a clock signal to the shift register through the clock signal lines, and the starting time of the effective level of each clock signal is sequentially different by 1H, where H is a unit scanning time; The driving method includes: In the second display mode, the timing controller provides M clock signals for the N clock signal lines, and the starting times of the rising effective levels of the M clock signals differ by 1H respectively; M is less than N, and M and N are both positive integers; wherein, the clock signals received by at least some of the clock signal lines are the same.

11. A display device comprising the display panel according to any one of claims 1 to 9.

Images