Display device, driving circuit board and control method thereof

Abstract

The invention provides a display device, a driving circuit board and a control method thereof, and the driving circuit board comprises a system-on-chip which comprises a debugging module and a communication module, the debugging module comprises a debugging interface, and the communication module comprises a communication interface; the switching circuit is electrically coupled with the debugging interface and the communication interface, and is configured to switch the electrical coupling between the debugging interface or the communication interface and the level conversion circuit; the level conversion circuit is electrically coupled with the switching circuit and the first interface of the connector, and is configured to perform level conversion on a level signal transmitted by the switching circuit or the connector; the connector comprises a first interface and a second interface; the first interface is electrically coupled with the level conversion circuit, and a control pin of the first interface is electrically coupled with the switching circuit; when the second interface is connected with a communication line, the control pin is suspended, or when the second interface is connected with a debugging line of debugging equipment, the control pin is connected with an electric signal.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device, a driving circuit board, and a control method thereof. Background Art

[0002] System-on-a-chip (SoC) devices typically include multiple interfaces. The Universal Asynchronous Receiver / Transmitter (UART) interface is a key debugging tool for electronic devices. To facilitate debugging and adapt to industrial environments, level conversion chips are commonly used to convert UART signals to RS-232-compliant levels and output them via a standard nine-pin (DB9) connector. With the trend toward device miniaturization and the need to simplify external interface layout, there is a need to multiplex both debugging and general communication functions on a single standard nine-pin (DB9) connector.

[0003] However, existing multiplexing solutions have significant limitations. One approach involves software-based multiplexing. However, during the initial chip startup, the debug UART's transmit signals can crosstalk with the receiver, causing startup failure. Another approach involves implementing custom DB9 pin multiplexing. However, this requires custom debugging tools, which lose compatibility with general-purpose tools and significantly increases cost and inconvenience. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a display device, a driving circuit board and a control method thereof to solve or partially solve the above problems.

[0005] As one aspect of the present application, a driver circuit board is provided, comprising:

[0006] A system-on-chip, comprising a debugging module and a communication module, wherein the debugging module comprises a debugging interface and the communication module comprises a communication interface;

[0007] a switching circuit, electrically coupled to the debug interface and the communication interface, respectively, and configured to switch the electrical coupling between the debug interface or the communication interface and the level conversion circuit;

[0008] a level conversion circuit, electrically coupled to the switching circuit and the first interface of the connector, and configured to perform level conversion on a level signal transmitted by the switching circuit or the connector;

[0009] The connector includes a first interface and a second interface; the first interface is electrically coupled to the level conversion circuit, and a control pin of the first interface is electrically coupled to the switching circuit; when the second interface is connected to a communication line, the control pin is left floating, or when the second interface is connected to a debug line of a debugging device, the control pin receives an electrical signal;

[0010] The switching circuit is further configured to: electrically couple the level conversion circuit to the communication interface when the second interface is connected to the communication line; or electrically couple the level conversion circuit to the debug interface when the second interface is connected to the debug line.

[0011] As a second aspect of the present application, a control method applied to the driving circuit board is provided, comprising:

[0012] In response to the second interface of the connector of the driving circuit board being connected to an external device through a communication line, the switching circuit of the driving circuit board electrically couples the level conversion circuit of the driving circuit board with the communication interface of the system-on-chip of the driving circuit board, so that the system-on-chip communicates with the external device;

[0013] In response to the second interface of the connector of the driving circuit board being connected to a debugging device via a debugging line, the switching circuit electrically couples the level conversion circuit to the debugging interface of the system-on-chip, so that the debugging device debugs the system-on-chip.

[0014] As a third aspect of the present application, a display device is provided, comprising:

[0015] Display panel;

[0016] The driving circuit board is electrically coupled to the display panel and is configured to provide a driving signal to the display panel.

[0017] As can be seen from the above, the display device, driver circuit board and control method thereof provided by the present application include a system-on-chip, a switching circuit, a level conversion circuit, a connector and a debugging device. The system-on-chip includes a debugging module and a communication module, wherein the debugging module includes a debugging interface and the communication module includes a communication interface; the switching circuit is electrically coupled to the debugging interface and the communication interface, respectively, and is configured to switch the electrical coupling between the debugging interface or the communication interface and the level conversion circuit; the level conversion circuit is electrically coupled to the switching circuit and the first interface of the connector, respectively, and is configured to level-convert the level signal transmitted by the switching circuit or the connector; the connector includes a first interface and a second interface; the first interface is electrically coupled to the level conversion circuit, and the control pin of the first interface is electrically coupled to the switching circuit; when the second interface is connected to the communication line, the control pin is left floating, or when the second interface is connected to the debug line of the debugging device, the control pin is connected to the electrical signal; wherein the switching circuit is further configured to: when the second interface is connected to the communication line, electrically couple the level conversion circuit to the communication interface; or when the second interface is connected to the debug line, electrically couple the level conversion circuit to the debugging interface. A switching circuit allows the debug module and communication module to reuse the same level conversion circuit and connector, enabling both debugging and general communication functions while reducing the number of components used and saving material costs. Furthermore, the connection type is automatically identified based on the status of the connector control pins, and the entire switching process is automatically controlled by hardware. During power-up, the debug module is physically disconnected from the level conversion circuit, preventing abnormal signals from the debug interface during power-up, ensuring normal chip startup, and improving the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in this application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are merely embodiments of this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0019] Figure 1 A schematic structural diagram of a driver circuit board provided in an embodiment of the present application;

[0020] Figure 2 A schematic structural diagram of another driver circuit board provided in an embodiment of the present application;

[0021] Figure 3 A schematic structural diagram of a connector provided in an embodiment of the present application;

[0022] Figure 4 A schematic diagram of the structure of a switching circuit provided in an embodiment of the present application;

[0023] Figure 5 A schematic diagram of a control method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] To make the objectives, technical solutions, and advantages of this application more clearly understood, the following describes this application in further detail with reference to specific embodiments and the accompanying drawings. It is apparent that the embodiments described are only a portion of the embodiments of this application, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments in this application without creative effort are intended to fall within the scope of protection of this application.

[0025] It should be noted that, in the embodiments of the present application, words such as "exemplarily" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design. Specifically, the use of words such as "exemplarily" or "for example" is intended to present related concepts in a concrete way. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should have the usual meaning understood by people with ordinary skills in the field to which this application belongs.

[0026] It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments. In addition, the transistors used in all embodiments of the present disclosure can be thin-film transistors or field-effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present disclosure are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as the signal input terminal, and the drain is referred to as the signal output terminal. According to the form in the accompanying drawings, the middle end of the transistor is defined as the control electrode, which can also be called the gate, the first electrode is the source, and the second electrode is the drain. In addition, the switching transistor used in the embodiment of the present disclosure may include any one of a P-type switching transistor and an N-type switching transistor, wherein the P-type switching transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level (that is, for the P-type transistor, it is turned on when the potential of the signal received by the gate is a low potential, and is turned off when the potential of the signal received by the gate is a high potential, that is, the low potential is the effective potential, and the high potential is the invalid potential), and the N-type switching transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level (that is, for the N-type transistor, it is turned on when the potential of the signal received by the gate is a high potential, and is turned off when the potential of the signal received by the gate is a low potential, that is, the high potential is the effective potential, and the low potential is the invalid potential).

[0027] Figure 1This is a schematic diagram of the structure of a driver circuit board provided in an embodiment of the present application. Figure 1 As shown, in some embodiments, the driver circuit board may include: a system-on-chip 10, a switching circuit 20, a level conversion circuit 30, and a connector 40. In some embodiments, the driver circuit board (Printed Circuit Board, PCB) is the physical foundation of the entire electronic device, organizing the SoC and other scattered electronic components (such as power management chips, external memory, sensors, various interface connectors, resistors, capacitors, etc.) to form a complete circuit system. The system-on-chip 10 is a highly integrated microchip that integrates most or all components required for an electronic system (such as a central processing unit (CPU), a graphics processing unit (GPU), memory, interface controller, wireless communication module, dedicated hardware accelerator, etc.) into a single silicon chip, capable of performing various complex computing and control tasks for many electronic devices (such as smartphones, tablets, smart TVs, Internet of Things devices, automotive electronics).

[0028] In some embodiments, as Figure 2As shown, in the related art, the system-on-chip 10 includes a debugging module 11 (Port0Debug_UART) and a communication module 12 (Port1 UART). The debugging module 11 includes a debugging interface, and the communication module 12 includes a communication interface. Among them, the debugging module 11 is connected to the outside of the driver circuit board through the interface 1 of the connector 40 after level conversion by the level conversion circuit 31, so that developers and after-sales service engineers can perform system debugging, firmware burning, log analysis and fault diagnosis. The communication module 12 is connected to the outside of the driver circuit board through the interface 2 of the connector 40 after level conversion by the level conversion circuit 32, and conducts business communications with users. After the system-on-chip 10 is powered on, the debugging module 11 will start immediately and send out bootloader information and the boot log of the system-on-chip 10 through the transmitting end (Transmit, abbreviated as TX) of the debugging interface. At the same time, the receiving end (Receive, abbreviated as RX) of the debugging interface is in a listening state, waiting for debugging instructions. During this initial startup phase, if the RX path receives an erroneous instruction, or if an erroneous signal such as electrical interference or a short circuit occurs on the RX signal line, the boot loading process of the SoC 10 will be interrupted, causing confusion in the instruction execution logic, which in turn will cause a loading anomaly or even a crash, preventing the SoC 10 from starting and operating normally. Especially during on-site wiring or construction, due to distance and flexibility considerations, the interface 3 of the connector 40 and the debugging device 53 will be connected using a long-distance network cable, such as a twisted pair. The high-speed data signal of the TX will interfere with the adjacent receiving end RX signal line through electromagnetic induction or capacitive coupling, causing the data received by the RX end to be contaminated, resulting in bit errors, data frame errors, or even the complete inability to recognize valid data, thereby seriously affecting the reliability of UART communication and the normal operation of the debugging function.

[0029] It should be understood that during the development and debugging of embedded systems, UART can be selected as a debugging interface, but the UART signal is a transistor-transistor logic (TTL) / complementary metal-oxide-semiconductor (CMOS) level and cannot be directly connected to a standard personal computer (PC) serial port (RS-232). In order to facilitate the debugging of the entire machine and on-site fault diagnosis, a level conversion circuit 30 is deployed to convert the debugging module 11 on the driver circuit board into a differential level signal that complies with the RS-232 standard protocol through an RS-232 level conversion chip (such as the MAX232 series). The converted signal is led out to the outside of the entire machine through the connector 40 interface 3. The presence of the level conversion circuit 30 ensures signal compatibility between different voltage levels (for example, the internal level of the SoC and the level of the external device 54 / debugging device 53), effectively preventing signal distortion or damage caused by voltage mismatch, and improving the reliability of signal transmission and the stability of the device.

[0030] In order to reduce costs and reduce the size of the whole machine, such as Figure 1 As shown, it can be Figure 2 On the basis of the above, the level conversion circuit 31 and the level conversion circuit 32 are merged into a level conversion circuit 30, and a switching circuit 20 is added at the front end of the level conversion circuit 30. At this time, the interface 1 of the connector 40 and the interface 2 of the connector 40 are merged into the first interface 41 of the connector 40, and the interface 3 of the connector 40 is the second interface 42 of the connector 40, thereby realizing dual-port multiplexing of debugging and ordinary communication.

[0031] In some embodiments, the connector 40 may be a DB9 connector, a Joint Test Action Group (JTAG) connector, a Serial Wire Debug (SWD) connector, a high-speed differential connector, a Board-to-Board (BTB) connector, etc. This embodiment is described by taking the connector 40 as a DB9 connector as an example. Figure 3As shown, the DB9 connector includes a male connector and a female connector. Taking the external interface of the driver circuit board as an example, the TX channel of the debugging module 11 and the communication module 12 is connected to pin 2 (the transmit data (TXD) pin) after the level is converted by the level conversion circuit 30. The RX channel of the debugging module 11 and the communication module 12 is connected to pin 3 (the receive data (RXD) pin) after the level is converted by the level conversion circuit 30. Pin 5 (the ground (GND) pin) is shared with the GND of the driver circuit board. Pin 4 is connected to the (Ctrl) control pin of the switching circuit 20 as a trigger control signal.

[0032] In conventional communication scenarios, one end of the twisted-pair cable is connected to a DB9 female connector (matching the driver circuit board interface) and the other end is connected to an external device 54 for communication. Pin 3 of the DB9 connector 40 on the twisted-pair cable is connected to the TXD pin of the external device 54, pin 2 is connected to the RXD pin of the external device 54, and pin 5 is connected to GND. The other pins are left floating. In debugging scenarios, engineers or after-sales personnel perform debugging by connecting one end of the twisted-pair cable to a DB9 female connector (matching the driver circuit board interface) and the other end to the debugging device 53. The pins of the debugging device 53 can be defined as follows: pin 1 (Data Carrier Detect, DCD), pin 2 (Receive Data), pin 3 (TXD), pin 4 (Data Terminal Ready, DTR), pin 5 (GND), pin 6 (Data Set Ready, DSR), pin 7 (Request To Send, RTS), pin 8 (Clear To Send, CTS), and pin 9 (Ring Indicator, RI). In this embodiment, the debugging device 53 only uses pin 2 RXD, pin 3 TXD, pin 5 GND and pin 6 DSR, and the remaining pins are left floating.

[0033] In some embodiments, the switching circuit 20 is electrically coupled to the debug interface (transmitter TX0 and receiver RX0) and the communication interface (transmitter TX1 and receiver RX1), and is configured to switch the electrical coupling between the debug interface or the communication interface and the level conversion circuit 30. The level conversion circuit 30 is electrically coupled to the switching circuit 20 and the first interface 41 of the connector 40, and is configured to convert the level of the level signal transmitted by the switching circuit 20 or the connector 40. The connector 40 includes a first interface 41 and a second interface 42. The first interface 41 is electrically coupled to the level conversion circuit 30, and a control pin (Ctrl) of the first interface 41 is electrically coupled to the switching circuit 20. When the second interface 42 is connected to the communication line 51, the control pin is left floating, or when the second interface 42 is connected to the debug line 52 of the debugging device 53, the control pin receives an electrical signal.

[0034] The switching circuit 20 is further configured to electrically couple the level shifting circuit 30 to the communication interface when the second interface 42 is connected to the communication line 51; or to electrically couple the level shifting circuit 30 to the debug interface when the second interface 42 is connected to the debug line 52. It should be understood that the communication line 51 can be used to connect to an external device 54 for communication. The communication line 51 and the debug line 52 can be the twisted pair cables described above.

[0035] In some embodiments, the time when the second interface 42 of the connector 40 is connected can be compared to the time when the driver circuit board is powered on to determine whether the second interface 42 is the communication line 51 used by the customer or the debug line 52 used by developers or after-sales personnel. Furthermore, the conduction path of the switching circuit 20 is controlled based on the determination result. For example, if the second interface 42 of the connector 40 is connected before the driver circuit board is powered on, it is determined that the second interface 42 is connected to the debug line 52, and the control pin is connected to the electrical signal. If the second interface 42 of the connector 40 is connected after the driver circuit board is powered on, it is determined that the second interface 42 is connected to the communication line 51, and the control pin is left floating to avoid misjudgment that may cause the customer to accidentally enter the debug mode.

[0036] Alternatively, as Figure 4 As shown, the switching circuit 20 further includes a control circuit 21, which is electrically coupled to the control pin and the signal switching circuit 22, and is configured to provide a first control signal or a second control signal to the signal switching circuit 22 when the control pin is floating or receiving an electrical signal. The control circuit 21 accurately controls the interface switching through the first control signal or the second control signal to avoid signal conflicts.

[0037] In some embodiments, the control circuit 21 further includes: a first resistor R1, a first end of the first resistor R1 is connected to the first voltage terminal, and a second end of the first resistor R1 is connected to the first node A; a second resistor R2, a first end of the second resistor R2 is connected to the first node, and a second end of the second resistor R2 is connected to the second node B; a first capacitor C1, a first end of the first capacitor C1 is connected to the second voltage terminal, and the first end of the first capacitor C1 is connected to the second node B. For example, the capacitance value of the first capacitor C1 is 100nF; a first transistor Q1, a control end of the first transistor Q1 is connected to the second node B, a first end of the first transistor Q1 is connected to the third node C, and a second end of the first transistor Q1 is connected to the third voltage terminal. The control circuit 21 realizes automatic recognition of the control pin state of the connector 40 (suspended or connected to an electrical signal). When the control pin is suspended, the circuit state is a communication state, and when an electrical signal is connected, the circuit state is a debugging state, which provides an accurate judgment basis for subsequent interface switching.

[0038] Optionally, the switching circuit 20 further includes a signal switching circuit 22 electrically coupled to the control circuit 21, the first control terminal VCC0, and the second control terminal VCC1, respectively. The signal switching circuit 22 is configured to: provide a first electrical signal through the first control terminal VCC0 and a second electrical signal through the second control terminal VCC1 under the control of a first control signal; or provide a second electrical signal through the first control terminal VCC0 and the first electrical signal through the second control terminal VCC1 under the control of a second control signal. The signal switching circuit 22 is configured to switch the electrical signals provided to the first control terminal VCC0 and the second control terminal VCC1 according to the control circuit 21. By independently controlling the output levels of the first control terminal VCC0 and the second control terminal VCC1, circuit stability is enhanced.

[0039] Optionally, the signal switching circuit 22 further includes a first signal sub-circuit 221, which is electrically coupled to the control circuit 21 and the first control terminal VCC0, respectively, and is configured to: provide a first electrical signal through the first control terminal VCC0 under the control of the first control signal; or provide a second electrical signal through the first control terminal VCC0 under the control of the second control signal.

[0040] In some embodiments, the first signal sub-circuit 221 further includes a third resistor R3, a first end of the third resistor R3 is connected to the third node C, and a second end of the third resistor R3 is connected to the control end of the second transistor Q2; a fourth resistor R4, a first end of the fourth resistor R4 is connected to the third node C, and a second end of the fourth resistor R4 is connected to the driving end VCC; a second transistor Q2, the control end of the second transistor Q2 is connected to the third node C, the first end of the second transistor Q2 is connected to the first control end VCC0, and the second end of the second transistor Q2 is connected to the driving end VCC; a second capacitor C2, a first end of the second capacitor C2 is connected to the fourth voltage end, and a second end of the second capacitor C2 is connected to the driving end VCC. Exemplarily, the capacitance value of the second capacitor C2 is 4.7uF.

[0041] Exemplarily, in the communication state, the control pin is suspended, the control signal is pulled low by the first resistor R1, the second node B is at a low level, the first transistor Q1 is an N-type transistor in an off state, the third node C is at a high level, the control circuit 21 provides a first control signal to the first signal sub-circuit 221, and the second transistor Q3 is a P-type transistor in an off state. At this time, under the control of the first control signal, a first electrical signal is provided through the first control terminal VCC0, and the first electrical signal is used to indicate that the voltage is 0V.

[0042] Exemplarily, in the debugging state, the control pin is connected to the DTR pin of the debugging device 53. After the debugging tool is working, the control pin is connected to an electrical signal, so that the potential of the control pin is pulled high, the control signal becomes a high level, the second node B is a high level, the first transistor Q1 is an N-type transistor in the on state, the third node C is a low level, the control circuit 21 provides a second control signal to the first signal sub-circuit 221, and the second transistor Q3 is a P-type transistor in the on state. At this time, under the control of the second control signal, a second electrical signal is provided through the first control terminal VCC0. At this time, the second electrical signal is used to indicate that the voltage is the voltage of the driving terminal VCC.

[0043] Optionally, the signal switching circuit 22 further includes a second signal sub-circuit 222 electrically coupled to the control circuit 21 and the second control terminal VCC1, and configured to: provide the second electrical signal through the second control terminal VCC1 under the control of the first control signal; or provide the first electrical signal through the second control terminal VCC1 under the control of the second control signal. Decomposing the signal switching circuit 22 into two independent sub-circuits, each controlling the first control terminal VCC0 and the second control terminal VCC1, facilitates precise control and faster response of the circuit.

[0044] In some embodiments, the second signal sub-circuit 222 further includes: a fifth resistor R5, wherein a first end of the fifth resistor R5 is connected to the third node C, and a second end of the fifth resistor R5 is connected to the fourth node D; a third capacitor C3, wherein a first end of the third capacitor C3 is connected to the fifth voltage terminal, and a second end of the third capacitor C3 is connected to the fourth node D. Exemplarily, the capacitance of the third capacitor C3 is 100 nF; a third transistor Q3, wherein a control end of the third transistor Q3 is connected to the fourth node D, a first end of the third transistor Q3 is connected to the control end of the fourth transistor Q4, and a second end of the third transistor Q3 is connected to the sixth voltage terminal; a sixth resistor R6, wherein a first end of the sixth resistor R6 is connected to the first end of the third transistor Q3, and a second end of the sixth resistor R6 is connected to the control end of the fourth transistor Q4; a seventh resistor R7, wherein a first end of the seventh resistor R7 is connected to the first end of the third transistor Q3, and a second end of the seventh resistor R7 is connected to the driving terminal VCC; and a fourth transistor Q4, wherein a control end of the fourth transistor Q4 is connected to the first end of the third transistor Q3, a first end of the fourth transistor Q4 is connected to the second control terminal VCC1, and a second end of the fourth transistor Q4 is connected to the driving terminal VCC.

[0045] Exemplarily, in the communication state, the control pin is suspended, the control signal is pulled low by the first resistor R1, the second node B is at a low level, the first transistor Q1 is an N-type transistor in an off state, the third node C is at a high level, the control circuit 21 provides a first control signal to the second signal sub-circuit 222, the fourth node D is pulled high, the third transistor Q3 is an N-type transistor in an on state, and the fourth transistor Q4 is a P-type transistor in an on state. At this time, under the control of the first control signal, a second electrical signal is provided through the second control terminal VCC1. At this time, the second electrical signal is used to indicate that the voltage is the voltage of the driving terminal VCC.

[0046] Exemplarily, in the debugging state, the control pin is connected to the DTR pin of the debugging device 53. After the debugging tool is working, the control pin is connected to an electrical signal, so that the potential of the control pin is pulled high, the control signal becomes a high level, the second node B is a high level, the first transistor Q1 is an N-type transistor in the on state, the third node C is a low level, the control circuit 21 provides a second control signal to the second signal sub-circuit 222, the fourth node D is a low level, the third transistor Q3 is an N-type transistor in the off state, and the fourth transistor Q4 is a P-type transistor in the off state. At this time, under the control of the second control signal, the first electrical signal is provided through the second control terminal VCC1, and the second electrical signal is used to indicate that the voltage is 0V.

[0047] It should be understood that the first signal sub-circuit 221 and the second signal sub-circuit 222 ensure that the first control terminal VCC0 and the second control terminal VCC1 can stably and reliably output the required first electrical signal or second electrical signal through the precise configuration of resistors, capacitors and transistors, thereby providing accurate control voltage for the interface switching circuit 23.

[0048] Optionally, the switching circuit 20 further includes an interface switching circuit 23 electrically coupled to the debug interface, the communication interface, the first control terminal VCC0, the second control terminal VCC1, and the level shifting circuit 20, respectively. The circuit 23 is configured to electrically couple the level shifting circuit 30 to the communication interface under the control of a first electrical signal provided by the first control terminal VCC0 and a second electrical signal provided by the second control terminal VCC1; or to electrically couple the level shifting circuit 30 to the debug interface under the control of a second electrical signal provided by the first control terminal VCC0 and a first electrical signal provided by the second control terminal VCC1. Decomposing the switching function into three modules—the control circuit 21, the signal switching circuit 22, and the interface switching circuit 23—makes the overall control logic clearer and more modular. Precise and controllable switching between the communication interface and the debug interface is achieved through the first and second control signals generated by the control circuit 21 and the differentiated electrical signals provided by the signal switching circuit 22. This level-based switching mechanism offers faster switching speeds and better signal isolation than simple on-off switching. Furthermore, the coordinated operation of the signal switching circuit 22 and the interface switching circuit 23 enables automatic interface switching based on the control pin status, further improving the level of automation and reducing reliance on operators. Furthermore, when signal transmission problems arise, this modular design helps narrow the scope of troubleshooting and improves debugging efficiency.

[0049] Optionally, the interface switching circuit 23 further includes a first interface sub-circuit 231, which is electrically coupled to the debug interface, the first control terminal VCC0 and the level switching circuit 20, respectively, and is configured to: electrically couple the level conversion circuit 30 to the communication interface under the control of a first electrical signal provided by the first control terminal VCC0; or electrically couple the level conversion circuit 30 to the debug interface under the control of a second electrical signal provided by the first control terminal VCC0.

[0050] In some embodiments, the first interface sub-circuit 231 further includes an eighth resistor R8, a first end of the eighth resistor R8 is connected to the first control end VCC0, and a second end of the eighth resistor R8 is connected to the control end of the fifth transistor Q5; a fifth transistor Q5, the control end of the fifth transistor Q5 is connected to the eighth resistor R8, a first end of the fifth transistor Q5 is connected to the transmitting end of the level conversion circuit 30, and a second end of the fifth transistor Q5 is connected to the transmitting end of the debugging interface; a ninth resistor R9, a first end of the ninth resistor R9 is connected to the first control end VCC0, and a second end of the ninth resistor R9 is connected to the control end of the sixth transistor Q6; a sixth transistor Q6, the control end of the sixth transistor Q6 is connected to the ninth resistor R9, a first end of the sixth transistor Q6 is connected to the receiving end of the debugging interface, and a second end of the sixth transistor Q6 is connected to the receiving end of the level conversion circuit 30.

[0051] For example, in the above-mentioned communication state, the first control terminal VCC0 is 0V, the fifth transistor Q5 and the sixth transistor Q6 are N-type transistors in a closed state. At this time, even if data is sent from the transmitting end of the debug interface, the signal cannot be transmitted backward, that is, it cannot be transmitted to the twisted pair, thereby avoiding the twisted pair coupling signal to the receiving end of the debug interface, so that the startup process proceeds smoothly.

[0052] For example, in the above-mentioned debugging state, the voltage of the first control terminal VCC0 is equal to the voltage of the driving terminal VCC, the fifth transistor Q5 and the sixth transistor Q6 are N-type transistors in the on state, and data is sent from the transmitting end of the debugging interface, which can be transmitted to the transmitting end of the level conversion circuit 30, and then transmitted to the interface of the debugging device 53 after level conversion by the level conversion circuit 30. The debugging device 53 is directly connected to the interface of the driving circuit board without a long twisted pair coupling, so no abnormal signal will appear on the receiving end of the debugging interface, and the startup process can proceed smoothly.

[0053] Optionally, the interface switching circuit 23 further includes a second interface sub-circuit 232 electrically coupled to the communication interface, the second control terminal VCC1, and the level shifting circuit 20, respectively. The second interface sub-circuit 232 is configured to electrically couple the level shifting circuit 30 to the communication interface under the control of a second electrical signal provided by the second control terminal VCC1; or to electrically couple the level shifting circuit 30 to the debug interface under the control of a first electrical signal provided by the second control terminal VCC1. The interface switching circuit 23 is decomposed into two independent sub-circuits, each responsible for connecting the level shifting circuit 30 to the communication interface or the debug interface. This design ensures that signals can be accurately routed from the level shifting circuit 30 to the target interface, or vice versa, during the switching process. Furthermore, by controlling the connection of different interfaces through independent interface sub-circuits, crosstalk between interfaces in the non-operating state can be effectively reduced, signal isolation can be improved, and the purity of data transmission can be ensured.

[0054] The first signal subcircuit 221 is electrically coupled to the first interface subcircuit 231, and the second signal subcircuit 222 is electrically coupled to the second interface subcircuit 232. This correspondence makes the control logic of the entire circuit very clear and easy to understand and implement.

[0055] In some embodiments, the second interface sub-circuit 232 further includes a tenth resistor R10, a first end of the tenth resistor R10 is connected to the second control terminal VCC1, and a second end of the tenth resistor R10 is connected to the control terminal of the seventh transistor Q7; a seventh transistor Q7, the control terminal of the seventh transistor Q7 is connected to the tenth resistor R10, a first end of the seventh transistor Q7 is connected to the transmitting terminal of the level conversion circuit 30, and a second end of the seventh transistor Q7 is connected to the transmitting terminal of the communication interface; an eleventh resistor R11, a first end of the eleventh resistor R11 is connected to the second control terminal VCC1, and a second end of the eleventh resistor R11 is connected to the control terminal of the eighth transistor Q8; an eighth transistor Q8, the control terminal of the eighth transistor Q8 is connected to the eleventh resistor R11, a first end of the eighth transistor Q8 is connected to the receiving terminal of the communication interface, and a second end of the eighth transistor Q8 is connected to the receiving terminal of the level conversion circuit 30.

[0056] For example, in the above-mentioned communication state, the voltage of the second control terminal VCC1 is equal to the voltage of the driving terminal VCC, the seventh transistor Q7 and the eighth transistor Q8 are N-type transistors in the on state, and the ordinary UART communication signal is connected to the transmitting end and the receiving end channel of the level conversion circuit 30 through the seventh transistor Q7 and the eighth transistor Q8 respectively, and after the level conversion by the level conversion circuit 30, it is connected to the twisted pair.

[0057] For example, in the above debugging state, the second control terminal VCC1 is 0V, and the seventh transistor Q7 and the eighth transistor Q8 are N-type transistors and are always in the off state.

[0058] It should be understood that the first interface subcircuit 231 and the second interface subcircuit 232, through a combination of transistors and resistors, enable bidirectional switching of transmit and receive signals between the level shifter circuit 30 and the debug / communication interface. This ensures that debug or communication signals are correctly routed, regardless of whether they are input or output.

[0059] Among them, the first resistor R1, the fourth resistor R4, and the seventh resistor R7 have a first resistance value; the second resistor R2, the third resistor R3, the fifth resistor R5, and the sixth resistor R6 have a second resistance value; the eighth resistor R8, the ninth resistor R9, the tenth resistor R10, and the eleventh resistor R11 have a third resistance value; the first resistance value is greater than the third resistance value, and the third resistance value is greater than the second resistance value. Resistors corresponding to the first resistance value can be used for voltage division, current limiting, or pull-up / pull-down to reduce power consumption or provide a weaker bias current; resistors corresponding to the second resistance value can be used for fast charging and discharging, provide a stronger drive current, or serve as bias resistors for transistors to ensure fast response and stable operation; resistors corresponding to the third resistance value can be used as base / gate resistors for transistors to balance drive capability and power consumption and ensure appropriate switching speed. Appropriate resistor configuration can ensure that the transistor operates in an optimal state, prevent overcurrent or underdrive, thereby extending component life and improving the long-term stability and reliability of the circuit.

[0060] Exemplarily, the first resistance is 10k, the second resistance is 1k, and the third resistance is 4.7k.

[0061] In summary, the embodiment of the present disclosure provides a driving circuit board, which includes a system-on-chip 10, a switching circuit 20, a level conversion circuit 30, a connector 40, and a debugging device 53. The system-on-chip 10 includes a debugging module 11 and a communication module 12, wherein the debugging module 11 includes a debugging interface, and the communication module 12 includes a communication interface; the switching circuit is electrically coupled to the debugging interface and the communication interface, respectively, and is configured to switch the electrical coupling between the debugging interface or the communication interface and the level conversion circuit 30; the level conversion circuit 30 is electrically coupled to the switching circuit 20 and the first interface 41 of the connector 40, respectively, and is configured to level convert the level signal transmitted by the switching circuit 20 or the connector 40; the connector 40 includes a first interface 41 and a second interface 42. Interface 42; first interface 41 is electrically coupled to level conversion circuit 30, and a control pin of first interface 41 is electrically coupled to switching circuit 20; when second interface 42 is connected to communication line 51, the control pin is left floating, or, when second interface 42 is connected to debug line 52 of debugging device 53, the control pin is connected to an electrical signal; wherein switching circuit 20 is further configured to: electrically couple level conversion circuit 30 to the communication interface when second interface 42 is connected to communication line 51; or, electrically couple level conversion circuit 30 to the debugging interface when second interface 42 is connected to debug line 52. A single switching circuit 20 enables the debugging module 11 and the communication module 12 to reuse the same level conversion circuit 30 and connector 40, thereby achieving both debugging and general communication functions, while reducing the number of components used and saving material costs. In addition, the connection type is automatically identified based on the control pin status of the connector 40, and the entire process is automatically switched through hardware control. When power is turned on, the debugging module 11 and the level conversion circuit 30 are physically disconnected to avoid abnormal signals in the debugging interface when power is turned on, ensuring the normal startup of the chip and improving the user experience.

[0062] Based on the same invention concept, Figure 5 As shown, an embodiment of the present application provides a control method, which is applied to the driver circuit board of any of the above embodiments, including:

[0063] S50. In response to the second interface of the connector of the driving circuit board being connected to an external device through a communication line, the switching circuit of the driving circuit board electrically couples the level conversion circuit of the driving circuit board with the communication interface of the system-level chip of the driving circuit board, so that the system-level chip communicates with the external device.

[0064] In some embodiments, the driver circuit board is capable of performing regular data exchange with an external device 54 through its connector 40. When the external device 54 is connected to the second interface 42 of the driver circuit board via the communication line 51, the driver circuit board first performs connection detection and device type identification to confirm that the connected external device 54 is not for debugging. Subsequently, the switching circuit 20 is activated by the system-level chip 10 to selectively establish an electrical path from the second interface 42 via the level conversion circuit 30 to the internal communication interface of the system-level chip 10. The level conversion circuit 30 ensures that the external signal voltage is compatible with the internal logic voltage of the system-level chip 10, protects the system-level chip 10 and ensures signal integrity. Once the physical and level paths are ready, the system-level chip 10 will activate the corresponding communication protocol stack (such as UART) to perform bidirectional data exchange with the external device 54 and execute preset application functions, such as receiving instructions, transmitting data or coordinating operations, to achieve the normal working mode of the driver circuit board.

[0065] S52 . In response to the second interface of the connector of the driving circuit board being connected to the debugging device through the debugging line, the switching circuit electrically couples the level conversion circuit to the debugging interface of the system-on-chip, so that the debugging device debugs the system-on-chip.

[0066] In some embodiments, when a debugging device 53 is connected to the second interface 42 via the debug line 52, the driver circuit board recognizes that a debugging device 53 is connected. Unlike S401, the switching circuit 20 receives a different control signal, thereby reconfiguring its internal connections and establishing an electrical path from the second interface 42 through the level shifting circuit 30 to the internal debug interface of the SoC 10. Once this path is established, the debugging device 53 can use these debug interfaces to perform various debugging operations on the SoC 10, including but not limited to firmware flashing, real-time code single-stepping, breakpoint setting, register viewing, memory modification, and obtaining system debug logs, greatly facilitating embedded system development and troubleshooting.

[0067] The disclosed embodiments provide a control method that implements automatic identification and automatic switching after an interface is connected. Whether for device debugging or normal communication, the user only needs to connect the corresponding communication line or debugging line to automatically complete the interface configuration, simplifying user operations and improving the efficiency of development, testing, and use. At the same time, plug-and-play for external devices is achieved, and users do not need to pay attention to the complex underlying interface switching logic; they only need to connect and use it. At the same time, automatic switching at the hardware level avoids software configuration errors and reduces the risk of system crashes.

[0068] It should be noted that the above description is limited to some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in an order different from that described in the above embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0069] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments and methods, the present application also provides a display device, comprising: a display panel; a driving circuit board as described in any of the above-mentioned embodiments, electrically coupled to the display panel and configured to provide a driving signal to the display panel.

[0070] Optionally, the display device provided in the embodiment of the present disclosure may include: a display, a mobile phone, a television, a laptop computer and / or a navigator, etc. Other essential components of the display device should be understood by ordinary technicians in this field and will not be described in detail.

[0071] It should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features indicated. Thus, a feature designated "first" or "second" may explicitly or implicitly include one or more of the features.

[0072] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. Within the scope of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0073] The embodiments of the present application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of this application.

Claims

1. A driving circuit board, characterized in that: include: A system-on-chip, comprising a debugging module and a communication module, wherein the debugging module comprises a debugging interface and the communication module comprises a communication interface; a switching circuit, electrically coupled to the debug interface and the communication interface, respectively, and configured to switch the electrical coupling between the debug interface or the communication interface and the level conversion circuit; a level conversion circuit, electrically coupled to the switching circuit and the first interface of the connector, and configured to perform level conversion on a level signal transmitted by the switching circuit or the connector; The connector includes a first interface and a second interface; the first interface is electrically coupled to the level conversion circuit, and a control pin of the first interface is electrically coupled to the switching circuit; when the second interface is connected to a communication line, the control pin is left floating, or when the second interface is connected to a debug line of a debugging device, the control pin receives an electrical signal; The switching circuit is further configured to: electrically couple the level conversion circuit to the communication interface when the second interface is connected to the communication line; or electrically couple the level conversion circuit to the debug interface when the second interface is connected to the debug line.

2. The driving circuit board according to claim 1, wherein: The switching circuit further comprises: a control circuit electrically coupled to the control pin and the signal switching circuit, respectively, and configured to provide a first control signal or a second control signal to the signal switching circuit when the control pin is suspended or connected to the electrical signal; The signal switching circuit is electrically coupled to the control circuit, the first control terminal (VCC0), and the second control terminal (VCC1), respectively, and is configured to: under the control of the first control signal, provide a first electrical signal through the first control terminal (VCC0) and provide a second electrical signal through the second control terminal (VCC1); or, under the control of the second control signal, provide the second electrical signal through the first control terminal (VCC0) and provide the first electrical signal through the second control terminal (VCC1); The interface switching circuit is electrically coupled to the debug interface, the communication interface, the first control terminal (VCC0), the second control terminal (VCC1), and the level switching circuit, respectively, and is configured to: electrically couple the level conversion circuit to the communication interface under the control of the first electrical signal provided by the first control terminal (VCC0) and the second electrical signal provided by the second control terminal (VCC1); or electrically couple the level conversion circuit to the debug interface under the control of the second electrical signal provided by the first control terminal (VCC0) and the first electrical signal provided by the second control terminal (VCC1).

3. The driving circuit board according to claim 2, wherein: The signal switching circuit further comprises: a first signal sub-circuit electrically coupled to the control circuit and the first control terminal (VCC0), respectively, and configured to: provide the first electrical signal through the first control terminal (VCC0) under the control of the first control signal; or provide the second electrical signal through the first control terminal (VCC0) under the control of the second control signal; The second signal sub-circuit is electrically coupled to the control circuit and the second control terminal (VCC1), respectively, and is configured to: provide the second electrical signal through the second control terminal (VCC1) under the control of the first control signal; or provide the first electrical signal through the second control terminal (VCC1) under the control of the second control signal.

4. The driving circuit board according to claim 3, wherein: The interface switching circuit further comprises: a first interface sub-circuit electrically coupled to the debug interface, the first control terminal (VCC0), and the level shifting circuit, respectively, and configured to: electrically couple the level shifting circuit to the communication interface under the control of the first electrical signal provided by the first control terminal (VCC0); or electrically couple the level shifting circuit to the debug interface under the control of the second electrical signal provided by the first control terminal (VCC0); The second interface sub-circuit is electrically coupled to the communication interface, the second control terminal (VCC1) and the level switching circuit, respectively, and is configured to: electrically couple the level conversion circuit to the communication interface under the control of the second electrical signal provided by the second control terminal (VCC1); or electrically couple the level conversion circuit to the debugging interface under the control of the first electrical signal provided by the second control terminal (VCC1).

5. The driving circuit board according to claim 4, characterized in that: The first signal sub-circuit is electrically coupled to the first interface sub-circuit; and the second signal sub-circuit is electrically coupled to the second interface sub-circuit.

6. The driving circuit board according to claim 4, characterized in that: The control circuit further comprises: a first resistor (R1), wherein a first end of the first resistor (R1) is connected to a first voltage terminal, and a second end of the first resistor (R1) is connected to a first node (A); a second resistor (R2), wherein a first end of the second resistor (R2) is connected to the first node, and a second end of the second resistor (R2) is connected to a second node (B); a first capacitor (C1), wherein a first end of the first capacitor (C1) is connected to the second voltage end, and a first end of the first capacitor (C1) is connected to the second node (B); A first transistor (Q1), wherein a control end of the first transistor (Q1) is connected to the second node (B), a first end of the first transistor (Q1) is connected to a third node (C), and a second end of the first transistor (Q1) is connected to a third voltage end.

7. The driving circuit board according to claim 6, characterized in that: The first signal sub-circuit further comprises: a third resistor (R3), wherein a first end of the third resistor (R3) is connected to the third node (C), and a second end of the third resistor (R3) is connected to the control end of the second transistor (Q2); a fourth resistor (R4), wherein a first end of the fourth resistor (R4) is connected to the third node (C), and a second end of the fourth resistor (R4) is connected to the driving terminal (VCC); the second transistor (Q2), wherein the control terminal of the second transistor (Q2) is connected to the third node (C), the first terminal of the second transistor (Q2) is connected to the first control terminal (VCC0), and the second terminal of the second transistor (Q2) is connected to the driving terminal (VCC); a second capacitor (C2), wherein a first end of the second capacitor (C2) is connected to the fourth voltage end, and a second end of the second capacitor (C2) is connected to the driving end (VCC); The second signal sub-circuit further includes: a fifth resistor (R5), wherein a first end of the fifth resistor (R5) is connected to the third node (C), and a second end of the fifth resistor (R5) is connected to the fourth node (D); a third capacitor (C3), wherein a first end of the third capacitor (C3) is connected to the fifth voltage terminal, and a second end of the third capacitor (C3) is connected to the fourth node (D); a third transistor (Q3), wherein a control terminal of the third transistor (Q3) is connected to the fourth node (D), a first terminal of the third transistor (Q3) is connected to the control terminal of the fourth transistor (Q4), and a second terminal of the third transistor (Q3) is connected to a sixth voltage terminal; a sixth resistor (R6), a first end of the sixth resistor (R6) connected to the first end of the third transistor (Q3), and a second end of the sixth resistor (R6) connected to the control end of the fourth transistor (Q4); a seventh resistor (R7), wherein a first end of the seventh resistor (R7) is connected to the first end of the third transistor (Q3), and a second end of the seventh resistor (R7) is connected to the driving end (VCC); The fourth transistor (Q4), the control end of the fourth transistor (Q4) is connected to the first end of the third transistor (Q3), the first end of the fourth transistor (Q4) is connected to the second control end (VCC1), and the second end of the fourth transistor (Q4) is connected to the driving end (VCC).

8. The driving circuit board according to claim 7, wherein: The first interface subcircuit further includes: an eighth resistor (R8), a first end of the eighth resistor (R8) being connected to the first control end (VCC0), and a second end of the eighth resistor (R8) being connected to the control end of the fifth transistor (Q5); the fifth transistor (Q5), a control end of the fifth transistor (Q5) being connected to the eighth resistor (R8), a first end of the fifth transistor (Q5) being connected to the transmitting end of the level conversion circuit, and a second end of the fifth transistor (Q5) being connected to the transmitting end of the debug interface; a ninth resistor (R9), wherein a first end of the ninth resistor (R9) is connected to the first control end (VCC0), and a second end of the ninth resistor (R9) is connected to the control end of the sixth transistor (Q6); a sixth transistor (Q6), a control end of the sixth transistor (Q6) being connected to the ninth resistor (R9), a first end of the sixth transistor (Q6) being connected to the receiving end of the debugging interface, and a second end of the sixth transistor (Q6) being connected to the receiving end of the level conversion circuit; The second interface subcircuit further includes: a tenth resistor (R10), a first end of the tenth resistor (R10) connected to the second control end (VCC1), and a second end of the tenth resistor (R10) connected to the control end of the seventh transistor (Q7); the seventh transistor (Q7), a control end of the seventh transistor (Q7) being connected to the tenth resistor (R10), a first end of the seventh transistor (Q7) being connected to the transmitting end of the level conversion circuit, and a second end of the seventh transistor (Q7) being connected to the transmitting end of the communication interface; an eleventh resistor (R11), a first end of the eleventh resistor (R11) being connected to the second control end (VCC1), and a second end of the eleventh resistor (R11) being connected to the control end of the eighth transistor (Q8); The eighth transistor (Q8), the control end of the eighth transistor (Q8) is connected to the eleventh resistor (R11), the first end of the eighth transistor (Q8) is connected to the receiving end of the communication interface, and the second end of the eighth transistor (Q8) is connected to the receiving end of the level conversion circuit.

9. The driving circuit board according to claim 8, characterized in that: The first resistor (R1), the fourth resistor (R4) and the seventh resistor (R7) have a first resistance value; the second resistor (R2), the third resistor (R3), the fifth resistor (R5) and the sixth resistor (R6) have a second resistance value; the eighth resistor (R8), the ninth resistor (R9), the tenth resistor (R10) and the eleventh resistor (R11) have a third resistance value; the first resistance value is greater than the third resistance value, and the third resistance value is greater than the second resistance value.

10. A control method for a driving circuit board according to any one of claims 1 to 9, characterized in that: The method comprises: In response to the second interface of the connector of the driving circuit board being connected to an external device through a communication line, the switching circuit of the driving circuit board electrically couples the level conversion circuit of the driving circuit board with the communication interface of the system-on-chip of the driving circuit board, so that the system-on-chip communicates with the external device; In response to the second interface of the connector of the driving circuit board being connected to a debugging device via a debugging line, the switching circuit electrically couples the level conversion circuit to the debugging interface of the system-on-chip, so that the debugging device debugs the system-on-chip.

11. A display device, characterized in that: include: Display panel; The driving circuit board according to any one of claims 1 to 9 is electrically coupled to the display panel and configured to provide a driving signal to the display panel.

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