Electronic device

Abstract

The invention provides an electronic device. The electronic device comprises an electronic panel, a plurality of signal drivers and a controller. The electronic panel includes a plurality of signal lines. The plurality of signal lines are divided into a plurality of signal line groups. The plurality of signal drivers are electrically connected to the plurality of signal line groups, respectively. Every two adjacent signal drivers among the plurality of signal drivers are electrically connected with each other. The controller transmits a clock embedded digital signal to a first-stage signal driver among the plurality of signal drivers. The plurality of signal drivers are connected in a point-to-point manner, and clock embedded digital signals are sequentially transmitted from the first-stage signal driver to the Nth-stage signal driver among the plurality of signal drivers in a cascade manner by the plurality of signal drivers in a point-to-point manner. Wherein N is greater than 1.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and more particularly to an electronic device that transmits signals based on a point-to-point connection. Background Art

[0002] Current electronic devices may include multiple signal drivers and controllers. The multiple signal drivers respectively drive part of the circuits or part of the pixels in the electronic device. The controller can use a point-to-point online method to send a first drive signal to a first signal driver among the multiple signal drivers, and send a second drive signal to a second signal driver among the multiple signal drivers, and so on. However, the controller must transmit the drive signal to each of the multiple signal drivers. In addition, in the design of the circuit, the number of ports of the controller increases as the number of signal drivers increases. Therefore, the cost of the controller will be increased. Summary of the Invention

[0003] The present disclosure provides an electronic device capable of reducing the cost of a controller of the electronic device.

[0004] According to an embodiment of the present disclosure, an electronic device includes an electronic panel, a plurality of signal drivers, and a controller. The electronic panel includes a plurality of signal lines. The plurality of signal lines are divided into a plurality of signal line groups. The plurality of signal drivers are electrically connected to the plurality of signal line groups, respectively. Two adjacent ones of the plurality of signal drivers are electrically connected to each other. The controller is electrically connected to a first-level signal driver among the plurality of signal drivers. The controller transmits a clock-embedded digital signal to the first-level signal driver. The plurality of signal drivers transmit the clock-embedded digital signal in a cascade manner from the first-level signal driver to the Nth-level signal driver among the plurality of signal drivers in a point-to-point connection. Wherein N is greater than 1.

[0005] Based on the above, the controller transmits the clock-embedded digital signal to the first-stage signal driver. Furthermore, the clock-embedded digital signal is sequentially transmitted from the first-stage signal driver to the Nth-stage signal driver via a point-to-point connection. It should be noted that the controller does not need to send the drive signal to each of the multiple signal drivers. Therefore, the number of controller ports does not need to increase as the number of signal drivers increases. Consequently, the cost of the controller is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0007] Figure 2is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0008] Figure 3 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0009] Figure 4 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0010] Figure 5 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0011] Figure 6 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0012] Figure 7 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0013] Figure 8 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0014] Figure 9 is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0015] Figure 10 FIG. 1 is a schematic diagram of a signal driver according to an embodiment of the present disclosure.

[0016] Description of Reference Numerals

[0017] 100, 200, 300, 400, 500, 600, 700, 800, 900: electronic devices

[0018] 110: First Electronic Panel

[0019] 111, 111': Gate driver

[0020] 120_1 to 120_6, 120_1' to 120_6', 220_1: Signal drivers

[0021] 130: Controller

[0022] 221: Receiving circuit

[0023] 222: Transmitting circuit

[0024] 223: Latch

[0025] 224: Digital-to-Analog Converter (DAC)

[0026] 225: Output buffer

[0027] 310: Second electronic panel

[0028] D1_1~D1_m: data drive signal

[0029] L1_1 to L1_m, L2_2 to L2_m, L3_1 to L3_m, L4_m to L4_m, L5_1 to L5_m, L6_1 to L6_m: signal lines

[0030] LG1~LG6: signal line group

[0031] FS1~FS6、FS1'~FS6':Flat cable structure

[0032] P0n~P6n, P0p~P6p, P0n'~P5n', P0p'~P5p', PGC1, PGC2, PGC': routing

[0033] P1: First side

[0034] P2: Second side

[0035] PCB1, PCB2: circuit boards

[0036] PX, PX': pixels

[0037] S1: Schematic diagram of the first side

[0038] S2: Schematic diagram of the second side

[0039] SCE: Clock Embedded Digital Signal

[0040] SD1_1~SD1_m: data signal

[0041] SGC: Gate control signal

[0042] SS: Scan signal

[0043] TCON: Timing Controller DETAILED DESCRIPTION

[0044] The present disclosure may be understood by referring to the following detailed description in conjunction with the accompanying drawings, as described below. It should be noted that for the purposes of clarity and ease of understanding, the various figures of the present disclosure illustrate portions of electronic devices, and that certain components in the various figures may not be drawn to scale. Furthermore, the number and size of each device shown in the figures are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

[0045] Certain terms are used throughout the description and in the following claims to refer to specific components. As will be understood by those skilled in the art, electronic device manufacturers may refer to components by different names. This document is not intended to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms "include," "including," and "have" are used in an open-ended manner and should therefore be interpreted to mean "including, but not limited to..." Therefore, when the terms "include," "include," and / or "have" are used in the description of this disclosure, it will indicate the presence of corresponding features, regions, steps, operations, and / or components, but is not limited to the presence of one or more corresponding features, regions, steps, operations, and / or components.

[0046] It should be understood that when a component is referred to as being “coupled to,” “connected to,” or “connected to” another component, the component may be directly connected to the other component and an electrical connection may be directly established, or an intermediate component may be present between the components for relaying the electrical connection (indirect electrical connection). In contrast, when a component is referred to as being “directly coupled to,” “directly connected to,” or “directly connected to” another component, there are no intermediate components.

[0047] Although terms such as first, second, and third may be used to describe different components, such components are not limited by these terms. The terms are used only to distinguish a component from other components in the specification. The scope of protection may not use the same terms, but may use the terms first, second, and third relative to the required order of the components. Therefore, in the following description, the first component may be the second component in the scope of protection.

[0048] The electronic device disclosed herein may include a display device, an antenna device, a sensing device, a light-emitting device, a touch electronic device, a curved electronic device, or a free-shape electronic device, but is not limited thereto. The electronic device may include a bendable or flexible electronic device. The electronic device may, for example, include liquid crystal, a light-emitting diode, a quantum dot (QD), fluorescence, phosphorescence, other suitable display media, or a combination of the above materials, but is not limited thereto. The light-emitting diode may, for example, include an organic light-emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED, or a quantum dot light-emitting diode (QDLED), or other suitable materials, or a combination of the above, but is not limited thereto. The display device may, for example, include a spliced ​​display device, but is not limited thereto. The antenna device may, for example, be a liquid crystal antenna, but is not limited thereto. The antenna device may, for example, include an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any of the aforementioned arrangements and combinations, but is not limited thereto. In addition, the appearance of the electronic device may be rectangular, circular, polygonal, a shape with curved edges, or other suitable shapes. The electronic device may have a peripheral system such as a drive system, a control system, a light source system, etc. to support a display device, an antenna device, or a splicing device, but the present disclosure is not limited thereto. The sensing device may include a camera or an infrared sensor (infrared sensor) or a fingerprint sensor, etc., and the present disclosure is not limited thereto. In some embodiments, the sensing device may also include a flash, an infrared (IR) light source, other sensors, electronic components, or a combination thereof, but is not limited thereto.

[0049] In the present disclosure, embodiments use the term "pixel" or "pixel unit" to describe a specific area containing at least one functional circuit for at least one specific function. The area of ​​a "pixel" depends on the unit used to provide the specific function. Adjacent pixels may share the same components or conductors, but may also include their own specific components. For example, adjacent pixels may share the same scan line or the same data line, but a pixel may also include at least one of its own transistors, capacitors, and at least one light-emitting diode.

[0050] It should be noted that the technical features in the different embodiments described below may be replaced, recombined, or mixed with each other to constitute another embodiment without departing from the spirit of the present disclosure.

[0051] Please refer to Figure 1 , Figure 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. In this embodiment, electronic device 100 includes a first electronic panel 110, signal drivers 120_1-120_6, and a controller 130. While electronic device 100 may be a display device, the present disclosure is not limited thereto. In some embodiments, first electronic panel 110 may be an antenna panel, a sensor panel, a light-emitting panel, a touch display panel, a curved display panel, or a free-form display panel.

[0052] In this embodiment, the first electronic panel 110 includes signal lines L1_1-L1_m, L2_2-L2_m, L3_1-L3_m, L4_1-L4_m, L5_1-L5_m, and L6_1-L6_m. The signal lines L1_1-L1_m, L2_2-L2_m, L3_1-L3_m, L4_1-L4_m, L5_1-L5_m, and L6_1-L6_m are divided or grouped into signal line groups LG1-LG6. For example, L1_1-L1_m are divided into signal line group LG1. Signal lines L2_2-L2_m are divided into signal line group LG2, and so on. In this embodiment, signal drivers 120_1-120_6 are each configured to drive at least one corresponding circuit or at least one corresponding pixel in the first electronic panel 110.

[0053] In this embodiment, two adjacent ones of the signal drivers 120_1 - 120_6 are electrically connected to each other. In other words, the signal drivers 120_1 - 120_6 are electrically connected in series.

[0054] In this embodiment, the controller 130 is electrically connected to the signal driver 120_1. The controller 130 transmits a clock-embedded digital signal SCE to the signal driver 120_1. The signal drivers 120_1 to 120_6 are connected in a point-to-point manner, sequentially transmitting the clock-embedded digital signal SCE from the signal driver 120_1 (i.e., the first-stage signal driver) to the signal driver 120_6 (i.e., the sixth-stage signal driver) in a cascade fashion.

[0055] It's worth noting that the controller 130 transmits the clock-embedded digital signal SCE to the signal driver 120_1. Furthermore, the clock-embedded digital signal SCE is sequentially transmitted from the signal driver 120_1 to the signal driver 120_6 via a point-to-point connection. It should be noted that the controller 130 does not need to send a different drive signal to each of the signal drivers 120_1 through 120_6. Therefore, the number of ports on the controller 130 does not need to increase as the number of signal drivers 120_1 through 120_6 increases. Consequently, the cost of the controller 130 is reduced. Furthermore, the workload of the controller 130 can be reduced.

[0056] For ease of description, the number of the signal drivers 120_1 to 120_6 in this embodiment is 6, but the present disclosure is not limited thereto. The number of the signal drivers in the present disclosure can be multiple.

[0057] In this embodiment, the clock-embedded digital signal SCE is a differential signal, so the clock-embedded digital signal SCE is less susceptible to electromagnetic interference (EMI) and electrostatic discharge (ESD).

[0058] In this embodiment, the signal drivers 120_1 to 120_6 each include a source driver circuit, and each of the signal drivers 120_1 to 120_6 provides data according to the clock-embedded digital signal SCE, and utilizes the data to drive corresponding circuits or pixels in the first electronic panel 110 .

[0059] In this embodiment, the first electronic panel 110 further includes a gate driver 111. The controller 130 is electrically connected to the gate driver 111. The controller 130 transmits a gate control signal SGC to the gate driver 111. The gate driver 111 can provide a scan signal SS according to the gate control signal SGC.

[0060] In this embodiment, the controller 130 includes a timing controller TCON that generates a clock-embedded digital signal SCE and a gate control signal SGC.

[0061] Please refer to Figure 2 , Figure 2 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. Figure 2A schematic diagram S1 of a first side of an electronic device 200 and a schematic diagram S2 of a second side of the electronic device 200 are shown. In this embodiment, the electronic device 200 includes a first electronic panel 110, signal drivers 120_1-120_6, and a controller 130. The controller 130 is disposed on a circuit board PCB1. The signal drivers 120_1-120_6 are electrically connected to the circuit board PCB1 via any form of chip-on-film (COF) packaging. Adjacent pairs of the signal drivers 120_1-120_6 are electrically connected to each other via traces on the circuit board PCB1.

[0062] In this embodiment, circuit board PCB1 includes traces P0n-P5n, P0p-P5p, and PGC1. Traces P0n and P0p are configured as a differential trace pair. Traces P1n and P1p are configured as another differential trace pair, and so on. The controller 130 is electrically connected to the signal driver 120_1 via traces P0n and P0p, and provides the clock-embedded digital signal SCE to the signal driver 120_1 via traces P0n and P0p. Adjacent two of the signal drivers 120_1-120_6 are electrically connected via a differential trace pair. The signal driver 120_1 transmits the clock-embedded digital signal SCE to the signal driver 120_2 via traces P1n and P1p. The signal driver 120_2 transmits the clock-embedded digital signal SCE to the signal driver 120_3 via traces P2n and P2p, and so on.

[0063] In this embodiment, the first electronic panel 110 includes a plurality of pixels PX and a gate driver 111. The pixels PX are arranged on the first surface P1 of the first electronic panel 110. The signal drivers 120_1 to 120_6 are electrically connected to the second surface P2 of the first electronic panel 110 and the circuit board PCB1 through a COF packaging method. The second surface P2 is opposite to the first surface P1. The signal lines (e.g., Figure 1 The signal lines L1_1 to L1_m, L2_2 to L2_m, L3_1 to L3_m, L4_1 to L4_m, L5_1 to L5_m, and L6_1 to L6_m) can be electrically connected to one of the signal drivers 120_1 to 120_6 via a through-hole connection structure or a sidewall connection structure. Therefore, the first electronic panel 110 can retain a larger active area.

[0064] The controller 130 provides the gate control signal SGC to the gate driver 111 through the trace PGC1 of the circuit board PCB1 and the trace in the COF of the signal driver 120_1. In this embodiment, the gate driver 111 can Figure 1The first electronic panel 110 includes a plurality of gate drivers 111. Each of the plurality of gate drivers 111 provides a scan signal to a corresponding row of pixels. In some embodiments, the first electronic panel 110 includes a plurality of gate drivers 111. Each of the plurality of gate drivers 111 provides a scan signal to a corresponding row of pixels. In some embodiments, the first electronic panel 110 includes a single gate driver 111. The gate driver 111 provides scan signals to different rows of pixels sequentially or simultaneously.

[0065] Please refer to Figure 3 , Figure 3 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. In this embodiment, the electronic device 300 is a splicing device. The electronic device 300 includes a first electronic panel 110, a second electronic panel 310, signal drivers 120_1 to 120_6, 120_1' to 120_6', a controller 130, and circuit boards PCB1 and PCB2. The first electronic panel 110, signal drivers 120_1 to 120_6, and controller 130 and the implementation thereof have been previously described. Figure 2 The above is clearly described in the embodiments, so it will not be repeated here.

[0066] In this embodiment, the circuit board PCB1 is electrically connected to the circuit board PCB2 via a signal transmission interface CI. The signal driver 120_6 transmits the clock-embedded digital signal SCE to the circuit board PCB2 via the circuit board PCB1 and the signal transmission interface CI. Furthermore, the controller 130 transmits the gate control signal SGC to the circuit board PCB2 via the circuit board PCB1 and the signal transmission interface CI.

[0067] In this embodiment, the signal transmission interface CI can be any form of bus or signal transmission cable, such as a coaxial cable.

[0068] In this embodiment, signal drivers 120_1' to 120_6' are electrically connected between circuit board PCB2 and the second electronic panel 310 via a COF package. Circuit board PCB2 includes traces P0n' to P5n', P0p' to P5p', and PGC'. The second electronic panel 310 includes a plurality of pixels PX' and a gate driver 111'. Signal driver 120_6 is electrically connected to signal driver 120_1' via traces P6n and P6p of circuit board PCB1, a signal transmission interface CI, and traces P0n' and P0p' of circuit board PCB2. Signal driver 120_6 provides a clock-embedded digital signal SCE to signal driver 120_1' via traces P6n and P6p of circuit board PCB1, a signal transmission interface CI, and traces P0n' and P0p' of circuit board PCB2. Signal driver 120_1' transmits the clock-embedded digital signal SCE to signal driver 120_2' via traces P1n' and P1p'. The signal driver 120_2 ′ transmits the clock-embedded digital signal SCE to the signal driver 120_3 ′ through the traces P2n′ and P2p′, and so on.

[0069] The controller 130 provides the gate control signal SGC to the gate driver 111' through the trace PGC2 of the circuit board PCB1, the signal transmission interface CI, the trace PGC' of the circuit board PCB2, and the trace in the COF of the signal driver 120_1'. In this embodiment, the gate driver 111' can Figure 1 The scanning signal SS) is provided to at least one of the plurality of pixels PX'. In some embodiments, the second electronic panel 310 includes a plurality of gate drivers 111'. Each of the plurality of gate drivers 111' provides a scanning signal to a corresponding pixel row. In some embodiments, the second electronic panel 310 includes a plurality of gate drivers 111'. Each of the plurality of gate drivers 111' provides a scanning signal to a corresponding pixel row. In some embodiments, the first electronic panel 110 includes a single gate driver 111. The gate driver 111 provides scanning signals to different pixel rows sequentially or simultaneously.

[0070] In some embodiments, the electronic panel 310, the signal drivers 120_1' to 120_6' and the circuit board PCB2 can be implemented by Figure 5 、 Figure 7 、 Figure 9 is implemented by one of the implementation methods.

[0071] Please refer to Figure 4 , Figure 4 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. Figure 4A schematic diagram S1 of a first side of an electronic device 400 and a schematic diagram S2 of a second side of an electronic device 200 are shown. In this embodiment, the electronic device 400 includes a first electronic panel 110, signal drivers 120_1-120_6, and a controller 130. The controller 130 is disposed on a circuit board PCB1. The signal drivers 120_1-120_6 are electrically connected to the circuit board PCB1 via a COF package. Adjacent pairs of the signal drivers 120_1-120_6 are electrically connected to each other via traces on the first electronic panel 110.

[0072] In this embodiment, the circuit board PCB1 includes traces P0n, P0p, and PGC1. The first electronic panel 110 includes traces P1n-P5n, P1p-P5p, PGC1, a plurality of pixels PX, and a gate driver 111. The controller 130 is electrically connected to the signal driver 120_1 via the traces P0n and P0p, and provides the clock-embedded digital signal SCE to the signal driver 120_1 via the traces P0n and P0p. Adjacent two of the signal drivers 120_1-120_6 are electrically connected via differential trace pairs. The signal driver 120_1 transmits the clock-embedded digital signal SCE to the signal driver 120_2 via the traces P1n and P1p. The signal driver 120_2 transmits the clock-embedded digital signal SCE to the signal driver 120_3 via the traces P2n and P2p, and so on.

[0073] In this embodiment, pixels PX are disposed on the first surface P1 of the first electronic panel 110. Signal drivers 120_1-120_6 are electrically connected to the second surface P2 of the first electronic panel 110 and the printed circuit board PCB1 via a COF package. Signal lines of the first electronic panel 110 can be electrically connected to one of the signal drivers 120_1-120_6 via a through-hole connection structure or a sidewall connection structure. As a result, the first electronic panel 110 can retain a larger active area.

[0074] In this embodiment, the controller 130 provides the gate control signal SGC to the gate driver 111 through the trace PGC1 of the circuit board PCB1 and the traces in the COF of the signal driver 120_1 .

[0075] Please refer to Figure 5 , Figure 51 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. In this embodiment, the electronic device 500 is a splicing device. The electronic device 500 includes a first electronic panel 110, a second electronic panel 310, signal drivers 120_1 to 120_6, 120_1' to 120_6', a controller 130, and circuit boards PCB1 and PCB2. The first electronic panel 110, signal drivers 120_1 to 120_6, and controller 130 and the implementation thereof have been previously described. Figure 4 The above is clearly described in the embodiments, so it will not be repeated here.

[0076] In this embodiment, the circuit board PCB1 is electrically connected to the circuit board PCB2 via a signal transmission interface CI. The signal driver 120_6 transmits the clock-embedded digital signal SCE to the circuit board PCB2 via the circuit board PCB1 and the signal transmission interface CI. Furthermore, the controller 130 transmits the gate control signal SGC to the circuit board PCB2 via the circuit board PCB1 and the signal transmission interface CI.

[0077] In this embodiment, the signal drivers 120_1' to 120_6' are electrically connected between the circuit board PCB2 and the second electronic panel 310 via a COF packaging method. The circuit board PCB2 includes traces P0n', P0p', and PGC'. The second electronic panel 310 includes traces P1n' to P5n', P1p' to P5p', a plurality of pixels PX', and a gate driver 111'. The signal driver 120_6 is electrically connected to the signal driver 120_1' via the traces P6n and P6p of the circuit board PCB1, the signal transmission interface CI, and the traces P0n' and P0p' of the circuit board PCB2. The signal driver 120_6 provides the clock embedded digital signal SCE to the signal driver 120_1' via the traces P6n and P6p of the circuit board PCB1, the signal transmission interface CI, and the traces P0n' and P0p' of the circuit board PCB2. The signal driver 120_1' transmits the clock-embedded digital signal SCE to the signal driver 120_2' via the traces P1n' and P1p'. The signal driver 120_2' transmits the clock-embedded digital signal SCE to the signal driver 120_3' via the traces P2n' and P2p', and so on.

[0078] The controller 130 provides the gate control signal SGC to the gate driver 111 ′ through the trace PGC2 of the circuit board PCB1 , the signal transmission interface CI, the trace PGC′ of the circuit board PCB2 , and the traces in the COF of the signal driver 120_1 ′.

[0079] In some embodiments, the electronic panel 310, the signal drivers 120_1' to 120_6' and the circuit board PCB2 can be implemented by Figure 3、 Figure 7 、 Figure 9 is implemented by one of the implementation methods.

[0080] Please refer to Figure 6 , Figure 6 FIG2 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. In this embodiment, the electronic device 600 includes a first electronic panel 110, signal drivers 120_1-120_6, and a controller 130. The controller 130 is disposed on a circuit board PCB1. The signal drivers 120_1-120_6 are disposed on the first electronic panel 110. Adjacent pairs of the signal drivers 120_1-120_6 are electrically connected to each other via a flat cable structure and traces on the circuit board PCB1.

[0081] In this embodiment, circuit board PCB1 is electrically connected to signal drivers 120_1-120_6 via flat cable structures FS1-FS6. Circuit board PCB1 includes traces P0n-P5n, P0p-P5p, and PGC1. Controller 130 is electrically connected to signal driver 120_1 via traces P0n, P0p, and the flat cable structure FS1. Controller 130 provides clock-embedded digital signals SCE to signal driver 120_1 via traces P0n, P0p, and the flat cable structure FS1. Signal driver 120_1 transmits clock-embedded digital signals SCE to signal driver 120_2 via the flat cable structure FS1, traces P1n, P1p, and the flat cable structure FS2. Signal driver 120_2 transmits clock-embedded digital signals SCE to signal driver 120_3 via the flat cable structure FS2, traces P2n, P2p, and the flat cable structure FS3, and so on.

[0082] Furthermore, the controller 130 provides the gate control signal SGC to the gate driver 111 via the trace PGC1 of the circuit board PCB1 and the flat cable structure FS1 .

[0083] In this embodiment, the flat cable structures FS1 - FS6 may be flexible flat cable (FFC) components, but the present disclosure is not limited thereto.

[0084] Please refer to Figure 7 , Figure 7 Schematic diagram of an electronic device according to an embodiment of the present disclosure. In this embodiment, the electronic device 700 is a splicing device. The electronic device 300 includes a first electronic panel 110, a second electronic panel 310, signal drivers 120_1 to 120_6, 120_1' to 120_6', a controller 130, and circuit boards PCB1 and PCB2. The first electronic panel 110, signal drivers 120_1 to 120_6, and controller 130 and the implementation thereof have been previously described. Figure 6 The above is clearly described in the embodiments, so it will not be repeated here.

[0085] In this embodiment, the circuit board PCB1 is electrically connected to the circuit board PCB2 via a signal transmission interface CI. The signal driver 120_6 transmits the clock-embedded digital signal SCE to the circuit board PCB2 via the circuit board PCB1 and the signal transmission interface CI. Furthermore, the controller 130 transmits the gate control signal SGC to the circuit board PCB2 via the circuit board PCB1 and the signal transmission interface CI.

[0086] In this embodiment, the signal drivers 120_1' to 120_6' are arranged on the second electronic panel 310. The second electronic panel 310 includes a plurality of pixels PX' and a gate driver 111'. The circuit board PCB2 is electrically connected to the signal drivers 120_1' to 120_6' via a flat cable structure FS1' to FS6'. The circuit board PCB2 includes traces P0n' to P5n', P0p' to P5p', and PGC'. The signal driver 120_6 is electrically connected to the signal driver 120_1' via the flat cable structure FS6, the traces P6n and P6p of the circuit board PCB1, the signal transmission interface CI, the traces P0n' and P0p' of the circuit board PCB2, and the flat cable structure FS1'. Signal driver 120_6 provides a clock-embedded digital signal SCE to signal driver 120_1' via flat cable structure FS6, traces P6n and P6p on circuit board PCB1, signal transmission interface CI, traces P0n' and P0p' on circuit board PCB2, and flat cable structure FS1'. Signal driver 120_1' transmits the clock-embedded digital signal SCE to signal driver 120_2' via traces P1n' and P1p'. Signal driver 120_2' transmits the clock-embedded digital signal SCE to signal driver 120_3' via traces P2n' and P2p', and so on.

[0087] The controller 130 provides the gate control signal SGC to the gate driver 111 ′ through the trace PGC2 of the circuit board PCB1 , the signal transmission interface CI, the trace PGC′ of the circuit board PCB2 , and the flat cable structure FS1 ′.

[0088] In this embodiment, the flat cable structures FS1 ′ to FS6 ′ may be FFC components, but the present disclosure is not limited thereto.

[0089] In some embodiments, the electronic panel 310, the signal drivers 120_1' to 120_6' and the circuit board PCB2 can be implemented by Figure 3 、 Figure 5 、 Figure 9 is implemented by one of the implementation methods.

[0090] Please refer to Figure 8 , Figure 8 FIG1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure. In this embodiment, the electronic device 800 includes a first electronic panel 110, signal drivers 120_1-120_6, and a controller 130. The controller 130 is disposed on a circuit board PCB1. The signal drivers 120_1-120_6 are disposed on the first electronic panel 110. Adjacent pairs of the signal drivers 120_1-120_6 are electrically connected to each other via traces on the first electronic panel 110.

[0091] In this embodiment, the circuit board PCB1 includes traces P0n, P0p, and PGC1. The electronic panel 110 includes traces P1n-P5n, P1p-P5p, PGC1, a plurality of pixels PX, and a gate driver 111. The controller 130 is electrically connected to the signal driver 120_1 via the traces P0n, P0p, and the flat cable structure FS1. The controller 130 provides the clock-embedded digital signal SCE to the signal driver 120_1 via the traces P0n, P0p, and the flat cable structure FS1. Adjacent two of the signal drivers 120_1-120_6 are electrically connected via differential trace pairs. The signal driver 120_1 transmits the clock-embedded digital signal SCE to the signal driver 120_2 via the traces P1n and P1p. The signal driver 120_2 transmits the clock-embedded digital signal SCE to the signal driver 120_3 via the traces P2n and P2p, and so on.

[0092] In this embodiment, the controller 130 provides the gate control signal SGC to the gate driver 111 via the trace PGC1 and the flat cable structure FS1 .

[0093] Please refer to Figure 9 , Figure 9 Schematic diagram of an electronic device according to an embodiment of the present disclosure. In this embodiment, the electronic device 900 is a splicing device. The electronic device 300 includes a first electronic panel 110, a second electronic panel 310, signal drivers 120_1 to 120_6, 120_1' to 120_6', a controller 130, and circuit boards PCB1 and PCB2. The first electronic panel 110, signal drivers 120_1 to 120_6, and controller 130 and the implementation thereof have been previously described. Figure 8 The above is clearly described in the embodiments, so it will not be repeated here.

[0094] In this embodiment, circuit board PCB1 is electrically connected to circuit board PCB2 via a signal transmission interface CI. Signal driver 120_6 transmits clock-embedded digital signal SCE to circuit board PCB2 via flat cable structure FS6, circuit board PCB1, and signal transmission interface CI. Furthermore, controller 130 transmits gate control signal SGC to circuit board PCB2 via circuit board PCB1 and signal transmission interface CI.

[0095] In this embodiment, signal drivers 120_1' to 120_6' are disposed on the second electronic panel 310. The signal driver 120_1 is electrically connected to the circuit board PCB2 via a flat cable structure FS1'. The circuit board PCB2 includes traces P0n', P0p', and PGC'. The second electronic panel 310 includes traces P1n' to P5n', P1p' to P5p', a plurality of pixels PX', and a gate driver 111'. The signal driver 120_6 is electrically connected to the signal driver 120_1' via the flat cable structure FS6, traces P6n and P6p of the circuit board PCB1, a signal transmission interface CI, traces P0n' and P0p' of the circuit board PCB2, and the flat cable structure FS1'. Signal driver 120_6 provides a clock-embedded digital signal SCE to signal driver 120_1' via the flat cable structure FS2, traces P6n and P6p on PCB1, the signal transmission interface CI, traces P0n' and P0p' on PCB2, and the flat cable structure FS1'. Signal driver 120_1' transmits the clock-embedded digital signal SCE to signal driver 120_2' via traces P1n' and P1p'. Signal driver 120_2' transmits the clock-embedded digital signal SCE to signal driver 120_3' via traces P2n' and P2p', and so on.

[0096] The controller 130 provides the gate control signal SGC to the gate driver 111 ′ through the trace PGC2 of the circuit board PCB1 , the signal transmission interface CI, the trace PGC′ of the circuit board PCB2 , and the flat cable structure FS1 ′.

[0097] In some embodiments, the electronic panel 310, the signal drivers 120_1' to 120_6' and the circuit board PCB2 can be implemented by Figure 3 、 Figure 5 、 Figure 7 It is implemented by one of the implementation methods.

[0098] Please refer to Figure 1 as well as Figure 10 , Figure 10FIG2 is a schematic diagram of a signal driver according to an embodiment of the present disclosure. In this embodiment, signal driver 220_1 is suitable for use as signal driver 120_1. Signal driver 220_1 includes a receiving circuit 221, a transmitting circuit 222, a latch 223, a digital-to-analog converter (DAC) 224, and an output buffer 225. The receiving circuit 221 is electrically connected to the controller 130. The receiving circuit 221 receives the clock-embedded digital signal SCE provided by the controller 130. The transmitting circuit 222 is electrically connected to the receiving circuit 221 and the next-stage signal driver (e.g., signal driver 120_2).

[0099] The latch 223 is electrically connected to the receiving circuit 221. The latch 223 receives the clock-embedded digital signal SCE through the receiving circuit 221. In this embodiment, the clock-embedded digital signal SCE includes data signals SD1_1-SD1_m and a point-to-point communication protocol. The latch 223 receives the data signals SD1_1-SD1_m according to the point-to-point communication protocol. The data signals SD1_1-SD1_m are digital signals. After receiving the data signals SD1_1-SD1_m, the latch 223 instructs the receiving circuit 221 to provide the clock-embedded digital signal SCE to the transmitting circuit 222. The transmitting circuit 222 then transmits the clock-embedded digital signal SCE to the next-stage signal driver.

[0100] In this embodiment, the DAC 224 is electrically connected to the latch 223. The DAC 224 receives data signals SD1_1-SD1_m. The DAC 224 converts the data signals SD1_1-SD1_m into data drive signals D1_1-D1_m. The data drive signals D1_1-D1_m are analog signals. The data drive signals D1_1-D1_m can be voltage signals, current signals, pulse-width modulation (PWM) signals, or pulse-amplitude modulation (PAM) signals. The output buffer 225 is electrically connected to the DAC 224. The output buffer 225 receives the data drive signals D1_1-D1_m and provides the data drive signals D1_1-D1_m to the signal line group LG1. For example, the output buffer 225 provides the data drive signal D1_1 to the signal line L1_1. The output buffer 225 provides the data driving signal D1_2 to the signal line L1_2, and so on.

[0101] also, Figure 1 The signal drivers 120_2 to 120_6 and Figures 2 to 9The circuit designs of the signal drivers 120_1 ˜ 120_6 , 120_1 ′˜ 120_6 ′ may be similar to the signal driver 120_1 of the present embodiment.

[0102] In summary, the controller transmits the clock-embedded digital signal to the first-stage signal driver. The clock-embedded digital signal is sequentially transmitted from the first-stage signal driver to the final-stage signal driver via a point-to-point connection. It should be noted that the controller does not need to send the drive signal to each of the multiple signal drivers. Therefore, the number of controller ports does not need to increase as the number of signal drivers increases. This reduces the cost of the controller.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An electronic device, characterized in that: The electronic device comprises: A first electronic panel comprising a plurality of signal lines, wherein the plurality of signal lines are divided into a plurality of signal line groups; a plurality of first signal drivers, each electrically connected to the plurality of signal line groups, and two adjacent ones of the plurality of signal drivers are electrically connected to each other; and a controller electrically connected to a first-stage signal driver among the plurality of signal drivers, and configured to transmit a clock-embedded digital signal to the first-stage signal driver; The plurality of signal drivers are connected point-to-point to sequentially transmit the clock-embedded digital signal from the first-stage signal driver to the Nth-stage signal driver among the plurality of signal drivers in a cascade manner, where N is greater than 1.

2. The electronic device according to claim 1, wherein: The clock embedded digital signal is a differential signal.

3. The electronic device according to claim 1, wherein: The first electronic panel further includes: The gate driver includes a controller that further transmits a gate control signal to the gate driver.

4. The electronic device according to claim 3, wherein: The controller is provided on a circuit board, and The controller is electrically connected to the gate driver and the first-stage signal driver via a flat cable structure and traces on the circuit board.

5. The electronic device according to claim 1, wherein: The controller is arranged on a circuit board, The plurality of signal drivers are electrically connected to the circuit board through a chip-on-film packaging method, and Two adjacent ones of the plurality of signal drivers are electrically connected to each other through traces on the circuit board.

6. The electronic device according to claim 5, wherein: The first electronic panel further includes: pixels, arranged on the first surface of the first electronic panel, The plurality of signal drivers are electrically connected between the second surface of the first electronic panel and the circuit board through the chip-on-film packaging method.

7. The electronic device according to claim 1, wherein: The controller is arranged on a circuit board, The plurality of signal drivers are electrically connected to the circuit board through a chip-on-film packaging method, and Two adjacent ones of the plurality of signal drivers are electrically connected to each other through wiring on the first electronic panel.

8. The electronic device according to claim 1, wherein: The plurality of signal drivers are arranged on the first electronic panel, The controller is provided on a circuit board, and Two adjacent ones of the plurality of signal drivers are electrically connected to each other through a flat cable structure and traces on the circuit board.

9. The electronic device according to claim 1, wherein: The plurality of signal drivers are arranged on the first electronic panel, The controller is provided on a circuit board, and Two adjacent ones of the plurality of signal drivers are electrically connected to each other through wiring on the first electronic panel.

10. The electronic device according to claim 1, wherein: The electronic device further comprises: a second electronics panel; and a second circuit board, electrically connected to the second electronic panel, The controller is arranged on the first circuit board. The first circuit board is electrically connected to the second circuit board via a signal transmission interface, and The Nth-stage signal driver transmits the clock-embedded digital signal to the second circuit board through the circuit board and the signal transmission interface.

11. The electronic device according to claim 10, wherein: The controller transmits the gate control signal to the second circuit board through the circuit board and the signal transmission interface.

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