Display device and electronic apparatus

Abstract

The invention provides a display device and an electronic apparatus capable of driving a data line at a high speed. The display device includes: a plurality of first light-emitting elements; a plurality of second light-emitting elements; a data transmission line; a first data line extending in a first direction; a second data line extending in the first direction and adjacent to the first data line along the first direction; a plurality of first pixel circuits which are connected to the first data line and are respectively connected to the plurality of first light-emitting elements; a plurality of second pixel circuits which are connected to the second data line and are respectively connected to the plurality of second light-emitting elements; a first switching circuit that controls electrical connection between the first data line and a data transfer line; and a second switching circuit that controls an electrical connection between the second data line and the data transmission line, the first switching circuit overlapping at least one of the plurality of first light emitting elements in a plan view.

Description

Technical Field

[0001] The present invention relates to a display device and an electronic device. Background Art

[0002] Display devices including light-emitting elements such as organic EL (Electro Luminescence) elements are known. In such display devices, a large number of pixel circuits including a plurality of transistors for driving the light-emitting elements and controlling light emission timing are connected to a single data line.

[0003] For example, Patent Document 1 discloses a display device in which a threshold voltage of a driving transistor of a light-emitting element is maintained at one end of a coupling capacitor provided between a data line and a pixel circuit, and data is then written to the pixel circuit from the other end of the coupling capacitor through a voltage change corresponding to grayscale data.

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 2021-96418

[0005] However, in the display device described in Patent Document 1, if the load capacitance of the data line increases with the increase in the number of pixels and the increase in screen size due to the high-definition display image, it becomes difficult to drive the data line at high speed, and the time required to initialize the voltage of the data line and write data becomes longer. Summary of the Invention

[0006] One embodiment of a display device according to the present invention includes: a plurality of first light-emitting elements; a plurality of second light-emitting elements; a data transmission line; a first data line extending in a first direction; a second data line extending in the first direction and adjacent to the first data line along the first direction; a plurality of first pixel circuits connected to the first data line and connected to the plurality of first light-emitting elements, respectively; a plurality of second pixel circuits connected to the second data line and connected to the plurality of second light-emitting elements, respectively; a first switching circuit controlling electrical connection between the first data line and the data transmission line; and a second switching circuit controlling electrical connection between the second data line and the data transmission line, wherein the first data line is supplied with a signal for causing each of the plurality of first light-emitting elements to emit light from the data transmission line via the first switching circuit, and the second data line is supplied with a signal for causing each of the plurality of second light-emitting elements to emit light from the data transmission line via the second switching circuit, and the first switching circuit overlaps with at least one of the plurality of first light-emitting elements when viewed from above.

[0007] One embodiment of an electronic device according to the present invention includes one embodiment of the above-mentioned display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a perspective view schematically showing the display device of this embodiment.

[0009] Figure 2 FIG. 1 is a plan view schematically showing a display panel of a display device.

[0010] Figure 3 This is a block diagram showing the electrical configuration of the display device according to the first embodiment.

[0011] Figure 4 It is a diagram showing the configuration of a pixel circuit and a data potential generating circuit.

[0012] Figure 5 This is a timing chart showing an example of waveforms of various signals in a display device.

[0013] Figure 6 A diagram for explaining the operation of the display device.

[0014] Figure 7 A diagram for explaining the operation of the display device.

[0015] Figure 8 A diagram for explaining the operation of the display device.

[0016] Figure 9 A diagram for explaining the operation of the display device.

[0017] Figure 10 is a cross-sectional view schematically showing a portion of the display panel.

[0018] Figure 11 It is a plan view showing a configuration example of a layout of a portion of the pixel circuit blocks BLK- 1 and BLK- 2 in the first embodiment.

[0019] Figure 12 It is a plan view showing a part of the layout of each pixel circuit block in the first embodiment in more detail.

[0020] Figure 13 This is a block diagram showing the electrical configuration of a display device according to the second embodiment.

[0021] Figure 14 It is a plan view showing a configuration example of a layout of a portion of pixel circuit blocks BLK- 1 and BLK- 2 in the second embodiment.

[0022] Figure 15 It is a plan view showing a part of the layout of each pixel circuit block in the second embodiment in more detail.

[0023] Figure 16 It is a perspective view schematically showing the head mounted display according to this embodiment.

[0024] Figure 17 This is a diagram schematically showing an image forming device and a light guide device of the head mounted display according to the present embodiment.

[0025] Description of labels

[0026] 1: Display device; 2: Display panel; 3: Control circuit; 11: Scan line; 12, 12R, 12B, 12G: Data line; 15: Power supply line; 17, 17-1, 17-2, 17-3, 17R, 17B, 17G: Data transmission line; 20, 20-1, 20-2, 20-3, 20R, 20B, 20G: Pixel circuit; 21: Scan line driver circuit; 22, 22-1, 22-2, 22-3, 22R, 22B, 22G: Switch circuit; 23, 23-1 , 23-2, 23-3: data potential generating circuit; 24, 24-1, 24-2, 24-3: MOSFET; 25: capacitor; 27, 27R, 27B, 27G: light-emitting element; 30: insulating layer; 40: organic EL element; 41: pixel electrode; 42: light-emitting functional layer; 43: common electrode; 44: light-emitting region; 50: substrate; 51: impurity region; 52: gate insulating layer; 53: gate electrode; 54, 55, 56, 57: interlayer insulating layer; 58: wiring layer; 5 9: Reflective layer; 60: Insulating layer; 62: Opening; 70: Sealing layer; 80: Coloring layer; 90: Counter substrate; 92: Adhesive layer; 112: Display area; 120: FPC substrate; 124: External connection terminal; 130: Housing; 201: Capacitor; 202-206: MOSFET; 208R, 208B, 208G: Through hole; 209R, 209B, 209G: Wiring; 221R, 221B, 221G: Through hole; 222R, 222B, 222 G: Wiring; 231-0 to 231-9: Capacitor element; 232: Capacitor element; 233-0 to 233-9, 234: Switching circuit; 900: Head-mounted display; 910a: First display unit; 910b: Second display unit; 911: Image forming device; 912: External component; 914: Projection device; 915: Light guiding device; 916: Image light guiding component; 917: Reflective layer; 918: Transparent component; 920: Frame; 930a: First temple; 930b: Second temple. DETAILED DESCRIPTION

[0027] Hereinafter, preferred embodiments of the present invention will be described in detail using the accompanying drawings. Furthermore, the embodiments described below are not intended to unduly limit the content of the present invention as described in the claims. Furthermore, not all of the structures described below are necessarily essential components of the present invention.

[0028] 1. Display device

[0029] 1-1. First embodiment

[0030] 1-1-1. Overall Structure of Display Device

[0031] Figure 1 It is a perspective view schematically showing the display device 1 according to the present embodiment. Figure 2 1 is a top view schematically showing the display panel 2 of the display device 1 according to this embodiment. Figure 1 as well as Figure 2 In FIG, an X-axis, a Y-axis, and a Z-axis are shown as three axes that are orthogonal to each other.

[0032] The display device 1 is, for example, a microdisplay that displays a color image in an HMD, etc. HMD is an abbreviation of Head Mount Display.

[0033] like Figure 1 As shown, the display device 1 includes a display panel 2, an FPC board 120, and a housing 130. FPC is an abbreviation of Flexible Printed Circuits.

[0034] The display panel 2 includes a plurality of light-emitting elements, a plurality of pixel circuits connected to the plurality of light-emitting elements, and a drive circuit for driving the pixel circuits. In this embodiment, the plurality of light-emitting elements, the plurality of pixel circuits, and the drive circuit of the display panel 2 are formed on a silicon substrate, and the light-emitting elements are OLEDs. OLED is the abbreviation for Organic Light Emitting Diode.

[0035] like Figure 2 As shown, the display panel 2 has a display area 112. In the example shown in the figure, the display area 112 is a rectangle with a long side parallel to the X-axis. In the display area 112, a plurality of pixels P as display units are displayed in a matrix at a prescribed configuration pitch. In the example shown in the figure, a plurality of pixels P are displayed in a matrix in the X-axis direction and the Y-axis direction. Below, a case where m×n pixels P are displayed as m rows in the Y-axis direction and as n columns in the X-axis direction is described. In addition, m and n are integers greater than 2. In addition, the spacing refers to the distance along the prescribed direction from the end of one side of the prescribed direction in one element to the end of one side of the prescribed direction in an adjacent element when a plurality of elements are arranged along a prescribed direction.

[0036] Pixel P has luminance information and may also have color information. When pixel P has luminance information but not color information, a black and white image is displayed in display area 112. On the other hand, when pixel P has both luminance information and color information, a color image is displayed in display area 112. The following description assumes that pixel P has both luminance information and color information.

[0037] Each of the m×n pixels P is composed of three sub-pixels SP of red, green, and blue.

[0038] like Figure 1 As shown, the display panel 2 is housed and fixed in a frame-shaped housing 130 opened in the display area 112, and is connected to one end of the FPC substrate 120. A plurality of external connection terminals 124 are provided at the other end of the FPC substrate 120, and the plurality of external connection terminals 124 are connected to an external circuit not shown. On the FPC substrate 120, a control circuit 3 as a semiconductor chip is mounted using COF technology, and a synchronization signal and image data synchronized with the synchronization signal are supplied from the external circuit via the plurality of external connection terminals 124. COF is the abbreviation of Chip On Film. The synchronization signal includes a vertical synchronization signal indicating the start of vertical scanning of the image data, a horizontal synchronization signal indicating the start of horizontal scanning of the image data, and a dot clock signal indicating the timing of one pixel of the image data.

[0039] The control circuit 3 supplies various control signals and various potentials generated based on the synchronization signal to the display panel 2 , and also supplies data corresponding to each pixel P included in the image data to the display panel 2 in a time-division manner.

[0040] 1-1-2. Functional Structure of Display Device

[0041] Figure 3 1 is a block diagram showing the electrical structure of the display device 1 according to the first embodiment. Figure 3 As shown, the display device 1 includes a control circuit 3, a plurality of pixel circuits 20, a scan line driver circuit 21, a plurality of switch circuits 22, a plurality of data potential generating circuits 23, and a plurality of P-channel MOSFETs 24. The display panel 2 includes a plurality of pixel circuits 20, a scan line driver circuit 21, a plurality of switch circuits 22, a plurality of data potential generating circuits 23, and a plurality of MOSFETs 24. As described above, the control circuit 3 is mounted on the FPC substrate 120, but it can also be provided on the display panel 2.

[0042] In the display panel 2, m scanning lines 11 are arranged along the horizontal direction in the figure, and 3n data transmission lines 17 are arranged along the vertical direction in the figure. Figure 3 In the horizontal direction, it is equivalent to Figure 1 and Figure 2The direction of the X axis is equivalent to the vertical direction Figure 1 and Figure 2 In the Y-axis direction, m×3n pixel circuits 20 are provided corresponding to the m scanning lines 11 and the 3n data transmission lines 17. That is, one pixel circuit 20 is provided corresponding to one scanning line 11 and one data transmission line 17, and the m×3n pixel circuits 20 are arranged in a matrix with m rows in the vertical direction and 3n columns in the horizontal direction.

[0043] The m×3n pixel circuits 20 are divided into q pixel circuit blocks BLK-1 to BLK-q, wherein the p×3n pixel circuits 20 connected to any one of the p scanning lines 11 constitute a pixel circuit block. p and q are integers greater than 2 that satisfy p×q=m. Figure 3 , the first pixel circuit block BLK-1 from the top includes p×3n pixel circuits 20 connected to any one of the p scanning lines 11 in the 1st to pth rows. Furthermore, the second pixel circuit block BLK-2 includes p×3n pixel circuits 20 connected to any one of the p scanning lines 11 in the p+1th to 2pth rows. Generally speaking, the kth pixel circuit block BLK-k includes p×3n pixel circuits 20 connected to any one of the p scanning lines 11 in the (k-1)×p+1th to k×pth rows. k is an integer greater than 1 and less than q.

[0044] In each pixel circuit block BLK-k, 3n data lines 12 are arranged along the longitudinal direction, and p pixel circuits 20 are connected to each data line 12. The 3n data lines 12 form a group of 3 and are divided into n groups. Among the n groups, the jth group from the left includes the 3j-2nd column data line 12, the 3j-1st column data line 12, and the 3jth column data line 12. In addition, j is an integer greater than 1 and less than n. The data line 12 in the 3j-2nd column is connected to n pixel circuits 20 for making n red sub-pixels SP emit light respectively, the data line 12 in the 3j-1st column is connected to n pixel circuits 20 for making n blue sub-pixels SP emit light respectively, and the data line 12 in the 3jth column is connected to n pixel circuits 20 for making n green sub-pixels SP emit light respectively. In Figure 3 In FIG. 1 , the pixel circuit 20 that causes the red sub-pixel SP to emit light is denoted by “R”, the pixel circuit 20 that causes the blue sub-pixel SP to emit light is denoted by “B”, and the pixel circuit 20 that causes the green sub-pixel SP to emit light is denoted by “G”.

[0045] Furthermore, each pixel circuit block BLK-k includes 3n switch circuits 22. Each of the 3n switch circuits 22 controls the electrical connection between each of the 3n data lines 12 and each of the 3n data transmission lines 17 under the control of the control circuit 3. Specifically, when each switch circuit 22 is turned on, each data line 12 is electrically connected to each data transmission line 17, and when each switch circuit 22 is turned off, each data line 12 is electrically disconnected from each data transmission line 17. Specifically, when the switch circuit 22 connected to the data line 12 in the 3j-2 column is turned on, the data line 12 in the 3j-2 column is electrically connected to the data transmission line 17 in the 3j-2 column; when the switch circuit 22 connected to the data line 12 in the 3j-1 column is turned on, the data line 12 in the 3j-1 column is electrically connected to the data transmission line 17 in the 3j-1 column; and when the switch circuit 22 connected to the data line 12 in the 3j column is turned on, the data line 12 in the 3j column is electrically connected to the data transmission line 17 in the 3j column.

[0046] The 3n data transmission lines 17 are connected to the drains of the 3n MOSFETs 24. The control circuit 3 supplies a common potential VINI to the sources of the 3n MOSFETs 24 and a common control signal XGINI to the gates of the 3n MOSFETs 24.

[0047] Furthermore, 3n power supply lines 15 are provided along the longitudinal direction of the display panel 2. The power supply line 15 in the 3j-2 column is connected to m pixel circuits 20 corresponding to the red sub-pixels SP of the m pixels P in the j column. The power supply line 15 in the 3j-1 column is connected to m pixel circuits 20 corresponding to the blue sub-pixels SP of the m pixels P in the j column. The power supply line 15 in the 3j column is connected to m pixel circuits 20 corresponding to the green sub-pixels SP of the m pixels P in the j column. A potential V0 is commonly supplied from the control circuit 3 to the 3n power supply lines 15. The potential V0 is, for example, ground potential VSS, which serves as a reference for zero potential, or a potential close to ground potential VSS. Specifically, the potential V0 is a potential such that, when applied to a light-emitting element, no current flows through the element.

[0048] The control circuit 3 controls various components based on image data VID, vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC, and dot clock signal DCLK supplied from an external circuit. Image data VID specifies the grayscale level of each pixel P of the image to be displayed on display area 112, for example, using 8 bits per RGB. Specifically, image data VID is 24-bit RGB data corresponding to the brightness and color information of each pixel P, switching with each cycle of dot clock signal DCLK.

[0049] Here, the characteristics of brightness represented by grayscale levels do not match the characteristics of the luminance of the light-emitting element. Therefore, the control circuit 3 converts the image data VID specifying the grayscale level of the pixel P into image data VIDX specifying the luminance corresponding to that grayscale level. Specifically, the control circuit 3 up-converts the 8-bit R, G, and B data of each pixel P included in the image data VID into, for example, 10-bit R, G, and B data specifying the luminance of the corresponding light-emitting element, thereby generating the image data VIDX. This up-conversion utilizes a lookup table that pre-stores the correspondence between the 8-bit R, G, and B data and the 10-bit R, G, and B data.

[0050] The scan line driver circuit 21 drives the pixel circuits 20 arranged in m rows and 3n columns for each row under the control of the control circuit 3, outputting various signals. For example, the scan line driver circuit 21 sequentially supplies scan signals XGWR[1] to XGWR[m] to the scan lines 11 in rows 1 through m. In other words, the scan signal XGWR[i] is supplied to the scan line 11 in row i.

[0051] One data potential generating circuit 23 is provided for each data transmission line 17. That is, the display panel 2 includes 3n data potential generating circuits 23.

[0052] The 3j-2nd data potential generating circuit 23 from the left generates the data potential VDATA[3j-2] to be supplied to the data transmission line 17 in the 3j-2nd column based on the image data VIDX supplied from the control circuit 3, under the control of the control circuit 3. Similarly, the 3j-1st data potential generating circuit 23 from the left generates the data potential VDATA[3j-1] to be supplied to the data transmission line 17 in the 3j-1st column based on the image data VIDX supplied from the control circuit 3, under the control of the control circuit 3. Similarly, the 3jth data potential generating circuit 23 from the left generates the data potential VDATA[3j] to be supplied to the data transmission line 17 in the 3j-3rd column based on the image data VIDX supplied from the control circuit 3, under the control of the control circuit 3. Specifically, the 3j-2nd data potential generating circuit 23 includes a capacitive DAC that acquires the R data of the pixel P in the i-th row and j-th column included in the image data VIDX at a timing specified by the control circuit 3, performs D / A conversion, and outputs the data potential VDATA[3j-2] to the data transmission line 17 in the 3j-2nd column. Furthermore, the 3j-1st data potential generating circuit 23 includes a capacitive DAC that acquires the B data of the pixel P in the i-th row and j-th column included in the image data VIDX at a timing specified by the control circuit 3, performs D / A conversion, and outputs the data potential VDATA[3j-1] to the data transmission line 17 in the 3j-1st column. Furthermore, the 3jth data potential generating circuit 23 includes a capacitive DAC that acquires the G data of the pixel P in the i-th row and j-th column included in the image data VIDX at a timing specified by the control circuit 3, performs D / A conversion, and outputs the data potential VDATA[3j] to the data transmission line 17 in the 3j-3rd column.

[0053] In addition, the control circuit 3 supplies various control signals and various potentials to the display panel 2, but Figure 3 Only a portion thereof is shown in the figure.

[0054] 1-1-3. Structure of Pixel Circuit and Data Potential Generating Circuit

[0055] Figure 4 1 is a diagram showing the structure of three pixel circuits 20 and three data potential generating circuits 23 corresponding to the pixel P of row i and column j. These three pixel circuits 20 are included in the k-th pixel circuit block BLK-k. Figure 4In FIG. 1 , the three pixel circuits 20 corresponding to the pixel P in row i and column j are respectively divided into pixel circuits 20-1, 20-2, and 20-3. However, these three pixel circuits 20 have the same structure, and the same components are denoted by the same reference numerals. Pixel circuit 20-1 is the pixel circuit 20 corresponding to the red sub-pixel SP of pixel P, pixel circuit 20-2 is the pixel circuit 20 corresponding to the blue sub-pixel SP of pixel P, and pixel circuit 20-3 is the pixel circuit 20 corresponding to the green sub-pixel SP of pixel P.

[0056] In addition, Figure 4 In FIG, the three light emitting elements 27 connected to the pixel circuits 20-1, 20-2, and 20-3 are respectively divided into light emitting elements 27-1, 27-2, and 27-3, but the structures of the three light emitting elements 27 are the same. Figure 4 In FIG, the three data potential generating circuits 23 are respectively divided into data potential generating circuits 23-1, 23-2, and 23-3. However, the structures of the three data potential generating circuits 23 are the same, and only the structure of the data potential generating circuit 23-1 is shown. The data potential generating circuits 23-1, 23-2, and 23-3 are the 3j-2nd, 3j-1st, and 3jth data potential generating circuits 23, respectively. Figure 4 In the embodiment, the three data transmission lines 17 connected to the data potential generating circuits 23-1, 23-2, and 23-3 are respectively divided into data transmission lines 17-1, 17-2, and 17-3. Furthermore, the three switch circuits 22 connected to the data transmission lines 17-1, 17-2, and 17-3 are respectively divided into switch circuits 22-1, 22-2, and 22-3, but the structures of these three switch circuits 22 are identical. Furthermore, the three MOSFETs 24 connected to the data transmission lines 17-1, 17-2, and 17-3 are respectively divided into MOSFETs 24-1, 24-2, and 24-3, but the structures of these three MOSFETs 24 are identical.

[0057] like Figure 4 As shown, the pixel circuit 20 includes a capacitor 201 and P-channel MOSFETs 202 to 206, which are connected to the light emitting element 27. MOSFET is an abbreviation of Metal Oxide Semiconductor Field Effect Transistor.

[0058] The light-emitting element 27 is an OLED, which is a structure in which a light-emitting functional layer is sandwiched between a pixel electrode and a common electrode (not shown). The pixel electrode functions as an anode, and the common electrode is light-transmitting and functions as a cathode. In the light-emitting element 27, when current flows from the anode to the cathode, the holes injected from the anode and the electrons injected from the cathode recombine in the light-emitting functional layer to generate excitons, generating white light. The generated white light then resonates in an optical resonator composed of a reflective layer and a semi-reflective and semi-transmissive layer (not shown), and is emitted at a resonant wavelength set corresponding to any one of red, green, and blue. A color filter corresponding to the color is provided on the emission side of the light emitted from the optical resonator. Therefore, the emitted light from the light-emitting element 27 is colored based on the optical resonator and the color filter and is visually recognized by the observer. In addition, when the display area 112 displays a black and white image, the color filter is omitted.

[0059] A potential VEL is supplied to one end of capacitor element 201 from control circuit 3, and the other end of capacitor element 201 is connected to the gate of MOSFET 202 and the drain of MOSFET 203. A potential VEL is supplied to the source of MOSFET 202, and the drain of MOSFET 202 is connected to the drain of MOSFET 204 and the source of MOSFET 205. The drain of MOSFET 205 is connected to the drain of MOSFET 206 and the anode of light-emitting element 27. A potential VCT is supplied to the cathode of light-emitting element 27 from control circuit 3.

[0060] The source of the MOSFET 203 and the source of the MOSFET 204 are connected to the data line 12. The source of the MOSFET 206 is connected to the power supply line 15, and is supplied with the potential V0 from the control circuit 3.

[0061] A scan signal XGWR[i] is input to the gate of the MOSFET 203 from the scan line driver circuit 21. A control signal XGCMP[i] is input to the gate of the MOSFET 204 from the scan line driver circuit 21. A control signal XGEL[i] is input to the gate of the MOSFET 205 from the scan line driver circuit 21. A control signal XGOR[i] is input to the gate of the MOSFET 206 from the scan line driver circuit 21.

[0062] MOSFET 202 supplies a current corresponding to the voltage between the gate and source to light emitting element 27. Specifically, as the voltage between the gate and source of MOSFET 202 increases, the current flowing through light emitting element 27 increases, and the amount of light emitted by light emitting element 27 increases.

[0063] MOSFET 203 controls the electrical connection between the data line 12 and the gate of MOSFET 202 based on the potential of the scan line 11. Specifically, when the scan signal XGWR[i] supplied to the scan line 11 is at an L level, MOSFET 203 is turned on, and the data line 12 and the gate of MOSFET 202 are electrically connected. When the scan signal XGWR[i] is at an H level, MOSFET 203 is turned off, and the data line 12 and the gate of MOSFET 202 are electrically disconnected.

[0064] MOSFET 204 controls the electrical connection between the data line 12 and the drain of MOSFET 202. Specifically, when the control signal XGCMP[i] is at an L level, MOSFET 204 is turned on, electrically connecting the data line 12 to the drain of MOSFET 202. When the control signal XGCMP[i] is at an H level, MOSFET 204 is turned off, electrically disconnecting the data line 12 from the drain of MOSFET 202.

[0065] MOSFET 205 controls the electrical connection between light-emitting element 27 and the drain of MOSFET 202. Specifically, when control signal XGEL[i] is at an L level, MOSFET 205 is turned on, electrically connecting the anode of light-emitting element 27 to the drain of MOSFET 202. When control signal XGEL[i] is at an H level, MOSFET 205 is turned off, electrically disconnecting the anode of light-emitting element 27 from the drain of MOSFET 202.

[0066] MOSFET 206 controls the electrical connection between power supply line 15 and light-emitting element 27. Specifically, when control signal XGOR[i] is at an L level, MOSFET 206 is turned on, electrically connecting power supply line 15 to the anode of light-emitting element 27. When control signal XGOR[i] is at an H level, MOSFET 206 is turned off, electrically disconnecting power supply line 15 from the anode of light-emitting element 27.

[0067] like Figure 4 As shown, a capacitor 25 is provided between the data line 12 connected to the pixel circuit 20 and the power supply line 15. The capacitor 25 may be a parasitic capacitor between the data line 12 and the power supply line 15, or a capacitor formed by sandwiching an insulating layer between different conductive layers in the silicon substrate.

[0068] like Figure 4As shown, switch circuit 22 is a transmission gate in which the sources of an N-channel MOSFET and a P-channel MOSFET are connected to each other, and their drains are connected to each other. Hereinafter, in switch circuit 22, the gate of the N-channel MOSFET is referred to as the "first control terminal," the gate of the P-channel MOSFET is referred to as the "second control terminal," the connection node between the sources of the N-channel MOSFET and the P-channel MOSFET is referred to as the "input terminal," and the connection node between the drains of the N-channel MOSFET and the P-channel MOSFET is referred to as the "output terminal."

[0069] The source of the MOSFET 24-1 is supplied with a potential VINI from the control circuit 3, and the drain of the MOSFET 24-1 is connected to the data line 12 connected to the pixel circuit 20-1. The input terminal of the switch circuit 22-1 is connected to the data transmission line 17-1, and the output terminal of the switch circuit 22-1 is connected to the data line 12 connected to the pixel circuit 20-1.

[0070] Similarly, the potential VINI is supplied to the source of the MOSFET 24-2 from the control circuit 3, and the drain of the MOSFET 24-2 is connected to the data line 12 connected to the pixel circuit 20-2. The input terminal of the switch circuit 22-2 is connected to the data transmission line 17-2, and the output terminal of the switch circuit 22-2 is connected to the data line 12 connected to the pixel circuit 20-2.

[0071] Similarly, the potential VINI is supplied to the source of the MOSFET 24-3 from the control circuit 3, and the drain of the MOSFET 24-3 is connected to the data line 12 connected to the pixel circuit 20-3. The input terminal of the switch circuit 22-3 is connected to the data transmission line 17-3, and the output terminal of the switch circuit 22-3 is connected to the data line 12 connected to the pixel circuit 20-3.

[0072] A control signal XGINI is input from the control circuit 3 to the gates of the MOSFETs 24-1, 24-2, and 24-3. Furthermore, a control signal SEL[k] is commonly input from the control circuit 3 to the first control terminals of the switch circuits 22-1, 22-2, and 22-3, and a control signal XSEL[k] is commonly input from the control circuit 3 to the second control terminals of the switch circuits 22-1, 22-2, and 22-3. The control signals SEL[k] and XSEL[k] are digital signals with inverted logic levels.

[0073] MOSFET 24-1 controls the supply of potential VINI to data transmission line 17-1. MOSFET 24-2 controls the supply of potential VINI to data transmission line 17-2. MOSFET 24-3 controls the supply of potential VINI to data transmission line 17-3. Specifically, when control signal XGINI is at an L level, MOSFET 24-1 is turned on and supplies potential VINI to data transmission line 17-1. MOSFET 24-2 is turned on and supplies potential VINI to data transmission line 17-2. MOSFET 24-3 is turned on and supplies potential VINI to data transmission line 17-3. Furthermore, when control signal XGINI is at an H level, MOSFET 24-1 is turned off and does not supply potential VINI to data transmission line 17-1. MOSFET 24-2 is turned off and does not supply potential VINI to data transmission line 17-2. MOSFET 24-3 is turned off and does not supply potential VINI to data transmission line 17-3.

[0074] The switch circuit 22-1 controls the electrical connection between the data line 12 connected to the pixel circuit 20-1 and the data transmission line 17-1. The switch circuit 22-2 controls the electrical connection between the data line 12 connected to the pixel circuit 20-2 and the data transmission line 17-2. The switch circuit 22-3 controls the electrical connection between the data line 12 connected to the pixel circuit 20-3 and the data transmission line 17-3. Specifically, when the control signals SEL[k] and XSEL[k] are at the H level and the L level, respectively, the switch circuit 22-1 is turned on, electrically connecting the data line 12 connected to the pixel circuit 20-1 and the data transmission line 17-1. The switch circuit 22-2 is turned on, electrically connecting the data line 12 connected to the pixel circuit 20-2 and the data transmission line 17-2. The switch circuit 22-3 is turned on, electrically connecting the data line 12 connected to the pixel circuit 20-3 and the data transmission line 17-3. In addition, when the control signals SEL[k] and XSEL[k] are at L level and H level respectively, the switch circuit 22-1 is turned off, and the data line 12 and the data transmission line 17-1 connected to the pixel circuit 20-1 are electrically disconnected; the switch circuit 22-2 is turned off, and the data line 12 and the data transmission line 17-2 connected to the pixel circuit 20-2 are electrically disconnected; the switch circuit 22-3 is turned off, and the data line 12 and the data transmission line 17-3 connected to the pixel circuit 20-3 are electrically disconnected.

[0075] Furthermore, when the data line 12 connected to the pixel circuit 20-1 is electrically connected to the data transmission line 17-1 via the switch circuit 22-1, the data potential VDATA[3j-2] is transmitted from the data transmission line 17-1 to the data line 12. Similarly, when the data line 12 connected to the pixel circuit 20-2 is electrically connected to the data transmission line 17-2 via the switch circuit 22-2, the data potential VDATA[3j-1] is transmitted from the data transmission line 17-2 to the data line 12. Similarly, when the data line 12 connected to the pixel circuit 20-3 is electrically connected to the data transmission line 17-3 via the switch circuit 22-3, the data potential VDATA[3j] is transmitted from the data transmission line 17-3 to the data line 12.

[0076] Furthermore, the control signal XGINI is commonly input to the 3n MOSFETs 24 , and the control signals SEL[k] and XSEL[k] are commonly input to the 3n switch circuits 22 included in the k-th pixel circuit block BLK-k.

[0077] like Figure 4 As shown, the control circuit 3 inputs 10-bit image data VIDX which is switched to R data, B data, and G data of j columns of pixels P in a time-division manner to the data potential generating circuits 23-1, 23-2, and 23-3. Figure 4 In the figure, the image data VIDX is marked as D9, D8, D7, D6, D5, D4, D3, D2, D1, and D0 in order from the highest bit.

[0078] The data potential generating circuit 23 - 1 includes a capacitive DAC having capacitive elements 231 - 0 to 231 - 9 and 232 and switch circuits 233 - 0 to 233 - 9 and 234 .

[0079] One end of each of capacitor elements 231-0 to 231-4 is connected to the output terminal of switch circuit 234, and one end of capacitor element 232. One end of each of capacitor elements 231-5 to 231-9 is connected to the other end of capacitor element 232 and data transmission line 17-1. The other end of each of capacitor elements 231-0 to 231-9 is connected to the output terminals of switch circuits 233-0 to 233-9. A potential VL is supplied from control circuit 3 to the first input terminal of each of switch circuits 233-0 to 233-9, and a potential VH, which is higher than VL, is supplied from control circuit 3 to the second input terminal of each of switch circuits 233-0 to 233-9. Bits D0 to D9 of image data VIDX are input from control circuit 3 to the control terminals of each of switch circuits 233-0 to 233-9, respectively. When bit Dr is at an L level, the first input terminal and output terminal of switch circuit 233-r are electrically connected. When bit Dr is at an H level, the second input terminal and output terminal of switch circuit 233-r are electrically connected. That is, the switch circuit 233 - r outputs the potential VL when the bit Dr is at an L level, and outputs the potential VH when the bit Dr is at an H level. r is an integer greater than or equal to 0 and less than or equal to 9.

[0080] If the capacitance value of capacitor element 231-r is Cr, for example, C0:C1:C2:C3:C4:C5:C6:C7:C8:C9 = 1:2:4:8:16:1:2:4:8:16. Furthermore, the capacitance value Cser of capacitor element 232 may be the same as C0 and C5. Furthermore, as long as the capacitance values ​​C0-C9 and Cser maintain linearity between the value of the input 10-bit image data VIDX and the output data potential VDATA[3j-2], a certain degree of error is acceptable.

[0081] A potential VRST is supplied from control circuit 3 to the input terminal of switch circuit 234, and a control signal XRST is supplied from control circuit 3 to the control terminal of switch circuit 234. When control signal XRST is at an L level, the input and output terminals of switch circuit 234 are electrically conductive, and when control signal XRST is at an H level, the input and output terminals are electrically non-conductive. Therefore, when control signal XRST is at an L level, potential VRST is supplied to one end of each of capacitor elements 231-0 to 231-4 and one end of capacitor element 232. Furthermore, one end of capacitor elements 231-5 to 231-9 and the other end of capacitor element 232 are connected to data transmission line 17-1, and therefore, are supplied with potential VINI when control signal XGINI is at an L level. Therefore, when both control signal XRST and control signal XGINI are at an L level, the charge accumulated in capacitor elements 231-0 to 231-9 and 232 is initialized.

[0082] On the other hand, when both control signal XRST and control signal XGINI are at H level, charges corresponding to the logic levels of bits D0 to D9 are accumulated in each of capacitor elements 231-0 to 231-9. One end of each of capacitor elements 231-0 to 231-4 is connected to one end of capacitor element 232, so that one end of capacitor element 232 assumes a potential corresponding to the logic levels of bits D0 to D4. Furthermore, one end of each of capacitor elements 231-5 to 231-9 is connected to the other end of capacitor element 232, so that the other end of capacitor element 232 assumes a potential corresponding to the logic levels of bits D5 to D9, shifted by the potential at one end of capacitor element 232. Consequently, the potential at the other end of capacitor element 232 changes linearly with respect to bits D9 to D0 and is supplied to data transmission line 17-1 as data potential VDATA[3j-2].

[0083] In addition, the structures of the data potential generating circuits 23-2 and 23-3 are the same as the data potential generating circuit 23-1. The data potential generating circuit 23-2 generates the data potential VDATA[3j-1] and supplies it to the data transmission line 17-2, and the data potential generating circuit 23-3 generates the data potential VDATA[3j] and supplies it to the data transmission line 17-3.

[0084] Thus, under the control of the control circuit 3, the 3j-2nd data potential generating circuit 23 obtains the R data of the m pixels P in the jth column included in the image data VIDX output from the control circuit 3 at the timing specified by the control circuit 3, performs D / A conversion, and generates the data potential VDATA[3j-2] that is supplied to the data transmission line 17 in the 3j-2nd column. Furthermore, under the control of the control circuit 3, the 3j-1st data potential generating circuit 23 obtains the B data of the m pixels P in the jth column included in the image data VIDX output from the control circuit 3 at the timing specified by the control circuit 3, performs D / A conversion, and generates the data potential VDATA[3j-1] that is supplied to the data transmission line 17 in the 3j-1st column. Furthermore, under the control of the control circuit 3, the 3jth data potential generating circuit 23 obtains the G data of the m pixels P in the jth column included in the image data VIDX output from the control circuit 3 at the timing specified by the control circuit 3, performs D / A conversion, and generates the data potential VDATA[3j] that is supplied to the data transmission line 17 in the 3jth column. Therefore, the data potentials VDATA[3j-2], VDATA[3j-1], and VDATA[3j] are switched in a time-division manner at the timing of writing R data, B data, or G data to the 3m pixel circuits 20 corresponding to the m pixels P in the j column.

[0085] 1-1-4. Operation of the display device

[0086] Reference Figures 5 to 9 The operation of the display device 1 will be described. Figure 5 1 is a timing chart showing an example of waveforms of various signals in the display device 1. Figures 6 to 9 Yes Figure 4 Added diagrams showing the on / off state of the MOSFET and switch circuits in each period, and the supply paths of various potentials.

[0087] like Figure 5 As shown, the period of one cycle from the timing when the horizontal synchronization signal HSYNC input from the external circuit of the display device 1 changes from the H level to the L level to the timing when the next horizontal synchronization signal HSYNC changes from the H level to the L level corresponds to the horizontal scanning period 1H. In each horizontal scanning period 1H, data is written to the 3n pixel circuits 20 corresponding to the n pixels P of each row. In each horizontal scanning period 1H, the scanning line driving circuit 21 commonly outputs the control signals XGEL[i], XGOR[i], XGCMP[i] and the scanning signal XGWR[i] to the 3n pixel circuits 20 corresponding to the n pixels P of the i-th row. In addition, the control circuit 3 commonly outputs the control signal XGINI to the n MOSFETs 24. In addition, the control circuit 3 commonly outputs the control signals SEL[k] and XSEL[k] to the n switch circuits 22 included in the k-th pixel circuit block BLK-k. In addition, Figure 5 This is a timing chart focusing on the horizontal scanning period 1H of the i-th row after the horizontal scanning period 1H of the 1st to i-1th rows ends. The 3n pixel circuits 20 connected to the scanning line 11 of the i-th row are included in the k-th pixel circuit block BLK-k.

[0088] like Figure 5 As shown, the horizontal scanning period (1H) of the i-th row includes an initialization period (a), a compensation period (b) following initialization period (a), and a writing period (c) following compensation period (b). After writing period (c), there is an interval that leads to a light-emitting period (d), and after one frame, the horizontal scanning period (1H) of the i-th row is reached again. A single frame corresponds to one cycle of the vertical synchronization signal (VSYNC) and is the period required to display one frame of the image specified by the image data (VID). For example, when the frequency of the vertical synchronization signal (VSYNC) is 60 Hz, the single frame period is approximately 16.7 milliseconds.

[0089] like Figure 5As shown, during the horizontal scanning period 1H of the i-th row, during the initialization period a, the scanning signal XGWR[i] is at the L level. In addition, the control signal XGOR[i] is at the L level, and the control signals XGEL[i] and XGCMP[i] are at the H level. In addition, the control signals XGINI and XRST are at the L level. In addition, the control signal SEL[k] is at the H level, and the control signal XSEL[k] is at the L level. Therefore, as shown in FIG. Figure 6 As shown, during the initialization period a, in the pixel circuits 20-1, 20-2, and 20-3, the MOSFETs 203 and 206 are turned on, and the MOSFETs 204 and 205 are turned off. Furthermore, the MOSFETs 24-1, 24-2, and 24-3 are turned on, and the switch circuits 22-1, 22-2, and 22-3 are turned on. Consequently, a potential VINI is supplied from the control circuit 3 via the MOSFETs 24-1, 24-2, and 24-3 to the data transmission lines 17-1, 17-2, and 17-3. A predetermined potential VINI is supplied from the data transmission lines 17-1, 17-2, and 17-3 via the switch circuits 22-1, 22-2, and 22-3, respectively, to the data lines 12 connected to the pixel circuits 20-1, 20-2, and 20-3. Furthermore, in pixel circuits 20-1, 20-2, and 20-3, a potential VINI is supplied to the gate of MOSFET 202 and the other end of capacitor 201 via data line 12. Furthermore, a potential V0 is supplied to the anode of light-emitting element 27 via power supply line 15. In other words, the potentials of data line 12, the gate of MOSFET 202, and the other end of capacitor 201 are initialized to potential VINI, and the potential of the anode of light-emitting element 27 is initialized to potential V0. Furthermore, a predetermined potential VINI is supplied to one end of each of capacitors 231-0 to 231-9 and the other end of capacitor 232 in the capacitive DAC, and a potential VRST is supplied to one end of each of capacitors 231-0 to 231-4 and one end of capacitor 232, thereby initializing the charge accumulated in capacitors 231-0 to 231-9 and 232.

[0090] like Figure 5 As shown, in the horizontal scanning period 1H of the i-th row, in the compensation period b, the scanning signal XGWR[i] is at the L level. In addition, the control signals XGOR[i] and XGCMP[i] are at the L level, and the control signal XGEL[i] is at the H level. In addition, the control signals XGINI and XRST are at the H level. In addition, the control signal SEL[k] is at the L level, and the control signal XSEL[k] is at the H level. Therefore, as shown in FIG. Figure 7As shown, during compensation period b, in pixel circuits 20-1, 20-2, and 20-3, MOSFETs 203, 204, and 206 are on, and MOSFET 205 is off. Furthermore, MOSFETs 24-1, 24-2, and 24-3 are off, and switch circuits 22-1, 22-2, and 22-3 are off. Consequently, in pixel circuits 20-1, 20-2, and 20-3, current flows from the power supply line at potential VEL through MOSFETs 202, 204, and 203 to the gate of MOSFET 202, causing the potentials of data line 12, the gate of MOSFET 202, and the other end of capacitor 201 to rise from potential V11. At this point, MOSFET 202 is in a gate-drain connected state, i.e., a diode-connected state. Therefore, the voltage between the gate and source of MOSFET 202 converges to the threshold voltage Vth of MOSFET 202. Since MOSFET 202 is a P-channel type, threshold voltage Vth is a negative voltage. Since the potential VEL is supplied to the source of the MOSFET 202, the potentials of the data line 12, the gate of the MOSFET 202, and the other end of the capacitor 201 converge to the potential (VEL-|Vth|). The anode of the light emitting element 27 maintains the potential V0.

[0091] like Figure 5 As shown, in the horizontal scanning period 1H of the i-th row, in the writing period c, the scanning signal XGWR[i] is at the L level. In addition, the control signal XGOR[i] is at the L level, and the control signals XGCMP[i] and XGEL[i] are at the H level. In addition, the control signals XGINI and XRST are at the H level. In addition, the control signal SEL[k] is at the H level, and the control signal XSEL[k] is at the L level. Therefore, as shown in FIG. Figure 8As shown, during write period c, in pixel circuits 20-1, 20-2, and 20-3, MOSFETs 203 and 206 are turned on, while MOSFETs 204 and 205 are turned off. Furthermore, data potential generating circuits 23-1, 23-2, and 23-3 generate data potentials VDATA[3j-2], VDATA[3j-1], and VDATA[3j], respectively, and output them to data transmission lines 17-1, 17-2, and 17-3, respectively. Data potential VDATA[3j-2] is then transmitted from data transmission line 17-1 via switch circuit 22-1 to data line 12 connected to pixel circuit 20-1. In pixel circuit 20-1, data potential VDATA[3j-2] is supplied to the other end of capacitor 201 and the gate of MOSFET 202 via MOSFET 203. Furthermore, the data potential VDATA[3j-1] is transmitted from the data transmission line 17-2 to the data line 12 connected to the pixel circuit 20-2 via the switch circuit 22-2. In the pixel circuit 20-2, the data potential VDATA[3j] is supplied to the other end of the capacitor 201 and the gate of the MOSFET 202 via the MOSFET 203. Furthermore, the data potential VDATA[3j] is transmitted from the data transmission line 17-3 to the data line 12 connected to the pixel circuit 20-3 via the switch circuit 22-3. In the pixel circuit 20-3, the data potential VDATA[3j] is supplied to the other end of the capacitor 201 and the gate of the MOSFET 202 via the MOSFET 203.

[0092] Here, immediately before both the MOSFET 203 and the switch circuit 22-1 of the pixel circuit 20-1 are turned on, the potential of the data line 12 is (VEL - |Vth|). When both the MOSFET 203 and the switch circuit 22-1 are turned on, the potential of the data transmission line 17-1 becomes the data potential VDATA[3j-2]. Therefore, through the capacitive coupling between the capacitor 25 and the capacitor elements 231-0 to 231-9, and 232 of the data potential generating circuit 23-1, the potential of the data line 12 becomes ((Cd (VEL - |Vth|) + Cst VDATA[3j-2]) / (Cd + Cst)). Note that Cd is the capacitance value of the capacitor 25, and Cst is the combined capacitance value of the capacitor elements 231-0 to 231-9, and 232. Similarly, the potential of the data line 12 connected to the pixel circuit 20-2 becomes the potential ((Cd·(VEL-|Vth|)+Cst·VDATA[3j-1]) / (Cd+Cst)), and the potential of the data line 12 connected to the pixel circuit 20-3 becomes the potential ((Cd·(VEL-|Vth|)+Cst·VDATA[3j]) / (Cd+Cst)). Thereafter, when the scanning signal XGWR[j] becomes L level, in the pixel circuits 20-1, 20-2, and 20-3, the MOSFET 203 is turned off, and the potential of the gate of the MOSFET 202 is determined to be the above-mentioned potentials.

[0093] like Figure 5 As shown in FIG. 1 , during the horizontal scanning period 1H of the i-th row, during the light-emitting period d, the scanning signal XGWR[i] is at the H level. In addition, the control signal XGEL[i] is at the L level, and the control signals XGCMP[i] and XGOR[i] are at the H level. Therefore, Figure 9As shown, during light-emission period d, in pixel circuits 20-1, 20-2, and 20-3, MOSFET 205 is on, while MOSFETs 203, 204, and 206 are off. Consequently, the current flowing from the source to the drain of MOSFET 202 is supplied to light-emitting element 27 via MOSFET 205, causing light-emitting element 27 to emit light. In pixel circuit 20-1, the potential of the source of MOSFET 202 is VEL, and the potential of the gate of MOSFET 202 is ((Cd·(VEL-|Vth|)+Cst·VDATA[3j-2]) / (Cd+Cst)). Therefore, a current corresponding to data potential VDATA[3j-2] is supplied to light-emitting element 27 in a state compensated for the threshold voltage Vth of MOSFET 202. Similarly, in the pixel circuit 20-2, the potential of the gate of the MOSFET 202 is the potential ((Cd·(VEL-|Vth|)+Cst·VDATA[3j-1]) / (Cd+Cst)), and therefore, the current corresponding to the data potential VDATA[3j-1] is supplied to the light-emitting element 27 in a state compensated for the threshold voltage Vth of the MOSFET 202. Similarly, in the pixel circuit 20-3, the potential of the gate of the MOSFET 202 is the potential ((Cd·(VEL-|Vth|)+Cst·VDATA[3j]) / (Cd+Cst)), and therefore, the current corresponding to the data potential VDATA[3j] is supplied to the light-emitting element 27 in a state compensated for the threshold voltage Vth of the MOSFET 202.

[0094] In addition, if Figure 5 As shown, the control signals XGEL[i+1], XGOR[i+1], XGCMP[i+1] and the scanning signal XGWR[i+1] in the horizontal scanning period 1H of the i+1th row following the horizontal scanning period 1H of the i-th row become waveforms in which the control signals XGEL[i], XGOR[i], XGCMP[i] and the scanning signal XGWR[i] are respectively shifted by a time equivalent to the period of the horizontal scanning period 1H.

[0095] 1-1-5. Display Panel Structure

[0096] Figure 10 2 is a cross-sectional view schematically showing a portion of the display panel 2. Figure 10 As shown, the display panel 2 includes, for example, a substrate 50 , interlayer insulating layers 54 , 55 , 56 , and 57 , a wiring layer 58 , a reflective layer 59 , an insulating layer 30 , an organic EL element 40 , an insulating layer 60 , a sealing layer 70 , a colored layer 80 , and an opposing substrate 90 .

[0097] The substrate 50 is, for example, a silicon substrate. Impurity regions 51 into which impurities are ion-implanted are provided on the substrate 50. Impurity regions 51 function as the source or drain of the aforementioned MOSFETs 202 to 206. A gate insulating layer 52 is provided on the substrate 50. The material of the gate insulating layer 52 is, for example, silicon oxide. A gate electrode 53 is provided on the gate insulating layer 52. The material of the gate electrode 53 is, for example, metal, polysilicon, or the like. The gate electrode 53 functions as the gate of the aforementioned MOSFETs 202 to 206.

[0098] Interlayer insulating layer 54 covers gate insulating layer 52 and gate electrode 53. Interlayer insulating layers 54, 55, 56, and 57 are stacked in this order from the substrate 50 side. Interlayer insulating layers 54, 55, 56, and 57 are, for example, silicon oxide layers.

[0099] The wiring layer 58 is provided on the interlayer insulating layer 54, the interlayer insulating layer 55, and the interlayer insulating layer 56. The wiring layer 58 is made of a metal such as aluminum or copper.

[0100] The reflective layer 59 is provided on the interlayer insulating layer 57. The reflective layer 59 is provided for each of the plurality of sub-pixels SP. Figure 10 , two sub-pixels SP are shown. The reflective layer 59 is made of a metal such as aluminum. The reflective layer 59 reflects light generated by the organic EL element 40 and directed toward the substrate 50 toward the colored layer 80 .

[0101] The insulating layer 30 is provided on the reflective layer 59. The insulating layer 30 has different thicknesses in the red, green, and blue sub-pixels SP. The insulating layer 30 has, for example, a stacked structure comprising multiple layers. The number of stacked layers in the insulating layer 30 varies in the red, green, and blue sub-pixels SP. The insulating layer 30 may be, for example, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0102] The organic EL element 40 is provided on the insulating layer 30. The organic EL element 40 is, for example, an OLED, and functions as the aforementioned light-emitting element 27. The organic EL element 40 includes a pixel electrode 41, a light-emitting functional layer 42, and a common electrode 43.

[0103] The pixel electrode 41 is provided on the insulating layer 30. The pixel electrode 41 is provided for each of the plurality of sub-pixels SP. The pixel electrode 41 transmits light generated by the light-emitting functional layer 42. The pixel electrode 41 is a transparent electrode made of, for example, ITO. The pixel electrode 41 is used to inject current into the light-emitting functional layer 42. ITO is an abbreviation for Indium Tin Oxide.

[0104] The light-emitting functional layer 42 is provided on the pixel electrode 41. The light-emitting functional layer 42 is continuously provided in the plurality of sub-pixels SP. The light-emitting functional layer 42 is formed by stacking a plurality of light-emitting layers, for example. The light-emitting functional layer 42 emits white light, for example.

[0105] The common electrode 43 is disposed on the light-emitting functional layer 42. The common electrode 43 is a common electrode continuously disposed in the plurality of sub-pixels SP. The common electrode 43 is made of, for example, an alloy of magnesium and silver. The common electrode 43 is another electrode for injecting current into the light-emitting functional layer 42.

[0106] The common electrode 43, the insulating layer 30, and the reflective layer 59 form an optical resonant structure. The thickness of the insulating layer 30 is adjusted so that a standing wave having a predetermined wavelength is formed between the reflective layer 59 and the common electrode 43. This allows the organic EL element 40 to emit light having a predetermined wavelength for each of the plurality of sub-pixels SP.

[0107] The insulating layer 60 is provided on the pixel electrode 41. The insulating layer 60 is, for example, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer.

[0108] An opening 62 is formed in the insulating layer 60. The opening 62 penetrates the insulating layer 60. The insulating layer 60 defines the light emitting region 44 of the organic EL element 40. The light emitting region 44 is a region that overlaps with the opening 62 of the organic EL element 40 in a plan view.

[0109] The sealing layer 70 is provided on the common electrode 43. The sealing layer 70 is continuous across the plurality of sub-pixels SP. The sealing layer 70 is formed, for example, by stacking an inorganic layer and an organic layer. Alternatively, the sealing layer 70 may be formed by sandwiching an organic layer between a pair of inorganic layers. Examples of the inorganic layer include a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. The inorganic layer protects the light-emitting functional layer 42 from moisture, oxygen, and other influences. The organic layer is, for example, an acrylic resin layer. The organic layer improves the flatness of the upper surface of the sealing layer 70.

[0110] The colored layer 80 is provided on the sealing layer 70. The colored layer 80 is a color filter configured to transmit a predetermined wavelength in each of the red sub-pixel SP, the green sub-pixel SP, and the blue sub-pixel SP. The colored layer 80 is made of, for example, color resist.

[0111] The counter substrate 90 is provided on the colored layer 80. In the illustrated example, the counter substrate 90 is bonded to the colored layer 80 via an adhesive layer 92. The counter substrate 90 and the adhesive layer 92 transmit light emitted from the colored layer 80. The counter substrate 90 functions as a protective substrate that protects the organic EL element 40 and the colored layer 80.

[0112] In addition, the display panel 2 is manufactured using, for example, a well-known semiconductor manufacturing process.

[0113] In this embodiment, as described above, the m×3n pixel circuits 20 included in the display panel 2 are divided into q pixel circuit blocks BLK-1 to BLK-q. Each pixel circuit block BLK-k includes p×n light-emitting elements 27, p×n pixel circuits 20, and n switch circuits 22, corresponding to the p×n red sub-pixels SP. Furthermore, each pixel circuit block BLK-k includes p×n light-emitting elements 27, p×n pixel circuits 20, and n switch circuits 22, corresponding to the p×n blue sub-pixels SP. Furthermore, each pixel circuit block BLK-k includes p×n light-emitting elements 27, p×n pixel circuits 20, and n switch circuits 22, corresponding to the p×n green sub-pixels SP. Therefore, each pixel circuit block BLK-k includes p×3n light-emitting elements 27, p×3n pixel circuits 20, and 3n switch circuits 22.

[0114] On the other hand, in the display area 112 of the display panel 2, m×n pixels P are arranged in m rows and n columns. Therefore, n pixels P are arranged at equal intervals in the X-axis direction per row, and m pixels P are arranged at equal intervals in the Y-axis direction per column. Each pixel P is composed of three light-emitting elements 27 corresponding to a red subpixel SP, a blue subpixel SP, and a green subpixel SP. Therefore, by aligning the dimensions of the arrangement area for the p×3n pixel circuits 20 and 3n switch circuits 22 included in each pixel circuit block BLK-k with the arrangement area for the p×3n light-emitting elements 27 included in that pixel circuit block BLK-k, the layout area of ​​the display panel 2 is reduced.

[0115] Figure 11 1 is a top view showing a configuration example of a layout of a portion of the pixel circuit blocks BLK-1 and BLK-2. Figure 11 In FIG, only a portion of the layout corresponding to one column of pixels P in the pixel circuit blocks BLK-1 and BLK-2 is shown. Figure 11 In the embodiment, the light-emitting elements 27 corresponding to the red, blue, and green sub-pixels SP are divided into light-emitting elements 27R, 27B, and 27G, respectively. Furthermore, the pixel circuits 20 are divided into pixel circuits 20R, 20B, and 20G, respectively. Furthermore, the switch circuits 22 connected to the pixel circuits 20R, 20B, and 20G, respectively, are divided into switch circuits 22R, 22B, and 22G, respectively. Furthermore, the data lines 12 connected to the switch circuits 22R, 22B, and 22G, respectively, are divided into data lines 12R, 12B, and 12G, respectively.

[0116] exist Figure 11 In FIG. 1 , as shown by L1, the pixel circuit block BLK- 1 includes p pixel configuration areas PA. The p pixel configuration areas PA are adjacently arranged in the Y-axis direction. Figure 11In the figure, for convenience, the p pixel arrangement areas PA are divided into PA-1 to PA-p, but the layout of the p pixel arrangement areas PA is the same, and the light emitting elements 27R, 27B, and 27G are arranged in the pixel arrangement areas PA.

[0117] In addition, as shown in L2, the pixel circuit block BLK-1 includes p pixel circuit arrangement areas CA. The p pixel circuit arrangement areas CA are provided adjacent to each other in the Y-axis direction in a layer below the p pixel arrangement areas PA. Figure 11 For convenience, the p pixel circuit configuration areas CA are divided into CA-1 to CA-p, but the layout of the p pixel circuit configuration areas CA is the same. In the pixel circuit configuration area CA, the three pixel circuits 20R, 20B, and 20G are adjacent to each other in the X-axis direction.

[0118] In addition, Figure 11 As shown in FIG. 2 , pixel circuit block BLK-1 includes one switch circuit arrangement area SA, as shown in FIG. The switch circuit arrangement area SA is provided adjacent to the pixel circuit arrangement area CA-p in the Y-axis direction in a layer below the p pixel arrangement areas PA. In the switch circuit arrangement area SA, three switch circuits 22R, 22B, and 22G are adjacent to each other in the X-axis direction, and are also adjacent to the three pixel circuits 20R, 20B, and 20G of the pixel circuit arrangement area CA-p in the Y-axis direction.

[0119] In addition, Figure 11 As shown in FIG. 2 , in pixel circuit block BLK-1, data line 12 (data line 12R) is arranged in the 3j-2 column extending in the Y-axis direction, data line 12B is arranged in the 3j-1 column extending in the Y-axis direction, and data line 12G is arranged in the 3j column extending in the Y-axis direction. Data line 12R is supplied with data potential VDATA[3j-2], a signal for causing p light-emitting elements 27R to emit light, via switch circuit 22R. Data line 12B is supplied with data potential VDATA[3j-1], a signal for causing p light-emitting elements 27B to emit light, via switch circuit 22B. Data line 12G is supplied with data potential VDATA[3j], a signal for causing p light-emitting elements 27G to emit light, via switch circuit 22G. Data line 12R is arranged to overlap with p pixel circuits 20R and switch circuit 22R, and p pixel circuits 20R and switch circuit 22R are connected to data line 12R. Data line 12B is arranged to overlap with p pixel circuits 20B and switch circuits 22B, and the p pixel circuits 20B and switch circuits 22B are connected to data line 12B. Data line 12G is arranged to overlap with p pixel circuits 20G and switch circuits 22G, and the p pixel circuits 20G and switch circuits 22G are connected to data line 12.

[0120] like Figure 11 As shown, the pixel circuit block BLK-2 is arranged adjacent to the pixel circuit block BLK-1 in the Y-axis direction. The layout of the pixel circuit block BLK-1 is exactly the same as the layout of the pixel circuit block BLK-2.

[0121] That is, in Figure 11 In FIG, as shown in L1, the pixel circuit block BLK-2 includes p pixel configuration areas PA-1 to PA-p, and as shown in L2, the pixel circuit block BLK-2 includes p pixel circuit configuration areas CA-1 to CA-p and a switch circuit configuration area SA. Figure 11 As shown in FIG. 1 , in pixel circuit block BLK-2, data line 12 in the 3j-2 column, i.e., data line 12R, is configured, extending in the Y-axis direction; data line 12 in the 3j-1 column, i.e., data line 12B, is configured, extending in the Y-axis direction; and data line 12 in the 3j column, i.e., data line 12G, is configured, extending in the Y-axis direction. Data line 12R included in pixel circuit block BLK-2 is adjacent to data line 12R included in pixel circuit block BLK-1 along the Y-axis direction. Similarly, data line 12B included in pixel circuit block BLK-2 is adjacent to data line 12B included in pixel circuit block BLK-1 along the Y-axis direction. Similarly, data line 12G included in pixel circuit block BLK-2 is adjacent to data line 12G included in pixel circuit block BLK-1 along the Y-axis direction.

[0122] The data line 12R is supplied with a data potential VDATA[3j-2], a signal for causing each of the p light-emitting elements 27R to emit light, via the switch circuit 22R. The data line 12B is supplied with a data potential VDATA[3j-1], a signal for causing each of the p light-emitting elements 27B to emit light, via the switch circuit 22B. The data line 12G is supplied with a data potential VDATA[3j], a signal for causing each of the p light-emitting elements 27G to emit light, via the switch circuit 22G. The data line 12R is arranged to overlap with the p pixel circuits 20R and the switch circuit 22R, and the p pixel circuits 20R and the switch circuit 22R are connected to the data line 12R. The data line 12B is arranged to overlap with the p pixel circuits 20B and the switch circuit 22B, and the p pixel circuits 20B and the switch circuit 22B are connected to the data line 12B. The data line 12G is arranged to overlap with the p pixel circuits 20G and the switch circuit 22G, and the p pixel circuits 20G and the switch circuit 22G are connected to the data line 12G.

[0123] Although not shown in the figure, in each of pixel circuit blocks BLK-1 and BLK-2, p pixel arrangement areas PA-1 to PA-p are arranged adjacent to each other in n columns in the X-axis direction, and p pixel circuit arrangement areas CA-1 to CA-p and the switch circuit arrangement area SA are arranged adjacent to each other in n columns in the X-axis direction. Furthermore, pixel circuit blocks BLK-3 to BLK-q are arranged sequentially adjacent to pixel circuit block BLK-2 in the Y-axis direction. The layout of pixel circuit blocks BLK-3 to BLK-q is identical to that of pixel circuit blocks BLK-1 and BLK-2.

[0124] like Figure 11 As shown, in pixel circuit block BLK-1, p light-emitting elements 27R are arranged at a first pitch w1 in the Y-axis direction, and p pixel circuits 20R are arranged at a second pitch w2 in the Y-axis direction. Similarly, p light-emitting elements 27B are arranged at a first pitch w1 in the Y-axis direction, and p pixel circuits 20B are arranged at a second pitch w2 in the Y-axis direction. Similarly, p light-emitting elements 27G are arranged at a first pitch w1 in the Y-axis direction, and p pixel circuits 20G are arranged at a second pitch w2 in the Y-axis direction. The first pitch w1 matches the width of one pixel arrangement area PA in the Y-axis direction, and the second pitch w2 matches the width of one pixel circuit arrangement area CA in the Y-axis direction.

[0125] Here, because the second pitch w2 is smaller than the first pitch w1, the Y-axis width w2×p of the p-pixel circuit arrangement area CA is smaller than the Y-axis width w1×p of the p-pixel arrangement area PA. The difference between these two widths is equal to the product of the difference (w1-w2) between the first pitch w1 and the second pitch w2 and the number p of light-emitting elements 27R, (w1-w2)×p. Therefore, by making the Y-axis width w3 of the switch circuit arrangement area SA equal to (w1-w2)×p, the Y-axis width of the area formed by the p-pixel arrangement area PA is equal to the Y-axis width of the area formed by the p-pixel circuit arrangement area CA and the switch circuit arrangement area SA.

[0126] Furthermore, in a plan view, the switch circuit 22R overlaps with at least one of the p light-emitting elements 27R, the switch circuit 22B overlaps with at least one of the p light-emitting elements 27B, and the switch circuit 22G overlaps with at least one of the p light-emitting elements 27G. Specifically, in a plan view, the switch circuits 22R, 22B, and 22G overlap with the light-emitting elements 27R, 27B, and 27G arranged in the pixel arrangement area PA-p, respectively.

[0127] Furthermore, in a plan view, the switch circuit 22R is arranged in a region between the arrangement region of the p pixel circuits 20R included in the pixel circuit block BLK-1 and the arrangement region of the p pixel circuits 20R included in the pixel circuit block BLK-2. Similarly, in a plan view, the switch circuit 22B is arranged in a region between the arrangement region of the p pixel circuits 20B included in the pixel circuit block BLK-1 and the arrangement region of the p pixel circuits 20B included in the pixel circuit block BLK-2. Similarly, in a plan view, the switch circuit 22G is arranged in a region between the arrangement region of the p pixel circuits 20G included in the pixel circuit block BLK-1 and the arrangement region of the p pixel circuits 20G included in the pixel circuit block BLK-2.

[0128] Furthermore, since the first pitch w1 and the second pitch w2 are different, the larger the value s between the pixel arrangement area PA-s and the pixel circuit arrangement area CA-s, the larger the positional offset in the Y-axis direction. s is an integer greater than 1 and less than p.

[0129] On the other hand, the pixel electrode 41 serving as the anode of the light-emitting element 27R arranged in the pixel configuration area PA-s is connected to the drains of the MOSFETs 205 and 206 of the pixel circuit 20R arranged in the pixel circuit configuration area CA-s. Similarly, the pixel electrode 41 serving as the anode of the light-emitting element 27B arranged in the pixel configuration area PA-s is connected to the drains of the MOSFETs 205 and 206 of the pixel circuit 20B arranged in the pixel circuit configuration area CA-s. Similarly, the pixel electrode 41 serving as the anode of the light-emitting element 27G arranged in the pixel configuration area PA-s is connected to the drains of the MOSFETs 205 and 206 of the pixel circuit 20G arranged in the pixel circuit configuration area CA-s. Therefore, in this embodiment, as Figure 12 As shown, the positions of the through holes 208R, 208B, and 208G that respectively connect the three wirings 209R, 209B, and 209G are staggered according to each pixel configuration area PA-s and pixel circuit configuration area CA-s. The three wirings 209R, 209B, and 209G connect the three anodes of the light-emitting elements 27R, 27B, and 27G and the drains of the MOSFETs 205 and 206 of the pixel circuits 20R, 20B, and 20G.

[0130] Figure 12 is a top view showing the layout of a portion of each pixel circuit block BLK-k in more detail. Figure 11 The same components are marked with the same reference numerals. Figure 12As shown in L2, three wirings 209R, 209B, and 209G are provided in the upper wiring layer for each of the p pixel circuit configuration areas CA-1 to CA-p. Specifically, p wirings 209R, 209B, and 209G are provided in each pixel circuit block BLK-k, extending in the Y-axis direction. Furthermore, the p wirings 209R have the same shape and are arranged at a second pitch w2 in the Y-axis direction. Similarly, the p wirings 209B have the same shape and are arranged at a second pitch w2 in the Y-axis direction. Similarly, the p wirings 209G have the same shape and are arranged at a second pitch w2 in the Y-axis direction.

[0131] exist Figure 12 In the diagram, as indicated by L1 and L2, the p light-emitting elements 27R each overlap with one of the p wirings 209R in the Z-axis direction, with a through-hole 208R arranged in the overlapping region. Similarly, the p light-emitting elements 27B each overlap with one of the p wirings 209B in the Z-axis direction, with a through-hole 208B arranged in the overlapping region. Similarly, the p light-emitting elements 27G each overlap with one of the p wirings 209G in the Z-axis direction, with a through-hole 208G arranged in the overlapping region. Therefore, the relative positions of the wirings 209R, 209B, and 209G and the through-holes 208R, 208B, and 208G differ for each pixel arrangement area PA and pixel circuit arrangement area CA. In this way, by staggering the positions of p through holes 208R, p through holes 208B, and p through holes 208G in each pixel circuit block BLK-k, it is possible to arrange p wirings 209R, p wirings 209B, and p wirings 209G in the area formed by the pixel circuit configuration areas CA-1 to CA-p and the switch circuit configuration area SA, thereby suppressing the increase in layout area caused by these wirings.

[0132] In addition, if the width w3 of the switching circuit configuration area SA = (w1-w2)×p is less than the first pitch w1, the p pixel configuration areas PA-1 to PA-p can be set to the same layout, the p pixel circuit configuration areas CA-1 to CA-p can be set to the same layout, and the p through holes 208R, the p through holes 208B, and the p through holes 208G can be arranged in staggered positions.

[0133] In addition, Figure 12In each pixel circuit block BLK-k, as shown by L2, wirings 222R, 222B, and 222G are provided in the switch circuit configuration area SA to connect to the input terminals of the switch circuits 22R, 22B, and 22G. Furthermore, as shown by L3, data transmission lines 17R, 17B, and 17G are arranged to extend in the Y-axis direction in the wiring layer between the region formed by the pixel circuit configuration areas CA-1 to CA-p and the switch circuit configuration area SA, and the pixel configuration areas PA-1 to PA-p. Furthermore, as shown by L2 and L3, in each pixel circuit block BLK-k, through-holes 221R, 221B, and 221G, respectively, connecting the data transmission lines 17R, 17B, and 17G to the wirings 222R, 222B, and 222G, are provided at positions overlapping with the switch circuit configuration area SA in the Z-axis direction. In this way, in each pixel circuit block BLK-k, when viewed from above, the data transmission lines 17R, 17B, and 17G are configured to overlap with the area formed by the pixel circuit configuration areas CA-1 to CA-p and the switch circuit configuration area SA and the pixel configuration areas PA-1 to PA-p, and through holes 221R, 221B, and 221G are configured at positions overlapping with the switch circuit configuration area SA, thereby suppressing the increase in layout area caused by the connection with the data transmission lines 17R, 17B, and 17G.

[0134] In the first embodiment, the p light-emitting elements 27R in the 3j-2nd column included in the pixel circuit block BLK-1 are an example of "plurality of first light-emitting elements," and the p light-emitting elements 27R in the 3j-2nd column included in the pixel circuit block BLK-2 are an example of "plurality of second light-emitting elements." The p pixel circuits 20R in the 3j-2nd column included in the pixel circuit block BLK-1 are an example of "plurality of first pixel circuits," and the p pixel circuits 20R in the 3j-2nd column included in the pixel circuit block BLK-2 are an example of "plurality of second pixel circuits." Furthermore, the switch circuit 22R in the 3j-2nd column included in the pixel circuit block BLK-1 is an example of a "first switch circuit," and the switch circuit 22R in the 3j-2nd column included in the pixel circuit block BLK-2 is an example of a "second switch circuit." The data line 12R in the 3j-2 column of the pixel circuit block BLK-1 is an example of a "first data line," and the data line 12R in the 3j-2 column of the pixel circuit block BLK-2 is an example of a "second data line." Furthermore, the Y-axis direction is an example of a "first direction."

[0135] 1-1-6. Effects

[0136] As described above, in the display device 1 of the first embodiment, the m pixel circuits 20 in the same column are not connected in common to the data transmission line 17. Instead, the p pixel circuits 20 included in each pixel circuit block BLK-k are connected to the data line 12 branching from the data transmission line 17 via the switch circuit 22. Therefore, the p pixel circuits 20 act as a load on the data line 12, but the np pixel circuits 20 do not, thereby reducing the load on the data line 12. Furthermore, the switch circuit 22 included in each pixel circuit block BLK-k acts as a load on the data transmission line 17, but the m pixel circuits 20 do not, thereby also reducing the load on the data transmission line 17. Therefore, according to the display device 1 of the first embodiment, each data transmission line 17 and each data line 12 can be driven at high speed, thereby enabling, for example, the display of high-definition images.

[0137] Furthermore, in the display device 1 of the first embodiment, in each pixel circuit block BLK-k, the switch circuit 22 overlaps with at least one of the p light-emitting elements 27 in a plan view. In particular, by making the second pitch w2 between the p pixel circuits 20 arranged in the Y-axis direction smaller than the first pitch w1 between the p light-emitting elements 27 in the Y-axis direction, the switch circuit 22 can be arranged in the switch circuit arrangement area SA, which is formed by subtracting the area consisting of the p pixel circuit arrangement area CA from the area consisting of the p pixel arrangement area PA, in a plan view. Therefore, according to the display device 1 of the first embodiment, the increase in the layout area of ​​the display panel 2 caused by the switch circuit 22 can be suppressed. In this embodiment, when the switch circuit 22 overlaps with the light-emitting element 27 in a plan view, for example, any of the source, gate, and drain of the N-channel MOSFET, the source, gate, and drain of the P-channel MOSFET, and the wiring electrically connecting them, constituting the switch circuit 22, overlaps with the light-emitting area of ​​the light-emitting element 27 in a plan view.

[0138] 1-2. Second embodiment

[0139] Hereinafter, regarding the display device 1 of the second embodiment, the same reference numerals are assigned to the same configurations as those of the first embodiment, and the same description as that of the first embodiment will be omitted or simplified, with the description focusing on the differences from the first embodiment.

[0140] A perspective view of a display device 1 according to a second embodiment Figure 1 Similarly, the top view of the display panel 2 in the second embodiment is the same as Figure 2 The same, therefore, the illustration and description are omitted.

[0141] Figure 13This is a block diagram showing the electrical configuration of the display device 1 according to the second embodiment. Figure 3 The display device 1 of the first embodiment shown is the same as that of the first embodiment, but Figure 13 As shown, in each pixel circuit block BLK-k, the physical positions of the 3n switch circuits 22 are different from those of the display device 1 of the first embodiment. k is an integer greater than 1 and less than q. Specifically, in each pixel circuit block BLK-k, the switch circuit 22 that controls the electrical connection between the data line 12 connected to the p pixel circuits 20 in the 3j-2 column and the data transmission line 17 in the 3j-2 column is arranged between the two pixel circuits 20 included in the p pixel circuits 20. Similarly, the switch circuit 22 that controls the electrical connection between the data line 12 connected to the p pixel circuits 20 in the 3j-1 column and the data transmission line 17 in the 3j-1 column is arranged between the two pixel circuits 20 included in the p pixel circuits 20. Similarly, the switch circuit 22 that controls the electrical connection between the data line 12 connected to the p pixel circuits 20 in the 3j-1 column and the data transmission line 17 in the 3j-1 column is arranged between the two pixel circuits 20 included in the p pixel circuits 20. j is an integer greater than or equal to 1 and less than or equal to n.

[0142] In addition, the structures of the pixel circuit 20 and the data potential generating circuit 23 are similar to those of the Figure 4 The same, therefore, the illustration and description thereof are omitted.

[0143] Figure 14 1 is a plan view showing a configuration example of a layout of a portion of the pixel circuit blocks BLK-1 and BLK-2 according to the second embodiment. Figure 14 , only a portion of the layout corresponding to one column of pixels P in the pixel circuit blocks BLK- 1 and BLK- 2 is shown.

[0144] exist Figure 14 In the example shown in L1, Figure 11 Likewise, in the pixel circuit block BLK- 1 , p pixel arrangement areas PA- 1 to PA-p are provided adjacent to each other in the Y-axis direction.

[0145] In addition, Figure 14 As shown in L2, in the pixel circuit block BLK-1, in a layer lower than the pixel circuit configuration areas PA-1 to PA-p, t pixel circuit configuration areas CA-1 to CA-t are adjacently arranged in the Y-axis direction, pt pixel circuit configuration areas CA-(t+1) to CA-p are adjacently arranged in the Y-axis direction, and a switch circuit configuration area SA is provided between the pixel circuit configuration area CA-t and the pixel circuit configuration area CA-(t+1). t is a specified integer greater than or equal to 1 and less than or equal to p-1. Figure 11Likewise, the p pixel circuit arrangement regions CA have the same layout, and in the pixel circuit arrangement region CA, three pixel circuits 20R, 20B, and 20G are arranged adjacent to each other in the X-axis direction.

[0146] In the switch circuit arrangement area SA, the three switch circuits 22R, 22B, and 22G are adjacent to each other in the X-axis direction, and are adjacent to each of the three pixel circuits 20R, 20B, and 20G in the pixel circuit arrangement area CA-t in the Y-axis direction. Furthermore, they are adjacent to each of the three pixel circuits 20R, 20B, and 20G in the pixel circuit arrangement area CA-(t+1) in the Y-axis direction. That is, in a plan view, the switch circuit 22R is arranged in the area between two of the p pixel circuits 20R. Similarly, in a plan view, the switch circuit 22B is arranged in the area between two of the p pixel circuits 20B. Similarly, in a plan view, the switch circuit 22G is arranged in the area between two of the p pixel circuits 20G.

[0147] By arranging the switch circuit arrangement area SA between the pixel circuit arrangement area CA-t and the pixel circuit arrangement area CA-(t+1), the distance from the switch circuits 22R, 22B, and 22G to the pixel circuits 20R, 20B, and 20G located at the ends in the Y-axis direction is shortened compared to the first embodiment. This reduces the difference in the time constant when writing data to each pixel P, thereby reducing unevenness in the image displayed in the display area 112. Furthermore, to minimize the difference in the time constant when writing data to each pixel P, it is preferable to set p to an even number, such that t = p / 2. That is, the switch circuit arrangement area SA is preferably arranged to overlap the center in the Y-axis direction of the region formed by the p pixel arrangement areas PA-1 to PA-p.

[0148] In addition, Figure 14 As shown in FIG. 1 , in pixel circuit block BLK-1, as shown in FIG. 2 , the data line 12R in the 3j-2 column extending along the Y-axis direction is arranged to overlap with p pixel circuits 20R and switch circuits 22R, and the p pixel circuits 20R and switch circuits 22R are connected to the data line 12R. Furthermore, in pixel circuit block BLK-1, the data line 12B in the 3j-1 column extending along the Y-axis direction is arranged to overlap with p pixel circuits 20B and switch circuits 22B, and the p pixel circuits 20B and switch circuits 22B are connected to the data line 12B. Furthermore, in pixel circuit block BLK-1, the data line 12G in the 3j column extending along the Y-axis direction is arranged to overlap with p pixel circuits 20G and switch circuits 22G, and the p pixel circuits 20G and switch circuits 22G are connected to the data line 12G.

[0149] like Figure 14As shown, the pixel circuit block BLK-2 is arranged adjacent to the pixel circuit block BLK-1 in the Y-axis direction. The layout of the pixel circuit block BLK-1 is exactly the same as that of the pixel circuit block BLK-2. Although not shown in the figure, in each of the pixel circuit blocks BLK-1 and BLK-2, the p pixel configuration areas PA-1 to PA-p are arranged adjacent to each other in n columns in the X-axis direction, and the p pixel circuit configuration areas CA-1 to CA-p and the switch circuit configuration area SA are arranged adjacent to each other in n columns in the X-axis direction. In addition, the pixel circuit blocks BLK-3 to BLK-q are arranged in sequence adjacent to the pixel circuit block BLK-2 in the Y-axis direction. The layout of the pixel circuit blocks BLK-3 to BLK-q is also exactly the same as that of the pixel circuit blocks BLK-1 and BLK-2.

[0150] In the second embodiment, as in the first embodiment, in the pixel circuit block BLK-1, the second pitch w2 between the p pixel circuits 20R arranged in the Y-axis direction is smaller than the first pitch w1 between the p light-emitting elements 27R arranged in the Y-axis direction. Therefore, by setting the Y-axis width w3 of the switch circuit arrangement area SA to (w1-w2)×p, the Y-axis width of the region formed by the p pixel arrangement areas PA is made equal to the Y-axis width of the region formed by the p pixel circuit arrangement areas CA and the switch circuit arrangement area SA. s is an integer greater than or equal to 1 and less than or equal to p.

[0151] Furthermore, in a plan view, the switch circuit 22R overlaps with at least one of the p light-emitting elements 27R, the switch circuit 22B overlaps with at least one of the p light-emitting elements 27B, and the switch circuit 22G overlaps with at least one of the p light-emitting elements 27G. Specifically, in a plan view, the switch circuit 22B overlaps with the light-emitting element 27B arranged in the pixel arrangement area PA-t, and the switch circuits 22R and 22G overlap with the light-emitting elements 27R and 27G arranged in the pixel arrangement area PA-(t+1), respectively.

[0152] In the second embodiment, similarly to the first embodiment, Figure 15 As shown, the positions of the through holes 208R, 208B, and 208G that connect the three wirings 209R, 209B, and 209G are staggered according to each pixel configuration area PA-s and pixel circuit configuration area CA-s. The three wirings 209R, 209B, and 209G connect the three anodes of the light-emitting elements 27R, 27B, and 27G to the drains of the MOSFETs 205 and 206 of the pixel circuits 20R, 20B, and 20G.

[0153] Figure 15 is a top view showing the layout of a portion of each pixel circuit block BLK-k in more detail. Figure 14The same components are marked with the same reference numerals. Figure 15 As shown in L2, three wirings 209R, 209B, and 209G are provided in the upper wiring layer for each of the p pixel circuit configuration areas CA-1 to CA-p. Specifically, p wirings 209R, 209B, and 209G are provided in each pixel circuit block BLK-k, extending in the Y-axis direction. The p wirings 209R have the same shape and are arranged at a second pitch w2 in the Y-axis direction. Similarly, the p wirings 209B have the same shape and are arranged at a second pitch w2 in the Y-axis direction. Similarly, the p wirings 209G have the same shape and are arranged at a second pitch w2 in the Y-axis direction.

[0154] exist Figure 15 In the diagram, as indicated by L1 and L2, each of the p light-emitting elements 27R overlaps with one of the p wirings 209R in the Z-axis direction, with a through-hole 208R arranged in the overlapping region. Similarly, each of the p light-emitting elements 27B overlaps with one of the p wirings 209B in the Z-axis direction, with a through-hole 208B arranged in the overlapping region. Similarly, each of the p light-emitting elements 27G overlaps with one of the p wirings 209G in the Z-axis direction, with a through-hole 208G arranged in the overlapping region. Therefore, the relative positions of the wirings 209R, 209B, and 209G and the through-holes 208R, 208B, and 208G differ for each pixel arrangement area PA and pixel circuit arrangement area CA. In this way, by staggering the positions of p through holes 208R, p through holes 208B, and p through holes 208G in each pixel circuit block BLK-k, it is possible to arrange p wirings 209R, p wirings 209B, and p wirings 209G in the area formed by the pixel circuit configuration areas CA-1 to CA-p and the switch circuit configuration area SA, thereby suppressing the increase in layout area caused by these wirings.

[0155] In addition, if the width w3 of the switching circuit configuration area SA = (w1-w2)×p is less than the first pitch w1, the p pixel configuration areas PA-1 to PA-p can be set to the same layout, the p pixel circuit configuration areas CA-1 to CA-p can be set to the same layout, and the p through holes 208R, the p through holes 208B, and the p through holes 208G can be arranged in staggered positions.

[0156] In addition, Figure 15In each pixel circuit block BLK-k, as shown by L2, wirings 222R, 222B, and 222G are provided in the switch circuit configuration area SA to connect to the input terminals of the switch circuits 22R, 22B, and 22G. Furthermore, as shown by L3, data transmission lines 17R, 17B, and 17G are arranged to extend in the Y-axis direction in the wiring layer between the region formed by the pixel circuit configuration areas CA-1 to CA-p and the switch circuit configuration area SA, and the pixel configuration areas PA-1 to PA-p. Furthermore, as shown by L2 and L3, in each pixel circuit block BLK-k, through-holes 221R, 221B, and 221G, respectively, connecting the data transmission lines 17R, 17B, and 17G to the wirings 222R, 222B, and 222G, are provided at positions overlapping with the switch circuit configuration area SA in the Z-axis direction. In this way, in each pixel circuit block BLK-k, when viewed from above, the data transmission lines 17R, 17B, and 17G are configured to overlap with the area formed by the pixel circuit configuration areas CA-1 to CA-p and the switch circuit configuration area SA and the pixel configuration areas PA-1 to PA-p, and through holes 221R, 221B, and 221G are configured at positions overlapping with the switch circuit configuration area SA, thereby suppressing the increase in layout area caused by the connection with the data transmission lines 17R, 17B, and 17G.

[0157] In the second embodiment, the p light-emitting elements 27R in the 3j-2nd column included in the pixel circuit block BLK-1 are an example of "plurality of first light-emitting elements," and the p light-emitting elements 27R in the 3j-2nd column included in the pixel circuit block BLK-2 are an example of "plurality of second light-emitting elements." The p pixel circuits 20R in the 3j-2nd column included in the pixel circuit block BLK-1 are an example of "plurality of first pixel circuits," and the p pixel circuits 20R in the 3j-2nd column included in the pixel circuit block BLK-2 are an example of "plurality of second pixel circuits." Furthermore, the switch circuit 22R in the 3j-2nd column included in the pixel circuit block BLK-1 is an example of a "first switch circuit," and the switch circuit 22R in the 3j-2nd column included in the pixel circuit block BLK-2 is an example of a "second switch circuit." The data line 12R in the 3j-2 column of the pixel circuit block BLK-1 is an example of a "first data line," and the data line 12R in the 3j-2 column of the pixel circuit block BLK-2 is an example of a "second data line." Furthermore, the Y-axis direction is an example of a "first direction."

[0158] The display device 1 according to the second embodiment described above can achieve the same effects as the display device 1 according to the first embodiment. Furthermore, in the display device 1 according to the second embodiment, in each pixel circuit block BLK-k, the switch circuit configuration area SA is provided between two pixel circuit configuration areas CA. This shortens the distance from each switch circuit 22 to each pixel circuit 20 located at the end in the Y-axis direction. Consequently, the difference in the time constant when writing data to each pixel P is reduced, and unevenness in the image displayed in the display area 112 is reduced.

[0159] 2. Electronic devices

[0160] As an example of the electronic device according to this embodiment, a head-mounted display will be described. Figure 16 1 is a perspective view schematically showing a head mounted display 900 as an example of the electronic device according to the present embodiment.

[0161] like Figure 16 As shown, head-mounted display 900 is a head-mounted display with an appearance similar to glasses. Head-mounted display 900 is worn on the head of an observer. The observer is the user who uses head-mounted display 900. Head-mounted display 900 enables the observer to visually recognize image light based on a virtual image and to visually recognize external images through a transparent method.

[0162] The head mounted display 900 includes, for example, a first display portion 910 a , a second display portion 910 b , a frame 920 , a first temple 930 a , and a second temple 930 b .

[0163] The first display unit 910a and the second display unit 910b display images. Specifically, the first display unit 910a displays a virtual image for the observer's right eye. The second display unit 910b displays a virtual image for the observer's left eye. The display units 910a and 910b each include, for example, an image forming device 911 and a light guide device 915.

[0164] The image forming device 911 forms image light. The image forming device 911 includes, for example, an optical system such as a light source and a projection device, and an external component 912. The external component 912 houses the light source and the projection device.

[0165] The light guide device 915 covers the front of the observer's eyes and guides the image light formed by the image forming device 911 so that the external light and the image light overlap and are seen by the observer.

[0166] The frame 920 supports the first display unit 910a and the second display unit 910b. The frame 920 surrounds the display units 910a and 910b, for example. In the illustrated example, the image forming device 911 of the first display unit 910a is attached to one end of the frame 920. The image forming device 911 of the second display unit 910b is attached to the other end of the frame 920.

[0167] The first temple 930a and the second temple 930b extend from the frame 920. In the illustrated example, the first temple 930a extends from one end of the frame 920, and the second temple 930b extends from the other end of the frame 920.

[0168] The first temple 930a and the second temple 930b are suspended from the ears of the observer when the head mounted display 900 is worn by the observer. The observer's head is positioned between the temples 930a and 930b.

[0169] Figure 17 This diagram schematically illustrates the image forming device 911 and light guide device 915 of the first display unit 910a of the head-mounted display 900. The first display unit 910a and the second display unit 910b have essentially the same structure. Therefore, the following description of the first display unit 910a applies to the second display unit 910b as well.

[0170] like Figure 17 As shown, the image forming device 911 includes, for example, a display device 1 as a light source and a projection device 914 for imaging.

[0171] The projection device 914 projects the image light emitted from the display device 1 toward the light guide device 915. The projection device 914 is, for example, a projection lens. As the lens constituting the projection device 914, a lens having an axially symmetric surface as a lens surface may be used.

[0172] The light guide device 915 is, for example, screwed to the lens barrel of the projection device 914 and is positioned with high precision relative to the projection device 914. The light guide device 915 includes, for example, an image light guide member 916 for guiding image light and a see-through member 918 for see-through.

[0173] Image light emitted from projection device 914 enters image light guide 916. Image light guide 916 is a prism that guides the image light toward the viewer's eyes. The image light entering image light guide 916 is repeatedly reflected by the inner surface of image light guide 916 before being reflected by reflective layer 917 and emitted from image light guide 916. The image light emitted from image light guide 916 reaches the viewer's eyes. Reflective layer 917 is composed, for example, of a metal or dielectric multilayer film. Reflective layer 917 may also be a half-mirror.

[0174] The see-through component 918 is adjacent to the image light guide component 916. The see-through component 918 is fixed to the image light guide component 916. The outer surface of the see-through component 918 is, for example, continuous with the outer surface of the image light guide component 916. The see-through component 918 allows the viewer to see through external light. The image light guide component 916, in addition to guiding the image light, also allows the viewer to see through external light. Alternatively, the head-mounted display 900 may be configured so that the viewer does not see through external light.

[0175] According to the electronic device of this embodiment, since it includes the display device 1 capable of high-speed driving of the data lines 12 , it is possible to cause the display device 1 to display a high-definition image, for example.

[0176] The electronic device having the display device 1 is not limited to a head-mounted display, and may be, for example, an EVF, a projector, a wearable display such as a smartwatch, or a head-up display for a vehicle. EVF is an abbreviation for Electronic View Finder.

[0177] The present invention is not limited to the present embodiment, and various modifications can be implemented within the scope of the gist of the present invention.

[0178] For example, in each of the above-described embodiments, the data potential generating circuit 23 includes a capacitive DAC, but other configurations are also possible. For example, the j-th data potential generating circuit 23 may include a D / A conversion circuit and an amplifier circuit. The D / A conversion circuit acquires the R data, B data, and G data of the m pixels P in the j-column included in the image data VIDX output from the control circuit 3 at a timing specified by the control circuit 3 and performs D / A conversion on the data in a time-division manner. The amplifier circuit amplifies the potential after D / A conversion and outputs the data potential VDATA[j].

[0179] The above-mentioned embodiments and modifications are merely examples and are not limiting. For example, the embodiments and modifications may be appropriately combined.

[0180] The present invention includes structures that are substantially the same as the structures described in the embodiments, such as structures having the same functions, methods, and results, or structures having the same purposes and effects. In addition, the present invention includes structures that replace non-essential parts of the structures described in the embodiments. In addition, the present invention includes structures that have the same effects as the structures described in the embodiments, or structures that can achieve the same purposes. In addition, the present invention includes structures that add known technologies to the structures described in the embodiments.

[0181] The following contents are derived from the above-mentioned embodiment and modification examples.

[0182] One embodiment of a display device includes: a plurality of first light-emitting elements; a plurality of second light-emitting elements; a data transmission line; a first data line extending in a first direction; a second data line extending in the first direction and adjacent to the first data line along the first direction; a plurality of first pixel circuits connected to the first data line and connected to each of the plurality of first light-emitting elements; a plurality of second pixel circuits connected to the second data line and connected to each of the plurality of second light-emitting elements; a first switching circuit controlling electrical connection between the first data line and the data transmission line; and a second switching circuit controlling electrical connection between the second data line and the data transmission line, wherein the first data line is supplied with a signal for causing each of the plurality of first light-emitting elements to emit light from the data transmission line via the first switching circuit, and the second data line is supplied with a signal for causing each of the plurality of second light-emitting elements to emit light from the data transmission line via the second switching circuit, and the first switching circuit overlaps at least one of the plurality of first light-emitting elements in a plan view.

[0183] In this display device, the plurality of first pixel circuits and the plurality of second pixel circuits are not connected in common to the data transmission line. Instead, the plurality of first pixel circuits are connected to the first data line branched from the data transmission line via the first switching circuit, and the plurality of second pixel circuits are connected to the second data line branched from the data transmission line via the second switching circuit. Therefore, the plurality of first pixel circuits become a load connected to the first data line, but the plurality of second pixel circuits do not become a load connected to the first data line, thereby reducing the load on the first data line. Similarly, the plurality of second pixel circuits become a load connected to the second data line, but the plurality of first pixel circuits do not become a load connected to the second data line, thereby reducing the load on the second data line. In addition, the first switching circuit and the second switching circuit become a load connected to the data transmission line, but the plurality of first pixel circuits and the plurality of second pixel circuits do not become a load connected to the data transmission line, thereby also reducing the load on the data transmission line. Therefore, according to this display device, since the data transmission line, the first data line, and the second data line can be driven at high speed, it is possible to display a high-definition image, for example.

[0184] Furthermore, in this display device, the first switching circuit overlaps with at least one of the plurality of first light-emitting elements in a plan view, and thus an increase in layout area due to the first switching circuit can be suppressed.

[0185] In one embodiment of the display device, the plurality of first light-emitting elements may be arranged at a first pitch in the first direction, and the plurality of first pixel circuits may be arranged at a second pitch in the first direction, wherein the second pitch is smaller than the first pitch.

[0186] In this display device, the second pitch between the plurality of first pixel circuits arranged in the first direction is smaller than the first pitch between the plurality of first light-emitting elements arranged in the first direction. Therefore, the arrangement area of ​​the plurality of first pixel circuits is smaller than the arrangement area of ​​the plurality of first light-emitting elements. Therefore, when the arrangement area of ​​the plurality of first light-emitting elements overlaps with a layer above the arrangement area of ​​the plurality of first pixel circuits, the first switching circuit can be arranged in an area excluding the arrangement area of ​​the plurality of first pixel circuits from the arrangement area of ​​the plurality of first light-emitting elements when viewed from above. Therefore, according to this display device, an increase in the layout area caused by the first switching circuit can be suppressed.

[0187] In one embodiment of the display device, the first switch circuit may be arranged in a region between two of the plurality of first pixel circuits in a plan view.

[0188] According to this display device, since the distance from the first switching circuit to the pixel circuit located at the end in the first direction is shortened, the difference in time constant when writing data to each pixel is reduced, and unevenness in the displayed image is reduced.

[0189] In one aspect of the display device, the first switch circuit may be arranged in a region between an arrangement region of the plurality of first pixel circuits and an arrangement region of the plurality of second pixel circuits in a plan view.

[0190] In one embodiment of the display device, a product of a difference between the first pitch and the second pitch and the number of the first light-emitting elements may be equal to or smaller than the first pitch.

[0191] In this display device, when the arrangement region for the plurality of first pixel circuits overlaps with the arrangement region for the plurality of first light-emitting elements on a layer above the arrangement region for the plurality of first pixel circuits, the plurality of wirings and the plurality of through-holes that respectively connect the plurality of first light-emitting elements to the plurality of first pixel circuits can be arranged in the region where the arrangement region for the plurality of first pixel circuits overlaps with the arrangement region for the plurality of first light-emitting elements. Therefore, according to this display device, an increase in layout area caused by the plurality of wirings and the plurality of through-holes can be suppressed.

[0192] One embodiment of an electronic device includes one embodiment of the display device.

[0193] According to this electronic device, since it includes a display device capable of high-speed driving of data lines, it is possible to display a high-definition image on the display device, for example.

Claims

1. A display device comprising: a plurality of first light-emitting elements; a plurality of second light-emitting elements; Data transmission line; a first data line extending in a first direction; a second data line extending in the first direction and adjacent to the first data line along the first direction; a plurality of first pixel circuits connected to the first data line and respectively connected to the plurality of first light-emitting elements; a plurality of second pixel circuits connected to the second data line and respectively connected to the plurality of second light-emitting elements; a first switch circuit for controlling the electrical connection between the first data line and the data transmission line; as well as a second switch circuit for controlling the electrical connection between the second data line and the data transmission line; The first data line is supplied with a signal for causing each of the plurality of first light emitting elements to emit light from the data transmission line via the first switch circuit. The second data line is supplied with a signal for causing each of the plurality of second light emitting elements to emit light from the data transmission line via the second switch circuit. The first switch circuit overlaps with at least one of the plurality of first light emitting elements in a plan view.

2. The display device according to claim 1, wherein The plurality of first light emitting elements are arranged at a first pitch in the first direction, The plurality of first pixel circuits are arranged at a second pitch in the first direction, The second interval is smaller than the first interval.

3. The display device according to claim 1, wherein The first switch circuit is arranged in a region between two of the plurality of first pixel circuits in a plan view.

4. The display device according to claim 1, wherein In a plan view, the first switch circuit is arranged in a region between an arrangement region of the plurality of first pixel circuits and an arrangement region of the plurality of second pixel circuits.

5. The display device according to claim 2, wherein A product of a difference between the first pitch and the second pitch and the number of the first light-emitting elements is equal to or smaller than the first pitch. 6 . An electronic device comprising the display device according to claim 1 .

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