Liquid crystal display control method, driving chip and storage medium

Abstract

The embodiment of the invention relates to a liquid crystal display control method, a driving chip and a storage medium, the driving chip is electrically connected with an LED backlight source, the driving chip comprises a plurality of driving modules, each driving module comprises a plurality of cascaded driving units, the LED backlight source comprises a plurality of groups of LED lamp beads, and each driving unit is electrically connected with one group of LED lamp beads. The brightness data set is forwarded to the corresponding driving module through the driving chip, the driving unit in the driving module is controlled to sample and obtain the brightness data corresponding to the driving unit in the brightness data set based on the high-frequency clock of the preset frequency, the transmission rate of the brightness data can be greatly improved, and the transmission efficiency of the brightness data is improved. Therefore, the control signal can be efficiently generated and sent to the LED lamp bead electrically connected with the driving unit, so that the LED lamp bead is rapidly driven to present the brightness corresponding to the brightness data, the requirement of liquid crystal display on the data transmission rate under the condition of high refresh rate is met, and the use experience is improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of liquid crystal display technology, and in particular to a liquid crystal display control method, a driver chip, and a storage medium. Background Art

[0002] With the rapid advancement of display technology, demands for LCD (Liquid Crystal Display) displays are becoming increasingly stringent, with high-resolution and high-contrast image display becoming key research areas in the industry. LCDs are passive displays; the liquid crystals themselves do not emit light and require a backlight to provide illumination. The resulting display quality is closely tied to the performance of the backlight. To fully reflect the brightness characteristics of the entire image and enhance visual quality, the backlight must be able to implement a large number of independent dimming zones, potentially thousands or even tens of thousands, enabling precise dynamic dimming of the backlight. Backlight brightness information can be effectively integrated with the displayed image content, significantly improving image quality and enhancing product competitiveness. LED backlights, with their low power consumption, long lifespan, environmental friendliness, and reduced screen thickness, are widely used in both civilian and military display products. Therefore, the design of a high-performance LED backlight driver chip is essential.

[0003] In the related art, the communication protocol between the LED backlight driver chip and the data sending device usually adopts the communication method of unipolar return-to-zero code data. Its internal analog circuit receives and shapes the return-to-zero code data, but the data transmission rate of the return-to-zero code data is slow and cannot meet the data transmission rate requirements of the liquid crystal display under high refresh rate conditions. Summary of the Invention

[0004] In view of this, one purpose of the embodiments of the present application is to provide a liquid crystal display control method, a driver chip and a storage medium, aiming to solve the technical problem of slow data transmission rate of return-to-zero code data in LED backlight driver chips in the prior art.

[0005] To solve the above technical problems, the embodiments of the present application provide the following technical solutions: In a first aspect, an embodiment of the present application provides a liquid crystal display control method, which is applied to a driver chip, wherein the driver chip is electrically connected to an LED backlight source, the driver chip includes multiple driver modules, and the driver modules include multiple cascaded driver units. The LED backlight source includes multiple groups of LED lamp beads, and each of the driver units is electrically connected to a group of the LED lamp beads; The method comprises: Acquire a brightness data set, the brightness data set including a plurality of brightness data groups, the number of the brightness data groups being the same as the number of the driving modules, each brightness data group corresponding to one driving module, the brightness data group including brightness data of a plurality of driving units of the driving module corresponding to the brightness data group, the brightness data being in a return-to-zero code format; Controlling a target driving unit to obtain target brightness data from a target brightness data group based on a high-frequency clock of a preset frequency, wherein the target driving unit is any one of a plurality of cascaded driving units of a target driving module, the target driving module is any one of a plurality of driving modules, the target brightness data group is a brightness data group corresponding to the target driving module in the brightness data set, and the target brightness data is brightness data of the target driving unit; The target driving unit is controlled to generate a target control signal based on the target brightness data, and the target control signal is sent to the target LED lamp bead so that the target LED lamp bead presents a brightness corresponding to the target brightness data. The target LED lamp bead is a group of LED lamp beads electrically connected to the target driving unit among the multiple groups of LED lamp beads.

[0006] In some embodiments, the driver chip is further connected to a data device for communication, the first driver unit among the plurality of cascaded driver units of the driver module is a reference driver unit, and the reference driver unit is connected to the data device for communication; The obtaining of the brightness data set includes: The reference driving unit is controlled to receive the brightness data group sent by the data device, wherein the brightness data groups received by all the reference driving units are the brightness data sets.

[0007] In some embodiments, the target brightness data group includes a read / write mode configuration header, a register address configuration header, and a read / write data length configuration header, and the control target driving unit obtains target brightness data from the target brightness data group based on a high-frequency clock of a preset frequency, including: In response to determining that the target drive unit is in write mode according to the read / write mode configuration header, determining a target register address according to the register address configuration header; Determine the target number of data words according to the read / write data length configuration header; The target driving unit is controlled to obtain brightness data of the target data word number corresponding to the target driving unit from the target brightness data group based on a high-frequency clock of a preset frequency, and the brightness data of the target data word number is stored in the target register address. The brightness data of the target data word number corresponding to the target driving unit is the target brightness data.

[0008] In some embodiments, the target brightness data group further includes a target operation bit, and controlling the target driving unit to obtain brightness data of the target data word quantity corresponding to the target driving unit from the target brightness data group based on a high-frequency clock of a preset frequency includes: In response to the display synchronization signal received by the signal receiving port of the target driving unit being in a high state and the target operation bit being detected, controlling the data sending port of the target driving unit to output a low level; During the low level output time of the data sending port, the target driving unit is controlled to obtain the brightness data of the target data word quantity from the target data bit of the target brightness data group based on the high-frequency clock, where the target data bit is the next data bit of the target operation bit; In response to detecting the next target operation bit, the target driving unit is controlled to stop acquiring brightness data.

[0009] In some embodiments, after the response to detecting the next target operation bit and controlling the target driving unit to stop acquiring brightness data, the method further includes: The data sending port of the target driving unit is controlled to output a high level, and the target brightness data group is sent to a next driving unit of the target driving unit, so that the next driving unit obtains brightness data from the target brightness data group.

[0010] In some embodiments, the driver chip is further communicatively connected to a testing device, and the method further includes: receiving test data sent by the test device, wherein the test data is used to test the driving unit; Controlling a drive unit to be tested to obtain target data according to the test data, wherein the drive unit to be tested is any one of a plurality of cascaded drive units of a drive module to be tested, and the drive module to be tested is any one of a plurality of drive modules; The driving unit to be tested is controlled to send the target data to the testing device.

[0011] In some embodiments, the test data includes a read / write mode configuration header, a register address configuration header, a read / write data length configuration header, and a target operation bit, and controlling the drive unit to be tested to obtain target data according to the test data includes: In response to determining that the drive unit to be tested is in read mode according to the read-write mode configuration header, determining a target register address according to the register address configuration header; Determine the target number of data words according to the read / write data length configuration header; In response to detecting the target operation bit, the drive unit to be tested is controlled to obtain data of the target data word quantity according to the target register address, and the data of the target data word quantity is the target data.

[0012] In some embodiments, the test data further includes a communication frequency configuration header, and the controlling the drive unit under test to send the target data to the test device includes: determining a target data transmission rate according to the communication frequency configuration header; The drive unit under test is controlled to send the target data to the test device at the target data transmission rate.

[0013] In a second aspect, an embodiment of the present application provides a driver chip, comprising: A controller and a plurality of drive modules respectively connected to the controller for communication, wherein the drive modules include a plurality of cascaded drive units; The driving unit includes a signal port and a data port, the signal port includes a signal sending port and a signal receiving port, and the data port includes a data sending port and a data receiving port, the signal receiving port and the data receiving port of any driving unit are respectively connected to the signal sending port and the data sending port of the previous driving unit, and the signal sending port and the data sending port of the driving unit are respectively connected to the signal receiving port and the data receiving port of the next driving unit; The controller is used to execute any one of the liquid crystal display control methods proposed in the first aspect.

[0014] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, which stores computer program instructions executable by a processor, and the processor executes the computer program instructions to enable the computer to execute any one of the liquid crystal display control methods proposed in the first aspect.

[0015] The embodiments of the present application have the following beneficial effects: Different from the prior art, the liquid crystal display control method provided by the embodiments of the present application is applied to a driver chip, the driver chip is electrically connected to the LED backlight source, the driver chip includes multiple driver modules, the driver module includes multiple cascaded driver units, the LED backlight source includes multiple groups of LED lamp beads, and each driver unit is electrically connected to a group of LED lamp beads. The method includes: obtaining a brightness data set, the brightness data set including multiple brightness data groups, the number of brightness data groups is the same as the number of driving modules, each brightness data group corresponds to a driving module, the brightness data group includes brightness data of multiple driving units of the driving module corresponding to the brightness data group, and the brightness data is in a return-to-zero code format; controlling a target driving unit to obtain target brightness data from the target brightness data group based on a high-frequency clock of a preset frequency, the target driving unit is any one of multiple cascaded driving units of the target driving module, the target driving module is any one of multiple driving modules, the target brightness data group is a brightness data group corresponding to the target driving module in the brightness data set, and the target brightness data is the brightness data of the target driving unit; controlling the target driving unit to generate a target control signal based on the target brightness data, and sending the target control signal to a target LED lamp bead so that the target LED lamp bead presents a brightness corresponding to the target brightness data, and the target LED lamp bead is a group of LED lamp beads in the multiple groups of LED lamp beads that are electrically connected to the target driving unit.

[0016] The embodiment of the present application forwards the brightness data group to the corresponding driving module through the driving chip, and controls the driving unit in the driving module to sample and obtain the brightness data corresponding to the driving unit in the brightness data group based on a high-frequency clock of a preset frequency, which can greatly improve the transmission rate of the brightness data, thereby efficiently generating and sending control signals to the LED lamp beads electrically connected to the driving unit, thereby quickly driving the LED lamp beads to present the brightness corresponding to the brightness data, meeting the data transmission rate requirements of the liquid crystal display under high refresh rate conditions, and improving the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for describing the prior art or embodiments. Obviously, the drawings described below only illustrate certain embodiments of the present application and should not be considered as limiting the scope of protection. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without inventive effort.

[0018] Figure 1 is a schematic diagram of the structure of a driver chip provided in some embodiments of the present application; Figure 2 This is a schematic diagram of the connection between the driver chip and the LED backlight provided in some embodiments of the present application; Figure 3 This is a schematic diagram of the connection between the driver chip and the data device provided in some embodiments of the present application; Figure 4 is a schematic diagram of the structure of a controller in a driver chip provided in some embodiments of the present application; Figure 5 is a flow chart of a liquid crystal display control method provided by some embodiments of the present application; Figure 6 is a schematic diagram of the data flow of a brightness data group in a write mode in some embodiments of the present application; Figure 7a is a data flow diagram of a brightness data group in a write mode in some other embodiments of the present application; Figure 7b is a schematic diagram of the circuit structure of the driving unit in some embodiments of the present application; Figure 8 This is a schematic diagram of the data format of the brightness data group in the write mode in some embodiments of the present application; Figure 9a This is a schematic diagram of the connection between the driver chip and the test device provided in some embodiments of the present application; Figure 9b 1 is a data flow diagram of test data and target data in a read mode of a drive unit in some embodiments of the present application; Figure 10 3 is a state transition diagram of a state machine of a drive unit in some embodiments of the present application. DETAILED DESCRIPTION

[0019] In order to make the purposes and advantages of the embodiments of the present application easier to understand, the technical solutions of the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. The detailed description of the embodiments of the present application in the drawings below does not limit the scope of protection claimed in this application, but only represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0020] It should be noted that, if no conflict is constituted, the various technical features involved in the embodiments of the present application described below can be combined with each other and are all within the scope of protection of the present application. In addition, although the functional modules are divided in the device or structural diagram and the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in a different order than the module division in the device or in the flow chart. In addition, the "first", "second", "third" and other similar expressions used herein do not limit the data and execution order, but are only for the purpose of convenience of explanation and to distinguish between the same items or similar items with basically the same functions and effects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features.

[0021] Unless otherwise defined, the technical and scientific terms used in this specification have the same meanings as those commonly understood by those skilled in the art in the field of this application. The terms used in this specification are intended solely to describe specific embodiments and are not intended to limit this application. It should be understood that the term "and / or" as used in this specification includes any and all combinations of one or more of the listed items.

[0022] See also Figure 1 , Figure 1 The schematic diagram shows the structure of the driver chip provided in some embodiments of the present application.

[0023] like Figure 1 As shown, driver chip 100 includes a controller 110 and multiple driver modules. Controller 110 is communicatively connected to each driver module. The multiple driver modules include driver module 10a, driver module 20a, driver module 30a, ..., and driver module n0a. Driver chip 100 can be any suitable type of chip, such as a linear LED driver chip, a multi-channel constant current driver chip, or a non-isolated buck driver chip.

[0024] For details, please refer to Figure 2 Each driving module (i.e., driving module 10a, driving module 20a, driving module 30a, ..., and driving module n0a) includes multiple cascaded driving units. For example, driving module 10a includes cascaded driving unit 10a1, driving unit 10a2, driving unit 10a3, ..., and driving unit 10an, and driving module 20a includes cascaded driving unit 20a1, driving unit 20a2, driving unit 20a3, ..., and driving unit 20an.

[0025] Each drive unit (i.e., drive unit 10a1, drive unit 10a2, ..., and drive unit 10an, etc.) includes a data port 11 and a signal port 12. Data port 11 includes a data receiving port 11a and a data transmitting port 11b, and signal port 12 includes a signal receiving port 12a and a signal transmitting port 12b. Multiple cascaded drive units mean that the signal receiving port 12a and the data receiving port 11a of any one drive unit are connected to the signal transmitting port 12b and the data transmitting port 11b of the previous drive unit, respectively. Furthermore, the signal transmitting port 12b and the data transmitting port 11b of that drive unit are connected to the signal receiving port 12a and the data receiving port 11a of the next drive unit, respectively.

[0026] Please continue reading Figure 2 The driver chip 100 is electrically connected to the LED backlight 200. The LED backlight 200 includes a plurality of partial LED beads, wherein the plurality of partial LED beads include a first partial LED bead 10b, a second partial LED bead 20b, a third partial LED bead 30b, ..., and an nth partial LED bead n0b. Each partial LED bead includes multiple groups of LED beads, and each group of LED beads is electrically connected to a driver unit. For example, the first partial LED bead 10b includes a first group of LED beads 10b1, a second group of LED beads 10b2, a third group of LED beads 10b3, ..., and an nth group of LED beads n0b. The first group of LED beads 10b1, the second group of LED beads 10b2, the third group of LED beads 10b3, ..., and the nth group of LED beads n0b are electrically connected to the driver unit 10a1, the driver unit 10a2, the driver unit 10a3, ..., and the driver unit 10an, respectively.

[0027] See also Figure 3 In actual applications where a driver chip drives LED lamps to display corresponding brightness, the driver chip 100 is in communication with the data device 300. The communication protocol between the driver chip 100 and the data device 300 uses unipolar return-to-zero data. After receiving the brightness data from the image display control device, the data device 300 transmits the brightness data to the driver chip 100. The internal analog circuit of the driver chip 100 receives and shapes the brightness data in return-to-zero format to obtain the brightness data corresponding to each driver unit. Each driver unit then outputs a corresponding drive signal to the LED lamp, driving the LED lamp to the corresponding brightness.

[0028] The inventors have found that the transmission rate of the brightness data in the above-mentioned return-to-zero code format is slow and cannot meet the data transmission rate requirements of the liquid crystal display under high refresh rate conditions, resulting in a poor user experience.

[0029] In view of this, an embodiment of the present application provides a liquid crystal display control method, in which the driving chip forwards the brightness data group in the received brightness data set to the corresponding driving module, and controls the driving unit in the driving module to sample and obtain the brightness data corresponding to the driving unit in the brightness data group based on a high-frequency clock of a preset frequency. In this way, the transmission rate of the brightness data can be greatly improved, so that the brightness data can be efficiently sent to the LED lamp beads electrically connected to the driving unit, and the LED lamp beads can be quickly driven to present the brightness corresponding to the brightness data, thereby meeting the data transmission rate requirements of the liquid crystal display under high refresh rate conditions and improving the user experience.

[0030] In this embodiment, to quickly respond to changes in the display, certain requirements are placed on the communication rate of the driver unit. Specifically, the driver chip includes 52 driver modules, each of which includes four driver units. The brightness display resolution is 12 bits, so the data transmission rate must reach at least 6.6 Mbps.

[0031] The data device 300 includes 52 SDI data lines and 13 SYNC synchronization control lines. Every four groups of SDI data lines share one SYNC synchronization control line. The SYNC frequency supports up to 8Khz. Figure 3 The first of the multiple cascaded drive units in the drive module serves as the reference drive unit (i.e., drive unit 10a1, drive unit 20a1, drive unit 30a1, ..., and drive unit n0a1). The data device 300 is connected to the data receiving port 12a of the reference drive unit via an SDI data line and to the signal receiving port 11a of the reference drive unit via a SYNC synchronization control line. This means that the reference drive unit is in communication with the data device 300. The data device 300 transmits the brightness data of each drive module to the reference drive unit in that drive module, and the reference drive unit receives the brightness data of that drive module. After the reference drive unit obtains its own brightness data from the received brightness data, it transmits the remaining brightness data to the next drive unit. The next drive unit then obtains its own brightness data from the received brightness data. The cascaded driving units in the driving module all obtain the brightness data corresponding to themselves from the received brightness data until all driving units obtain the brightness data corresponding to themselves. Then the driving units output corresponding driving signals to the LED lamp beads electrically connected to the driving units according to their corresponding brightness data, thereby driving the LED lamp beads electrically connected to the driving units to present the brightness corresponding to the brightness data, thereby realizing the control of the liquid crystal display.

[0032] It should be understood that Figures 1 to 3The structure of the driver chip 100 and the LED backlight source 200, the connection method between the driver chip 100 and the LED backlight source 200, and the connection method between the driver chip 100 and the data device 300 are only schematically shown. It does not impose any restrictions on any situation such as the structure, type and quantity of the driver chip and LED backlight source in other embodiments, nor does it impose any restrictions on the connection method between the driver chip and the LED backlight source, and the connection method between the driver chip and the data device.

[0033] See also Figure 4 , Figure 4 The schematic diagram shows the structure of the controller in the driver chip provided in some embodiments of the present application.

[0034] like Figure 4 As shown, the controller 110 includes at least one processor 111 and a memory 112 that are communicatively connected. The processor 111 is also communicatively connected to each drive module. Figure 4 In the example, the bus system 113 is connected to a processor. The various components in the controller 110 are coupled together through the bus system 113, and the bus system 113 is used to realize the connection and communication between the various components. It should be understood that the bus system 113 includes not only a data bus, but also a power bus, a control bus, and a status signal bus. However, for the sake of clarity and brevity, Figure 4 In FIG, various buses are labeled as bus system 113. It can be understood that Figure 4 The structure shown in the embodiment is only for illustration and does not impose any limitation on the structure of the above-mentioned driver chip. For example, the above-mentioned driver chip may also include Figure 4 The structures shown may have more or fewer components, or may have Figure 4 Different configurations of the structure are shown.

[0035] Specifically, the processor 111 is used to provide computing and control capabilities to control the controller 110 to perform corresponding tasks, for example, to control the controller 110 to perform any of the liquid crystal display control methods provided in the embodiments of the present application, or to perform the steps of any possible implementation of any of the liquid crystal display control methods provided in the embodiments of the present application. Those skilled in the art will understand that the processor 111 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0036] The memory 112 is a non-transitory computer-readable storage medium that can be used to store non-transitory software programs, non-transitory computer executable programs, instructions, and modules, for example, the programs, instructions, and modules corresponding to the liquid crystal display control method in the embodiment of the present application. In some embodiments, the memory 112 may include a program storage area and a data storage area. The program storage area may store an operating system, an application required for at least one function, and the data storage area may store data created according to the use of the processor 111. The processor 111 executes various functional applications and data processing of the controller 110 by running the non-transitory software programs, instructions, and modules stored in the memory 112, thereby implementing any liquid crystal display control method provided in the embodiment of the present application, or executing the steps of any possible implementation of any liquid crystal display control method provided in the embodiment of the present application. In some embodiments, the memory 112 may include a high-speed random access memory and may also include a non-transitory memory. For example, at least one disk storage device, a flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 112 may also include a memory remotely located relative to the processor 111, and these remotely located memories may be connected to the processor 111 via a communication network. It should be understood that examples of the above-mentioned communication networks include but are not limited to the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0037] As can be understood from the above, any of the liquid crystal display control methods provided in the embodiments of the present application can be implemented by a controller in a driver chip of any suitable type having certain computing and control capabilities, for example, the controller 110 described above. In some feasible implementations, any of the liquid crystal display control methods provided in the embodiments of the present application can be implemented by a processor executing computer program instructions stored in a memory.

[0038] The liquid crystal display control method provided in the embodiment of the present application will be described in detail below in combination with the exemplary application and implementation of the driver chip provided in the embodiment of the present application.

[0039] See also Figure 5 , Figure 5 The flowchart of the liquid crystal display control method provided by some embodiments of the present application is schematically shown.

[0040] Those skilled in the art will appreciate that the liquid crystal display control method provided in the embodiments of the present application can be applied to the aforementioned driver chip (eg, driver chip 100). Specifically, the liquid crystal display control method is executed by one or at least two controllers of the driver chip.

[0041] like Figure 5 As shown, the liquid crystal display control method includes but is not limited to the following steps S100-S300: S100: Acquire a brightness dataset.

[0042] In this step, the brightness data set includes multiple brightness data groups. The number of brightness data groups is the same as the number of driving modules. Each brightness data group corresponds to a driving module. The brightness data group includes the brightness data of multiple driving units of the driving module corresponding to the brightness data group. For example, see Figure 2 Assuming that a brightness data group is Sa, and the brightness data group Sa corresponds to the driving module 10a, the brightness data group Sa includes the brightness data of multiple driving units in the driving module 10a, that is, the brightness data of the driving unit 10a1, the driving unit 10a2, the driving unit 10a3, ..., and the driving unit 10an in the driving module 10a.

[0043] The brightness data is in a return-to-zero code format. Data in the return-to-zero code format transmits information based on level changes. The level is returned to zero at the beginning of each transmission cycle. The return-to-zero code data parsing circuit decodes the transmitted information by detecting the level changes. For example, in some embodiments, a high level duration longer than a low level duration is a 1 code, and a high level duration shorter than a low level duration is a 0 code.

[0044] Exemplarily, the brightness dataset is stored in the local storage of the driver chip, and the embodiments of the present application obtain the brightness dataset directly from the local storage. In some embodiments, the brightness dataset is stored in other devices or storage media, and the embodiments of the present application obtain the brightness dataset by reading from other devices or storage media via a network. In some embodiments, the brightness dataset can also be sent to the driver chip via a network by other devices or storage media, so that the driver chip obtains the brightness dataset. Of course, the driver chip can also obtain the brightness dataset in any other suitable manner, and the embodiments of the present application do not impose any limitations on this.

[0045] In some embodiments, obtaining a brightness data set includes, but is not limited to, the following steps S110: S110: Control the reference driving unit to receive the brightness data group sent by the data device.

[0046] In this embodiment, the driver chip is also connected to the data device through the network. The first driver unit in the plurality of cascaded driver units of the driver module is a reference driver unit, which is connected to the data device through the network. Figure 3 The reference driving units are driving unit 10a1, driving unit 20a1, driving unit 30a1, ..., and driving unit n0a1, and all reference driving units (i.e., driving unit 10a1, driving unit 20a1, driving unit 30a1, ..., and driving unit n0a1) are communicatively connected to the data device.

[0047] Specifically, the data device acquires or receives brightness data for all driver units from the preceding image engine SOC via an LVDS interface or an SPI interface. It then divides the brightness data into multiple brightness data groups based on the driver modules of the driver chip. Each brightness data group corresponds to a driver module, and each brightness data group includes brightness data for multiple driver units of the driver module corresponding to that brightness data group. After grouping to obtain multiple brightness data groups, the data device sends the multiple brightness data groups as brightness data sets to the driver chip, specifically sending a corresponding brightness data set to each reference driver unit. The driver chip controls all reference driver units to receive the brightness data groups sent by the data device. The brightness data groups received by all reference driver units constitute the brightness data sets.

[0048] S200: Controlling the target driving unit to obtain target brightness data from the target brightness data group based on a high-frequency clock of a preset frequency.

[0049] In this step, the target driving unit is any one of the multiple cascaded driving units of the target driving module, the target driving module is any one of the multiple driving modules, the target brightness data group is the brightness data group corresponding to the target driving module in the brightness data set, and the target brightness data is the brightness data of the target driving unit.

[0050] In the embodiment of the present application, the brightness data is in a return-to-zero format, that is, the brightness data is transmitted in a return-to-zero format. Exemplarily, the embodiment of the present application samples and decodes the brightness data in the return-to-zero format based on a high-frequency clock of a preset frequency, thereby obtaining brightness data from the brightness data group.

[0051] In some embodiments, a high-frequency clock of a preset frequency is generated by a PLL (Phase-Locked Loop) circuit, which is a phase-locked loop circuit. Optionally, the frequency of the high-frequency clock generated by the PLL circuit in the embodiment of the present application is as low as 64 MHz, which greatly improves the sampling and acquisition speed of brightness data, thereby improving the transmission rate of brightness data, and can meet the data transmission rate requirements of liquid crystal displays under high refresh rates, thereby improving the user experience.

[0052] Exemplarily, a driver module is arbitrarily selected as a target driver module. The brightness data set received by the reference driver unit in the target driver module is the target brightness data set, i.e., the target brightness data set is the brightness data set corresponding to the target driver module in the brightness data set. Any driver unit in the target driver module is selected as the target driver unit. After detecting and identifying the brightness data corresponding to the target driver unit in the target brightness data set (i.e., the target brightness data), the target driver unit is controlled to sample and obtain the target brightness data from the target brightness data set based on a high-frequency clock of a preset frequency, i.e., the brightness data belonging to the target driver unit is extracted from the target brightness data set. The target driver unit generates a drive signal based on the target brightness data and sends the drive signal to a target LED lamp bead electrically connected to the target driver unit, thereby driving the target LED lamp bead to exhibit the brightness corresponding to the target brightness data, thereby realizing liquid crystal display control.

[0053] For example, see Figure 6, the data receiving port (i.e. IC1_SDI) of the reference driving unit in the driving module receives the brightness data group sent by the data device. After detecting and identifying the brightness data corresponding to each driving unit, starting from the first driving unit in the driving module, each driving unit is controlled to obtain the brightness data corresponding to the driving unit (i.e. target brightness data) from the brightness data group based on a high-frequency clock of a preset frequency. After the current driving unit samples and obtains the brightness data corresponding to the driving unit, it sends the brightness data group to the next driving unit. The next driving unit also obtains the brightness data corresponding to the driving unit from the brightness data group based on a high-frequency clock of a preset frequency. In this way, each driving unit obtains the brightness data corresponding to the driving unit. Specifically, Figure 6 As shown, the driving module includes four driving units. The brightness data corresponding to the first driving unit is Data of P1, the brightness data corresponding to the second driving unit is Data of P2, the brightness data corresponding to the third driving unit is Data of P3, and the brightness data corresponding to the fourth driving unit is Data of P4. The first driving unit obtains Data of P1 from the brightness data group based on a high-frequency clock of a preset frequency, the second driving unit obtains Data of P2 from the brightness data group based on a high-frequency clock of a preset frequency, the third driving unit obtains Data of P3 from the brightness data group based on a high-frequency clock of a preset frequency, and the fourth driving unit obtains Data of P4 from the brightness data group based on a high-frequency clock of a preset frequency. In this way, each driving unit obtains the brightness data corresponding to the driving unit.

[0054] Of course, a drive module can also include any number of other drive units, for example, Figure 7a As shown, the driving module includes 8 driving units, and the brightness data corresponding to the 1st to 8th driving units are Data of P1, Data of P2, Data of P3, ..., Data of P8, respectively. The 1st to 8th driving units respectively obtain data Data of P1, Data of P2, Data of P3, ..., Data of P8 from the brightness data group based on a high-frequency clock of a preset frequency. In this way, each driving unit obtains the brightness data corresponding to the driving unit.

[0055] Understandably, see Figure 6 or Figure 7aAs shown in the figure, the data flow of the brightness data group is communication frequency configuration header (Freq Det) + read / write mode configuration header (R / W) + register address configuration header (Register Address) + read / write data length configuration header (Data Length) + no operation bit (NOP) + data packet (D1) + no operation bit (NOP) + data packet (D2) +, ..., + data packet (Dn) + no operation bit (NOP). Among them, the number of data words contained in the data packet is consistent with the number of data words carried by the read / write data length configuration header (Data Length). The number of data words carried by the read / write data length configuration header (Data Length) is the number of data words that each driver unit needs to receive in one data transmission communication.

[0056] In some embodiments, controlling the target driving unit to obtain target brightness data from the target brightness data group based on a high-frequency clock of a preset frequency specifically includes but is not limited to the following steps S210-S230: S210 : In response to determining that the target drive unit is in the write mode according to the read / write mode configuration header, determine the target register address according to the register address configuration header.

[0057] In the embodiment of the present application, the target brightness data group includes a read / write mode configuration header, a register address configuration header, and a read / write data length configuration header. For example, see Figure 6 or Figure 7a , read and write mode configuration header (R / W, the second header in the target brightness data group, Figure 6 or Figure 7a The read / write mode configuration header shown is W, indicating write mode, write mode or write state) to transmit 1 bit of data. The read / write mode configuration header indicates whether the current data transmission direction is to write data to the drive unit or to read the internal data of the drive unit.

[0058] The register address configuration header (Register Address, i.e. the third header in the target brightness data group) transmits 7 bits of data, which is used to represent the register address to be read or written. The embodiment of the present application can address 1 to 128 register addresses.

[0059] The Data Length header (the fourth header in the target brightness data group) transmits 7 bits of data, indicating the number of data words to be read or written. In this embodiment, a single data transmission can continuously write or read 128 data words. These 128 data words are divided into 8 data packets, each containing 16 data words, and each data word contains 12 bits of data.

[0060] In an embodiment of the present application, a single driver unit can control the OUTn outputs of 16 constant current sink channels. When controlling the LED chip display, the OUTn_pin is connected to the cathode of the LED lamp bead, and the power supply for the LED backlight is connected to the anode of the LED lamp bead. Each data word is used to control the brightness output information of a sink channel. Thus, 16 data words control the brightness output information of 16 sink channels. After the driver unit obtains the corresponding brightness data, it generates a sink current through its internal digital logic circuit. Specifically, it sends the brightness data of the corresponding sink channel to the analog DAC circuit, which then generates the sink current. The driver unit controls the on / off switching of the sink channel OUTn. When the sink channel OUTn is on, the sink current flows into the OUTn_pin, and the sink channel outputs the brightness information to the LED lamp bead, controlling the LED lamp bead to emit the corresponding brightness. When the sink channel OUTn is off, the OUTn_pin is in a high-impedance state, and no sink current is output to the sink channel. It is understood that the backlight brightness data of the driver unit is updated with each frame of the image. With each frame of the image, the backlight brightness data is also updated. Each frame image display process is divided into multiple sub-periods. The driving unit controls the brightness data displayed in each sub-period through the display synchronization signal SYNC received by the signal receiving port, thereby realizing liquid crystal display control.

[0061] Specifically, the driver chip parses the target brightness data group and extracts the read / write mode configuration header, register address configuration header, and read / write data length configuration header from the target brightness data group. The read / write mode configuration header is used to determine whether the target driver unit is in write mode or read mode. If the read / write mode configuration header determines that the target driver unit is in write mode, the register address configuration header is used to determine the target register address, i.e., the register address of the data to be written. The target register address is used to store the data to be written.

[0062] For example, when the 1-bit data of the read / write mode configuration header is parsed to be 0, it indicates that the target drive unit is in write mode, and the target register address is determined according to the 7-bit data in the register address configuration header.

[0063] S220: Determine the target number of data words according to the header configuration of the read and write data length.

[0064] Specifically, after determining the target register address, the target number of data words is determined based on the read / write data length configuration header. Specifically, the target number of data words (i.e., the number of data words of brightness data to be written by the target drive unit in a single data transmission communication) is determined based on the 7 bits of data in the read / write data length configuration header. In this embodiment of the present application, a single data transmission communication continuously writes 128 words of brightness data.

[0065] S230: Control the target driving unit to obtain brightness data of a target data word number corresponding to the target driving unit from the target brightness data group based on a high-frequency clock of a preset frequency, and store the brightness data of the target data word number into the target register address.

[0066] Specifically, after determining the target register address and the target number of data words, the controller controls the target driving unit to sample, based on a high-frequency clock having a preset frequency, the target brightness data group to obtain brightness data corresponding to the target driving unit, with the target number of data words (i.e., 128 data words). The brightness data corresponding to the target driving unit with the target number of data words is the target brightness data. The controller then controls the target driving unit to store the target number of brightness data words (i.e., the target brightness data) in the target register address and ultimately transmits the target brightness data to the control signal generation circuit. The control signal generation circuit generates a corresponding control signal based on the target brightness data.

[0067] In some embodiments, controlling the target driving unit to obtain the target data word quantity of brightness data corresponding to the target driving unit from the target brightness data group based on a high-frequency clock of a preset frequency specifically includes but is not limited to the following steps S231-S233: S231: In response to the display synchronization signal received by the signal receiving port of the target driving unit being in a high state and the target operation bit being detected, controlling the data sending port of the target driving unit to output a low level.

[0068] In this embodiment, the target brightness data group also includes a target operation bit, that is, the target brightness data group includes a read / write mode configuration header, a register address configuration header, a read / write data length configuration header, and a target operation bit. For example, see Figure 6 or Figure 7aAs shown, the NOP bit in the target brightness data group is the target operation bit. The target operation bit is located before the brightness data corresponding to each driver unit. The target operation bit is a special bit data used to separate the configuration header and the brightness data corresponding to the driver unit. After detecting the target operation bit, the driver unit begins to receive the brightness data corresponding to the driver unit (i.e., the brightness data belonging to itself). The target operation bit is also used to separate the brightness data corresponding to the current driver unit from the brightness data corresponding to the next driver unit of the current driver unit. In this way, each driver unit can obtain the brightness data corresponding to the driver unit from the brightness data group based on a high-frequency clock of a preset frequency. In some embodiments, the target operation bit can be a no-operation bit, which is a special bit with a high-level duration greater than 100ns and a low-level duration greater than 100ns. Of course, the target operation bit can also be any other suitable operation bit. Designers can also design and obtain the target operation bit based on actual needs and engineering experience. The embodiments of the present application do not impose any restrictions on this.

[0069] In an embodiment of the present application, a display refresh synchronization signal SYNC is used as an indication signal indicating that data transmission communication is valid. The display refresh synchronization signal SYNC is transmitted to the drive unit via a synchronization control line, and the drive unit receives the display refresh synchronization signal SYNC via a signal receiving port. While the display refresh synchronization signal SYNC is high, the drive unit determines that the brightness data currently transmitted from the communication port is valid, and then acquires the transmitted brightness data based on a high-frequency clock of a preset frequency. If the display refresh synchronization signal SYNC is low, the drive unit determines that the brightness data currently transmitted from the communication port is invalid, and does not acquire the brightness data.

[0070] Specifically, when the display synchronization signal (i.e., display refresh synchronization signal SYNC) received by the signal receiving port of the target driving unit is detected to be in a high state (i.e., pulled high), and the target operation bit in the target brightness data group is detected, indicating that the brightness data currently transmitted by the communication port is valid, the target driving unit is controlled to generate a MASK enable. When the next target operation bit is detected, the MASK enable is turned off. In other words, during the effective time of the MASK enable, the data transmission port of the target driving unit is controlled to output a low-level signal.

[0071] S232: During the low level output time of the data transmission port, the target driving unit is controlled to obtain brightness data of target data word quantity from the target data bits of the target brightness data group based on the high frequency clock.

[0072] Specifically, during the period when MASK is enabled, that is, during the time when the data sending port of the target driving unit outputs a low level, the target driving unit is controlled to start from the target data bit of the target brightness data group, and obtain brightness data of the target data word quantity (that is, target brightness data) based on the high-frequency clock sampling of the preset frequency, and the target data bit is the next data bit of the target operation bit.

[0073] S233: In response to detecting the next target operation bit, controlling the target driving unit to stop acquiring brightness data.

[0074] Specifically, when the next target operation bit in the target brightness data group is detected, it indicates that the target driving unit has obtained brightness data (i.e., target brightness data) of the target data word quantity corresponding to the target driving unit from the target brightness data group, and the target driving unit is controlled to stop obtaining brightness data from the target brightness data group.

[0075] For example, see Figure 7a and Figure 8 Assuming that the target driving unit is the first driving unit in the driving module (i.e. IC1), after the target driving unit receives the target brightness data group through the data receiving port (i.e. IC1_SDI), when it is determined that the received display synchronization signal is in a high state and the first target operation bit of the target brightness data group is detected (i.e. Figure 7a or Figure 8 When the first no-operation bit NOP is shown, the data sending port of the first drive unit (i.e. Figure 8 IC1_SDO shown in the figure) outputs a low level (that is, a MASK is enabled. During the effective time of the MASK enable, the data transmission port IC1_SDO will continue to output a low level signal, that is, HOLD-LOW). During the time when the data transmission port of the first driver unit outputs a low level, the first driver unit is controlled to start from the target data bit of the target brightness data group (that is, the next data bit of the first target operation bit / the first data bit of Data of P1 / the first data bit of Data(IC1)), and obtain the brightness data of the target data word quantity (that is, Data of P1 / target brightness data / Data(IC1)) based on the high-frequency clock sampling. When the next target operation bit of the target brightness data group (that is, the first data bit of the first target operation bit / the first data bit of Data of P1 / the first data bit of Data(IC1)) is detected, the target brightness data is obtained based on the high-frequency clock sampling. Figure 7a or Figure 8 When the second no operation bit NOP is set, the target drive unit is controlled to stop acquiring brightness data.

[0076] Through the above method, each driving unit receives the same configuration header. After receiving the configuration header information, in response to determining that the brightness data is valid and detecting the first no-operation bit, the driving unit is controlled to obtain brightness data of the target data word quantity corresponding to the driving unit from the brightness data group.

[0077] In some embodiments, in response to detecting the next target operation bit, after controlling the target driving unit to stop acquiring brightness data, the liquid crystal display control method further includes but is not limited to the following steps S234: S234: Control the data sending port of the target driving unit to output a high level, and send the target brightness data group to the next driving unit of the target driving unit, so that the next driving unit obtains brightness data from the target brightness data group.

[0078] In an embodiment of the present application, when the next target operation bit of the target brightness data group is detected, the target driving unit is controlled to stop acquiring brightness data, and the data transmission port of the target driving unit is controlled to output a high level, thereby sending the target brightness data group to the next driving unit of the target driving unit, so that the next driving unit acquires brightness data from the target brightness data group. After the data receiving port of the next driving unit receives the target brightness data group, when it is detected that the display synchronization signal (i.e., the display refresh synchronization signal SYNC) received by the signal receiving port of the next driving unit is in a high state (i.e., pulled high state), and the target operation bit of the target brightness data group is detected, indicating that the brightness data currently transmitted by the communication port is valid, the data transmission port of the next driving unit is controlled to output a low level signal, and within the time period during which the data transmission port of the next driving unit outputs the low level signal, the next driving unit is controlled to acquire brightness data (i.e., target brightness data) corresponding to the target data number of the target data bits of the target brightness data group based on the high-frequency clock. When the next target operation bit of the target brightness data group is detected, the next driving unit is controlled to stop acquiring brightness data.

[0079] In the process of writing brightness data to the driver unit, please refer to Figure 7b , the driving unit processes the brightness data group as follows: 1) The driving unit inputs the brightness data group input from SDI (ie, the data receiving port) and the display refresh synchronization signal SYNC input from SYNCI (ie, the signal receiving port) into the first filter and the second filter respectively for filtering processing.

[0080] 2) Input the filtered display refresh synchronization signal SYNC to the state machine. If the display refresh synchronization signal SYNC is in a low state, the state machine remains in an idle state. When the display refresh synchronization signal SYNC is in a high state, the state machine starts to jump, obtain the brightness data group input by SDI, and identify the brightness data information in the brightness data group input by SDI through the return-to-zero code analysis circuit (that is, the "0" / "1" information transmitted by each data bit).

[0081] 3) Inputting the filtered brightness data group into a first detector and a second detector, the first detector is used to detect the high level of the data bit waveform in the brightness data group, and the second detector is used to detect the low level of the data bit waveform in the brightness data group.

[0082] 4) The return-to-zero code analysis circuit includes a first counter and a second counter. The first counter counts the number of high-level pulse widths, while the second counter counts the number of low-level pulse widths. The return-to-zero code analysis circuit detects the rising edge of the waveform and resets the first and second counters. When the first detector detects a high level in the waveform, the first counter increments by one. When the second detector detects a low level in the waveform, the second counter increments by one.

[0083] 5) When the return-to-zero code analysis circuit detects the rising edge of the next waveform, the count value of the first counter and the count value of the second counter are input into the comparator. The comparator compares the count value of the first counter with the count value of the second counter. If the count value of the first counter is less than or equal to the count value of the second counter, it is determined that bit "0" data is obtained. If the count value of the first counter is greater than the count value of the second counter, it is determined that bit "1" data is obtained.

[0084] 6) When the state machine is in the stage of acquiring configuration information (i.e., read-write mode configuration header, register address configuration header, and read-write data length configuration header, etc.), after the return-to-zero code parsing circuit detects the rising edge of the waveform, it identifies the previous bit data content, adds one to the count value of the third counter, and updates the configuration information to the corresponding configuration register according to the current state of the state machine. When it is recognized that the read-write mode configuration header is 0, it is determined that the current communication is in write mode. After the state machine jumps to the target operation bit, the MASK enable is turned on to prepare for acquiring the data packet. After the return-to-zero code parsing circuit detects the rising edge of the next waveform, the state machine jumps to the stage of acquiring the data packet. In this embodiment, the data packet includes at least one data word, and each data word of the data packet includes 12 bits of data.

[0085] 7) During the data packet acquisition phase, the fourth counter increments after each 12 bits of data are acquired. When the fourth counter's value matches the target value (one minus the value in the read / write data length configuration header) and the next data word is acquired, the state machine jumps to the target operation bit. While in the target operation bit, the mask enable is turned off, and data packet acquisition ceases. Finally, the acquired data packets are stored in the receive buffer. The display refresh synchronization signal SYNC passes through a first-level buffer and is output as SYNCO (the signal transmission port) for transmission to the next driver unit.

[0086] S300: Control the target driving unit to generate a target control signal based on the target brightness data, and send the target control signal to the target LED lamp bead, so that the target LED lamp bead presents a brightness corresponding to the target brightness data.

[0087] In this embodiment, the target LED lamp bead is a group of LED lamp beads in a plurality of groups of LED lamp beads that are electrically connected to the target driving unit. Figure 2 When the target driving unit is the driving unit 10a1, a group of LED lamp beads electrically connected to the target driving unit 10a1 is the LED lamp beads 10b1, and the target LED lamp beads are the LED lamp beads 10b1.

[0088] Specifically, after the target driving unit obtains the target brightness data, it controls the target driving unit to generate a target control signal based on the target brightness data and transmits the target control signal to the target LED lamp bead, so that the target LED lamp bead presents the brightness corresponding to the target brightness data. After receiving the target control signal, the target LED lamp bead emits the brightness corresponding to the target control signal according to the target control signal, thereby achieving the brightness corresponding to the target brightness data.

[0089] The embodiment of the present application forwards the brightness data group to the corresponding driving module through the driving chip, and controls the driving unit in the driving module to sample and obtain the brightness data corresponding to the driving unit in the brightness data group based on a high-frequency clock of a preset frequency, which can greatly improve the transmission rate of the brightness data, thereby efficiently generating and sending control signals to the LED lamp beads electrically connected to the driving unit, thereby quickly driving the LED lamp beads to present the brightness corresponding to the brightness data, meeting the data transmission rate requirements of the liquid crystal display under high refresh rate conditions, and improving the user experience.

[0090] In some embodiments, the liquid crystal display control method further includes but is not limited to the following steps S400-S600: S400: Receive test data sent by the test device.

[0091] In this embodiment, the driver chip is also connected to the test device for communication, for example, see Figure 9a The driver chip 100 is also in communication with the test device 400. The test device is used to test the driver unit or obtain status data of the driver unit.

[0092] In this step, the test device sends test data to the driver chip through the network, wherein the test data is used to test the driver unit. For example, by sending the test data to the driver chip, the driver unit in the driver chip responds to the test data, generates response data, and returns the response data to the test device. In this way, the test device can determine the status, performance, communication connection, etc. of the driver unit based on the response data, and complete the test of the driver unit.

[0093] Specifically, the driver chip receives the test data sent by the test device through a network, which may be a wired communication network (such as USB, CAN bus, etc.) or a wireless communication network (such as Wi-Fi, Bluetooth, etc.).

[0094] S500: Control the drive unit to be tested to obtain target data according to the test data.

[0095] In this step, the driving unit to be tested is any one of the multiple cascaded driving units of the driving module to be tested, and the driving module to be tested is any one of the multiple driving modules.

[0096] Specifically, after receiving the test data, the driver chip arbitrarily selects one driver module from multiple driver modules as the driver module to be tested, and uses any one driver unit from multiple cascaded driver units of the driver module to be tested as the driver unit to be tested, transmits the test data to the driver unit to be tested, and controls the driver unit to be tested to obtain target data according to the test data.

[0097] In some embodiments, the test data may be a test instruction, a command, or a message, for example. For example, the test data is a status acquisition instruction. After receiving the status acquisition instruction, the driver chip transmits the status acquisition instruction to the driver unit to be tested, controls the driver unit to parse or respond to the status acquisition instruction, determines that the test device needs to obtain its own current status, generates status data (i.e., target data) based on its own status, and sends the status data to the test device. In this way, the test device can determine the current status of the driver unit to be tested based on the status data.

[0098] In some embodiments, controlling the drive unit to be tested to obtain target data according to the test data specifically includes but is not limited to the following steps S510-S530: S510: In response to determining that the drive unit to be tested is in the read mode according to the read-write mode configuration header, determine the target register address according to the register address configuration header.

[0099] In this step, the test data includes the read / write mode configuration header, register address configuration header, read / write data length configuration header, and target operation bit. Figure 9b , read and write mode configuration header (R / W, also known as the second header of the test data, Figure 9bThe read / write mode configuration header is R, indicating read mode, read mode or read status) to transmit 1 bit of data, wherein the read / write mode configuration header indicates whether the current data transmission direction is to write data to the drive unit or to read the internal data of the drive unit.

[0100] Among them, the register address configuration header (Register Address, that is, the third header in the test data) transmits 7 bits of data, which is used to represent the register address to be read or written. The embodiment of the present application can address 1 to 128 register addresses.

[0101] The read / write data length configuration header (Data Length, the fourth header in the test data) transmits 7 bits of data, indicating the number of data words to be read or written. In this embodiment of the present application, a single data transmission can continuously write or read 128 data words, each containing 12 bits of data. When reading data words, every 16 data words constitute a data packet (Dn). If a single data transmission continuously writes or reads 128 data words, eight data packets are obtained, each containing 16 data words.

[0102] The target operation bit is located after the read / write data length configuration header. The target operation bit is a special bit data. The target operation bit serves as a start indication signal for reading register data. When the target operation bit is detected, the register data corresponding to the register address in the driver unit begins to be read. In some embodiments of the present application, the target operation bit can be a null operation bit, which is a special bit with a high level duration greater than 100ns and a low level duration greater than 100ns. Of course, the target operation bit can also be any other suitable operation bit. The designer can also design and obtain the target operation bit based on actual needs and engineering experience, and the embodiments of the present application do not impose any restrictions on this.

[0103] In this embodiment, the driver chip parses the test data and extracts the read / write mode configuration header, register address configuration header, and read / write data length configuration header from the test data. Based on the read / write mode configuration header, it determines whether the driver unit under test is in write mode or read mode. If the read / write mode configuration header determines that the driver unit under test is in read mode, the target register address (i.e., the register address of the data to be read) is determined based on the register address configuration header. Obviously, the target register address stores the register data to be read.

[0104] For example, when the 1-bit data of the read / write mode configuration header is parsed to be 1, it indicates that the drive unit to be tested is in write mode. The target register address is determined according to the 7-bit data in the register address configuration header.

[0105] S520: Determine the target number of data words according to the header configuration of the read / write data length.

[0106] Specifically, after determining the target register address, the target number of data words is determined according to the read / write data length configuration header, that is, the target number of data words (that is, the number of data words of register data read by the drive unit under test in one data transmission communication) is determined according to the 7 bits of data in the read / write data length configuration header.

[0107] In the embodiment of the present application, a data transmission communication can continuously read register data of up to 128 data words.

[0108] S530: In response to detecting the target operation bit, controlling the drive unit to be tested to obtain data of a target data word quantity according to the target register address.

[0109] Specifically, when parsing the test data, if the target operation bit in the test data is detected, indicating that the register data has started to be read, the drive unit under test is controlled to obtain data of the target data word quantity according to the determined target register address, that is, the target register address is addressed, and the register data of the target data word quantity stored is read from the target register address, thereby obtaining data of the target data word quantity, and the data of the target data word quantity is the target data.

[0110] For example, see Figure 9b The driver unit to be tested is IC1. Before reading the register data, the data receiving port of the driver unit to be tested (i.e. Figure 9b SDI) received as Figure 9b The data flow shown includes a communication frequency configuration header, a read / write mode configuration header, a register address configuration header, a read / write data length configuration header, and a target operation bit. After determining that the drive unit under test is in read mode according to the read / write mode configuration header, determining the target register address according to the register address configuration header, and determining the target number of data words according to the read / write data length configuration header, if the target operation bit is detected, the drive unit under test obtains the register data of the target number of data words stored at the target register address according to the target register address, that is, Figure 9b Data words Data 1 to Data n are shown.

[0111] S600: Control the drive unit to be tested to send target data to the testing device.

[0112] For example, after obtaining the target data, the drive unit to be tested is controlled to send the target data to the test device. In this way, the test device can determine the state, performance and communication connection of the drive unit according to the target data, thereby completing the test of the drive unit to be tested.

[0113] In some embodiments, controlling the drive unit to be tested to send target data to the testing device specifically includes but is not limited to the following steps S610-S620: S610: Determine a target data transmission rate according to the communication frequency configuration header.

[0114] S620: Control the drive unit to be tested to send target data to the test device at a target data transmission rate.

[0115] In this embodiment, the test data also includes a communication frequency configuration header. Figure 9b , the communication frequency configuration header (Freq Det, that is, the first header of the test data) transmits 2 bits of data. The communication frequency configuration header contains the current data transmission communication rate information. In the embodiment of the present application, the driver chip supports the reception and transmission of communication data at a communication rate of 2Mbp / s or 4Mbp / s or 6Mbp / s or 8Mbp / s.

[0116] It can be understood that when the communication rate configuration header acts in read mode, the internal logic circuit of the driving unit generates target data in a return-to-zero format matching the current communication rate according to the communication rate configuration header and returns it to the testing device.

[0117] Specifically, the test data is parsed, and after the communication frequency configuration header in the test data is extracted, the target data transmission rate is determined according to the communication frequency configuration header, and then the target data is converted into target data in a return-to-zero code format that matches the target data transmission rate according to the target data transmission rate, and the drive unit under test is controlled to send the target data in the return-to-zero code format to the test device at the target data transmission rate.

[0118] In an embodiment of the present application, target data in a return-to-zero code format is transmitted based on a high-frequency clock with a frequency of 64 MHz. When the target data transmission rate is 2 Mbps, for the waveform of the bit "1" to be transmitted, the number of clock cycles corresponding to its high level and low level are 24 clock cycles and 8 clock cycles, respectively. For the waveform of the bit "0" to be transmitted, the number of clock cycles corresponding to its high level and low level are 8 clock cycles and 24 clock cycles, respectively. When the target data transmission rate is 4 Mbps, for the waveform of the bit "1" to be transmitted, the number of clock cycles corresponding to its high level and low level are 12 clock cycles and 4 clock cycles, respectively. For the waveform of the bit "0" to be transmitted, the number of clock cycles corresponding to its high level and low level are 4 clock cycles and 12 clock cycles, respectively. When the target data transmission rate is 6 Mbps, for the waveform of a bit "1" to be transmitted, the number of clock cycles corresponding to its high level and low level are 8 clock cycles and 3 clock cycles, respectively. For the waveform of a bit "0" to be transmitted, the number of clock cycles corresponding to its high level and low level are 3 clock cycles and 8 clock cycles, respectively. When the target data transmission rate is 8 Mbps, for the waveform of a bit "1" to be transmitted, the number of clock cycles corresponding to its high level and low level are 5 clock cycles and 3 clock cycles, respectively. For the waveform of a bit "0" to be transmitted, the number of clock cycles corresponding to its high level and low level are 3 clock cycles and 5 clock cycles, respectively.

[0119] It can be understood that when the frequency of the high-frequency clock is not 64Mhz, at the same target data transmission rate, for the bit "1" or bit "0" waveform to be sent, the number of clock cycles corresponding to its high level and low level may be the same as or different from the number of clock cycles corresponding to the high level and low level of the bit "1" or bit "0" waveform to be sent when the frequency of the high-frequency clock is 64Mhz. The designer can design high-frequency clocks of different frequencies, different data transmission rates and the number of clock cycles corresponding to the high level and low level of sending data bit "1" or bit "0" under the corresponding high-frequency clocks and data transmission rates according to actual needs and engineering experience. The embodiments of the present application do not impose any restrictions on this.

[0120] In the process of reading the internal data of the drive unit, please refer to Figure 7b , the driver unit processes the test data as follows: When the read / write mode configuration header is detected as 1, the current communication is determined to be in read mode. After the state machine jumps to the target operation bit, it uses the target register address to obtain the register data corresponding to the register address. The register data corresponding to the register address is then stored in the shift register of the transmit buffer memory. During the data word transmission phase, the transmit buffer memory continuously shifts the register to the left. After the 11th bit of data (i.e., a data word) is transmitted, the register data with the subsequent incremented addresses are updated to the transmit buffer memory. This process repeats until the target data is transmitted.

[0121] When sending the target data in the return-to-zero code format, the driver unit calculates the number of clock cycles required to send one bit of data (this number of clock cycles includes the number of clock cycles spent on high and low levels) as N1 based on the data transmission rate carried by the communication frequency configuration header.

[0122] The driver configures the header based on the communication frequency and calculates the number of clock cycles required for a high level signal to transmit a bit "0" waveform or a bit "1" waveform. Assume that the number of clock cycles required for a high level signal to transmit a bit "0" waveform is N2, and the number of clock cycles required for a high level signal to transmit a bit "1" waveform is N3.

[0123] When transmitting each data bit, the driver unit uses the clk_cnt counter to count the length of the high and low levels generated by the current data bit. The clk_cnt counter is reset to zero after reaching N1, and the counting cycle restarts. When transmitting a bit "0" waveform, SDO (the data transmission port) outputs a high level while the clk_cnt count value is less than N2. When the clk_cnt count value is greater than N2, SDO (the data transmission port) outputs a low level. When transmitting a bit "1" waveform, SDO (the data transmission port) outputs a high level while the clk_cnt count value is less than N3. When the clk_cnt count value is greater than N3, SDO (the data transmission port) outputs a low level.

[0124] When sending each data word, the driver unit counts the number of bits of data sent using the third counter bit_cnt. When the count value of the counter clk_cnt reaches N1, the count value of the third counter bit_cnt is incremented by one. When the count value of the third counter bit_cnt reaches 12 (indicating that one data word has been sent), the count value of the third counter bit_cnt is cleared and the counting cycle begins again.

[0125] When sending each data packet, the driver unit counts the number of data words sent using the fourth counter, byte_cnt. When the third counter, bit_cnt, reaches 12 (indicating that one data word has been sent), the fourth counter, byte_cnt, increments by one. When the fourth counter, byte_cnt, reaches the number of data words specified in the read / write data length configuration header, all pending data packets have been sent, and the state machine transitions to the idle state.

[0126] See also Figure 10 The state machine contains nine internal states: IDLE, DET, RW, ADDR, LENTH, NOP, RX, TX, and RELAY. When the display refresh synchronization signal SYNC is low, the state machine transitions to IDLE. When SYNC is high and the rising edge of the SDI (data receive port) input data waveform is detected, the state machine transitions from IDLE to DET. Transitions between the remaining states are controlled by the communication protocol and the received data content.

[0127] To sum up, the liquid crystal display control method provided in the embodiment of the present application is applied to a driver chip, the driver chip is electrically connected to the LED backlight source, the driver chip includes multiple driver modules, the driver module includes multiple cascaded driver units, the LED backlight source includes multiple groups of LED lamp beads, and each driver unit is electrically connected to a group of LED lamp beads. The method includes: obtaining a brightness data set, the brightness data set including multiple brightness data groups, the number of brightness data groups is the same as the number of driving modules, each brightness data group corresponds to a driving module, the brightness data group includes brightness data of multiple driving units of the driving module corresponding to the brightness data group, and the brightness data is in a return-to-zero code format; controlling a target driving unit to obtain target brightness data from the target brightness data group based on a high-frequency clock of a preset frequency, the target driving unit is any one of multiple cascaded driving units of the target driving module, the target driving module is any one of multiple driving modules, the target brightness data group is a brightness data group corresponding to the target driving module in the brightness data set, and the target brightness data is the brightness data of the target driving unit; controlling the target driving unit to generate a target control signal based on the target brightness data, and sending the target control signal to a target LED lamp bead so that the target LED lamp bead presents a brightness corresponding to the target brightness data, and the target LED lamp bead is a group of LED lamp beads in the multiple groups of LED lamp beads that are electrically connected to the target driving unit.

[0128] The embodiment of the present application forwards the brightness data group to the corresponding driving module through the driving chip, and controls the driving unit in the driving module to sample and obtain the brightness data corresponding to the driving unit in the brightness data group based on a high-frequency clock of a preset frequency, which can greatly improve the transmission rate of the brightness data, thereby efficiently generating and sending control signals to the LED lamp beads electrically connected to the driving unit, thereby quickly driving the LED lamp beads to present the brightness corresponding to the brightness data, meeting the data transmission rate requirements of the liquid crystal display under high refresh rate conditions, and improving the user experience.

[0129] An embodiment of the present application provides a computer-readable storage medium, on which computer program instructions executable by a processor are stored. The processor executes the computer program instructions to enable a computer to execute any one of the liquid crystal display control methods provided in the embodiments of the present application, or to execute steps in any possible implementation of any one of the liquid crystal display control methods provided in the embodiments of the present application.

[0130] In some embodiments, the storage medium may be a flash memory, a hard disk, an optical disk, a register, a magnetic surface storage, a removable disk, a CD-ROM, a random access memory (RAM), a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM or any other form of storage medium known in the art, or various devices including one or any combination of the above storage media.

[0131] In some embodiments, computer program instructions may be in the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0132] As an example, computer program instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, for example, in one or more scripts within an HTML (HyperText Markup Language) document, or in a single file dedicated to the program in question, or in multiple coordinated files (for example, files storing one or more modules, subroutines, or code portions).

[0133] As an example, computer program instructions can be deployed to be executed on a computing device (including devices such as smart terminals and servers), or on multiple computing devices located in one location, or on multiple computing devices distributed in multiple locations and interconnected by a communication network. It is easy to understand that all or part of the steps of the method described in the embodiments provided above in this application can be directly implemented using electronic hardware or processor-executable computer program instructions, or a combination of the two.

[0134] Those skilled in the art will understand that the embodiments provided in this application are merely illustrative, and the order in which the steps in the methods of the embodiments are written does not imply a strict order of execution and does not constitute any limitation on the implementation process. The order can be adjusted, merged, and deleted according to actual needs. The modules or submodules, units, or subunits in the device or system of the embodiment can be merged, divided, and deleted according to actual needs. For example, the division of units is only a logical function division, and there can be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0135] Through the description of the above embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a general hardware platform, or can also be implemented using hardware. Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When executed, the computer program can include the processes of the above-mentioned method embodiments. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).

[0136] It should be noted that the above embodiments are intended to illustrate the technical concepts and features of the present application, and their purpose is to enable people familiar with this technology to understand the content of the present application and implement it accordingly. They cannot be used to limit the scope of protection of the present application. Ordinary technicians in this field can understand that all or part of the processes of the above embodiments can be implemented according to the technical solutions recorded in the embodiments of the present application, or some of the technical features can be equivalently replaced. It is understandable that these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application, and should be regarded as equal changes and modifications based on the embodiments of the present application, and should all fall within the scope of the claims of the present application.

Claims

1. A liquid crystal display control method, applied to a driver chip, characterized in that: The driver chip is electrically connected to the LED backlight source, the driver chip includes a plurality of driver modules, the driver module includes a plurality of cascaded driver units, the LED backlight source includes a plurality of groups of LED lamp beads, and each of the driver units is electrically connected to a group of the LED lamp beads; The method comprises: Acquire a brightness data set, the brightness data set including a plurality of brightness data groups, the number of the brightness data groups being the same as the number of the driving modules, each brightness data group corresponding to one driving module, the brightness data group including brightness data of a plurality of driving units of the driving module corresponding to the brightness data group, the brightness data being in a return-to-zero code format; Controlling a target driving unit to obtain target brightness data from a target brightness data group based on a high-frequency clock of a preset frequency, wherein the target driving unit is any one of a plurality of cascaded driving units of a target driving module, the target driving module is any one of a plurality of driving modules, the target brightness data group is a brightness data group corresponding to the target driving module in the brightness data set, and the target brightness data is brightness data of the target driving unit; The target driving unit is controlled to generate a target control signal based on the target brightness data, and the target control signal is sent to the target LED lamp bead so that the target LED lamp bead presents a brightness corresponding to the target brightness data. The target LED lamp bead is a group of LED lamp beads electrically connected to the target driving unit among the multiple groups of LED lamp beads.

2. The liquid crystal display control method according to claim 1, wherein: The driver chip is further connected to a data device for communication. The first driver unit among the multiple cascaded driver units of the driver module is a reference driver unit, and the reference driver unit is connected to the data device for communication. The obtaining of the brightness data set includes: The reference driving unit is controlled to receive the brightness data group sent by the data device, wherein the brightness data groups received by all the reference driving units are the brightness data sets.

3. The liquid crystal display control method according to claim 2, wherein: The target brightness data group includes a read / write mode configuration header, a register address configuration header, and a read / write data length configuration header, and the control target driving unit obtains target brightness data from the target brightness data group based on a high-frequency clock of a preset frequency, including: In response to determining that the target drive unit is in write mode according to the read / write mode configuration header, determining a target register address according to the register address configuration header; Determine the target number of data words according to the read / write data length configuration header; The target driving unit is controlled to obtain brightness data of the target data word number corresponding to the target driving unit from the target brightness data group based on a high-frequency clock of a preset frequency, and the brightness data of the target data word number is stored in the target register address. The brightness data of the target data word number corresponding to the target driving unit is the target brightness data.

4. The liquid crystal display control method according to claim 3, wherein: The target brightness data group further includes a target operation bit, and controlling the target driving unit to obtain brightness data of the target data word quantity corresponding to the target driving unit from the target brightness data group based on a high-frequency clock of a preset frequency includes: In response to the display synchronization signal received by the signal receiving port of the target driving unit being in a high state and the target operation bit being detected, controlling the data sending port of the target driving unit to output a low level; During the low level output time of the data sending port, the target driving unit is controlled to obtain the brightness data of the target data word quantity from the target data bit of the target brightness data group based on the high-frequency clock, where the target data bit is the next data bit of the target operation bit; In response to detecting the next target operation bit, the target driving unit is controlled to stop acquiring brightness data.

5. The liquid crystal display control method according to claim 4, wherein: After the response to detecting the next target operation bit and controlling the target driving unit to stop acquiring brightness data, the method further includes: The data sending port of the target driving unit is controlled to output a high level, and the target brightness data group is sent to a next driving unit of the target driving unit, so that the next driving unit obtains brightness data from the target brightness data group.

6. The liquid crystal display control method according to claim 1, wherein: The driver chip is also in communication with a testing device, and the method further includes: receiving test data sent by the test device, wherein the test data is used to test the driving unit; Controlling a drive unit to be tested to obtain target data according to the test data, wherein the drive unit to be tested is any one of a plurality of cascaded drive units of a drive module to be tested, and the drive module to be tested is any one of a plurality of drive modules; The driving unit to be tested is controlled to send the target data to the testing device.

7. The liquid crystal display control method according to claim 6, wherein: The test data includes a read / write mode configuration header, a register address configuration header, a read / write data length configuration header, and a target operation bit, and the controlling the drive unit to be tested to obtain target data according to the test data includes: In response to determining that the drive unit to be tested is in read mode according to the read-write mode configuration header, determining a target register address according to the register address configuration header; Determine the target number of data words according to the read / write data length configuration header; In response to detecting the target operation bit, the drive unit to be tested is controlled to obtain data of the target data word quantity according to the target register address, and the data of the target data word quantity is the target data.

8. The liquid crystal display control method according to claim 7, wherein: The test data further includes a communication frequency configuration header, and the controlling the drive unit to be tested to send the target data to the test device includes: determining a target data transmission rate according to the communication frequency configuration header; The drive unit under test is controlled to send the target data to the test device at the target data transmission rate.

9. A driver chip, characterized in that: include: A controller and a plurality of drive modules respectively connected to the controller for communication, wherein the drive modules include a plurality of cascaded drive units; The driving unit includes a signal port and a data port, the signal port includes a signal sending port and a signal receiving port, and the data port includes a data sending port and a data receiving port, the signal receiving port and the data receiving port of any driving unit are respectively connected to the signal sending port and the data sending port of the previous driving unit, and the signal sending port and the data sending port of the driving unit are respectively connected to the signal receiving port and the data receiving port of the next driving unit; The controller is used to execute the liquid crystal display control method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer program instructions executable by a processor, and the processor executes the computer program instructions to enable the computer to execute the liquid crystal display control method according to any one of claims 1 to 8.

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