LDPC (Low Density Parity Check) decoding capability test application method and device, storage equipment, storage medium and program product

Abstract

The embodiment of the invention provides an LDPC decoding capability test application method and device, storage equipment, a storage medium and a program product, and relates to the technical field of storage. According to the method, after the LDPC decoding function of the main control chip is started, reading operation is performed on the storage medium, the decoding failure probability corresponding to a plurality of invalid bit numbers is obtained, and the decoding capability performance of the main control chip for different invalid bit number scenes can be reflected. And reading operation is directly performed on the storage medium through the test platform to obtain the data volume ratio corresponding to the plurality of invalid bit numbers, so that the original error distribution characteristics of the storage medium under the condition that decoding correction is not performed can be reflected. And finally, through quantitative comparison and analysis of the original error distribution characteristics of the storage medium and the decoding performance of the main control chip, scientificity and reliability of LDPC decoding capability evaluation of the storage medium with different code rates by different main control chips are ensured, so that a solid technical basis and a clear judgment standard are provided for project decision making.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to an LDPC decoding capability test application method, apparatus, storage device, storage medium and program product. Background Art

[0002] Although Low Density Parity Check Code (LDPC) performs well in ideal additive white Gaussian noise (AWGN) channels, in actual 3D NAND applications, LDPC decoding capabilities often degrade significantly due to differences between channel characteristics and the ideal model.

[0003] Furthermore, the actual LDPC decoding capabilities of different controller chips may vary, and these differences directly impact the reliability of storage devices. However, there is currently a lack of effective testing methods to quantify the actual LDPC soft-decision decoding capabilities, making it impossible to accurately assess the reliability of storage media using a specific controller chip. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide an LDPC decoding capability test application method, apparatus, storage device, storage medium and program product, which can scientifically and reliably evaluate whether there is a reliability risk of the storage medium when using a main control chip, and provide a solid technical basis and clear judgment criteria for project decision-making.

[0005] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, the present invention provides an LDPC decoding capability test application method, which is applied to a storage device, wherein the storage device includes a main control chip and a storage medium, and the method includes: Performing a read operation on the storage medium through a test platform to obtain a data volume ratio corresponding to a plurality of failed bit numbers; the failed bit number indicates that the number of bits obtained by performing a read operation on a storage space of a preset size is different from the number of bits of data written to the storage space of the preset size; Activating the LDPC decoding function of the main control chip and performing a read operation on the storage medium to obtain decoding failure probabilities corresponding to multiple numbers of failed bits; Whether the LDPC decoding capability of the main control chip meets the decoding requirements of the storage medium is determined according to the data volume ratio corresponding to the multiple failure bit numbers and the decoding failure probability corresponding to the multiple failure bit numbers.

[0006] In an optional embodiment, the storage medium includes a plurality of storage blocks; and performing a read operation on the storage medium through a test platform to obtain data volume proportions corresponding to a plurality of failed bit numbers includes: Performing a read operation on storage blocks corresponding to different preset erase and write times through a test platform to obtain read data volumes of multiple failed bit numbers under different preset erase and write times; According to the read data volume and the total data volume of the multiple failed bit numbers under each of the preset erasure times, the data volume ratio corresponding to the multiple failed bit numbers under each of the preset erasure times is obtained.

[0007] In an optional embodiment, determining whether the LDPC decoding capability of the main control chip meets the decoding requirements of the storage medium according to the data volume ratio corresponding to the multiple numbers of failed bits and the decoding failure probability corresponding to the multiple numbers of failed bits includes: Determining the maximum number of failed bits among the multiple numbers of failed bits under all the preset erasure times as the target number of failed bits; When the product of the data volume ratio corresponding to the target number of failure bits and the decoding failure probability corresponding to the target number of failure bits is less than a preset value, it is determined that the LDPC decoding capability of the main control chip meets the decoding requirements of the storage medium; When the product of the data volume ratio corresponding to the target number of failure bits and the decoding failure probability corresponding to the target number of failure bits is not less than the preset value, it is determined that the LDPC decoding capability of the main control chip does not meet the decoding requirements of the storage medium.

[0008] In an optional implementation manner, enabling the LDPC decoding function to perform a read operation on the storage medium to obtain decoding failure probabilities corresponding to multiple numbers of failed bits includes: Decoding the data read from the storage medium using the LDPC decoding function to obtain decoding information; the decoding information includes a plurality of failure bit numbers and a number of soft decoding successes and a number of soft decoding failures corresponding to each of the failure bit numbers; According to the number of soft decoding successes and the number of soft decoding failures corresponding to each number of failed bits, a decoding failure probability corresponding to each number of failed bits is obtained.

[0009] In an optional embodiment, the number of soft decoding successes includes the number of 1-bit decoding successes, the number of 2-bit decoding successes, and the number of 3-bit decoding successes; and obtaining the decoding failure probability corresponding to each number of failure bits according to the number of soft decoding successes and the number of soft decoding failures corresponding to each number of failure bits includes: For each of the failed bit numbers, determine the number of 1-bit decoding failures, the number of 2-bit decoding failures, and the number of 3-bit decoding failures corresponding to the failed bit number according to the number of 2-bit decoding successes, the number of 3-bit decoding successes, and the number of soft decoding failures corresponding to the failed bit number; Determine a 1-bit decoding failure probability corresponding to the number of failed bits according to the number of 1-bit decoding successes and the number of 1-bit decoding failures corresponding to the number of failed bits; Determine a 2-bit decoding failure probability corresponding to the number of failed bits according to the number of 2-bit decoding successes and the number of 2-bit decoding failures corresponding to the number of failed bits; Determine a 3-bit decoding failure probability corresponding to the number of failed bits according to the number of 3-bit decoding successes and the number of 3-bit decoding failures corresponding to the number of failed bits; The decoding failure probability corresponding to the number of failed bits is determined according to the 1-bit decoding failure probability, the 2-bit decoding failure probability, and the 3-bit decoding failure probability corresponding to the number of failed bits.

[0010] In an optional embodiment, determining the number of 1-bit decoding failures, the number of 2-bit decoding failures, and the number of 3-bit decoding failures corresponding to the number of failed bits based on the number of 2-bit decoding successes, the number of 3-bit decoding successes, and the number of soft decoding failures includes: Determine the number of 1-bit decoding failures corresponding to the number of failed bits according to the number of 2-bit decoding successes corresponding to the number of failed bits, the number of 3-bit decoding successes, and the number of soft decoding failures; Determine the number of 2-bit decoding failures corresponding to the number of failed bits according to the number of 3-bit decoding successes corresponding to the number of failed bits and the number of soft decoding failures; The number of soft decoding failures corresponding to the number of failed bits is determined as the number of 3-bit decoding failures corresponding to the number of failed bits.

[0011] In a second aspect, the present invention provides an LDPC decoding capability test application device, which is applied to a storage device, wherein the storage device includes a main control chip and a storage medium, and the device includes: An access module is configured to perform a read operation on the storage medium through a test platform to obtain a data volume ratio corresponding to a plurality of failed bit numbers; the failed bit number indicates a number of bits that differ between data obtained by a read operation on a storage space of a preset size and data written to the storage space of the preset size; enable an LDPC decoding function of the main control chip, perform a read operation on the storage medium, and obtain a decoding failure probability corresponding to the plurality of failed bit numbers; The processing module is used to determine whether the LDPC decoding capability of the main control chip meets the decoding requirements of the storage medium according to the data volume ratio corresponding to the multiple failure bit numbers and the decoding failure probability corresponding to the multiple failure bit numbers.

[0012] In a third aspect, the present invention provides a storage device comprising a main control chip and a flash memory chip, wherein the flash memory chip stores a computer program that can be executed by the main control chip, and the main control chip can execute the computer program to implement the LDPC decoding capability test application method described in any of the aforementioned embodiments.

[0013] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a main control chip, implements the LDPC decoding capability test application method as described in any one of the aforementioned embodiments.

[0014] In a fifth aspect, the present invention provides a program product, which, when executed by a main control chip, implements the LDPC decoding capability test application method as described in any one of the aforementioned embodiments.

[0015] Compared to existing technologies, the LDPC decoding capability testing application method, apparatus, storage device, storage medium, and program product provided by embodiments of the present invention enable the LDPC decoding function of a master chip and perform a read operation on the storage medium to obtain the decoding failure probabilities corresponding to multiple numbers of failed bits, which can reflect the master chip's decoding capability under different failure bit number scenarios. Furthermore, through a test platform, a direct read operation on the storage medium is performed to obtain the data volume percentage corresponding to multiple failure bit numbers, which can reflect the original error distribution characteristics of the storage medium without decoding correction. Finally, combining the data volume percentage corresponding to multiple failure bit numbers and the decoding failure probability, a comprehensive analysis is conducted to determine whether the master chip's LDPC decoding capability meets the actual decoding requirements of the storage medium. By quantitatively comparing the original error distribution characteristics of various storage media and the decoding performance of various master chips, a rapid and accurate assessment of the LDPC decoding capabilities of various master chips is achieved, ensuring the scientific and reliable evaluation of the LDPC decoding capabilities of different master chips for storage media with different bit rates, thereby providing a solid technical basis and clear judgment criteria for project decision-making.

[0016] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A flow chart of an LDPC decoding capability test application method provided by an embodiment of the present invention is shown.

[0019] Figure 2 Another flow chart of an LDPC decoding capability test application method provided by an embodiment of the present invention is shown.

[0020] Figure 3 A data damage distribution diagram of a storage medium provided by an embodiment of the present invention is shown.

[0021] Figure 4 A decoding failure probability curve diagram provided by an embodiment of the present invention is shown.

[0022] Figure 5 Another decoding failure probability curve diagram provided by an embodiment of the present invention is shown.

[0023] Figure 6 A block diagram of an LDPC decoding capability test application device provided by an embodiment of the present invention is shown.

[0024] Figure 7 A block diagram of a storage device provided by an embodiment of the present invention is shown.

[0025] Icon: 300-LDPC decoding capability test application device; 301-access module; 302-processing module; 400-storage device; 410-main control chip; 420-flash memory chip. DETAILED DESCRIPTION

[0026] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but is merely intended to represent selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative work are within the scope of protection of the present invention.

[0028] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

[0029] LDPC is a high-performance error-correcting code widely used in NAND flash memory storage systems due to its excellent performance, approaching the Shannon limit, and low decoding complexity. In the LDPC decoding process, hard decision and soft decision are two different information processing methods. Typically, binary codes directly read using threshold voltages have only two codewords, 0 or 1, for decoding, which is called hard decision decoding. Soft decision decoding uses codewords that are not approximated and contain signal waveform information, resulting in a lower bit error rate than hard decision decoding. Typically, in an ideal AWGN channel, soft decision decoding achieves a 2-3 dB soft decision gain compared to hard decision decoding.

[0030] The inventors' research has revealed that while LDPC decoding capabilities are typically derived from idealized model simulations, 3D NAND channels are not ideal AWGN channels. In real-world 3D NAND channel applications, the actual LDPC decoding capabilities are significantly weaker than those claimed by manufacturers through idealized model simulations. Furthermore, the actual decoding capabilities of different master control chips for storage media with different bit rates vary.

[0031] The reliability of storage devices is generally determined by the actual decoding capability of LDPC. The characteristic test results of the storage medium need to be combined with the actual decoding capability of LDPC to provide corresponding test conclusions. Therefore, the actual decoding capability of LDPC is very important. Therefore, a test method that can quantify the LDPC decoding capability is urgently needed to determine whether the LDPC decoding capability of the main control chip meets the decoding requirements of the storage medium. In other words, whether there are any reliability issues in the storage medium under the main control application.

[0032] Based on this, embodiments of the present invention provide an LDPC decoding capability testing application method, apparatus, storage device, storage medium, and program product. This method enables the LDPC decoding function of a master chip and then reads the storage medium to obtain decoding failure probabilities corresponding to multiple numbers of failed bits, demonstrating the master chip's decoding capability under different failure bit count scenarios. Furthermore, a test platform directly reads the storage medium to obtain the data volume percentage corresponding to multiple numbers of failed bits, reflecting the raw error distribution characteristics of the storage medium without decoding correction. Finally, combining the data volume percentage corresponding to multiple numbers of failed bits and the decoding failure probability, a comprehensive analysis is conducted to determine whether the master chip's LDPC decoding capability meets the actual decoding requirements of the storage medium. By quantitatively comparing the raw error distribution characteristics of various storage media and the decoding performance of various master chips, a rapid and accurate assessment of the LDPC decoding capabilities of various master chips is achieved, ensuring the scientific and reliable evaluation of the LDPC decoding capabilities of different master chips for storage media with different bit rates, thereby providing a solid technical basis and clear judgment criteria for project decision-making.

[0033] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0034] Please refer to Figure 1 , Figure 1 A flow chart of an LDPC decoding capability test application method provided by an embodiment of the present invention is shown. The LDPC decoding capability test application method is applied to a storage device having a storage medium and a main control chip with LDPC decoding function installed on the storage device. The method includes the following steps: In step S10, a test platform performs a read operation on the storage medium to obtain a data volume ratio corresponding to multiple failure bit numbers; the failure bit number indicates that the data obtained by performing a read operation on a storage space of a preset size has a different number of bits from the data written into the storage space of the preset size.

[0035] In an embodiment of the present invention, to test the LDPC decoding capabilities of different master control chips at different bit rates, the master control chip and storage medium to be tested are sequentially installed on a storage device. The reassembly table is then modified, retaining only the table relevant to the test scenario, saving testing time. With the LDPC decoding function enabled, if an error occurs while reading data from the storage medium based on the default read voltage, error handling is performed based on the modified reassembly table and hard-decision decoding. If error handling fails, a matching reassembly table is found based on the hard-decision decoding result, and soft-decision decoding is performed using the matching reassembly table.

[0036] To ensure the comprehensiveness and accuracy of the test results, the storage medium can be erased and written multiple times, and erase scenarios with a preset number of erase and write times can be selected to simulate the aging state in actual use. This multi-dimensional test design makes the evaluation results closer to the actual application environment, thereby improving the reliability of the judgment basis.

[0037] After the data is written, the storage medium to be tested is subjected to a baking test. For example, a storage medium that retains data for 10 years is subjected to a baking test at 55 degrees Celsius to ensure that the soft decision decoding process can be entered at each number of failed bits when the LDPC decoding function is enabled. It should be noted that the test rules of the baking test can be set according to the reliability of the storage medium. For storage media with higher reliability, more severe test rules can be set, such as increasing the baking temperature. It is also possible to select some storage particles with poor reliability to form the storage medium to be tested, thereby reducing the difficulty of the baking test. The present invention is not limited to this.

[0038] The test platform directly reads the storage medium to obtain read data corresponding to each preset size. The preset size can be the size of a decoding unit such as a sector, 1K, or 4K. The decoding unit is used to store the original data (i.e., the written data to be encoded) and the check data (i.e., the error-corrected data generated by LDPC encoding).

[0039] The write data and read data corresponding to each preset size are compared to obtain the failed bit count (FBC) for that preset size. Assuming the preset size is 4KB, if the number of bits that differ between the read and written data is 200, then the failed bit count is 200. After generating the failed bit counts for each preset size, the same failed bit count is counted to determine the data volume percentage corresponding to each failed bit count. Testing using a test platform that directly accesses the storage medium reveals the distribution of data corruption within the storage medium without error correction capabilities.

[0040] Step S20 , enabling the LDPC decoding function of the main control chip, and performing a read operation on the storage medium to obtain decoding failure probabilities corresponding to multiple numbers of failed bits.

[0041] In an embodiment of the present invention, after the LDPC decoding function of the main control chip is enabled, the storage medium is read again, and the decoded data obtained by LDPC decoding is compared with the corresponding written data. At this time, the decoding failure probability corresponding to different numbers of failed bits can be statistically calculated.

[0042] Step S30 , determining whether the LDPC decoding capability of the main control chip meets the decoding requirements of the storage medium based on the data volume ratio corresponding to the multiple failed bit numbers and the decoding failure probability corresponding to the multiple failed bit numbers.

[0043] In an embodiment of the present invention, after combining the data volume ratio corresponding to each number of failed bits and the decoding failure probability, it is determined whether the LDPC decoding capability of the main control chip meets the actual decoding requirements of the storage medium.

[0044] In summary, the LDPC decoding capability testing application method provided by the embodiments of the present invention enables the LDPC decoding function of the master control chip, performs a read operation on the storage medium, and obtains the decoding failure probabilities corresponding to multiple numbers of failed bits. This method can reflect the master control chip's decoding capability performance under different failure bit number scenarios. Furthermore, through the test platform, a direct read operation on the storage medium is performed to obtain the data volume percentage corresponding to multiple numbers of failed bits, which can reflect the original error distribution characteristics of the storage medium without decoding correction. Finally, combining the data volume percentage corresponding to multiple numbers of failed bits and the decoding failure probability, a comprehensive analysis is conducted to determine whether the master control chip's LDPC decoding capability meets the actual decoding requirements of the storage medium. By quantitatively comparing the original error distribution characteristics of various storage media and the decoding performance of various master control chips, a rapid and accurate assessment of the LDPC decoding capabilities of various master control chips is achieved, ensuring the scientific and reliable evaluation of the LDPC decoding capabilities of different master control chips for storage media with different bit rates, thereby providing a solid technical basis and clear judgment criteria for project decision-making. Project decision-making includes selecting a master control chip that meets the decoding requirements for the storage medium.

[0045] Optionally, in actual applications, the storage medium includes multiple storage blocks. The following provides a possible implementation method for obtaining the data volume ratio corresponding to different numbers of failed bits by accessing the storage blocks. Figure 2 , Figure 1 The sub-steps of step S10 may include: Step S101 , performing a read operation on storage blocks corresponding to different preset erase and write times through a test platform to obtain read data volumes of multiple failed bit numbers under different preset erase and write times.

[0046] In this embodiment of the present invention, without using any decoding function, a test platform performs read operations on storage blocks corresponding to different preset erase / write cycles in a storage medium, thereby detecting data corruption at specific aging levels. By counting the number of failed bits obtained after each read operation and the corresponding amount of read data, a comprehensive understanding of the distribution of data corruption at different erase / write cycles can be achieved.

[0047] Step S102 , obtaining a data volume ratio corresponding to the multiple numbers of failed bits under each preset number of erase / write times according to the read data volume and the total data volume of the multiple numbers of failed bits under each preset number of erase / write times.

[0048] As a possible implementation method, assuming that the preset erase and write times are 1, 130, 1000 and 1300 respectively, read operations are performed on the storage block with the preset erase and write time of 1 in sequence to obtain the read data volume of multiple failed bit numbers corresponding to the preset erase and write time of 1. For example, the size of the decoding unit is 4K, and the read data volume with the failed bit number of 200 is 8K, then the number of failed bits in the two decoding units is 200. The sum of the read data volumes corresponding to all read operations is determined as the total data volume, and the read data volumes of each failed bit number under the four preset erase and write times of 1, 130, 1000 and 1300 are counted respectively, and the ratio of the read data volume of each failed bit number under each preset erase and write time to the total data volume is determined as the proportion of the data volume corresponding to each failed bit number under each preset erase and write time, thereby forming a detailed data damage distribution map (such as Figure 3 This provides a quantitative basis for the subsequent evaluation of the error correction capability of the main control chip.

[0049] As can be seen, the embodiment of the present invention presents data corruption under different preset erase and write times in the form of the number of failed bits and the corresponding data volume ratio, providing a clear and quantified data distribution characteristic. This allows the evaluation of the LDPC decoding capability of the main control chip to no longer be limited to a single idealized assumption, but to be based on various data corruption modes that may occur in a real environment. This multi-dimensional data collection method ensures the comprehensiveness and reliability of the test results, laying a solid foundation for the compatibility evaluation of the main control chip and storage media, and providing a more reliable reference basis for product design and optimization.

[0050] Optionally, the following provides a possible implementation method for determining the LDPC decoding capability of the main control chip using the data volume ratio and decoding failure probability corresponding to different numbers of failed bits. Figure 2 , Figure 1 The sub-steps of step S30 may include: Step S301: determining the maximum number of failed bits among a plurality of failed bit numbers under all preset erasure times as a target number of failed bits.

[0051] In the embodiment of the present invention, multiple failure bit numbers under all preset erase / write times are analyzed and the maximum value is selected as the target failure bit number. The target failure bit number represents the most serious data damage under specific aging conditions.

[0052] Step S302: When the product of the data volume ratio corresponding to the target number of failure bits and the decoding failure probability corresponding to the target number of failure bits is less than a preset value, it is determined that the LDPC decoding capability of the main control chip meets the decoding requirements of the storage medium.

[0053] Step S303: When the product of the data volume ratio corresponding to the target number of failure bits and the decoding failure probability corresponding to the target number of failure bits is not less than a preset value, it is determined that the LDPC decoding capability of the main control chip does not meet the decoding requirements of the storage medium.

[0054] In the embodiment of the present invention, the Uncorrectable Bit Error Rate (UBER) is a key indicator for measuring the reliability of storage media data, which is used to quantify the proportion of erroneous data that cannot be corrected under the error correction mechanism. The lower the UBER value, the higher the data reliability. The enterprise-level standard is no more than (i.e. every A maximum of 1 bit of unrecoverable error is allowed in the bit data), the consumer standard is no more than (i.e. every A maximum of one uncorrectable error is allowed in bit data. The preset value can be set according to the UBER in the product specifications of the storage medium. Each storage medium has a corresponding preset value.

[0055] The product of the target number of failed bits and the master chip's probability of decoding failure in this scenario is calculated and compared with a preset value. If the product is less than the preset value, the master chip's LDPC decoding capability is determined to be sufficient for the storage medium's decoding requirements. If the product is not less than the preset value, the master chip's LDPC decoding capability is determined to be insufficient for the storage medium's decoding requirements.

[0056] Continue with Figure 3 For example, assuming the preset value is 9.8e-08 and the target number of failed bits is 500, if the product of the data volume ratio corresponding to the target number of failed bits and the decoding failure probability corresponding to the target number of failed bits is less than 9.8e-08, it is determined that the LDPC decoding capability of the main control chip meets the decoding requirements of the storage medium, indicating that there is no reliability risk when using this storage medium under the main control chip.

[0057] It can be seen that the embodiment of the present invention can effectively focus on the most severe challenges that the storage medium may face by selecting the maximum number of failed bits as the target number of failed bits and performing a comprehensive evaluation based on the data volume percentage and decoding failure probability corresponding to the target number of failed bits. Since the maximum number of failed bits directly reflects the extreme case of data damage, and the data volume percentage and decoding failure probability are quantified from the two dimensions of damage range and error correction capability, respectively, the evaluation index formed by the combination of the three is highly targeted and accurate. In addition, by setting a preset value for the storage medium as a basis for judgment, the objectivity and comparability of the test results are further enhanced, providing clear and reliable guidance for the optimal adaptation of the main control chip and the storage medium.

[0058] Optionally, a possible implementation method is provided below for how to obtain the decoding failure probability for different numbers of failed bits. Figure 2 , Figure 1 The sub-steps of step S20 may include: Step S201 : Decode data read from a storage medium using an LDPC decoding function to obtain decoding information; the decoding information includes a plurality of failure bit numbers and the number of soft decoding successes and the number of soft decoding failures corresponding to each failure bit number.

[0059] In this embodiment of the present invention, decoding information is obtained by enabling the LDPC decoding function to read and decode the storage medium. This decoding information includes the total number of soft decoding attempts, the total number of decoding failures, the number of failed bits, and the number of soft decoding successes and failures corresponding to the number of failed bits. The total number of soft decoding attempts is the number of times soft decision decoding was initiated, and the firmware updates the total number of soft decoding attempts after each soft decision decoding attempt. The total number of decoding failures is the number of decoding failures by the main control chip, specifically the number of times 3-bit soft decision decoding still failed.

[0060] Step S202 : Obtain a decoding failure probability corresponding to each number of failure bits according to the number of soft decoding successes and the number of soft decoding failures corresponding to each number of failure bits.

[0061] In an embodiment of the present invention, by comparing and analyzing the number of soft decoding successes and soft decoding failures corresponding to each number of failed bits, the decoding failure probability under each number of failed bits is determined, which can fully reflect the error correction capability performance of the main control chip when facing different degrees of data corruption.

[0062] It can be seen that the embodiment of the present invention counts the number of soft decoding successes and failures corresponding to each number of failed bits in detail, and calculates the decoding failure probability corresponding to each number of failed bits based on this. This can accurately characterize the LDPC decoding capability of the main control chip based on the actual decoding results. In addition, through the comprehensive analysis of multiple numbers of failed bits, it can fully cover various error scenarios that the storage medium may encounter, thereby providing a more comprehensive and accurate basis for evaluating the LDPC decoding capability of the control chip, not only improving the credibility of the test results, but also providing a clear direction for subsequent optimization of the LDPC decoding function of the main control chip.

[0063] Optionally, in practical applications, the number of soft decoding successes includes the number of 1-bit decoding successes, the number of 2-bit decoding successes, and the number of 3-bit decoding successes. The following provides a possible implementation method for using the number of 1-bit decoding successes, the number of 2-bit decoding successes, the number of 3-bit decoding successes, and the number of soft decoding failures to obtain a decoding failure probability corresponding to each number of failed bits. Figure 2 Step S202 includes the following steps: For each number of failed bits, the number of 1-bit decoding failures, 2-bit decoding failures and 3-bit decoding failures corresponding to the failed bit number are determined based on the number of 2-bit decoding successes, 3-bit decoding successes and soft decoding failures corresponding to the failed bit number; the 1-bit decoding failure probability corresponding to the failed bit number is determined based on the number of 1-bit decoding successes and 1-bit decoding failures corresponding to the failed bit number; the 2-bit decoding failure probability corresponding to the failed bit number is determined based on the number of 2-bit decoding successes and 2-bit decoding failures corresponding to the failed bit number; the 3-bit decoding failure probability corresponding to the failed bit number is determined based on the number of 3-bit decoding successes and 3-bit decoding failures corresponding to the failed bit number; the decoding failure probability corresponding to the failed bit number is determined based on the 1-bit decoding failure probability, 2-bit decoding failure probability and 3-bit decoding failure probability corresponding to the failed bit number.

[0064] In this embodiment of the present invention, the number of 1-bit decoding successes refers to the number of times data is successfully recovered by increasing the amount of information by 1 bit during the soft decision decoding process, and is counted based on the number of failed bits. The number of 2-bit decoding successes refers to the number of times data is successfully recovered after further increasing the soft information precision to 2 bits when 1-bit soft decision decoding fails to fully recover data, and is counted based on the number of failed bits. The number of 3-bit decoding successes refers to the number of times data is successfully recovered after increasing the soft information precision to 3 bits, and is counted based on the number of failed bits. If data still cannot be recovered after 3 bits, the decoding is determined to have failed, and the total number of soft decoding failures is cumulatively updated.

[0065] The decoding information includes multiple failed bit numbers, the number of 1-bit decoding successes, 2-bit decoding successes, 3-bit decoding successes, and soft decoding failures corresponding to each failed bit number. Among them, the number of failed bits corresponding to 1-bit decoding success, the number of failed bits corresponding to 2-bit decoding successes, and the number of failed bits corresponding to 3-bit decoding successes are returned to the firmware after the main control chip successfully decodes. The firmware performs statistics based on the number of failed bits to obtain the number of 1-bit decoding successes, 2-bit decoding successes, and 3-bit decoding successes corresponding to each failed bit number. After the main control chip fails to decode, the firmware counts the total number of decoding failures, and uses the data retrieved through the test platform or the data before LDPC decoding obtained from the cache of the main control chip to compare with the written data to obtain the number of failed bits when the decoding fails, and counts the number of soft decoding failures corresponding to the number of failed bits.

[0066] By comprehensively analyzing the number of 2-bit decoding successes, 3-bit decoding successes and soft decoding failures corresponding to each number of failed bits, the number of 1-bit decoding failures, 2-bit decoding failures and 3-bit decoding failures corresponding to the number of failed bits can be further determined.

[0067] The number of 1-bit decoding successes and 1-bit decoding failures corresponding to each failure bit number are summed to obtain the number of 1-bit decoding successes corresponding to each failure bit number, and the ratio of the number of 1-bit decoding successes to the number of 1-bit decoding failures corresponding to each failure bit number is determined as the 1-bit decoding failure probability corresponding to each failure bit number.

[0068] The number of 2-bit decoding successes and the number of 2-bit decoding failures corresponding to each number of failed bits are summed to obtain the number of 2-bit decoding successes corresponding to each number of failed bits, and the ratio of the number of 2-bit decoding successes to the number of 2-bit decoding failures corresponding to each number of failed bits is determined as the 2-bit decoding failure probability corresponding to each number of failed bits.

[0069] The number of 3-bit decoding successes and 3-bit decoding failures corresponding to each number of failed bits is summed to obtain the number of 3-bit decodings corresponding to each number of failed bits. The ratio of the number of 3-bit decoding successes to the number of 3-bit decodings corresponding to each number of failed bits is determined as the probability of 3-bit decoding failure corresponding to each number of failed bits. Decoding failure probability curves are generated based on the 1-bit decoding failure probability, 2-bit decoding failure probability, and 3-bit decoding failure probability corresponding to all the number of failed bits. Taking the A-type main control chip and the storage medium with a bit rate of 0.886 as an example, assuming the preset size is 4K, the decoding failure probability curve is as follows: Figure 4 As shown, Figure 4 The horizontal coordinate is FBC / 4K, and the vertical coordinate is the decoding failure probability.

[0070] The decoding failure probability corresponding to each number of failed bits is obtained by combining the 1-bit decoding failure probability, 2-bit decoding failure probability, and 3-bit decoding failure probability corresponding to each number of failed bits, as shown in the following example: Figure 5 As shown. Figure 5 It can be seen that in When the number of failed bits is less than 540 (the preset size is 4K), the data can be successfully decoded through LDPC soft decision. When the number of failed bits is 540, the probability of decoding failure is 2.2e-03.

[0071] It can be seen that the embodiment of the present invention refines the granularity of the decoding performance evaluation by finely dividing the number of soft decoding successes into 1-bit decoding successes, 2-bit decoding successes, and 3-bit decoding successes, and combining the number of soft decoding failures to calculate the number of decoding failures and failure probabilities corresponding to each number of failed bits, thereby achieving accurate quantification of failure situations at different decoding levels under each number of failed bits. Furthermore, based on the comprehensive analysis of the decoding failure probabilities of the above-mentioned levels, the overall decoding failure probability is determined, thereby achieving a quantitative and accurate evaluation of the LDPC decoding capability of the main control chip, effectively improving the accuracy and reliability of the test results. This layer-by-layer subdivision and comprehensive analysis ensures the comprehensiveness and accuracy of the decoding failure probability, and provides solid technical support for the subsequent determination of whether the LDPC decoding function of the main control chip meets the storage medium decoding requirements.

[0072] Optionally, a possible implementation method for determining the number of 1-bit decoding failures, 2-bit decoding failures, and 3-bit decoding failures corresponding to the number of failed bits is provided below, including the following steps: The number of 1-bit decoding failures corresponding to the number of failed bits is determined based on the number of 2-bit decoding successes, the number of 3-bit decoding successes, and the number of soft decoding failures corresponding to the number of failed bits; the number of 2-bit decoding failures corresponding to the number of failed bits is determined based on the number of 3-bit decoding successes and the number of soft decoding failures corresponding to the number of failed bits; and the number of soft decoding failures corresponding to the number of failed bits is determined as the number of 3-bit decoding failures corresponding to the number of failed bits.

[0073] In this embodiment of the present invention, the sum of the number of 2-bit decoding successes, the number of 3-bit decoding successes, and the number of soft decoding failures for each failed bit number is calculated to obtain the number of 1-bit decoding failures for each failed bit number. In other words, LDPC 2-bit soft decoding is performed only after a 1-bit soft decoding failure, and LDPC 3-bit soft decoding is performed only after a 2-bit soft decoding failure. Using the number of 2-bit decoding successes, 3-bit decoding successes, and soft decoding failures for the same number of failed bits, it is possible to accurately separate the 1-bit LDPC soft decoding failures, ensuring that the statistics of 1-bit decoding failures are both comprehensive and accurate.

[0074] Similarly, the sum of the number of 3-bit decoding successes and the number of soft decoding failures corresponding to each failure bit number is calculated to obtain the number of 2-bit decoding failures corresponding to each failure bit number, and the number of soft decoding failures corresponding to each failure bit number is determined as the number of 3-bit decoding failures corresponding to each failure bit number.

[0075] As can be seen, the embodiments of the present invention, through detailed segmentation and precise calculation, can quantitatively analyze the number of decoding times at different levels for each number of failed bits. This hierarchical statistics more clearly demonstrates the actual decoding capabilities of the main control chip under storage media with different bit rates, enabling a comprehensive assessment of the main control chip's LDPC decoding capabilities and providing solid technical support for subsequent project decision-making.

[0076] Based on the same inventive concept, the basic principles and technical effects of the LDPC decoding capability test application device provided in the embodiment of the present invention are the same as those in the above embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference can be made to the corresponding contents in the above embodiment.

[0077] Please refer to Figure 6 , Figure 6 This figure illustrates a block diagram of an LDPC decoding capability test application device 300 according to an embodiment of the present invention. This device is applied to a storage device equipped with a storage medium and a main control chip capable of LDPC decoding. The device includes an access module 301 and a processing module 302.

[0078] Access module 301 is configured to perform a read operation on a storage medium through a test platform to obtain a data volume percentage corresponding to a plurality of failed bit numbers; the failed bit number indicates the number of bits that differ between data obtained by a read operation on a storage space of a preset size and data written to the storage space of the preset size; enable the LDPC decoding function of the main control chip, perform a read operation on the storage medium, and obtain a decoding failure probability corresponding to the plurality of failed bit numbers; The processing module 302 is configured to determine whether the LDPC decoding capability of the main control chip meets the decoding requirements of the storage medium according to the data volume ratio corresponding to the multiple failure bit numbers and the decoding failure probability corresponding to the multiple failure bit numbers.

[0079] In summary, the LDPC decoding capability testing application device provided by the embodiments of the present invention enables the LDPC decoding function of the master chip and performs a read operation on the storage medium to obtain the decoding failure probabilities corresponding to multiple numbers of failed bits, which can reflect the master chip's decoding capability performance under different failure bit number scenarios. Furthermore, through the test platform, a direct read operation on the storage medium is performed to obtain the data volume percentage corresponding to multiple numbers of failed bits, which can reflect the original error distribution characteristics of the storage medium without decoding correction. Finally, combining the data volume percentage corresponding to multiple numbers of failed bits and the decoding failure probability, a comprehensive analysis is conducted to determine whether the master chip's LDPC decoding capability meets the actual decoding requirements of the storage medium. By quantitatively comparing the original error distribution characteristics of various storage media and the decoding performance of various master chips, a rapid and accurate assessment of the LDPC decoding capabilities of various master chips is achieved, ensuring the scientific and reliable evaluation of the LDPC decoding capabilities of different master chips for storage media with different bit rates, thereby providing a solid technical basis and clear judgment criteria for project decision-making.

[0080] Optionally, the storage medium includes multiple storage blocks. The access module 301 is specifically configured to perform a read operation on the storage blocks corresponding to different preset erase / write times through a test platform to obtain read data volumes corresponding to multiple numbers of failed bits under different preset erase / write times; and obtain a data volume ratio corresponding to the multiple numbers of failed bits under each preset erase / write time based on the read data volumes and the total data volume of the multiple numbers of failed bits under each preset erase / write time.

[0081] Optionally, the processing module 302 is specifically used to determine the maximum number of failure bits among multiple failure bit numbers under all preset erase and write times as the target number of failure bits; when the product of the data volume ratio corresponding to the target number of failure bits and the decoding failure probability corresponding to the target number of failure bits is less than a preset value, it is determined that the LDPC decoding capability of the main control chip meets the decoding requirements of the storage medium; when the product of the data volume ratio corresponding to the target number of failure bits and the decoding failure probability corresponding to the target number of failure bits is not less than the preset value, it is determined that the LDPC decoding capability of the main control chip does not meet the decoding requirements of the storage medium.

[0082] Optionally, the access module 301 is specifically used to use the LDPC decoding function to decode the data read from the storage medium to obtain decoding information; the decoding information includes multiple failure bit numbers and the number of soft decoding successes and soft decoding failures corresponding to each failure bit number; based on the number of soft decoding successes and soft decoding failures corresponding to each failure bit number, the decoding failure probability corresponding to each failure bit number is obtained.

[0083] Optionally, the number of soft decoding successes includes the number of 1-bit decoding successes, the number of 2-bit decoding successes, and the number of 3-bit decoding successes. The access module 301 is specifically configured to determine, for each number of failed bits, the number of 1-bit decoding failures, the number of 2-bit decoding failures, and the number of soft decoding failures corresponding to the failed bit number; determine the 1-bit decoding failure probability corresponding to the failed bit number based on the number of 1-bit decoding successes and the number of 1-bit decoding failures corresponding to the failed bit number; determine the 2-bit decoding failure probability corresponding to the failed bit number based on the number of 2-bit decoding successes and the number of 2-bit decoding failures corresponding to the failed bit number; determine the 3-bit decoding failure probability corresponding to the failed bit number based on the number of 3-bit decoding successes and the number of 3-bit decoding failures corresponding to the failed bit number; and determine the decoding failure probability corresponding to the failed bit number based on the 1-bit decoding failure probability, the 2-bit decoding failure probability, and the 3-bit decoding failure probability corresponding to the failed bit number.

[0084] Optionally, the access module 301 is specifically used to determine the number of 1-bit decoding failures corresponding to the number of failed bits based on the number of 2-bit decoding successes, the number of 3-bit decoding successes, and the number of soft decoding failures corresponding to the number of failed bits; determine the number of 2-bit decoding failures corresponding to the number of failed bits based on the number of 3-bit decoding successes and the number of soft decoding failures corresponding to the number of failed bits; and determine the number of soft decoding failures corresponding to the number of failed bits as the number of 3-bit decoding failures corresponding to the number of failed bits.

[0085] Please refer to Figure 7 , is a block diagram of a storage device 400 according to an embodiment of the present invention. Storage device 400 includes a main control chip 410 and a flash memory chip 420. Main control chip 410 and flash memory chip 420 are electrically connected to each other to enable data transmission or exchange. For example, these components can be electrically connected via one or more communication buses or signal lines.

[0086] Flash memory chip 420 is a type of storage medium, comprising multiple blocks, which are used to store data and computer programs that can be executed by main control chip 410. The main control chip is used to read / write the data or computer programs stored in flash memory chip 420 and perform the corresponding functions. For example, when the computer program stored in flash memory chip 420 is executed by main control chip 410, the LDPC decoding capability test application method disclosed in the above embodiments can be implemented.

[0087] It should be understood that Figure 7 The structure shown is only a schematic diagram of the structure of the storage device 400. The storage device 400 may also include Figure 7 More or fewer components than shown, or with Figure 7 Different configurations shown. Figure 7 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0088] An embodiment of the present invention further provides a computer-readable storage medium storing a computer program. When the computer program is executed by the main control chip 410, the LDPC decoding capability test application method disclosed in the above embodiments is implemented.

[0089] The embodiment of the present invention further provides a program product. When the program product is executed by the main control chip 410, it implements the LDPC decoding capability test application method disclosed in the above embodiments.

[0090] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a portion of code, and the module, program segment or a portion of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or can be implemented using a combination of dedicated hardware and computer instructions.

[0091] In addition, the functional modules in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0092] If the functions are implemented as software modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or the portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage media include various media capable of storing program code, such as USB flash drives, mobile hard drives, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical disks.

[0093] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. An LDPC decoding capability test application method, characterized in that: Applied to a storage device, the storage device includes a main control chip and a storage medium, and the method includes: Performing a read operation on the storage medium through a test platform to obtain a data volume ratio corresponding to a plurality of failed bit numbers; the failed bit number indicates that the number of bits obtained by performing a read operation on a storage space of a preset size is different from the number of bits of data written to the storage space of the preset size; Activating the LDPC decoding function of the main control chip and performing a read operation on the storage medium to obtain decoding failure probabilities corresponding to multiple numbers of failed bits; Whether the LDPC decoding capability of the main control chip meets the decoding requirements of the storage medium is determined according to the data volume ratio corresponding to the multiple failure bit numbers and the decoding failure probability corresponding to the multiple failure bit numbers.

2. The LDPC decoding capability test application method according to claim 1, wherein: The storage medium includes a plurality of storage blocks; and the test platform performs a read operation on the storage medium to obtain a data volume ratio corresponding to a plurality of failed bit numbers, including: Performing a read operation on storage blocks corresponding to different preset erase and write times through a test platform to obtain read data volumes of multiple failed bit numbers under different preset erase and write times; According to the read data volume and the total data volume of the multiple failed bit numbers under each of the preset erasure times, the data volume ratio corresponding to the multiple failed bit numbers under each of the preset erasure times is obtained.

3. The LDPC decoding capability test application method according to claim 2, wherein: The determining, based on the data volume ratio corresponding to the multiple numbers of failed bits and the decoding failure probability corresponding to the multiple numbers of failed bits, whether the LDPC decoding capability of the main control chip meets the decoding requirements of the storage medium includes: Determining the maximum number of failed bits among the multiple numbers of failed bits under all the preset erasure times as the target number of failed bits; When the product of the data volume ratio corresponding to the target number of failure bits and the decoding failure probability corresponding to the target number of failure bits is less than a preset value, it is determined that the LDPC decoding capability of the main control chip meets the decoding requirements of the storage medium; When the product of the data volume ratio corresponding to the target number of failure bits and the decoding failure probability corresponding to the target number of failure bits is not less than the preset value, it is determined that the LDPC decoding capability of the main control chip does not meet the decoding requirements of the storage medium.

4. The LDPC decoding capability test application method according to claim 1, wherein: The enabling of the LDPC decoding function of the main control chip and performing a read operation on the storage medium to obtain decoding failure probabilities corresponding to multiple numbers of failed bits include: Decoding the data read from the storage medium using the LDPC decoding function to obtain decoding information; the decoding information includes a plurality of failure bit numbers and a number of soft decoding successes and a number of soft decoding failures corresponding to each of the failure bit numbers; According to the number of soft decoding successes and the number of soft decoding failures corresponding to each number of failed bits, a decoding failure probability corresponding to each number of failed bits is obtained.

5. The LDPC decoding capability test application method according to claim 4, characterized in that: The number of successful soft decodings includes the number of successful 1-bit decodings, the number of successful 2-bit decodings, and the number of successful 3-bit decodings. Obtaining a decoding failure probability corresponding to each number of failure bits according to the number of soft decoding successes and the number of soft decoding failures corresponding to each number of failure bits includes: For each of the failed bit numbers, determine the number of 1-bit decoding failures, the number of 2-bit decoding failures, and the number of 3-bit decoding failures corresponding to the failed bit number according to the number of 2-bit decoding successes, the number of 3-bit decoding successes, and the number of soft decoding failures corresponding to the failed bit number; Determine a 1-bit decoding failure probability corresponding to the number of failed bits according to the number of 1-bit decoding successes and the number of 1-bit decoding failures corresponding to the number of failed bits; Determine a 2-bit decoding failure probability corresponding to the number of failed bits according to the number of 2-bit decoding successes and the number of 2-bit decoding failures corresponding to the number of failed bits; Determine a 3-bit decoding failure probability corresponding to the number of failed bits according to the number of 3-bit decoding successes and the number of 3-bit decoding failures corresponding to the number of failed bits; The decoding failure probability corresponding to the number of failed bits is determined according to the 1-bit decoding failure probability, the 2-bit decoding failure probability, and the 3-bit decoding failure probability corresponding to the number of failed bits.

6. The LDPC decoding capability test application method according to claim 5, characterized in that: The determining, based on the 2-bit decoding success number, the 3-bit decoding success number, and the soft decoding failure number corresponding to the number of failed bits, the number of 1-bit decoding failures, the number of 2-bit decoding failures, and the number of 3-bit decoding failures, includes: Determine the number of 1-bit decoding failures corresponding to the number of failed bits according to the number of 2-bit decoding successes corresponding to the number of failed bits, the number of 3-bit decoding successes, and the number of soft decoding failures; Determine the number of 2-bit decoding failures corresponding to the number of failed bits according to the number of 3-bit decoding successes corresponding to the number of failed bits and the number of soft decoding failures; The number of soft decoding failures corresponding to the number of failed bits is determined as the number of 3-bit decoding failures corresponding to the number of failed bits.

7. An LDPC decoding capability test application device, characterized in that: Applied to a storage device, the storage device includes a main control chip and a storage medium, and the apparatus includes: An access module is configured to perform a read operation on the storage medium through a test platform to obtain a data volume ratio corresponding to a plurality of failed bit numbers; the failed bit number indicates a number of bits that differ between data obtained by a read operation on a storage space of a preset size and data written to the storage space of the preset size; enable an LDPC decoding function of the main control chip, perform a read operation on the storage medium, and obtain a decoding failure probability corresponding to the plurality of failed bit numbers; The processing module is used to determine whether the LDPC decoding capability of the main control chip meets the decoding requirements of the storage medium according to the data volume ratio corresponding to the multiple failure bit numbers and the decoding failure probability corresponding to the multiple failure bit numbers.

8. A storage device, characterized in that: The invention comprises a main control chip and a flash memory chip, wherein the flash memory chip stores a computer program that can be executed by the main control chip, and the main control chip can execute the computer program to implement the LDPC decoding capability test application method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the main control chip, the LDPC decoding capability test application method according to any one of claims 1 to 6 is implemented.

10. A program product, characterized in that When the program product is executed by the main control chip, the LDPC decoding capability test application method according to any one of claims 1 to 6 is implemented.

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