TVS low-voltage chip and preparation method thereof

Abstract

The invention discloses a TVS (Transient Voltage Suppressor) low-voltage chip and a preparation method thereof, relates to the technical field of semiconductor device manufacturing, and particularly relates to a preparation method for generating an oxide layer by optimizing each process link, especially an interface structure, and adopting a dry oxygen oxide layer and hydrochloric acid mixed solution high-temperature treatment. And a multi-layer protection structure consisting of the compact oxide layer, the glass layer, the LTO layer, the nickel layer and the gold layer is constructed, so that the leakage current during low-voltage working is effectively reduced, the breakdown voltage is greatly improved, and the stability and the reliability of the device are enhanced. The prepared TVS chip not only can quickly respond to transient overvoltage and clamp the voltage to a safe level to provide reliable protection for a low-voltage circuit, but also can realize efficient heat dissipation by virtue of the heat conductivity of the glass layer, meet the protection requirement of a vehicle-gauge-level circuit, expand the application range of a product and have remarkable practical value.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a TVS low-voltage chip and a preparation method thereof. Background Art

[0002] With the continuous miniaturization and intelligence of electronic devices, as well as the increasing demand for energy efficiency, low-voltage circuits have been widely used in various electronic products. From everyday smartphones and tablets to sensors and controllers in industrial automation and various low-voltage modules in automotive electronic systems, the stable operation of low-voltage circuits is crucial to the performance and reliability of the entire device.

[0003] In low-voltage circuits, transient overvoltages are a common and potentially dangerous problem. These overvoltages can be caused by a variety of factors, including lightning induction, power switching transients, and electrostatic discharge. If the resulting high voltages are not promptly and effectively suppressed, they can damage sensitive components within the circuit, potentially causing failure of the entire electronic device. Therefore, efficient and reliable voltage protection components have become an indispensable component in low-voltage circuit design.

[0004] TVS (transient voltage suppressor diode), as a commonly used voltage protection device, plays a key role in dealing with transient overvoltage. However, existing TVS products have exposed many problems that need to be solved when applied to low-voltage 5V-12V circuits. For example: ① Electrical performance bottleneck. The leakage current of existing products generally exceeds 150μA at an operating voltage of ≤5.2V, and the highest can even reach 300μA. This is due to the high state density at the PN junction interface, the decrease in carrier mobility, and the accumulation of interface charges between the heavily doped substrate and the epitaxial layer to form additional leakage channels; ② Insufficient environmental adaptability. In a humid and hot environment, the passivation layer and the silicon interface in existing products are prone to electrochemical corrosion, resulting in a serious drop in breakdown voltage. In addition, reverse bias failure occurs at high temperatures, and the leakage current increases significantly under long-term operation. Therefore, an innovative design is urgently needed to break through the limitations of existing technology. Summary of the Invention

[0005] In view of this, an object of the present invention is to provide a TVS low-voltage chip and a preparation method thereof.

[0006] The object of the present invention is achieved through the following technical solutions:

[0007] <First Aspect>

[0008] The present invention provides a TVS low-voltage chip, comprising:

[0009] A sandwich structure consisting of a P-type substrate and conductive layers covering the upper and lower sides of the P-type substrate, at least one of the two conductive layers being of N-type conductivity;

[0010] A trench is provided at the edges of the N-type conductive layer, wherein the bottom of the trench extends into the P-type substrate layer, and the bottom of the trench gradually deepens from the center toward the periphery, and the sidewalls of the trench gradually deepen toward the center of the conductive layer when viewed from the P-type substrate toward the outer layer;

[0011] an oxide layer covering the mesa edge region and the surface of the trench region of the N-type conductive layer;

[0012] A glass layer covers the oxide layer from the sidewalls of the groove to the edge of the mesa, wherein the oxide layer covered by the glass layer has a scribe line, which can solve the reliability risk caused by glass cracks caused by scribe glass;

[0013] An LTO layer covering an area of ​​the oxide layer not covered by the glass layer;

[0014] A nickel-gold layer covers the non-oxidation layer-covered areas on the two conductive layers.

[0015] In some embodiments, the TVS low-voltage chip uses a P-type substrate as the middle layer, and the upper and lower sides have symmetrical structures.

[0016] In some embodiments, both of the two conductive layers are N-type doped regions.

[0017] In some embodiments, the TVS low-voltage chip uses a P-type substrate as the middle layer, and the upper and lower sides have asymmetrical structures.

[0018] In some embodiments, the two conductive layers are an N-type doped region and a P-type main extension region.

[0019] In some embodiments, the outer side of the P-type main expansion region is covered with a nickel-gold layer.

[0020] As an embodiment, the thickness of the P-type substrate is 240 to 300 μm, and the resistivity is 0.0010 to 0.0050 Ω·cm.

[0021] In some embodiments, the P-type substrate has a thickness of 275-300 μm.

[0022] As an embodiment, the thickness of the conductive layer is 0.3 μm to 40 μm.

[0023] As an embodiment, the thickness of the N-type doping region is 0.3-20 μm.

[0024] In some embodiments, the thickness of the N-type doping region is 16 μm.

[0025] As an embodiment, the thickness of the P-type main extension region is 20 μm to 40 μm.

[0026] In some embodiments, the thickness of the P-type main extension region is 25 μm.

[0027] As an embodiment, the groove has a depth of 50 μm to 70 μm and a width of 230 μm to 300 μm.

[0028] In some embodiments, the groove has a depth of 50 μm to 55 μm and a width of 230 μm to 240 μm.

[0029] As an embodiment, the thickness of the oxide layer is

[0030] In some embodiments, the oxide layer has a thickness of

[0031] As an embodiment, the oxide layer on the mesa of the TVS low-voltage chip is in the shape of a rounded rectangular ring with a ring edge width of 10 μm to 100 μm.

[0032] In some embodiments, the ring edge width is 20 μm to 30 μm.

[0033] As an embodiment, the glass layer has a thickness of 8 μm to 12 μm.

[0034] In some embodiments, the glass layer has a thickness of 10 μm.

[0035] As an embodiment, the height of the glass layer from the bottom of the groove is 50 μm to 70 μm.

[0036] In some embodiments, the height of the glass layer from the bottom of the groove is 50 μm to 55 μm.

[0037] As an embodiment, the thickness of the LTO layer is 500 μm to 2500 μm.

[0038] As an embodiment, the nickel-gold layer has a structure of nickel inside and gold outside, the nickel layer has a thickness of 0.3 to 0.8 μm, and the gold layer has a thickness of 0.3 to 0.5 μm.

[0039] In some embodiments, the nickel layer has a thickness of 0.4 μm, and the gold layer has a thickness of 0.4 μm.

[0040] As an embodiment, the LTO layer and the glass layer contact each other to form a transition zone, and the connection position between the two is such that the glass layer is at the bottom and the LTO layer is at the top.

[0041] As an embodiment, the length of the transition zone is 10 μm to 100 μm.

[0042] As an embodiment, the TVS low voltage chip size is 30 to 600 mil.

[0043] In some embodiments, the TVS low voltage chip size is 70 mil.

[0044] <Second Aspect>

[0045] The present invention provides a method for preparing a TVS low-voltage chip, comprising the following steps:

[0046] First, a conductive layer and a dry oxygen oxide layer are provided on both sides of a P-type substrate, respectively, to obtain a five-layer structure of dry oxygen oxide layer-conductive layer-P-type substrate-conductive layer-dry oxygen oxide layer, at least one of the conductive layers is an N-type doped region, and at most one of the conductive layers is a P-type main extension region;

[0047] Second, trench etching is performed on the surface of the dry oxygen oxide layer on the N-type doped region side;

[0048] Third, performing oxidation treatment on the surface of the dry oxygen oxide layer and the groove to obtain an oxide layer integrated with the dry oxygen oxide layer;

[0049] Fourth, a glass layer is formed on the groove bottom glass edge region and the table glass edge region on the oxide layer on one side of the N-type doped region to obtain a chip having a cover glass layer on the oxide layer;

[0050] Fifth, a low-temperature oxidation process is performed to obtain a chip in which the LTO layer is covered on the oxide layer in the non-glass layer area;

[0051] Sixth, etch out the lead hole, etching in the middle area of ​​the LTO layer until the adjacent conductive layer is exposed;

[0052] Seventh, a nickel-gold layer is prepared on the conductive layer not covered by the oxide layer.

[0053] As an embodiment, the N-type doping region is formed by first performing N-type doping on the surface of a P-type substrate and then performing a main expansion process.

[0054] In some embodiments, the N-type doping is performed by high-temperature decomposition of phosphorus oxychloride at 1000-1200° C. in an atmosphere of 0.5-1 L / min oxygen and 1.5-4 L / min nitrogen to dope P atoms into the P-type substrate.

[0055] In some embodiments, the main expansion process is performed at 1100-1280° C. in an atmosphere of 2-3 L / min nitrogen and 3 L / min oxygen.

[0056] As an implementation scheme, the preparation steps of the P-type main expansion zone are: first, the back side of the P-type substrate to be doped with N-type is sandblasted and cleaned to remove the pre-expansion zone on the back side, and then a boron latex source is applied to the back side, and the main expansion treatment is performed after baking at 180-200°C for 15-30s.

[0057] As an embodiment, the trench etching steps are: obtaining a trench pattern by photolithography in one step and removing the oxide layer on the trench area; etching to open the trench; and removing the photoresist.

[0058] In some embodiments, the etching to form the grooves is performed by immersing the sample after the first photolithography in a second mixed acid solution for etching, wherein the second mixed acid solution is prepared according to a mass ratio of nitric acid: hydrofluoric acid: glacial acetic acid = 5:4:4.

[0059] As an embodiment, the oxidation treatment is as follows: placing the chip after groove etching in a constant temperature zone of 600-1200°C, heating the hydrochloric acid mixture to 90-99°C, then connecting a water bath to the constant temperature zone with a gas pipe, introducing 2L-6L / min of oxygen to generate a wet oxygen oxide layer, and finally introducing 2L-6L / min of nitrogen.

[0060] In some embodiments, the hydrochloric acid solution is a mixed liquid of hydrochloric acid and water in a volume ratio of 1:5.

[0061] In some embodiments, the oxidation treatment is as follows: placing the chip after groove etching in a constant temperature zone of 1150°C, heating the hydrochloric acid mixture to 95°C, then connecting the water bath to the constant temperature zone with a gas pipe, passing 5L / min of oxygen for 90 minutes to generate a wet oxygen oxide layer, and finally passing 5L / min of nitrogen for 30 minutes.

[0062] As an embodiment, the preparation steps of the glass layer are: using photoresist to photoetch the dicing lanes, the glass edge area at the bottom of the groove and the glass edge area at the table, and then at 570-830°C, first introduce nitrogen at 10L / min for 2 minutes to burn off the photoresist on the chip surface, and then use oxygen at 3-7L / min for 90 minutes to passivate the glass to form a uniform and dense glass layer.

[0063] As an embodiment, the photoresist is made of negative photoresist and glass powder.

[0064] In some embodiments, the photoresist is made of negative photoresist and glass powder in a mass ratio of 10:9.5.

[0065] As an embodiment, the step of the low-temperature oxidation treatment is: placing the chip after the treatment in the fourth step in air at 360-500° C. for oxidation treatment.

[0066] In some embodiments, the temperature of the low temperature oxidation treatment is 430°C.

[0067] As an embodiment, the step of etching the lead hole is: performing photolithography three times on the surface of the LTO layer, then using wet etching to sequentially remove the LTO layer and the oxide layer corresponding to the lead hole area, and finally removing the photoresist.

[0068] In some embodiments, the wet etching is performed by immersing the chip after three photolithography steps in an ammonium fluoride etching solution to remove the LTO layer and the oxide layer corresponding to the lead hole area.

[0069] In some embodiments, the photoresist is removed by immersing the chip in sulfuric acid (with a concentration of 98%) at 70 to 120° C. for 30 to 60 minutes to remove the photoresist on the chip surface; and then ultrasonic cleaning is performed using deionized water.

[0070] As an embodiment, the preparation steps of the nickel-gold layer include two steps: nickel plating treatment, alloy treatment and back gold treatment.

[0071] As an embodiment, the nickel plating is performed by electroplating or chemical plating.

[0072] In some embodiments, the nickel plating process adopts chemical nickel plating, the plating solution components include nickel chloride, ammonium chloride, diammonium hydrogen citrate, citric acid, and sodium hypophosphite, and the plating temperature is 87-97°C.

[0073] As an embodiment, the alloy treatment is as follows: treating the nickel-plated chip at 520-560° C., with a nitrogen flow of 20-30 L / min, for 25-35 min.

[0074] In some embodiments, the nickel layer in the nickel-gold layer is obtained by nickel plating and alloying, repeating the nickel plating and alloying, and then performing nickel plating again.

[0075] In some embodiments, the back-gold treatment is to place the chip in a gold chloride solution and immerse it at 90-100° C. to obtain a gold layer of 0.3-0.5 μm.

[0076] Compared with the prior art, the present invention has the following beneficial effects:

[0077] 1) This invention focuses on the field of low-voltage 5V-12V TVS low-voltage chips. By optimizing various links in the process, especially the interface structure, it successfully achieves effective reduction of leakage current during low-voltage operation, while significantly improving the breakdown voltage and having good stability and reliability. This enables the chip to provide reliable and efficient voltage protection, expand the product's application range, and enhance its practical value.

[0078] 2) In the preparation method of the TVS chip of the present invention, a dry oxygen oxide layer is first generated, which not only protects the wafer from external impurity contamination, but also ensures good spreading and wetting of the photoresist during the first photolithography, and prevents the chip from deforming in the corrosion groove; subsequently, a hydrochloric acid mixture is used to grow the oxide layer at a high temperature, so that after the interface between the substrate surface and the silicon dioxide is treated with hydrochloric acid, defects and impurity accumulation at the interface can be reduced, thereby improving the electrical performance of the TVS low-voltage device, such as reducing leakage current and improving breakdown voltage stability.

[0079] 3) The TVS chip prepared by the present invention adopts a multi-layer protection structure of a dense oxide layer, a glass layer, an LTO layer, a nickel layer, and a gold layer, and adds a glass layer with scribe lines for protection. This glass layer cooperates with the oxide layer, etc. to improve the stability and reliability of the chip in different temperature environments, and relies on the thermal conductivity of the glass layer to help the chip dissipate heat efficiently, prevent performance degradation caused by overheating, and provide physical protection against potential damage such as external collisions and extrusion; and the glass layer with scribe lines effectively reduces leakage current during low-voltage operation, and can also respond quickly to transient overvoltages and clamp the voltage at a safe level, thereby providing a reliable and efficient voltage protection solution for low-voltage circuits and meeting automotive-grade circuit protection requirements.

[0080] 4) TVS chips are made from heavily doped raw materials. The conventional fabrication process involves adding a SIPOS passivation layer, which makes it easier for charges at the interface to interact with internal carriers, creating additional leakage paths and resulting in excessive leakage. This application, however, does not include a SIPOS layer, thus avoiding this issue. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] Other features, objects and advantages of the present invention will become more apparent upon reading the detailed description of non-limiting embodiments with reference to the following drawings:

[0082] Figure 1 Schematic diagram of the substrate sheet used in Examples 3 and 4 of the present invention;

[0083] Figure 2 The double-sided oxidation structure after the main expansion in Examples 3 and 4 of the present invention, wherein (a) corresponds to Example 3, and (b) corresponds to Example 4;

[0084] Figure 3 Schematic diagrams of the chips with grooves prepared in Examples 3 and 4 of the present invention, wherein (a) corresponds to Example 3, and (b) corresponds to Example 4;

[0085] Figure 4 Schematic diagram of the chip after oxidation in Examples 3 and 4 of the present invention, wherein (a) corresponds to Example 3, and (b) corresponds to Example 4;

[0086] Figure 5 Schematic diagrams of chips covered with a glass layer in Examples 3 and 4 of the present invention, wherein (a) corresponds to Example 3, and (b) corresponds to Example 4;

[0087] Figure 6 Schematic diagrams of chips depositing LTO layers in Examples 3 and 4 of the present invention, wherein (a) corresponds to Example 3, and (b) corresponds to Example 4;

[0088] Figure 7 Schematic diagram of the chip after step S20 in Examples 3 to 4 of the present invention, wherein (a) corresponds to Example 3, and (b) corresponds to Example 4;

[0089] Figure 8 Schematic diagrams of TVS devices in Examples 3 and 4 of the present invention, wherein (a) corresponds to Example 3, and (b) corresponds to Example 4;

[0090] Figure 9 These are the VRB test results of the TVS devices in Examples 3 and 4 of the present invention, where (a) corresponds to the breakdown voltage of Example 3, (b) corresponds to the breakdown voltage of Example 4, (c) corresponds to the leakage current of Example 3, and (d) corresponds to the leakage current of Example 4. DETAILED DESCRIPTION

[0091] The present invention is described in detail below with reference to the examples. The following examples will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that those skilled in the art may make several adjustments and improvements without departing from the scope of the present invention. These all fall within the scope of protection of the present invention.

[0092] It should be noted that the size of the TVS low-voltage chip prepared in this specific embodiment is 70 mil.

[0093] Example 1

[0094] This embodiment provides a P-type bidirectional symmetrical TVS low-voltage chip, including:

[0095] The sandwich structure consists of a P-type substrate and N-type doped regions located on the upper and lower sides of the P-type substrate;

[0096] The grooves are arranged on the four edges of the sandwich structure, with the bottom located in the P-type substrate layer, and the bottom of the grooves gradually deepens from the inside to the outside;

[0097] The nickel-gold layer has an inner layer of nickel and an outer layer of gold, and is located in the central area of ​​the outer surface of the N-type doped region;

[0098] an oxide layer disposed on the outer region adjacent to the central region and on the surface of the groove region;

[0099] A glass layer covers the oxide layer and is located on the sidewalls of the trench to the edge of the N-type doped region mesa;

[0100] The LTO layer covers the oxide layer except for the area covered by the glass layer.

[0101] Furthermore, the LTO layer and the glass layer contact each other to form a transition zone, and the connection position between the two is such that the glass layer is at the bottom and the LTO layer is at the top.

[0102] In this embodiment, the TVS chip uses a P-type substrate as the middle layer, and the upper and lower sides have symmetrical structures.

[0103] In this embodiment, the TVS device size is 70 mil, the substrate layer thickness is 300 μm, the resistivity is 0.050 Ω·cm; the N-type doping region thickness is 16 μm; the trench depth is 50 μm to 55 μm, the width is 230 μm to 240 μm; the oxide layer thickness is The thickness of the table glass layer is 10 μm; the width of the LTO layer is 20 μm to 30 μm; the thickness of the nickel layer in the nickel-gold layer is 0.4 μm, and the thickness of the gold layer is 0.4 μm.

[0104] Example 2

[0105] This embodiment provides a P-type unidirectional symmetrical TVS low-voltage chip, including:

[0106] The sandwich structure consists of a P-type substrate, an N-type doped region on the upper side of the P-type substrate, and a P-type main expansion region on the lower side of the P-type substrate.

[0107] The groove is provided on the four edges of the upper side of the sandwich structure, with the bottom located on the P-type substrate layer, and the bottom of the groove gradually deepens from the inside to the outside;

[0108] The nickel-gold layer has an inner layer of nickel and an outer layer of gold, and is provided in the central area of ​​the outer surface of the N-type doped region and the surface of the P-type main expansion region;

[0109] an oxide layer, a portion of which is disposed on the surface of the outer region and the trench region adjacent to the central region, and another portion of which covers the outer surface of the P-type main expansion region;

[0110] A glass layer covers the oxide layer and is located on the sidewalls of the trench to the edge of the N-type doped region mesa;

[0111] The LTO layer covers the oxide layer except for the area covered by the glass layer.

[0112] Furthermore, the LTO layer and the glass layer contact each other to form a transition zone, and the connection position between the two is such that the glass layer is at the bottom and the LTO layer is at the top.

[0113] In this embodiment, the TVS chip uses a P-type substrate as the middle layer, but the upper and lower sides of the chip are not symmetrical.

[0114] In this embodiment, the TVS device size is 70 mil, the substrate layer thickness is 275 μm, and the resistivity is 0.050 Ω·cm; the N-type doping region thickness is 16 μm, and the P-type main expansion region thickness is 25 μm; the trench depth is 50 μm to 55 μm, and the width is 230 μm to 240 μm; the thickness of the upper oxide layer is The thickness of the lower oxide layer is 6000; the thickness of the table glass layer is 10 μm; the width of the LTO layer is 20 μm to 30 μm; the thickness of the nickel layer in the nickel-gold layer is 0.4 μm, and the thickness of the gold layer is 0.4 μm.

[0115] Example 3

[0116] A method for preparing a P-type bidirectional symmetrical structure TVS low-voltage chip using an NPG manufacturing process, comprising the following steps:

[0117] S1. Silicon wafer inspection

[0118] Take a 5-inch P-type substrate (a P-type substrate in this embodiment), with a thickness of 240 to 320 μm (300 μm in this embodiment) and a resistivity of 0.0010 to 0.0050 Ω·cm (0.0050 Ω·cm in this embodiment), as shown in FIG. Figure 1 shown.

[0119] S2, surface acid corrosion

[0120] Prepare a first mixed acid solution according to the mass ratio of nitric acid: hydrofluoric acid: glacial acetic acid = 18:1:1, and prepare a hydrofluoric acid solution according to the mass ratio of hydrofluoric acid: pure water = 1:1;

[0121] First, the substrate in step S1 is immersed in the first mixed acid solution at room temperature for 25 to 35 seconds (30 seconds in this embodiment) to remove the damaged layer on the substrate surface; then the substrate is immersed in a hydrofluoric acid solution at room temperature of 25±5°C for 2 to 4 minutes (3 minutes in this embodiment) to remove the silicon powder and oxide layer on the substrate surface.

[0122] S3, pre-expansion processing

[0123] Prepare SC1 solution at a mass ratio of ammonium hydroxide: hydrogen peroxide: deionized water = 1:2:9.2, and prepare SC2 solution at a mass ratio of hydrochloric acid: hydrogen peroxide: deionized water = 1:2:9.2;

[0124] First, the substrate treated in step S2 is immersed in SC1 solution at 50-60°C (55°C in this embodiment) for 9-11 minutes (10 minutes in this embodiment) to remove organic pollutants and impurities on the substrate surface; then the substrate is immersed in SC2 solution at 45-65°C (55°C in this embodiment) for 9-11 minutes (10 minutes in this embodiment) to remove metal ions on the substrate surface.

[0125] S4, pre-expansion processing

[0126] Use diffusion equipment and materials to perform N-type doping on both sides of the S3-treated substrate;

[0127] The diffusion equipment is a high-temperature furnace and a quartz tube, and the materials are oxygen, nitrogen and phosphorus oxychloride;

[0128] The process conditions are as follows: diffusion temperature 1000-1200°C (1150°C in this embodiment), time 6-8 hours (7 hours in this embodiment), nitrogen 1.5-4 L / min (4 L / min in this embodiment), oxygen 0.5-1 L / min (0.7 L / min in this embodiment);

[0129] A substrate in which N-doping is performed on the upper and lower sides of a P-type substrate is obtained.

[0130] S5, pre-expansion post-processing

[0131] Prepare hydrofluoric acid solution by mixing hydrofluoric acid and water in a mass ratio of 1:1;

[0132] The substrate after the S4 treatment is cleaned with a hydrofluoric acid solution for 8 to 12 minutes (10 minutes in this embodiment) to remove surface diffusion source impurities and diffusion reaction byproducts.

[0133] S6, pre-expansion test

[0134] Test the sheet resistance of pre-expanded silicon wafers.

[0135] When the tested substrate resistance is 250 mΩ / □ to 450 mΩ / □, proceed to the next step.

[0136] In this embodiment, the sheet resistance of the substrate after the S5 process is 420 mΩ / □.

[0137] S7, main expansion pre-processing

[0138] Prepare SC1 solution and SC2 solution again, as shown in step S3;

[0139] The substrate that has passed the S6 inspection is immersed in SC1 solution at 50-60°C (55°C in this embodiment) for 9-11 minutes (10 minutes in this embodiment) to remove organic pollutants and impurities on the substrate surface; then the substrate is immersed in SC2 solution at 45-65°C (55°C in this embodiment) for 9-11 minutes (10 minutes in this embodiment) to remove metal ions on the substrate surface.

[0140] S8. Main expansion process (also referred to as dry oxygen oxidation process in this embodiment)

[0141] Use diffusion equipment and materials to perform main diffusion treatment on the surface of the substrate after S7 treatment;

[0142] The diffusion equipment is a high-temperature furnace and silicon carbide tube, and the materials are oxygen and nitrogen;

[0143] Process conditions: in a furnace tube at 1100-1280° C. (1250° C. in this embodiment), nitrogen 2-3 L / min, oxygen 3 L / min, main expansion to the corresponding cut-off voltage (6.5 V in this embodiment).

[0144] After the step S8, an ONPNO double-sided oxidation structure is obtained, in which N-type doping regions are covered on the upper and lower sides of the P-type substrate, and a dense dry oxygen oxide layer is covered on the surface of the N-type doping region (O represents the dry oxygen oxide layer, N represents the N-type doping region, and P represents the P-type substrate). Figure 2 As shown in (a).

[0145] S9, one-shot lithography

[0146] After the double-sided oxidation structure is processed in step S8, a trench pattern is formed by photolithography on both sides, and the oxide layer on the trench area is removed;

[0147] Process parameters: photoresist thickness 8±3 μm, exposure light intensity 12 mW-20 mW (13 mW in this embodiment), development time 9 min, rinse time 6 min, ammonium fluoride etching solution (reagent grade in this embodiment) temperature 40±2° C., etching time 6 min;

[0148] The equipment involved includes glue coating machine, double-sided exposure machine, developer and rinse machine, oxide layer etching machine, and the materials involved include photoresist, developer, rinse solution, and ammonium fluoride etching solution.

[0149] S10, open the chip in the corrosion groove

[0150] Prepare a second mixed acid solution according to the mass ratio of nitric acid: hydrofluoric acid: glacial acetic acid = 5:4:4;

[0151] The double-sided oxidized structure after step S9 is immersed in the second mixed acid solution for 0.5-10 minutes (340 seconds in this embodiment) to etch the silicon surface without photoresist protection to open a groove. The target depth of the groove is 50μm to 55μm. In this embodiment, the depth of the groove exceeds the PN junction by 15μm, forming a chip prototype.

[0152] S11. Remove photoresist

[0153] First, the chip treated in step S10 is immersed in sulfuric acid (concentration of 98%) at 70-120° C. (95° C. in this embodiment) for 45 minutes to remove the photoresist on the chip surface; then immersed in hydrogen peroxide for 0.8-1.2 minutes (1 minute in this embodiment); then ultrasonically cleaned with deionized water for 30 minutes; finally, immersed in ammonium fluoride etching solution (reagent grade in this embodiment) for 20 seconds.

[0154] The obtained chip is Figure 3 As shown in (a).

[0155] S12, acid corrosion groove

[0156] Prepare the first mixed acid solution and hydrofluoric acid solution according to step S2;

[0157] The chip treated in step S11 is immersed in the first mixed acid solution at room temperature for 30 to 60 seconds (45 seconds in this embodiment) to remove the surface damage layer; then the chip is immersed in hydrofluoric acid solution at room temperature for 3 minutes to remove the surface oxide layer and silicon powder.

[0158] After the S12 step, a chip with grooves and no oxide layer structure on both sides is obtained. Figure 2 As shown in (a), the bottom of the trench is located in the P-type substrate layer.

[0159] S13, RCA cleaning

[0160] Prepare SC1 solution and SC2 solution, as shown in step S3;

[0161] The chip treated in step S12 is immersed in SC1 solution at 50-60°C (55°C in this embodiment) for 9-11 minutes (10 minutes in this embodiment) to remove organic pollutants and impurities on the chip surface and grooves; then the substrate is immersed in SC2 solution at 45-65°C (55°C in this embodiment) for 9-11 minutes (10 minutes in this embodiment) to remove metal ions on the chip surface and grooves.

[0162] S14, oxidation

[0163] The chip processed in step S13 is subjected to oxidation treatment, involving equipment including a high-temperature furnace and a quartz tube, and materials including oxygen, nitrogen and hydrochloric acid solution (the hydrochloric acid solution is a mixed liquid of hydrochloric acid and water in a volume ratio of 1:5);

[0164] The chip is placed in a quartz tube constant temperature zone at 600-1200°C (1150°C in this embodiment), and the hydrochloric acid mixture is heated to 90-99°C (95°C in this embodiment) in a water bath. The water bath is then connected to the quartz tube with a gas pipe, and oxygen is introduced at 2L-6L / min (5L / min in this embodiment) to generate a wet oxygen oxide layer for 90 minutes. Finally, nitrogen is introduced at 2L-6L / min (5L / min in this embodiment) for 30 minutes to form a wet oxygen oxide layer. dense oxide layer (in this embodiment, the thickness of the dense oxide layer is ).

[0165] The chip after step S14 is as follows Figure 4 It should be noted that the dry oxygen oxidation layer is further oxidized to obtain an integrated oxidation layer.

[0166] S15, secondary lithography

[0167] Prepare photoresist according to the mass ratio of negative photoresist: glass powder = 10:9.5, wherein the negative photoresist uses RFJ-210-450 photoresist and the glass powder particle size is 5-14μm. Stir the two materials for 24 hours to mix them evenly before use;

[0168] Use photoresist to photoetch the dicing lines (the width of all dicing lines on the chip in this embodiment is 70μm~80μm), the bottom glass edge area and the table glass edge area on the chip after processing in step S14. The photolithography equipment involved includes a coating machine, a double-sided exposure machine and a spray development and rinsing machine. The materials involved include photoresist, developer and rinse solution; the process conditions are: photoresist thickness 12±5μm (14μm in this embodiment), exposure light intensity 12~20mW (12mW in this embodiment), spray development time 30±5s, and spray rinsing time 15±5s.

[0169] In this embodiment, the groove bottom glass edge area refers to the sidewall around the groove bottom, excluding the groove bottom; the table top glass edge area refers to the edge area of ​​the table top structure on the upper and lower sides of the chip, which is connected to the groove bottom glass edge area.

[0170] S16, Firing

[0171] After the chip is processed in step S15, nitrogen gas is first introduced at 570-830°C (820°C in this embodiment) for 2 minutes at a rate of 10 L / min to burn off the photoresist on the chip surface, and then oxygen gas is used at a rate of 3-7 L / min (5 L / min in this embodiment) for 90 minutes to perform glass passivation to form a uniform and dense glass layer.

[0172] The chip after step S16 is as follows Figure 5 As shown in (a), the groove bottom glass edge area and the table glass edge area on the upper and lower surfaces of the chip are covered with glass layers.

[0173] S17, low temperature oxidation treatment

[0174] The chip after step S16 is oxidized at 360-500°C (430°C in this embodiment) to form a thickness of (This embodiment is ) silicon dioxide film (LTO) is used to resist tin flowing into the glass edge area and external physical impact.

[0175] After the step S17, a chip with LTO layer covering the upper and lower surfaces of the chip except the glass layer area is obtained. Figure 6 As shown in (a).

[0176] S18, three-stage lithography

[0177] Photoetching lead hole areas on both the front and back sides of the chip processed in step S17;

[0178] Process parameters: photoresist thickness 12±3 μm (12 μm in this embodiment), exposure light intensity 12-20 mW (15 mW in this embodiment), development time 9 min, rinse time 6 min;

[0179] The equipment involved includes glue coating machine, single-sided exposure machine, developer and rinse machine, oxide layer etching machine, and the materials involved include photoresist, developer, and rinse solution.

[0180] The lead hole area is the middle area of ​​the mesa LTO layer.

[0181] S19, wet etching

[0182] Use ammonium fluoride etching solution (reagent grade in this embodiment) at 38-42° C. (40° C. in this embodiment) to soak for 5-7 minutes (7 minutes in this embodiment) to remove the unnecessary oxide layer and LTO layer on the chip mesa (i.e., the oxide layer and LTO layer in the lead hole area).

[0183] S20, remove photoresist

[0184] First, the chip treated in step S19 is immersed in sulfuric acid (concentration of 98%) at 70-120° C. (120° C. in this embodiment) for 45 minutes to remove the photoresist on the chip surface; then, it is ultrasonically cleaned with deionized water for 30 minutes.

[0185] The obtained chip has the oxide layer and LTO layer retained at the edge of the mesa, while the middle area of ​​the mesa is an N-type doped area, such as Figure 7 As shown in (a).

[0186] S21, Metallization

[0187] The chip after the processing in step S20 is subjected to nickel plating, and the process temperature is 87-97° C. (the temperature in this embodiment is 92° C.).

[0188] S22, alloy

[0189] The chip processed in step S21 is placed in a normal pressure furnace with a process temperature of 520-560°C (540°C in this embodiment), a time of 25-35 minutes (30 minutes in this embodiment), and a nitrogen flow of 20-30 L / min (25 L / min in this embodiment) to form good ohmic contact between silicon and metal.

[0190] S23. Repeated Metallization and Alloying

[0191] Repeat steps S21 and S21 once, and then repeat step S21 again, and the coating thickness is 0.3 to 0.8 μm (the thickness in this embodiment is 0.4 μm).

[0192] S24, back gold

[0193] The chip processed in step S23 is placed in a gold chloride solution for back-gold treatment at a process temperature of 90-100° C. (95° C. in this embodiment) to obtain a gold layer with a thickness of 0.3-0.5 μm (0.4 μm in this embodiment).

[0194] After the S24 step, a chip is obtained in which the middle of the mesa is an N-type doped area and the outer surface is covered with a nickel-gold layer. Figure 8 As shown in (a).

[0195] S25, test cutting

[0196] Inspect the performance of the die, cut and separate the chips, and select good products for packaging.

[0197] Example 4

[0198] This embodiment provides a method for preparing a P-type unidirectional symmetrical TVS low-voltage chip using an NPG manufacturing process. The steps are basically the same as those in Example 1, except that:

[0199] In step S4, the process conditions are the same, but N-type doping is performed only on the front side of the P-type substrate.

[0200] In step S6, the sheet resistance of the substrate is 350 mΩ / □.

[0201] After step S6 and before step S7, two steps of sandblasting and cleaning are added, specifically:

[0202] Sandblasting: Use diamond abrasive to remove the back of the P-type substrate, removing 20 to 30 μm of thickness (25 μm in this embodiment). The process parameters of sandblasting are belt speed 16.5 mm / s and sandblasting pressure 1.1 MPa.

[0203] Cleaning after sandblasting: Prepare hydrofluoric acid solution with hydrofluoric acid and water in a mass ratio of 1:1, and prepare alkaline cleaning solution with sodium hydroxide: deionized water = 4kg:20L;

[0204] First, the sandblasted substrate is placed in deionized water for ultrasonic cleaning for 30 minutes; then it is soaked in an alkaline cleaning solution at 45-55°C (50°C in this embodiment) for 5 minutes to remove the residual corundum on the substrate surface; and then it is soaked in a hydrofluoric acid solution for 4-6 minutes (5 minutes in this embodiment) to remove the alkaline solution and oxide layer on the substrate surface.

[0205] In step S8, a boron latex source is first evenly applied to the back of the substrate, and baked at 180-200° C. (200° C. in this embodiment) for 15-30 seconds (15 seconds in this embodiment), and then the main expansion process described in step S8 of Example 1 is performed. In this embodiment, the corresponding cutoff voltage is 6.5 V. For other references, refer to Example 1. After treatment, an ONPPO double-sided oxidation structure consisting of a dry oxygen oxide layer, an N-type doped region, a P-type substrate, a P-type main expansion region, and a dry oxygen oxide layer is obtained. Figure 2 (b) shown.

[0206] In step S9, a groove is photoetched on the front side of the double-sided oxidation structure processed in step S8, and the oxide layer on the groove is removed; the equipment, materials and process parameters refer to step S9 in Example 1, but the double-sided exposure machine in the equipment involved is replaced by a single-sided exposure machine.

[0207] After the substrate is processed in step S11, Figure 3 (b) shown.

[0208] The chip after step S14 is as follows Figure 4 (b) shown.

[0209] In step S15, scribe lines, groove bottom glass edge areas, and table glass edge areas are photoetched on the front side of the chip obtained in step S14, and the double-sided exposure machine in the equipment involved is replaced with a single-sided exposure machine.

[0210] In step S16, a uniform glass layer is formed on the glass edge area at the bottom of the groove and the glass edge area at the table top on the front side of the chip.

[0211] The chip after step S16 is as follows Figure 5 (b) shown.

[0212] The chip after step S17 is as follows Figure 6 (b) shown.

[0213] In step S18, the lead hole area is photoetched on the front side of the chip after the processing in step S17, but the double-sided exposure machine in the equipment involved is replaced with a single-sided exposure machine. After wet etching in step S19 and removing the photoresist in step S20, the chip is obtained in which the edge of the front mesa of the chip retains the oxide layer and the LTO layer, and the middle area of ​​the front mesa of the chip is an N-type doped area. Figure 7 (b) shown.

[0214] The chip after step S24 is as follows Figure 8 (b) shown.

[0215] Comparative Example 1

[0216] This comparative example provides a method for preparing a P-type unidirectional symmetrical TVS low-voltage chip using an NPG manufacturing process. The steps are basically the same as those in Example 1, except that:

[0217] In step S14, the oxidation step is replaced by:

[0218] The chip cleaned in step S13 was placed in the quartz tube constant temperature zone of a high temperature furnace, and 5L / min nitrogen and 5L / min oxygen were introduced to perform diffusion oxidation at 1150°C to generate Thickness of oxide layer.

[0219] Test Analysis

[0220] The TVS chips prepared in Example 1 and Example 2 were subjected to reliability tests using the GK-HTRB-C8 HTRB equipment. The cut-off voltage was 6.5V, covering six tests: high-temperature reverse bias test (HTRB), high-voltage accelerated aging test (PCT), reflow test (SR), temperature cycle test (TC), steady-state damp heat test (ST), and breakdown voltage test (VBR). The test conditions and test results are shown in Table 1, where ACC stands for qualified and NG stands for unqualified. It can be seen that the device did not show any defects under harsh conditions (the number of NGs was 0), and it has excellent stability and industrial-grade reliability, meeting the needs of surge protection scenarios. Specifically:

[0221] The long-term stability of TVS devices under high-temperature reverse bias was tested at 150°C with 100% reverse voltage for 168 hours. A total of 80 devices were tested, and the devices performed well under these conditions.

[0222] The device's internal potential defects and moisture resistance were evaluated at 121°C and a saturated vapor pressure of 0.11 MPa for 96 hours. The test results showed that the device has good stability in hot and humid environments.

[0223] The device's ability to withstand high soldering temperatures was evaluated at 260°C for 10 seconds. The results showed that the device can withstand high reflow temperatures.

[0224] The device was tested for reliability under drastic temperature changes by cycling 168 times between -55°C and 150°C, with each cycle lasting 30 minutes. The results showed that the device has a strong ability to adapt to temperature cycling.

[0225] The device's ability to withstand short-term high temperatures was tested at 245°C for 5 seconds. The results showed that the device performed stably under this high-temperature, short-term condition.

[0226] Under the conditions of reverse voltage of 7.25~7.95V and leakage current IR≤100μA, the device breakdown voltage range and leakage current were tested. The results showed that the device breakdown voltage and leakage current met the requirements.

[0227] Table 1

[0228]

[0229] The test results of the VBR test are as follows: Figure 9 (a) and Figure 9 (c) shown.

[0230] Breakdown voltage test: VBR1 represents the breakdown voltage in the direction of the chip marking surface, and VBR2 represents the breakdown voltage in the opposite direction. The breakdown voltage (VBR1 / 2) of Example 1 (hydrochloric acid-grown oxide layer) can be controlled within a maximum and minimum range of <0.1V, while the breakdown voltage (VBR1 / 2) of Comparative Example 1 (normally grown oxide layer) can be controlled within a maximum and minimum range of <0.4V. Compared to Comparative Example 1, the curves of VBR1 and VBR2 in Example 1 are relatively stable, with smaller fluctuations, which intuitively reflects the good stability of the TVS in terms of breakdown voltage and illustrates its consistency and reliability in voltage suppression performance.

[0231] Leakage current test: IR1 represents the leakage current in the direction of the marking surface, and IR2 represents the leakage current in the opposite direction. The actual test leakage current (IR1 / 2) of Example 1 (oxide layer grown by hydrochloric acid) can reach a level of <10uA, and the actual test leakage current (IR1 / 2) of Comparative Example 1 (oxide layer grown by ordinary means) can reach a level of <80uA. Relative to Comparative Example 1, the values ​​of IR1 and IR2 in Example 1 are very small as a whole, and the fluctuation range is very small, almost maintaining at a very low level, indicating that the leakage current of the TVS device is very small and stable. A small and stable leakage current means that the device has low power consumption under normal working conditions, has little impact on the circuit, can ensure stable operation of the circuit, and is not prone to additional interference or energy loss due to leakage current, reflecting that the TVS device performs well in terms of leakage current characteristics.

[0232] Example 1 and Comparative Example 1 Figure 9 (a) and Figure 9 (c) Test pairs such as Figure 9 (b) and Figure 9 As shown in (d), it can be seen that Figure 9 (a) and Figure 9 (c) The electrical uniformity of the oxide layer grown using hydrochloric acid is relatively excellent.

[0233] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art may make various variations or modifications within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A TVS low voltage chip, characterized in that: include: A sandwich structure consisting of a P-type substrate and conductive layers covering the upper and lower sides of the P-type substrate, at least one of the two conductive layers being of N-type conductivity; A trench is provided at the edges of the N-type conductive layer, wherein the bottom of the trench extends into the P-type substrate layer, and the bottom of the trench gradually deepens from the center toward the periphery, and the sidewalls of the trench gradually deepen toward the center of the conductive layer when viewed from the P-type substrate toward the outer layer; an oxide layer covering the mesa edge region and the surface of the trench region of the N-type conductive layer; a glass layer covering the sidewalls of the groove and the oxide layer extending to the edge of the mesa, wherein the oxide layer covered by the glass layer has a scribe line; An LTO layer covering an area of ​​the oxide layer not covered by the glass layer; A nickel-gold layer covers the non-oxidation layer-covered areas on the two conductive layers.

2. The chip according to claim 1, characterized in that It also includes one or more of the following technical features: A1. The TVS low-voltage chip has a P-type substrate as the middle layer, and the upper and lower sides are symmetrical; B1. Both of the conductive layers are N-type doped regions; C1. The TVS low-voltage chip uses a P-type substrate as the middle layer, and the upper and lower sides have asymmetrical structures; D1. The two conductive layers are an N-type doped region and a P-type main expansion region, and the outer side of the P-type main expansion region is covered with a nickel-gold layer.

3. The chip according to claim 1, characterized in that It also includes one or more of the following technical features: A2, the thickness of the oxide layer is B2. The oxide layer on the mesa of the chip is in the shape of a rounded rectangular ring with a ring edge width of 10 μm to 100 μm; C2, the thickness of the glass layer is 8 μm to 12 μm; D2, the height of the glass layer from the bottom of the groove is 50μm to 70μm; E2. The thickness of the LTO layer is 500 μm to 2500 μm; F2, the LTO layer and the glass layer are in contact with each other to form a transition zone, and the connection position between the two is such that the glass layer is at the bottom and the LTO layer is at the top. The length of the transition zone is 10 μm to 100 μm.

4. The chip according to claim 1, characterized in that A3. The thickness of the P-type substrate is 240 to 300 μm, and the resistivity is 0.0010 to 0.0050 Ω·cm; B3, the thickness of the conductive layer is 0.3 μm to 40 μm; C3, the groove depth is 50μm to 70μm, and the width is 230μm to 300μm; D3, the nickel-gold layer has a structure of inner nickel and outer gold, the nickel layer thickness is 0.3-0.8 μm, and the gold layer thickness is 0.3-0.5 μm; E3. The chip size is 30 to 600 mil.

5. A method for preparing a TVS low-voltage chip, characterized in that: The following steps are involved: First, a conductive layer and a dry oxygen oxide layer are provided on both sides of a P-type substrate, respectively, to obtain a five-layer structure of dry oxygen oxide layer-conductive layer-P-type substrate-conductive layer-dry oxygen oxide layer, at least one of the conductive layers is an N-type doped region, and at most one of the conductive layers is a P-type main extension region; Second, trench etching is performed on the surface of the dry oxygen oxide layer on the N-type doped region side; Third, performing oxidation treatment on the surface of the dry oxygen oxide layer and the groove to obtain an oxide layer integrated with the dry oxygen oxide layer; Fourth, a glass layer is formed on the groove bottom glass edge region and the table glass edge region on the oxide layer on one side of the N-type doped region to obtain a chip having a cover glass layer on the oxide layer; Fifth, a low-temperature oxidation process is performed to obtain a chip in which the LTO layer is covered on the oxide layer in the non-glass layer area; Sixth, etch out the lead hole, etching in the middle area of ​​the LTO layer until the adjacent conductive layer is exposed; Seventh, a nickel-gold layer is prepared on the conductive layer not covered by the oxide layer.

6. The preparation method according to claim 5, characterized in that The N-type doping region is formed by first performing N-type doping on the surface of a P-type substrate and then performing a main expansion process.

7. The preparation method according to claim 5, characterized in that The preparation steps of the P-type main expansion area are: first, the back side of the N-type doped P-type substrate is sandblasted and cleaned to remove the pre-expansion area on the back side, and then a boron latex source is applied to the back side, and the substrate is baked at 180-200°C for 15-30s before the main expansion process is performed.

8. The preparation method according to claim 5, characterized in that The oxidation treatment is as follows: placing the chip after groove etching in a constant temperature zone of 600-1200°C, heating the hydrochloric acid mixture to 90-99°C, then connecting a water bath to the constant temperature zone with a gas pipe, introducing 2L-6L / min of oxygen to generate a wet oxygen oxide layer, and finally introducing 2L-6L / min of nitrogen.

9. The preparation method according to claim 5, characterized in that The preparation steps of the glass layer are as follows: using photoresist to photoetch the dicing lanes, the bottom glass edge area and the table glass edge area, and then at 570-830°C, firstly introducing nitrogen gas at 10L / min for 2 minutes to burn off the photoresist on the chip surface, and then using oxygen gas at 3-7L / min for 90 minutes to passivate the glass to form a uniform and dense glass layer.

10. The preparation method according to claim 5, characterized in that The step of the low-temperature oxidation treatment is: placing the chip processed in the fourth step in air at 360-500° C. for oxidation treatment.

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