Asynchronous hardware state management method, electronic device, and medium

Abstract

The application relates to the chip technical field, in particular to an asynchronous hardware state management method, an electronic device and a medium, wherein the method sets a business pipeline and a register bus running in parallel, sets multiple register groups for each type of hardware state, executes a business data packet through the business pipeline, executes hardware state updating through the register bus and the register groups, and realizes synchronization and order preservation between the business pipeline and the register bus through an event data packet. The application reduces the situation that the hardware state updating blocks the execution of the business data packet, and improves the execution efficiency of the business data packet.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, and particularly to an asynchronous hardware state management method, an electronic device and a medium. BACKGROUND

[0002] When the software issues a service data packet, a hardware state update instruction is usually issued, and the service data packet is executed in different hardware states. In the prior art, the service data packet and the hardware state update instruction are usually issued to the same pipeline for serial execution, or the service data packet and the hardware state update are isolated and independently executed, but the execution of the service data packet needs to wait for the completion of the hardware state update. Since the hardware state update process may involve multiple hardware states and a large amount of data, the hardware state update occupies a long time, blocks the execution of the service data packet, and reduces the execution efficiency of the service data packet. Therefore, how to reduce the situation that the hardware state update blocks the execution of the service data packet and improve the execution efficiency of the service data packet becomes a technical problem to be solved. SUMMARY

[0003] The present application aims to provide an asynchronous hardware state management method, an electronic device and a medium, so that the hardware and the hardware state update and the execution of the service data packet are executed in parallel, and the execution efficiency of the service data packet is improved.

[0004] According to a first aspect of the present application, an asynchronous hardware state management method is provided, comprising:

[0005] Step S1, a current to-be-processed instruction is obtained, if the current to-be-processed instruction is a hardware state update instruction and the last to-be-processed instruction is a service execution instruction, step S2 is executed, if the current to-be-processed instruction is a hardware state update instruction and the last to-be-processed instruction is a hardware state update instruction, step S3 is executed, and if the current to-be-processed instruction is a service execution instruction, step S4 is executed.

[0006] Step S2, a to-be-updated hardware state identifier corresponding to the current hardware state update instruction is obtained, an event data packet is issued to a service pipeline, the event data packet contains the to-be-updated hardware state identifier and a target hardware state sequence number currently corresponding to the to-be-updated hardware state identifier, the current hardware state update instruction is issued to a register bus, the target hardware state sequence number corresponding to the to-be-updated hardware state identifier is updated, and step S5 is executed.

[0007] Step S3, a register group corresponding to the target hardware state sequence number corresponding to the to-be-updated hardware state identifier based on the current hardware state update instruction is updated, and the register group is used to store hardware state information, and step S5 is executed.

[0008] Step S4, add the hardware state identifier and the current corresponding target hardware state sequence number to the service data packet corresponding to the current service instruction, and send to the service pipeline to execute step S5.

[0009] Step S5, execute the service pipeline, and send a feedback signal to the register bus when the service pipeline executes the event data packet, and the register bus releases the target hardware state sequence number corresponding to the hardware state identifier in the event data packet and the register group corresponding to the target hardware state sequence number based on the received feedback signal.

[0010] According to the second aspect of the present application, an electronic device is provided, comprising: at least one processor; and a memory in communication connection with the at least one processor; wherein the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method according to the first aspect of the present application.

[0011] According to the third aspect of the present application, a computer readable storage medium is provided, which stores computer executable instructions for executing the method according to the first aspect of the present application.

[0012] Compared with the prior art, the present application has obvious advantages and beneficial effects. By the above technical solution, the asynchronous hardware state management method, electronic device and medium provided by the present application can achieve considerable technical progress and practicality, and have wide industrial utilization value. At least the following beneficial effects are achieved:

[0013] The present application provides a parallel running service pipeline and a register bus, sets multiple register groups for each type of hardware state, executes the service data packet through the service pipeline, executes the hardware state update through the register bus and the register group, and realizes the synchronization and order preservation between the service pipeline and the register bus through the event data packet. The present application reduces the situation that the hardware state update blocks the execution of the service data packet, and improves the execution efficiency of the service data packet. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0015] Figure 1 The asynchronous hardware state management method flowchart provided by the embodiments of the present application. DETAILED DESCRIPTION

[0016] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be clearly and completely described below, obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0017] The embodiment of the present application provides an asynchronous hardware state management method, as shown in the figure, comprising: Figure 1

[0018] Step S1, obtaining a current to-be-processed instruction, if the current to-be-processed instruction is a hardware state update instruction and the last to-be-processed instruction is a service execution instruction, executing step S2, if the current to-be-processed instruction is a hardware state update instruction and the last to-be-processed instruction is a hardware state update instruction, executing step S3, if the current to-be-processed instruction is a service execution instruction, executing step S4.

[0019] It should be noted that the current to-be-processed instruction is issued by software.

[0020] Step S2, obtaining a to-be-updated hardware state identifier corresponding to the current hardware state update instruction, issuing an event data packet to a service pipeline, the event data packet containing the to-be-updated hardware state identifier and a target hardware state sequence number currently corresponding to the to-be-updated hardware state identifier, issuing the current hardware state update instruction to a register bus, updating the target hardware state sequence number corresponding to the to-be-updated hardware state identifier, and executing step S5.

[0021] It should be noted that only when the current to-be-processed instruction is a hardware state update instruction and the last to-be-processed instruction is a service execution instruction, the target hardware state sequence number corresponding to the to-be-updated hardware state identifier needs to be updated, and the target hardware state sequence number is dynamically changed.

[0022] Step S3, updating a register group corresponding to the target hardware state sequence number corresponding to the to-be-updated hardware state identifier based on the current hardware state update instruction, the register group being used for storing hardware state information, and executing step S5.

[0023] It should be noted that if the current to-be-processed instruction is a hardware state update instruction and the last to-be-processed instruction is a hardware state update instruction, the target hardware state sequence number corresponding to the to-be-updated hardware state identifier will not be updated, but the register group corresponding to the target hardware state sequence number corresponding to the to-be-updated hardware state identifier will be updated based on the current hardware state update instruction. Although the target hardware state sequence number is dynamically changed, once the correspondence between the register group and the target hardware state sequence number is determined, the hardware state sequence number corresponding to the register group is determined, and the hardware state sequence number corresponding to the register group is unchanged before being released. ​

[0024] Step S4, add the hardware state identifier and the current corresponding target hardware state sequence number to the service data packet corresponding to the current service instruction, and send it to the service pipeline to execute step S5.

[0025] It should be noted that the hardware state identifier and the current corresponding target hardware state sequence number added in the service data packet are the hardware state sequence numbers corresponding to the hardware state required when the service data packet is executed, that is, the hardware state sequence number corresponding to the hardware state identifier in the service data packet is determined.

[0026] Step S5, execute the service pipeline, and send a feedback signal to the register bus when the event data packet is executed, and the register bus releases the target hardware state sequence number corresponding to the hardware state identifier in the event data packet and the register group corresponding to the target hardware state sequence number based on the received feedback signal.

[0027] It should be noted that when the event data packet is executed, it means that the hardware state in the target hardware state sequence number corresponding to the hardware state identifier in the event data packet and the register group corresponding to the target hardware state sequence number has been used by the service data packet before the event data packet, and the subsequent data packet needs to use the new state corresponding to the hardware state identifier in the event data packet to execute, therefore, the target hardware state sequence number corresponding to the hardware state identifier in the event data packet and the register group corresponding to the target hardware state sequence number are released, and the sequence number and the register group after release can be used for subsequent update of the hardware state.

[0028] As an embodiment, the step S1 further comprises:

[0029] Step S10, set f(n) groups of register entities for the nth type of hardware state, the f(n) groups of register entities corresponding to the nth type of hardware state are initially empty, n is in the range of 1 to N, N is the total number of hardware state categories, and f(n) is the total number of register entity groups of the nth type of hardware state.

[0030] Wherein, the size of f(n) is proportional to the update frequency of the nth type of hardware state, that is, the higher the update frequency of the hardware state type, the more register entity groups are set. It should be noted that the addresses of the f(n) groups of register entities set for the nth type of hardware state are the same, so that the subsequent update and switching of the hardware state based on the register group entity is transparent to the software.

[0031] Step S20, set the corresponding initial hardware state in the first group of register entities of the nth type of hardware state, and initially set the target state sequence number corresponding to the nth type of hardware state as 1.

[0032] As an embodiment, in the step S2, the obtaining of the to-be-updated hardware state identifier corresponding to the current hardware state update instruction comprises:

[0033] In the step S21, a target hardware state sequence number corresponding to the to-be-updated hardware state identifier corresponding to the current hardware state update instruction is obtained.

[0034] It should be noted that when the hardware state update instruction is received, not all categories of hardware states need to be updated, and therefore the target hardware state sequence number corresponding to the to-be-updated hardware state identifier corresponding to the current hardware state update instruction is obtained. The to-be-updated hardware state identifier included in the hardware state update instruction can be one or multiple, and only the target hardware state sequence number corresponding to the to-be-updated hardware state identifier corresponding to the current hardware state update instruction needs to be updated. The state update process of each to-be-updated hardware state identifier is independent of each other.

[0035] In the step S22, the to-be-updated hardware state identifier and the target hardware state sequence number corresponding to the to-be-updated hardware state identifier are added to the event data packet, the event data packet is set as a non-blocking feedback data packet, and then the event data packet is sent to the service pipeline.

[0036] It should be noted that the event data packet is set as a non-blocking feedback data packet, which means that the event data packet is set as a non-blocking mode, and a feedback signal needs to be generated after the execution. The non-blocking mode means that after the event data packet is issued, the data packet after the event data packet can be executed without waiting for the execution of the event data packet to be completed.

[0037] As an embodiment, in the step S2, the updating of the target hardware state sequence number corresponding to the to-be-updated hardware state identifier comprises:

[0038] In the step S23, it is determined whether there is an idle register group corresponding to the to-be-updated hardware state identifier. If there is, the step S24 is executed. If there is not, the step S24 is executed when there is an idle register group corresponding to the to-be-updated hardware state identifier.

[0039] It should be noted that the state update process of each to-be-updated hardware state identifier is independent of each other. When the hardware state corresponding to the to-be-updated hardware state identifier needs to be updated, the corresponding idle register group needs to exist. Each corresponding idle register group needs to be set with a corresponding state sequence number. If there is no idle register group corresponding to the to-be-updated hardware state identifier, the step S24 needs to be executed when there is an idle register group corresponding to the to-be-updated hardware state identifier. Since the number of register groups corresponding to the hardware state identifier is set according to the state update frequency in the embodiment of the present application, therefore, under most circumstances, there will be an idle register group corresponding to the to-be-updated hardware state identifier.

[0040] Step S24, select an idle register group corresponding to the hardware state to be updated, and copy the hardware state information in the register group corresponding to the target hardware state sequence number corresponding to the hardware state to be updated to the selected idle register group corresponding to the hardware state to be updated.

[0041] It should be noted that step S24 can be implemented based on hardware setting a clock cycle. In general, hardware state update only updates partial information, so the entire hardware state information is first copied to the selected idle register group corresponding to the hardware state to be updated quickly and accurately, and subsequent partial update can be performed, thereby reducing the time for updating the hardware state.

[0042] Step S25, if the target hardware state sequence number corresponding to the hardware state to be updated is equal to the total number of register entity groups corresponding to the hardware state to be updated, the target hardware state sequence number corresponding to the hardware state to be updated is updated to 1, otherwise, the target hardware state sequence number corresponding to the hardware state to be updated is updated to the target hardware state sequence number corresponding to the hardware state to be updated + 1, and the target hardware state sequence number of the updated hardware state to be updated is set to the hardware state sequence number corresponding to the selected idle register group corresponding to the hardware state to be updated.

[0043] As an embodiment, the step S3 comprises:

[0044] Step S31, based on the current hardware state update instruction, obtain the register to be updated and the corresponding state information to be updated.

[0045] Step S32, update the content of the register corresponding to the register to be updated in the register group corresponding to the target hardware state sequence number corresponding to the hardware state to be updated to the corresponding state information to be updated.

[0046] It should be noted that, on the basis of copying the entire hardware state information to the selected idle register group corresponding to the hardware state to be updated quickly and accurately, partial update is performed through steps S31 and S32, thereby reducing the time for updating the hardware state.

[0047] As an embodiment, the step S5 comprises:

[0048] Step S51, on the service pipeline, each service data packet is executed based on the corresponding hardware state identifier in the service data packet and the hardware state sequence number corresponding to the hardware state identifier.

[0049] It should be noted that the hardware state identifier added in the step S4 is the hardware state identifier corresponding to the service data packet, and the target hardware state sequence number corresponding to the added hardware state identifier is the hardware state sequence number corresponding to the service data packet.

[0050] In the step S52, when all the service data packets before the event data packet are executed, the event data packet is executed, and the hardware state sequence number corresponding to the hardware state identifier in the event data packet is obtained.

[0051] It should be noted that the hardware state identifier to be updated added in the step S2 is the hardware state identifier in the event data packet. The target hardware state sequence number corresponding to the hardware state identifier to be updated added in the step S2 is the hardware state sequence number corresponding to the hardware state identifier in the event data packet.

[0052] In the step S53, a feedback signal is generated based on the hardware state sequence number corresponding to the hardware state identifier in the event data packet, and the feedback signal is sent to the register bus.

[0053] In the step S54, the hardware state sequence number corresponding to the hardware state identifier in the event data packet and the register group corresponding to the hardware state sequence number are released based on the received feedback signal.

[0054] The step S54 can be implemented by setting a state control unit.

[0055] As an embodiment, the service pipeline can specifically include a GPU (Graphics Processing Unit) graphics pipeline and a shader, and the service data packet can specifically include a graphics service data packet and a computing service data packet.

[0056] It should be noted that some example embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts depict the steps in a particular order, many of the steps can be performed in parallel, concurrently or at the same time. In addition, the order of the steps can be rearranged. The process can be terminated when its operations are completed, but can also have additional steps not included in the figure. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0057] The embodiment of the application further provides an electronic device, including: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores instructions executed by the at least one processor, and the instructions are arranged to execute the method of the embodiment of the application.

[0058] The embodiment of the present application further provides a computer readable storage medium, which stores computer executable instructions, and the computer executable instructions are used for executing the method provided by the embodiment of the present application.

[0059] The embodiment of the present application sets a service pipeline and a register bus running in parallel, sets multiple register groups for each type of hardware state, executes service data packets through the service pipeline, executes hardware state updating through the register bus and the register groups, and realizes synchronization and order preservation between the service pipeline and the register bus through event data packets. The present application reduces the situation that hardware state updating blocks the execution of service data packets, and improves the execution efficiency of service data packets.

[0060] The above is only the preferred embodiment of the present application, and does not limit the present application in any form. Although the present application has been disclosed as above with the preferred embodiment, it is not intended to limit the present application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content to obtain equivalent embodiments with equivalent changes, without departing from the technical solution of the present application. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application still belong to the scope of the technical solution of the present application.

Claims

1. An asynchronous hardware state management method, characterized by, Comprising: Step S1, obtaining a current to-be-processed instruction, if the current to-be-processed instruction is a hardware state update instruction and the last to-be-processed instruction is a service execution instruction, executing step S2, if the current to-be-processed instruction is a hardware state update instruction and the last to-be-processed instruction is a hardware state update instruction, executing step S3, if the current to-be-processed instruction is a service execution instruction, executing step S4; Step S2, obtaining a to-be-updated hardware state identifier corresponding to the current hardware state update instruction, issuing an event data packet to the service pipeline, the event data packet containing the to-be-updated hardware state identifier and the target hardware state sequence number currently corresponding to the to-be-updated hardware state identifier, issuing the current hardware state update instruction to the register bus, updating the target hardware state sequence number corresponding to the to-be-updated hardware state identifier, and executing step S5; Step S3, updating the register group corresponding to the target hardware state sequence number corresponding to the to-be-updated hardware state identifier based on the current hardware state update instruction, the register group being used to store hardware state information, and executing step S5; Step S4, adding the hardware state identifier and the current corresponding target hardware state sequence number to the service data packet corresponding to the current service instruction, and issuing to the service pipeline, and executing step S5; Step S5, executing the service pipeline, when the service pipeline executes the event data packet, sending a feedback signal to the register bus, and the register bus releasing the target hardware state sequence number corresponding to the hardware state identifier in the event data packet and the register group corresponding to the target hardware state sequence number based on the received feedback signal.

2. The method of claim 1, wherein, before the step S1, further comprising: Step S10, setting f(n) register entities for the nth type of hardware state, the f(n) register entities corresponding to the nth type of hardware state being initially empty, n being in the range of 1 to N, N being the total number of hardware state categories, and f(n) being the total number of register entity groups of the nth type of hardware state; Step S20, setting the corresponding initial hardware state in the first group of register entities of the nth type of hardware state, and initially setting the target state sequence number corresponding to the nth type of hardware state as 1.

3. The method of claim 2, wherein, the size of f(n) is proportional to the update frequency of the nth type of hardware state.

4. The method of claim 1, wherein, in the step S2, the obtaining of the to-be-updated hardware state identifier corresponding to the current hardware state update instruction and the issuing of the event data packet to the service pipeline, comprises: Step S21, obtaining the target hardware state sequence number corresponding to the to-be-updated hardware state identifier corresponding to the current hardware state update instruction; Step S22, adding the to-be-updated hardware state identifier and the target hardware state sequence number currently corresponding to the to-be-updated hardware state identifier to the event data packet, setting the event data packet as a non-blocking feedback data packet, and then sending the event data packet to the service pipeline.

5. The method of claim 2, wherein, ​ ​ ​ The step S2 comprises: Step S23, judging whether there is an idle register group corresponding to the hardware state identifier to be updated, if there is, executing step S24, if not, executing step S24 when there is an idle register group corresponding to the hardware state identifier to be updated; Step S24, selecting an idle register group corresponding to the hardware state identifier to be updated, copying the hardware state information in the register group corresponding to the target hardware state sequence number corresponding to the hardware state identifier to be updated to the selected idle register group corresponding to the hardware state identifier to be updated; Step S25, if the target hardware state sequence number corresponding to the hardware state identifier to be updated is equal to the total number of register entity groups corresponding to the hardware state identifier to be updated, updating the target hardware state sequence number corresponding to the hardware state identifier to be updated to 1, otherwise, updating the target hardware state sequence number corresponding to the hardware state identifier to be updated to the target hardware state sequence number corresponding to the hardware state identifier to be updated + 1, and setting the updated target hardware state sequence number of the hardware state identifier to be updated as the hardware state sequence number corresponding to the selected idle register group corresponding to the hardware state identifier to be updated.

6. The method of claim 1, wherein, The step S3 comprises: Step S31, obtaining the register identifier to be updated and the corresponding updated state information based on the current hardware state update instruction; Step S32, updating the content of the register corresponding to the register identifier to be updated in the register group corresponding to the target hardware state sequence number corresponding to the hardware state identifier to be updated to the corresponding updated state information.

7. The method of claim 2, wherein, The step S5 comprises: Step S51, on the service pipeline, each service data packet selects the corresponding register group based on the hardware state identifier in the service data packet and the hardware state sequence number corresponding to the hardware state identifier to execute the service data packet; Step S52, when all service data packets before the event data packet are executed, the event data packet is executed, and the hardware state sequence number corresponding to the hardware state identifier in the event data packet is obtained; Step S53, generating a feedback signal based on the hardware state sequence number corresponding to the hardware state identifier in the event data packet and sending it to the register bus; Step S54, releasing the hardware state sequence number corresponding to the hardware state identifier in the event data packet and the register group corresponding to the hardware state sequence number based on the received feedback signal.

8. The method of claim 2, wherein, The service pipeline comprises a GPU graphics pipeline and a shader, and the service data packet comprises a graphics service data packet and a computing service data packet.

9. An electronic device, comprising: comprises: at least one processor; and a memory connected in communication with the at least one processor; wherein the memory stores instructions executed by the at least one processor, the instructions being configured to execute the method of any one of the preceding claims 1-8.

10. A computer-readable storage medium, characterized in that, Computer executable instructions are stored which are used to perform the method according to any one of the preceding claims 1 to 8.

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