Parallel interface test method and device, electronic equipment and computer storage medium

Abstract

The embodiment of the invention discloses a parallel interface testing method and device, electronic equipment and a computer storage medium. According to the embodiment of the invention, after the measurement-free area of the parallel interface is determined according to the reference voltage range and the time sequence parameter range of the parallel interface, the sampling point is determined according to the boundary point of the measurement-free area, and the sampling point is taken as a starting point to determine the plurality of target sampling points in an iteration mode; and determining an eye pattern of the parallel interface according to the number of the error codes of each target sampling point. In the embodiment of the invention, the target sampling point is determined according to the scanning step length and the scanning direction, and the scanning step length is determined according to the number of error codes of the previous target sampling point, so that the scanning number and the test data volume can be effectively reduced, and the test efficiency of the parallel interface is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and more particularly to a parallel interface testing method, device, electronic equipment and computer storage medium. Background Art

[0002] Eye diagram testing is an important method for evaluating parallel interface performance. Conventional eye diagram testing methods typically involve traversing the parallel interface's reference voltage range and timing parameter range, and counting the number of bit errors or bit error rate under different reference voltages and / or timing parameters. However, this method requires a large amount of test data, making parallel interface testing inefficient. Summary of the Invention

[0003] In view of this, an embodiment of the present invention provides a parallel interface testing method, device, electronic device and computer storage medium to determine the target sampling point according to the scanning step length and scanning direction, and determine the scanning step length according to the number of bit errors of the previous target sampling point, thereby effectively reducing the number of scans and the amount of test data, and improving the testing efficiency of the parallel interface.

[0004] In a first aspect, an embodiment of the present invention provides a method for testing a parallel interface, the method comprising:

[0005] Determining a test-free region of the parallel interface to be tested according to a reference voltage range and a timing parameter range of the parallel interface to be tested;

[0006] Determining a first sampling point according to a boundary point of the measurement-free area;

[0007] Taking the first sampling point as a starting point, determining a plurality of target sampling points in an iterative manner;

[0008] Determining an eye diagram of the parallel interface to be tested according to the number of bit errors corresponding to each target sampling point;

[0009] The target sampling point is determined as follows:

[0010] Scan the target sampling point to determine the corresponding number of bit errors, determine a scanning step size based on the number of bit errors, and update the next sampling point to the target sampling point based on the scanning step size and the first scanning direction until the number of bit errors at the target sampling point meets a first quantity condition and the number of bit errors at a sampling point previous to the target sampling point meets a second quantity condition.

[0011] Optionally, determining the test-free region of the parallel interface to be tested according to the reference voltage range and timing parameter range of the parallel interface to be tested includes:

[0012] Determining a second sampling point of the parallel interface to be tested according to the reference voltage range and the timing parameter range, wherein the second sampling point is a reference sampling point of the parallel interface to be tested in a training phase;

[0013] Taking the second sampling point as a starting point, sequentially scanning the sampling points along each second scanning direction, and determining the number of bit errors at each sampling point, until a sampling point having a non-zero number of bit errors is detected in each second scanning direction;

[0014] Determine the sampling points at which the number of bit errors is not 0 as vertices of the test-free area;

[0015] The detection-free area is determined according to each of the vertices.

[0016] Optionally, determining the first sampling point according to the boundary point of the measurement-free area includes:

[0017] Determine sampling points that are adjacent to the boundary point and do not belong to the exempted area as candidate sampling points, wherein the boundary point includes the vertex;

[0018] Determine the candidate sampling point adjacent to the vertex as the starting sampling point;

[0019] Taking the starting sampling point as a starting point, iteratively determining a plurality of designated sampling points, wherein the designated sampling points are candidate sampling points spaced apart from a previous designated sampling point by a second step length in a second direction, wherein the second direction and the first scanning direction are directions of different dimensions, and the dimensions include a reference voltage dimension and a timing parameter dimension;

[0020] Each of the designated sampling points is determined as the first sampling point.

[0021] Optionally, determining the scanning step length according to the number of bit errors includes:

[0022] In response to the number of bit errors satisfying a third quantity condition, determining the scanning step length to be a third step length;

[0023] In response to the number of bit errors satisfying the second quantity condition, determining the scanning step length to be a fourth step length;

[0024] In response to the number of bit errors satisfying the first quantity condition, determining the scanning step length to be a fifth step length;

[0025] The third step length and the fifth step length are both positive values, the third step length is smaller than the fifth step length, and the fourth step length is a negative value.

[0026] Optionally, the method further includes:

[0027] A test result of the parallel interface to be tested is determined according to the eye diagram.

[0028] Optionally, the number of bit errors corresponding to the target sampling point is determined by:

[0029] In response to detecting that the number of bit errors meets the second quantity condition, accumulating the number of bit errors is stopped.

[0030] In a second aspect, an embodiment of the present invention provides a parallel interface testing device, the device comprising:

[0031] An area determination unit, configured to determine a test-exempt area of ​​the parallel interface to be tested according to a reference voltage range and a timing parameter range of the parallel interface to be tested;

[0032] A first sampling point determining unit, configured to determine a first sampling point according to a boundary point of the measurement-free area;

[0033] a target sampling point determining unit, configured to iteratively determine a plurality of target sampling points starting from the first sampling point;

[0034] An eye diagram determining unit, configured to determine an eye diagram of the parallel interface to be tested according to the number of bit errors corresponding to each target sampling point;

[0035] The target sampling point is determined as follows:

[0036] Scan the target sampling point to determine the corresponding number of bit errors, determine a scanning step size based on the number of bit errors, and update the next sampling point to the target sampling point based on the scanning step size and the first scanning direction until the number of bit errors at the target sampling point meets a first quantity condition and the number of bit errors at a sampling point previous to the target sampling point meets a second quantity condition.

[0037] In a third aspect, an embodiment of the present invention provides an electronic device comprising a memory and a processor, wherein the memory is used to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement a method as described in any one of the first aspects.

[0038] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method as described in any one of the first aspects is implemented.

[0039] In a fifth aspect, an embodiment of the present invention provides a computer program product, which includes a computer program / instructions, and when the computer program / instructions are executed by a processor, implements the method as described in any one of the first aspects.

[0040] After determining a parallel interface's test-free region based on the parallel interface's reference voltage range and timing parameter range, the present invention determines a sampling point based on the boundary of the test-free region. Using this sampling point as a starting point, the system iteratively determines multiple target sampling points, and then determines the parallel interface's eye diagram based on the number of bit errors at each target sampling point. In this embodiment of the present invention, the target sampling point is determined based on the scan step size and scan direction, and the scan step size is determined based on the number of bit errors at the previous target sampling point. This effectively reduces the number of scans and the amount of test data, thereby improving parallel interface testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0042] Figure 1 It is a schematic diagram of the existing 2D Shmoo eye diagram;

[0043] Figure 2 is a flow chart of a method for testing a parallel interface according to an embodiment of the present invention;

[0044] Figure 3 is a flow chart of a method for testing a parallel interface according to an embodiment of the present invention;

[0045] Figure 4 is a schematic diagram of a scanning process according to an embodiment of the present invention;

[0046] Figure 5 is a flow chart of a method for testing a parallel interface according to an embodiment of the present invention;

[0047] Figure 6 is another schematic diagram of the scanning process of an embodiment of the present invention;

[0048] Figure 7 is another schematic diagram of the scanning process of an embodiment of the present invention;

[0049] Figure 8 is a schematic diagram of a parallel interface testing device according to an embodiment of the present invention;

[0050] Figure 9 is a schematic diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0051] The present application is described below based on the following embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without the description of these details. To avoid obscuring the essence of the present application, well-known methods, processes, procedures, components, and circuits are not described in detail.

[0052] Furthermore, persons of ordinary skill in the art will appreciate that the figures provided herein are for illustration purposes only and are not necessarily drawn to scale.

[0053] Unless the context clearly requires otherwise, words like “include”, “comprising” and the like throughout this application should be interpreted as including rather than exclusive or exhaustive; that is, as meaning “including but not limited to”.

[0054] In the description of this application, it should be understood that the terms "first", "second", etc. are used for descriptive purposes only and should not be understood to indicate or imply relative importance. In addition, in the description of this application, unless otherwise specified, "plurality" means two or more.

[0055] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0056] Eye diagrams can accurately reflect the signal integrity, timing margin, voltage margin, and other performance of parallel interfaces such as DDR (Double Data Rate) interfaces, D2D (Die-to-Die) interfaces, and PCI (Peripheral Component Interconnect) interfaces. Therefore, they are one of the important means of parallel interface testing. The eye diagram test process mainly involves the transmitting device or signal generator sending a known data pattern to the parallel interface to be tested. A common data pattern is a pseudo-random binary sequence (PRBS). After adjusting the timing parameters within the timing parameter range and / or adjusting the reference voltage within the reference voltage range, the parallel interface receives and decodes the received data. The test equipment compares the decoded result of the parallel interface with the original data pattern to determine the bit error rate or number of bit errors of the parallel interface under different timing parameters and / or reference voltages.

[0057] Figure 1 is a schematic diagram of the existing 2D Shmoo eye diagram. Figure 1 As shown in the figure, a 2D Shmoo eye diagram typically has the timing parameter (Timing) on ​​the horizontal axis and the reference voltage (Vref) on the vertical axis. The 2D Shmoo eye diagram can be divided into three regions based on the number of bit errors: the "eye" region, the "eyelid" region, and the "closed" region. The "eye" region, also known as region 11, represents the area with the best signal quality. The "eyelid" region, also known as region 12, corresponds to the fluctuation range of the signal's rising and falling edges and the hold phase. The thickness of the eyelid reflects the steepness of the signal edge and the jitter amplitude. The "closed" region, also known as region 13, indicates that the noise exceeds the tolerance and the signal is misjudged.

[0058] In conventional eye diagram testing methods, after presetting the timing parameters and / or reference voltage sampling intervals, the parallel interface typically needs to iterate through all possible timing parameter and reference voltage combinations before drawing the eye diagram. However, the data pattern transmitted by the transmitting device or signal generator in a single shot is large, and the number of timing parameter and reference voltage combinations is numerous. This results in a very large amount of test data being transmitted during eye diagram testing, thus limiting the efficiency of eye diagram testing.

[0059] To address the above-mentioned issues, embodiments of the present invention provide a parallel interface testing method, apparatus, electronic device, and computer storage medium, which determine a target sampling point based on a scan step length and a scan direction, and determine a scan step length based on the number of bit errors at the previous target sampling point, thereby effectively reducing the number of scans and the amount of test data, and improving the testing efficiency of the parallel interface.

[0060] The following is an explanation of the method by way of an embodiment. Figure 2 FIG. 1 is a flow chart of a method for testing a parallel interface according to an embodiment of the present invention. Figure 2 As shown, the method of this embodiment includes the following steps:

[0061] Step S100 : determining a test-exempt region of the parallel interface to be tested according to a reference voltage range and a timing parameter range of the parallel interface to be tested.

[0062] A 2D Shmoo eye diagram is generated by counting the number of bit errors in a parallel interface under different timing parameters and / or reference voltages. Different types of parallel interfaces may correspond to different timing parameter types or different timing parameter ranges. Taking the DDR3 interface (a type of DDR interface) as an example, the timing parameters of a DDR3 interface may include tCK (Clock Cycle Time), tCAS (CAS Latency), TRCD (RAS to CAS Delay, the delay between the row address strobe (RAS) and the column address strobe (CAS)), tRP (Row Precharge Time), tRAS (Active to Precharge Delay, the minimum time interval between the active and precharge commands), tRFC (Row Refresh Cycle Time), tRRD (Row Active to Row Active Delay, the minimum delay between active commands between different banks), tWTR (Write to Read Delay, the minimum wait time between a write operation and a read operation), and tWR (Write Recovery Time).

[0063] In this embodiment, the sampling point refers to a combination of the timing parameters and reference voltage of the parallel interface. After determining the reference voltage range and timing parameter range of the parallel interface, the values ​​of the timing parameters and reference voltage corresponding to each sampling point can be determined according to the preset sampling interval.

[0064] Taking the DDR3 interface as an example, the reference voltage range of the DDR3 interface can be [0.4, 0.8] (in volts); the value of tCK at 800 MHz is 1.25 nanoseconds, and the value at 667 MHz is 1.5 nanoseconds; the common value range of tCAS is [5, 8] (in clock cycles); the common value range of tRCD is [5, 7] (in clock cycles); the common value range of tRP is [5, 7] (in clock cycles); the common value range of tRAS is [12, 18] (in clock cycles); the common value range of tRFC is usually dozens of clock cycles; the common value range of tRRD is [2, 4] (in clock cycles); the common value range of tWTR is [4, 6] (in clock cycles); the common value range of tWR is [8, 12] (in clock cycles). The sampling interval for the reference voltage can be 5 mV, 10 mV, 20 mV, 50 mV, etc. The sampling interval for the timing parameters is usually 1 or 0.5 clock cycles. Therefore, multiple sampling points corresponding to the DDR3 interface can be determined based on the above ranges and sampling intervals.

[0065] In this step, the test-free region of the parallel interface to be tested can be determined according to the reference voltage range and timing parameter range of the parallel interface to be tested. In this embodiment, the test-free region refers to a region formed by sampling points that do not need to be tested.

[0066] In practical applications, when the reference voltage of the parallel interface is close to the voltage center and / or the timing parameters are close to the timing center, the parallel interface can maximize the noise margin and linearity, and optimize the driving capability, impedance matching and power consumption, while providing the largest timing window and skew tolerance. Therefore, the closer the reference voltage is to the voltage center and / or the closer the timing parameters are to the timing center, the higher the signal stability of the parallel interface is generally, and the bit error rate can be maintained at a low level, or even to zero. Therefore, in an optional implementation method, the voltage center and the timing center can be determined as the central sampling point based on the reference voltage range and the timing parameter range of the parallel interface to be tested, and the predetermined area centered on the central sampling point can be determined as the test-free area of ​​the parallel interface. According to the distribution law of the number of bit errors in the eye diagram, the shape of the predetermined area can be set to an ellipse, a diamond, etc., and this embodiment does not impose any restrictions on this.

[0067] Figure 3 FIG. 1 is a flow chart of a method for testing a parallel interface according to an embodiment of the present invention. Figure 3 As shown, in an optional implementation of this embodiment, step S100 may include the following steps:

[0068] Step S110 , determining a second sampling point of the parallel interface to be tested according to a reference voltage range and a timing parameter range.

[0069] In order to reduce the bit error rate of the Shmoo eye diagram test and improve the test efficiency of the Shmoo eye diagram test, the parallel interface is usually initially trained. Initialization training will automatically calibrate the parallel interface according to the reference voltage range and timing parameter range of the parallel interface after the parallel interface is powered on. The calibration methods may include ZQ calibration, VrefDQ training and DQS timing training. Among them, ZQ calibration is used to adjust the output driver impedance to ensure high-speed signal integrity; VrefDQ training scans different reference voltages to determine the reference voltage that can correctly distinguish between high and low levels of data; DQS timing training dynamically adjusts the DQS delay by sending a specific data pattern so that the sampling point is located in the center of the data eye. After automatic calibration, the parallel interface can also be iteratively tested according to the reference voltage range, timing parameter range and pre-set delay parameter range, and the reference sampling point of the parallel interface can be determined. Therefore, in this step, the reference sampling point (training point) determined by the parallel interface to be tested in the above training phase can be determined as the second sampling point.

[0070] In step S120 , starting from the second sampling point, each sampling point is scanned in sequence along each second scanning direction to determine the number of bit errors at each sampling point until a sampling point having a non-zero number of bit errors is detected in each second scanning direction.

[0071] In a 2D Shmoo eye diagram, the scanning direction of the parallel interface is achieved by changing the timing parameters and / or reference voltage of the parallel interface. Therefore, in this embodiment, to reduce the complexity of the Shmoo eye diagram test and improve the test efficiency of the Shmoo eye diagram test, the second scanning direction of this embodiment can be a vertical upward direction, a vertical downward direction, a horizontal left direction, and a horizontal right direction. In other words, in this step, the second sampling point can be used as the sampling starting point, and the parallel interface is scanned by changing only the reference voltage or only the timing parameters of the parallel interface. The number of bit errors at each sampling point is determined in sequence until two sampling points corresponding to the parallel interface with a non-zero number of bit errors are detected when only the reference voltage is changed, and two sampling points corresponding to the parallel interface with a non-zero number of bit errors are detected when only the timing parameters are changed.

[0072] Specifically, for any second scanning direction, if the first sampling point with a non-zero number of bit errors is detected in the scanning direction, scanning in the scanning direction is stopped; if the first sampling point with a non-zero number of bit errors is detected in each second scanning direction, scanning is stopped.

[0073] Figure 4 FIG. 1 is a schematic diagram of the scanning process of an embodiment of the present invention. Figure 4 As shown, after determining the reference sampling point, i.e., sampling point 41, each sampling point can be scanned in sequence along the scanning directions, i.e., directions 42, 43, 44, and 45, to determine the number of bit errors at each sampling point. When the first non-zero sampling point, i.e., sampling point 46, is found in direction 42, scanning in direction 42 stops. When the first non-zero sampling point, i.e., sampling point 47, is found in direction 43, scanning in direction 43 stops. When the first non-zero sampling point, i.e., sampling point 48, is found in direction 44, scanning in direction 44 stops. When the first non-zero sampling point, i.e., sampling point 49, is found in direction 45, scanning stops.

[0074] Step S130: Determine the sampling points where the number of bit errors is not 0 as vertices of the exempted detection area.

[0075] After determining the first sampling point in each scanning direction where the number of bit errors is not zero, in this step, the four sampling points where the number of bit errors is not zero may all be determined as vertices of the exempted detection area.

[0076] Step S140: determining a measurement-free area according to each vertex.

[0077] After determining the vertices, in order to reduce the complexity of determining the exempted area, the largest area formed by the lines connecting the four vertices can be determined as the exempted area. Figure 4 Taking the schematic diagram shown as an example, sampling point 46, sampling point 47, sampling point 48 and sampling point 49 can be determined as the four vertices of the exempted area, and then sampling point 46 and sampling point 48, sampling point 48 and sampling point 47, sampling point 47 and sampling point 49, and sampling point 49 and sampling point 46 are connected in sequence to obtain area 40 as the exempted area.

[0078] According to actual needs, the measurement-free area may also be in other shapes, which is not limited in this embodiment.

[0079] Step S200: determining a first sampling point according to the boundary points of the measurement-free area.

[0080] The exempted area usually cannot completely cover the entire "eye" area, which makes the sampling points outside the exempted area possible in any area of ​​the "eye" area, "eyelid" area and "closed" area. Therefore, in this step, the first sampling point can be determined according to the boundary point of the exempted area to scan the sampling points outside the exempted area.

[0081] Figure 5 FIG. 1 is a flow chart of a method for testing a parallel interface according to an embodiment of the present invention. Figure 5 As shown, in an optional implementation of this embodiment, step S200 may include the following steps:

[0082] Step S210: Determine sampling points that are adjacent to the boundary points and do not belong to the exempted area as candidate sampling points.

[0083] In this step, sampling points adjacent to the boundary points of the exempted area can be first determined, and then those belonging to the exempted area can be removed from these sampling points to obtain candidate sampling points. In this embodiment, the boundary points can include vertices of the exempted area. Optionally, if duplicate sampling points exist among the candidate sampling points, duplicate removal can be performed on the sampling points to determine the candidate sampling points.

[0084] Step S220 : Determine a candidate sampling point that is adjacent to the vertex and does not belong to the exempted area as a starting sampling point.

[0085] In this step, the candidate sampling points adjacent to the vertex can be determined as the starting sampling points. In this embodiment, there are multiple vertices, so some sampling points can be selected from the multiple candidate sampling points adjacent to the vertex as the starting sampling points according to actual needs.

[0086] To skip the exempted area during scanning, the scanning direction of the sampling points above the exempted area is generally opposite to the scanning direction of the sampling points below the exempted area. Similarly, the scanning direction of the sampling points to the left of the exempted area is generally opposite to the scanning direction of the sampling points to the right of the exempted area. Therefore, when selecting the starting sampling point, a candidate sampling point adjacent to the vertex and located to the left and right of the first sampling point can be selected as the starting sampling point, or a candidate sampling point adjacent to the vertex and located above and below the first sampling point can be selected as the starting sampling point.

[0087] Figure 6 This is another schematic diagram of the scanning process of an embodiment of the present invention. Taking the upper right part of the detection-free area as an example, Figure 6 As shown, the green sampling points are all sampling points that are adjacent to the boundary points of the exempted area but do not belong to the exempted area, that is, candidate sampling points. Among them, sampling point 61 is a candidate sampling point adjacent to sampling point 46, and sampling point 62 is a candidate sampling point adjacent to sampling point 49. Therefore, sampling point 61 or sampling point 62 can be determined as the starting sampling point.

[0088] In step S230 , a plurality of designated sampling points are determined iteratively, starting from the initial sampling point.

[0089] The area outside the test exemption zone also includes a large number of sampling points located in the "eye" area. Therefore, in this step, multiple designated sampling points can be determined from the candidate sampling points in an iterative manner to reduce the number of scans, thereby improving the test efficiency of the eye diagram test.

[0090] Specifically, the starting sampling point may be used as the starting point, the starting sampling point may be determined as the designated sampling point, and candidate sampling points spaced a second step apart from the designated sampling point in the second direction may be updated as designated sampling points until no candidate sampling points exist.

[0091] In this embodiment, the second direction is a direction of a different dimension from the first scanning direction. That is, if the first scanning direction is the direction of the reference voltage dimension (i.e., the vertical axis), then the second direction is the direction of the timing parameter dimension (i.e., the horizontal axis); if the first scanning direction is the direction of the timing parameter dimension, then the second direction is the direction of the reference voltage dimension.

[0092] The step length is used to characterize the number of sampling intervals between sampling points. Specifically, for any sampling point, if the direction of change from the timing parameter or reference voltage of the sampling point to the timing parameter or reference voltage of another sampling point is consistent with the second direction (or scanning direction), then the step length between the two sampling points can be the number of sampling intervals between the sampling points + 1; if the direction of change from the timing parameter or reference voltage of the sampling point to the timing parameter or reference voltage of another sampling point is inconsistent with the second direction (or scanning direction), then the step length between the two sampling points can be the negative value of the number of sampling intervals between the sampling points + 1. Figure 6 Taking the schematic diagram shown as an example, direction 66 is the second direction, which is the direction of increase of the timing parameter. The number of sampling intervals between sampling point 61 and sampling point 63 in the second direction is 1, and the direction of change from the timing parameter of sampling point 61 to the timing parameter of sampling point 63 is also the direction of increase of the timing parameter, which is consistent with the second direction. Therefore, the step size between sampling point 61 and sampling point 63 in the second direction is 2. In this embodiment, the second step size can be set according to actual needs and the distribution of candidate sampling points, for example, to ±2, ±3, ±5, etc., and this embodiment does not limit this.

[0093] Still Figure 6 Take the schematic diagram shown in the figure as an example. Direction 64 is the first scanning direction, the starting sampling point is sampling point 61, and the second step length in the second direction is 2. The first designated sampling point is sampling point 61, and the candidate sampling point separated from sampling point 61 by the second step length of 2 in the second direction is sampling point 63. Then, sampling point 63 can be updated to the designated sampling point. Furthermore, the candidate sampling point separated from sampling point 63 by the second step length of 2 in the second direction is updated to the designated sampling point (not shown in the figure) until no candidate sampling point exists.

[0094] Step S240: determine each designated sampling point as a first sampling point.

[0095] After the designated sampling points are determined in sequence, each designated sampling point may be determined as the first sampling point.

[0096] In step S300 , a plurality of target sampling points are determined iteratively, starting from the first sampling point.

[0097] In this embodiment, sampling points located in the "eye" region are sampling points whose number of bit errors meets the third quantity condition, sampling points located in the "eyelid" region are sampling points whose number of bit errors meets the first quantity condition, and sampling points located in the "closed" region are sampling points whose number of bit errors meets the second quantity condition. It will be readily understood that in this embodiment, the third quantity condition is less than the first quantity condition, and the first quantity condition is less than the second quantity condition. For example, the third quantity condition may be that the number of bit errors is between 0 and 100, the first quantity condition may be that the number of bit errors is between 101 and 200, and the second quantity condition may be that the number of bit errors is greater than or equal to 201.

[0098] Based on the distribution of bit errors at sampling points in the Shmoo eye diagram, after determining the sampling points in the "eyelid" region, we can clearly identify the sampling points in the "eye" region and the sampling points in the "closed" region. Therefore, the sampling points in the "eyelid" region are key sampling points in the Shmoo eye diagram, especially those at the edge of the "eyelid" region. Therefore, to further reduce the number of scans and improve eye diagram testing efficiency, in this step, multiple target sampling points can be iteratively determined from the sampling points for scanning.

[0099] Specifically, the first sampling point can be used as the first target sampling point, the target sampling point can be scanned, the number of bit errors corresponding to the target sampling point can be determined, the scanning step length can be determined according to the number of bit errors of the target sampling point, and the next sampling point can be updated to the target sampling point according to the scanning step length and the first scanning direction until the number of bit errors of the target sampling point meets the first number condition and the number of bit errors of the sampling point before the target sampling point meets the second number condition.

[0100] In an optional implementation, if the number of bit errors at the target sampling point meets the third quantity condition, the scanning step size can be determined to be the third step size; if the number of bit errors at the target sampling point meets the second quantity condition, the scanning step size can be determined to be the fourth step size; if the number of bit errors at the target sampling point meets the first quantity condition, the scanning step size can be determined to be the fifth step size. In this embodiment, the third and fifth step sizes can both be set to positive values, the third step size can be set to be smaller than the fifth step size, and the fourth step size can be set to a negative value. For example, the third step size can be 1, the fourth step size can be -1, and the fifth step size can be 2.

[0101] Figure 7 FIG. 1 is another schematic diagram of the scanning process of an embodiment of the present invention. Figure 7As shown, direction 71 is the first scanning direction. When sampling point 61 is the target sampling point, sampling point 61 can be scanned to determine the number of bit errors corresponding to sampling point 61. The number of bit errors at sampling point 51 meets the third quantity condition, and the scanning step size is 1. Therefore, based on direction 71 and the scanning step size, the next sampling point can be updated as the target sampling point, until sampling point 72 is determined as the target sampling point. After scanning sampling point 72 to determine that the number of bit errors corresponding to sampling point 72 meets the first quantity condition, the scanning step size can be determined to be 2. Therefore, based on direction 71 and the scanning step size, the next sampling point can be updated as the target sampling point, until sampling point 73 is determined as the target sampling point. After scanning sampling point 73 to determine that the number of bit errors corresponding to sampling point 73 meets the first quantity condition, the scanning step size can be determined to be 2. Therefore, based on direction 71 and the scanning step size, sampling point 75 can be determined as the target sampling point. After scanning sampling point 75 and determining that the number of bit errors corresponding to sampling point 75 meets the second quantity condition, the scanning step size can be determined to be -1. Therefore, sampling point 74 can be determined as the target sampling point based on direction 71 and the scanning step size. After scanning sampling point 74 and determining that the number of bit errors corresponding to sampling point 74 meets the first quantity condition, scanning starting from sampling point 61 can be stopped.

[0102] During the scanning of sampling points, a large number of data patterns are sent at once. In this embodiment, the data pattern sent is 10 million bits of data. Therefore, when counting the number of bit errors, it is generally necessary to traverse all bits of data. To reduce the statistical complexity of the number of bit errors, this embodiment stops accumulating the number of bit errors for any sampling point when it is detected that the number of bit errors at that sampling point meets a second number condition. For example, if the second number condition is that the number of bit errors is ≥ 255, then when the number of bit errors at any sampling point reaches 255, the number of bit errors for that sampling point is no longer accumulated.

[0103] Step S400 : determining an eye diagram of the parallel interface to be tested according to the number of bit errors corresponding to each target sampling point.

[0104] After determining the number of bit errors corresponding to the target sampling points, in this step, the number of bit errors of each target sampling point can be filled in the corresponding position according to the timing parameters and reference voltage corresponding to each target sampling point, thereby obtaining the eye diagram of the parallel interface to be tested.

[0105] In an optional implementation, the method of this embodiment may further include the following steps:

[0106] Step S500: determining a test result of the parallel interface to be tested according to the eye diagram.

[0107] After determining the eye diagram, the test results of the parallel interface to be tested can be determined based on the eye diagram. For example, the horizontal opening of the eye diagram can reflect the timing margin of the parallel interface to be tested. The larger the horizontal opening, the larger the signal's time tolerance range, which means the greater the allowable clock jitter and deviation, and the parallel interface can correctly transmit data under more relaxed clock conditions. The vertical opening of the eye diagram can reflect the voltage margin of the parallel interface to be tested. The larger the vertical opening, the greater the signal's noise tolerance, which means it can withstand greater noise interference without affecting the correct judgment of data. The vertical thickness of the "eyelid" area can also reflect the voltage margin of the parallel interface to be tested. The thinner the "eyelid" area, the smaller the signal level fluctuation and the larger the voltage margin. Conversely, the thinner the eyelid area, the smaller the voltage margin.

[0108] Through the method of the embodiment of the present invention, the number of scans during the eye diagram test can be effectively reduced, especially the number of scans in the "closed" area, thereby effectively reducing the amount of data during scanning, thereby improving the test efficiency of the parallel interface.

[0109] After determining a parallel interface's test-free region based on the parallel interface's reference voltage range and timing parameter range, the present invention determines a sampling point based on the boundary of the test-free region. Using this sampling point as a starting point, the system iteratively determines multiple target sampling points, and then determines the parallel interface's eye diagram based on the number of bit errors at each target sampling point. In this embodiment of the present invention, the target sampling point is determined based on the scan step size and scan direction, and the scan step size is determined based on the number of bit errors at the previous target sampling point. This effectively reduces the number of scans and the amount of test data, thereby improving parallel interface testing efficiency.

[0110] Figure 8 FIG. 1 is a schematic diagram of a parallel interface test device according to an embodiment of the present invention. Figure 8 As shown, the parallel interface test device of this embodiment includes an area determination unit 801 , a first sampling point determination unit 802 , a target sampling point determination unit 803 and an eye pattern determination unit 804 .

[0111] The region determination unit 801 is configured to determine a test-free region of the parallel interface to be tested according to a reference voltage range and a timing parameter range of the parallel interface to be tested; the first sampling point determination unit 802 is configured to determine a first sampling point according to a boundary point of the test-free region;

[0112] The target sampling point determination unit 803 is configured to iteratively determine multiple target sampling points starting from the first sampling point. The eye diagram determination unit 804 is configured to determine an eye diagram of the parallel interface to be tested based on the number of bit errors corresponding to each target sampling point. The target sampling points are determined by scanning the target sampling points to determine the corresponding number of bit errors, determining a scanning step size based on the number of bit errors, and updating the next sampling point to the target sampling point based on the scanning step size and a first scanning direction until the number of bit errors at the target sampling point meets a first quantity condition and the number of bit errors at the sampling point immediately preceding the target sampling point meets a second quantity condition.

[0113] Furthermore, the area determination unit 801 includes a first determination subunit, a first scanning subunit, a second determination subunit and a third determination subunit.

[0114] Among them, the first determination subunit is used to determine the second sampling point of the parallel interface to be tested based on the reference voltage range and the timing parameter range, and the second sampling point is the benchmark sampling point of the parallel interface to be tested in the training phase; the first scanning subunit is used to take the second sampling point as the starting point, and scan each of the sampling points in sequence according to each second scanning direction, to determine the number of bit errors at each of the sampling points, until the sampling points with non-zero number of bit errors are detected in each of the second scanning directions; the second determination subunit is used to determine each of the sampling points with non-zero number of bit errors as the vertex of the exempted area; and the third determination subunit is used to determine the exempted area based on each of the vertices.

[0115] Furthermore, the first sampling point determining unit 802 includes a fourth determining subunit, a fifth determining subunit, a sixth determining subunit, and a seventh determining subunit.

[0116] The fourth determining subunit is configured to determine sampling points adjacent to the boundary points and not belonging to the measurement-exempt area as candidate sampling points, wherein the boundary points include the vertices;

[0117] The fifth determining subunit is configured to determine the candidate sampling point adjacent to the vertex as a starting sampling point;

[0118] The sixth determining subunit is configured to iteratively determine a plurality of designated sampling points with the starting sampling point as a starting point, where the designated sampling points are candidate sampling points spaced apart from a previous designated sampling point by a second step length in a second direction, where the second direction and the first scanning direction are directions of different dimensions, where the dimensions include a reference voltage dimension and a timing parameter dimension. The seventh determining subunit is configured to determine each of the designated sampling points as the first sampling point.

[0119] Furthermore, the target sampling point determination unit 803 includes a first step length determination subunit, a second step length determination subunit, and a third step length determination subunit.

[0120] Among them, the first step length determination subunit is used to determine that the scanning step length is the third step length in response to the number of bit errors satisfying the third quantity condition; the second step length determination subunit is used to determine that the scanning step length is the fourth step length in response to the number of bit errors satisfying the second quantity condition; the third step length determination subunit is used to determine that the scanning step length is the fifth step length in response to the number of bit errors satisfying the first quantity condition; wherein, the third step length and the fifth step length are both positive values, and the third step length is smaller than the fifth step length, and the fourth step length is a negative value.

[0121] Furthermore, the device also includes a test result determination unit.

[0122] The test result determination unit is configured to determine a test result of the parallel interface to be tested according to the eye diagram.

[0123] Furthermore, the number of bit errors corresponding to the target sampling point is determined by a bit error number determining unit.

[0124] The bit error number determining unit is configured to stop accumulating the number of bit errors in response to detecting that the number of bit errors meets the second quantity condition.

[0125] After determining a parallel interface's test-free region based on the parallel interface's reference voltage range and timing parameter range, the present invention determines a sampling point based on the boundary of the test-free region. Using this sampling point as a starting point, the system iteratively determines multiple target sampling points, and then determines the parallel interface's eye diagram based on the number of bit errors at each target sampling point. In this embodiment of the present invention, the target sampling point is determined based on the scan step size and scan direction, and the scan step size is determined based on the number of bit errors at the previous target sampling point. This effectively reduces the number of scans and the amount of test data, thereby improving parallel interface testing efficiency.

[0126] Figure 9 Schematic diagram of an electronic device according to an embodiment of the present invention. In this embodiment, the electronic device 9 includes a server, a terminal, etc. Figure 9 As shown, the electronic device 9 includes: at least one processor 901; a memory 902 communicatively connected to the at least one processor 901; and a communication component 903 communicatively connected to the scanning device, and the communication component 903 receives and sends data under the control of the processor 901; wherein the memory 902 stores instructions that can be executed by the at least one processor 901, and the instructions are executed by the at least one processor 901 to implement the above-mentioned parallel interface test method.

[0127] Specifically, the electronic device includes: one or more processors 901 and a memory 902, Figure 9 A processor 901 is used as an example. The processor 901 and the memory 902 may be connected via a bus or other means. Figure 9 In the example, a bus connection is used. Memory 902, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer executable programs, and modules. Processor 901 executes the non-volatile software programs, instructions, and modules stored in memory 902 to perform various functional applications and data processing of the device, thereby implementing the aforementioned parallel interface testing method.

[0128] The memory 902 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store a list of options, etc. In addition, the memory 902 may include a high-speed random access memory and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 902 may optionally include a memory remotely located relative to the processor 901, and these remote memories may be connected to an external device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0129] One or more modules are stored in the memory 902 , and when executed by one or more processors 901 , perform the parallel interface testing method in any of the above method embodiments.

[0130] The above-mentioned product can execute the method provided in the embodiment of this application, and has the functional modules and beneficial effects corresponding to the execution method. For technical details not fully described in this embodiment, please refer to the method provided in the embodiment of this application.

[0131] After determining a parallel interface's test-free region based on the parallel interface's reference voltage range and timing parameter range, the present invention determines a sampling point based on the boundary of the test-free region. Using this sampling point as a starting point, the system iteratively determines multiple target sampling points, and then determines the parallel interface's eye diagram based on the number of bit errors at each target sampling point. In this embodiment of the present invention, the target sampling point is determined based on the scan step size and scan direction, and the scan step size is determined based on the number of bit errors at the previous target sampling point. This effectively reduces the number of scans and the amount of test data, thereby improving parallel interface testing efficiency.

[0132] Another embodiment of the present invention relates to a non-volatile storage medium for storing a computer-readable program, wherein the computer-readable program is used to enable a computer to execute part or all of the above method embodiments.

[0133] That is, those skilled in the art will understand that all or part of the steps in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a program, which is stored in a storage medium and includes a number of instructions for causing a device (which may be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the methods described in the embodiments of the present application. The aforementioned storage medium includes: a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, etc., various media that can store program code.

[0134] The foregoing is merely a preferred embodiment of the present application and is not intended to limit the present application. Persons skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application are intended to be within the scope of protection of the present application.

Claims

1. A parallel interface testing method, characterized in that: The method comprises: Determining a test-free region of the parallel interface to be tested according to a reference voltage range and a timing parameter range of the parallel interface to be tested; Determining a first sampling point according to a boundary point of the measurement-free area; Taking the first sampling point as a starting point, determining a plurality of target sampling points in an iterative manner; Determining an eye diagram of the parallel interface to be tested according to the number of bit errors corresponding to each target sampling point; The target sampling point is determined as follows: Scan the target sampling point to determine the corresponding number of bit errors, determine a scanning step size based on the number of bit errors, and update the next sampling point to the target sampling point based on the scanning step size and the first scanning direction until the number of bit errors at the target sampling point meets a first quantity condition and the number of bit errors at a sampling point previous to the target sampling point meets a second quantity condition.

2. The method according to claim 1, characterized in that Determining the test-free region of the parallel interface to be tested according to the reference voltage range and timing parameter range of the parallel interface to be tested includes: Determining a second sampling point of the parallel interface to be tested according to the reference voltage range and the timing parameter range, wherein the second sampling point is a reference sampling point of the parallel interface to be tested in a training phase; Taking the second sampling point as a starting point, sequentially scanning the sampling points along each second scanning direction, and determining the number of bit errors at each sampling point, until a sampling point having a non-zero number of bit errors is detected in each second scanning direction; Determine the sampling points at which the number of bit errors is not 0 as vertices of the test-free area; The detection-free area is determined according to each of the vertices.

3. The method according to claim 2, characterized in that Determining the first sampling point according to the boundary point of the measurement-free area includes: Determine sampling points that are adjacent to the boundary point and do not belong to the exempted area as candidate sampling points, wherein the boundary point includes the vertex; Determine the candidate sampling point adjacent to the vertex as the starting sampling point; Taking the starting sampling point as a starting point, iteratively determining a plurality of designated sampling points, wherein the designated sampling points are candidate sampling points spaced apart from a previous designated sampling point by a second step length in a second direction, wherein the second direction and the first scanning direction are directions of different dimensions, and the dimensions include a reference voltage dimension and a timing parameter dimension; Each of the designated sampling points is determined as the first sampling point.

4. The method according to claim 1, wherein Determining the scanning step length according to the number of bit errors includes: In response to the number of bit errors satisfying a third quantity condition, determining the scanning step length to be a third step length; In response to the number of bit errors satisfying the second quantity condition, determining the scanning step length to be a fourth step length; In response to the number of bit errors satisfying the first quantity condition, determining the scanning step length to be a fifth step length; The third step length and the fifth step length are both positive values, the third step length is smaller than the fifth step length, and the fourth step length is a negative value.

5. The method according to claim 1, wherein The method further comprises: A test result of the parallel interface to be tested is determined according to the eye diagram.

6. The method according to claim 1, characterized in that The number of bit errors corresponding to the target sampling point is determined by: In response to detecting that the number of bit errors meets the second quantity condition, accumulating the number of bit errors is stopped.

7. A parallel interface test device, characterized in that: The device comprises: An area determination unit, configured to determine a test-exempt area of ​​the parallel interface to be tested according to a reference voltage range and a timing parameter range of the parallel interface to be tested; A first sampling point determining unit, configured to determine a first sampling point according to a boundary point of the measurement-free area; a target sampling point determining unit, configured to iteratively determine a plurality of target sampling points starting from the first sampling point; An eye diagram determining unit, configured to determine an eye diagram of the parallel interface to be tested according to the number of bit errors corresponding to each target sampling point; The target sampling point is determined as follows: Scan the target sampling point to determine the corresponding number of bit errors, determine a scanning step size based on the number of bit errors, and update the next sampling point to the target sampling point based on the scanning step size and the first scanning direction until the number of bit errors at the target sampling point meets a first quantity condition and the number of bit errors at a sampling point previous to the target sampling point meets a second quantity condition.

8. An electronic device comprising a memory and a processor, characterized in that: The memory is configured to store one or more computer program instructions, wherein the one or more computer program instructions are executed by the processor to implement the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

10. A computer program product, characterized in that The computer program product comprises a computer program / instructions, which implement the method according to any one of claims 1 to 6 when executed by a processor.

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