An in-board synchronization method, device, acquisition board card and phased array radio telescope without digital function based on RFSoC

Abstract

The application relates to the technical field of synchronous processing, and discloses a board-in synchronous method without digital function based on RFSoC, which is suitable for a collection board card containing a plurality of data channels; in the case that the collection board card normally works, the time delay of the plurality of data channels in the collection board card is initialized; the time delay of the plurality of data channels is tested by using a synchronous pulse clock and a time delay synchronous clock, and the queue time delay of each data channel is obtained; in the case that there is a difference between the queue time delay of each data channel, the queue time delay is synchronously corrected, and the synchronous time delay boundary of the plurality of data channels is obtained; and the plurality of data channels are time delay-synchronously optimized based on the synchronous time delay boundary. The beneficial effect is that the queue time delay of each data channel in the collection board card is measured by using a clock signal, and the data channels are automatically synchronously optimized according to the queue time delay, the accuracy of the internal synchronization of the board card is improved, and the data channels are ensured to be in a time delay-synchronous state.

Description

Technical Field

[0001] This application relates to the field of synchronization processing technology, and in particular to an on-board synchronization method, device, acquisition board, and phased array radio telescope based on RFSoC without digital functions. Background Technology

[0002] A phased array system is an advanced technology that precisely controls the phase and amplitude of multiple antenna elements in an array to precisely regulate the transmission and reception of electromagnetic waves. With its rapid development, phased array systems have played a crucial role in various fields, including radio astronomy, radar, ultrasonic imaging, and meteorological observation, and have broad application prospects. Typically, a phased array contains multiple data channels, and the degree of synchronization between these channels significantly affects the signal quality of the phased array, even determining whether the array can function properly. Therefore, synchronization of the data channels is necessary to improve their synchronicity.

[0003] In related technologies, methods for synchronizing data channels often rely on the experience of operators, and manual operation also introduces uncertainty, so the accuracy of related solutions still needs to be improved. Summary of the Invention

[0004] This application provides an on-board synchronization method, device, acquisition board, and phased array radio telescope based on RFSoC without digital functions. It uses a clock signal to measure the queue delay of each data channel in the acquisition board and automatically optimizes the synchronization of the data channels based on the queue delay, thereby improving the accuracy of the internal synchronization of the board and ensuring that the data channels are in a time-delay synchronized state.

[0005] To achieve the above objectives, the main technical solutions adopted in this application include:

[0006] In a first aspect, embodiments of this application provide an on-board synchronization method based on RFSoC without digital functionality, applicable to acquisition boards containing several data channels; the method includes:

[0007] When the acquisition board is working normally, the latency of the several data channels in the acquisition board is initialized;

[0008] The delay of each data channel is obtained by using a synchronous pulse clock and a delay synchronization clock to perform delay tests on the data channels.

[0009] When there are differences in the queue delays of each data channel, the queue delays are synchronously corrected to obtain the synchronization delay boundaries of the data channels.

[0010] Based on the aforementioned synchronization delay boundary, the delay synchronization of the plurality of data channels is optimized so that the plurality of data channels can achieve synchronous signal acquisition.

[0011] The on-board synchronization method based on RFSoC without digital functions proposed in this application, after initializing the delay of several data channels, obtains the queue delay of each data channel using a synchronization pulse clock and a delay synchronization clock, and performs synchronization correction based on the difference between the queue delays to determine the synchronization delay boundary. This allows for automatic delay synchronization optimization of the data channels based on the synchronization delay boundary, ensuring that the data channels are in a delay-synchronized state. Compared with related technologies, this application uses a clock signal to test the delay of the data channels, improving the accuracy and feasibility of the queue delay test results. Furthermore, this application performs synchronization correction on the queue delay based on the difference between the queue delays to obtain the synchronization delay boundary used for delay synchronization optimization of the data channels. This enables the data channels to acquire synchronization signals based on the synchronization delay boundary, improving the accuracy of the synchronization reference between data channels and significantly improving the synchronization between data channels.

[0012] Optionally, the step of using a synchronization pulse clock and a delay synchronization clock to perform delay testing on the plurality of data channels to obtain the queue delay of each data channel includes:

[0013] The clock of the several data channels is calibrated according to the synchronization pulse clock to obtain the delay test clock;

[0014] The measurement start time is determined based on the time delay synchronization clock;

[0015] Based on the delay test clock and the measurement start time, delay measurement is performed on any one of the plurality of data channels to obtain the queue delay of any one data channel.

[0016] Optionally, the synchronization pulse clock is a continuously output periodic signal, and the clock calibration is performed after the process of the synchronization pulse clock being received by the plurality of data channels meets a preset capture condition.

[0017] Optionally, the step of synchronizing and correcting the queue delay to obtain the synchronization delay boundaries of the plurality of data channels includes:

[0018] The queue delay is filtered by delay boundary, and the queue delay that meets the preset delay boundary conditions is taken as the optimized delay boundary.

[0019] The synchronization delay boundary is obtained by performing redundancy delay compensation on the optimized delay boundary.

[0020] Optionally, the preset delay boundary condition is that the queue delay is the maximum value among all queue delays.

[0021] Optionally, the delay synchronization optimization of the plurality of data channels based on the synchronization delay boundary includes:

[0022] Using the time delay synchronization clock as a reference clock, the synchronization delay boundary is synchronously configured to the plurality of data channels so that the plurality of data channels begin synchronous acquisition after the synchronization delay boundary.

[0023] Optionally, the following method can be used to determine whether the acquisition board is working properly:

[0024] Perform a status check on the acquisition board;

[0025] Based on the results of the status check, it is determined whether the acquisition board is working properly.

[0026] Secondly, embodiments of this application provide an on-board synchronization device based on RFSoC without digital functionality, suitable for acquisition boards containing several data channels; the device includes:

[0027] The self-test initialization module is used to initialize the latency of the several data channels in the acquisition board when the acquisition board is working normally.

[0028] The delay test module is used to perform delay tests on the several data channels using a synchronization pulse clock and a delay synchronization clock, and to obtain the queue delay of each data channel.

[0029] The synchronization correction module is used to synchronize and correct the queue delay when there is a difference in the queue delay of each data channel, so as to obtain the synchronization delay boundary of the plurality of data channels.

[0030] The delay optimization module is used to perform delay synchronization optimization on the plurality of data channels based on the synchronization delay boundary, so that the plurality of data channels can achieve synchronous signal acquisition.

[0031] Thirdly, embodiments of this application provide an acquisition board without digital functions based on RFSoC, which performs on-board synchronization using the method described in any of the above embodiments.

[0032] Fourthly, this application provides a phased array radio telescope, including the acquisition board described in any of the above embodiments. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0034] Figure 1 This application provides a step diagram illustrating an on-board synchronization method without digital functionality based on an RFSoC.

[0035] Figure 2 This is a flowchart illustrating the latency testing steps in an embodiment of this application.

[0036] Figure 3 This is a diagram illustrating the steps for synchronizing queue latency in an embodiment of this application.

[0037] Figure 4 This is a diagram illustrating the steps for determining whether the acquisition board is working properly in an embodiment of this application.

[0038] Figure 5 A block diagram of an on-board synchronization device without digital functions based on RFSoC provided in this application embodiment;

[0039] Figure 6 This is a clock tree structure diagram of an RFSoC-based acquisition board without digital functionality in an embodiment of this application;

[0040] Figure 7 This application provides a schematic diagram of the structure of a computer device. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0042] A phased array system is an advanced technology that precisely controls the phase and amplitude of multiple antenna elements in an array to precisely regulate the transmission and reception of electromagnetic waves. With its rapid development, phased array systems have played a crucial role in various fields, including radio astronomy, radar, ultrasonic imaging, and meteorological observation, and have broad application prospects. Typically, a phased array contains multiple data channels, and the degree of synchronization between these channels significantly affects the signal quality of the phased array, even determining whether the array can function properly. Therefore, synchronization of the data channels is necessary to improve their synchronicity.

[0043] In related technologies, methods for on-board synchronization of multiple channels on a data acquisition board include fixed delay compensation and manual delay setting. Fixed delay compensation involves setting the same delay compensation value for each data channel to achieve synchronized signal acquisition. However, in practice, fixed delay compensation values ​​cannot adapt to timing variations caused by environmental changes during signal acquisition. Manual delay setting involves manually measuring the delay value of each data channel and compensating for delay based on the measurement results to ensure that the delay values ​​of each data channel are identical. However, the process of manually measuring delay values ​​is limited by the operator's experience, making it impossible to guarantee the consistency of the measurement results. Therefore, these technologies still have uncertainties, and their accuracy in synchronizing multiple data channels on a data acquisition board needs further improvement.

[0044] To address the aforementioned issues, this application provides an on-board synchronization method based on RFSoC without digital functionality, applicable to acquisition boards containing multiple data channels. Under normal operating conditions, the delay of each data channel on the acquisition board is initialized. Delay tests are performed on the data channels using a synchronization pulse clock and a delay synchronization clock to obtain the queue delay for each data channel. If differences exist between the queue delays of each data channel, the queue delays are synchronized and corrected to obtain the synchronization delay boundaries for the multiple data channels. Based on these synchronization delay boundaries, delay synchronization optimization is performed on the multiple data channels, enabling them to acquire synchronized signals.

[0045] The on-board synchronization method without digital functions based on RFSoC provided in this application, under the premise of initializing the delay of several data channels, uses the synchronization pulse clock and the delay synchronization clock to obtain the queue delay of each data channel, and performs synchronization correction according to the difference between the delays of each queue to determine the synchronization delay boundary. Thus, the data channels are automatically optimized for delay synchronization according to the synchronization delay boundary to ensure that the data channels are in a delay synchronization state.

[0046] Compared with related technologies, this application uses a clock signal to test the delay of the data channel, which improves the accuracy and feasibility of the queue delay test results. On this basis, this application also performs synchronization correction on the queue delay based on the difference between queue delays to obtain a synchronization delay boundary for delay synchronization optimization of the data channel. This enables the data channel to acquire synchronization signals based on the synchronization delay boundary, improves the accuracy of the synchronization reference between data channels, and significantly improves the synchronization between data channels.

[0047] The on-board synchronization method based on RFSoC without digital functionality provided in this manual can be applied to any acquisition board within a phased array system. Phased array systems can be used in various fields, including radio astronomy, radar, ultrasonic imaging, and meteorological observation. In radio astronomy, phased array systems can be used to construct phased array radio telescopes, enabling high-speed, real-time, and synchronous acquisition and preprocessing of large-scale, wide-band radio frequency signals. It should be noted that this acquisition board does not include digital functionality; that is, it does not perform digital signal processing on the acquired signals.

[0048] According to an embodiment of this application, an embodiment of an on-board synchronization method without digital functions based on RFSoC is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0049] This embodiment provides an on-board synchronization method without digital functionality based on RFSoC, which can be used in the aforementioned acquisition board. (Refer to...) Figure 1 As shown, this method is applicable to acquisition boards containing several data channels; the method includes:

[0050] S100. Under normal operating conditions of the acquisition board, initialize the latency of several data channels in the acquisition board.

[0051] S200. Use a synchronous pulse clock and a delay synchronization clock to perform delay tests on several data channels to obtain the queue delay of each data channel.

[0052] S300. When there are differences in the queue delay of each data channel, the queue delay is synchronously corrected to obtain the synchronization delay boundaries of several data channels.

[0053] S400. Based on the synchronization delay boundary, the delay synchronization of several data channels is optimized so that the several data channels can achieve synchronous signal acquisition.

[0054] The synchronization pulse clock can be a clock reference signal during the delay test process, used to set the starting reference for delay measurement of multiple data channels, so that each data channel can measure its own queue delay according to the same clock signal. For example, the synchronization pulse clock can be a low-frequency reference clock signal AMS_SYSREF generated and output by the clock chip on the acquisition board, and its frequency can be 10MHz, used to control the synchronization of the RFDC IP core with other modules on the acquisition board.

[0055] A delay synchronization clock can serve as a trigger reference signal during delay testing, providing a delay measurement observation window for multiple data channels. This allows each data channel to measure its queue delay within the same time range, enabling synchronization correction and delay synchronization optimization. For example, the delay synchronization clock can be a low-frequency reference clock signal PL_SYSREF generated and output by a clock chip on the acquisition board, with a frequency of 10MHz, used to control and synchronize logic operations within the programmable logic devices on the acquisition board.

[0056] Queue delay can be defined as the time delay between the entry of signal data into a First-In-First-Out (FIFO) queue and its subsequent reading from the queue. It represents the time delay between the acquisition and output of each channel's signal data. In essence, after the data channels acquire the signal data, this data first enters an independent FIFO buffer and is stored. Then, it is read sequentially according to the order in which it entered the FIFO buffer for subsequent signal processing.

[0057] Synchronization delay boundaries can be the same channel delay setting across all data channels. This ensures that even with different queue delays, each data channel can achieve synchronized acquisition and output of signals, reducing timing misalignment between data channels. Understandably, the duration of the synchronization delay boundary exceeds the queue delay of any data channel to ensure that the synchronization between data channels is not affected by differences in queue delays.

[0058] Specifically, for acquisition boards requiring on-board synchronization, the first step is to enable the synchronous sampling clock, synchronous pulse clock, and delay synchronization clock on the acquisition board. The synchronous sampling clock serves as the reference clock for each data channel during signal acquisition, enabling all data channels to acquire signals synchronously and reducing timing errors introduced during signal acquisition. Secondly, it is determined whether the acquisition board is functioning correctly, ensuring that the initial states of multiple modules and data channels on the acquisition board are stable and that no faults have occurred within the acquisition board, allowing the synchronization process between data channels to begin. If the acquisition board is determined to be functioning correctly, the delay settings of each data channel on the acquisition board are initialized to ensure that the initial delay of each data channel is the same before delay testing, improving the accuracy of delay testing and thus improving the accuracy of on-board synchronization. For example, the delay initialization process can be implemented by calling an API function. For Xilinx's RFDC IP core, the API function called could be XRFdc_MultiConverter_Sync.

[0059] Furthermore, a synchronization pulse clock and a delay synchronization clock are used as reference clocks for each data channel to align the delay test, ensuring timing consistency during the delay test process and thus improving the accuracy of the obtained queue delay. After clock alignment, delay test commands are issued to each data channel to control it to enter automatic delay test mode, obtaining the queue delay for each data channel. It should be noted that in automatic delay test mode, multiple data channels start delay testing simultaneously, reducing timing errors that may occur when each data channel performs delay testing individually. Moreover, each data channel automatically performs delay testing without manual intervention, reducing the impact of operator experience on the delay test results and improving the efficiency and accuracy of the delay test. For example, the delay test command can be issued by setting an initial delay for each data channel. For Xilinx's RFDC IP core, this can be done by setting the Target_latency of each data channel to -1 to initiate the automatic delay test mode for each data channel.

[0060] Furthermore, after obtaining the queue delays for each data channel, all queue delays are compared to determine whether synchronization correction is needed. If the duration of all queue delays is consistent, or the differences between queue delays are within a tolerable range, it indicates that the data channels are already in a time-delay synchronized state and no further synchronization correction is required. If there are differences in the queue delays of each data channel, it indicates that the data channels are in a time-delay asynchronous state. In this case, it is necessary to perform synchronization correction on the queue delays based on the time-delay distribution to determine the synchronization delay boundary used for time-delay synchronization optimization of all data channels, ensuring that the synchronization of the data channel output signals is not affected by the differences in queue delays.

[0061] Furthermore, delay synchronization optimization is performed on the data channels based on synchronization delay boundaries. The channel delay of all data channels is set to the synchronization delay boundary, ensuring that the signal data in each data channel is output after the synchronization delay boundary. It can be understood that the duration of the synchronization delay boundary exceeds the queue delay of any data channel. After the synchronization delay boundary, the signal data of all channels has been read from the FIFO buffer and is ready for output. Based on this, using a synchronization pulse clock as a reference clock, all data channels output signal data simultaneously, achieving synchronized output between the acquired signals.

[0062] It is understandable that for the same acquisition board, using the same logic file and clock system, the queue delay of each data channel is relatively stable and will not change significantly. Therefore, after determining the synchronization delay boundary of the acquisition board, the same synchronization delay boundary can also be used for the signal acquisition process of the acquisition board at different time points. By directly configuring the synchronization delay boundary, the resources consumed by the on-board synchronization process can be reduced, thereby improving the signal acquisition efficiency.

[0063] The on-board synchronization method without digital functions based on RFSoC provided in this embodiment, under the premise of initializing the delay of several data channels, uses the synchronization pulse clock and the delay synchronization clock to obtain the queue delay of each data channel, and performs synchronization correction according to the difference between the delays of each queue to determine the synchronization delay boundary. Thus, the data channels are automatically optimized for delay synchronization according to the synchronization delay boundary to ensure that the data channels are in a delay synchronization state.

[0064] Compared with related technologies, this application uses a clock signal to test the delay of the data channel, which improves the accuracy and feasibility of the queue delay test results. On this basis, this application also performs synchronization correction on the queue delay based on the difference between queue delays to obtain a synchronization delay boundary for delay synchronization optimization of the data channel. This enables the data channel to acquire synchronization signals based on the synchronization delay boundary, improves the accuracy of the synchronization reference between data channels, and significantly improves the synchronization between data channels.

[0065] Reference Figure 2 As shown, in one embodiment of this application, a delay test is performed on several data channels using a synchronization pulse clock and a delay synchronization clock to obtain the queue delay of each data channel, including:

[0066] S210. Perform clock calibration on several data channels based on the synchronization pulse clock to obtain the delay test clock.

[0067] S220. Determine the measurement start time based on the time delay synchronization clock.

[0068] S230. Based on the delay test clock and the measurement start time, perform delay measurement on any one of the several data channels to obtain the queue delay of any one data channel.

[0069] The synchronous pulse clock and the delay synchronous clock have the same clock frequency, and the phase difference between them is constant.

[0070] Specifically, each data channel receives a synchronization pulse clock and a delay synchronization clock. Each data channel uses the synchronization pulse clock as its own clock reference signal, aligning its own clock to the synchronization pulse clock to obtain a common delay test clock for all data channels. It can be understood that when performing delay testing using the delay test clock, the starting time of the measurement operation is determined by the rising edge of each cycle of the synchronization pulse clock. Based on the delay test clock, each data channel can synchronously measure the queue delay according to the same clock signal, effectively improving the synchronization between data channels during delay testing. Furthermore, the synchronization pulse clock can be stably captured by the data channels, and its stability further improves the synchronization of the data channels during delay testing.

[0071] Furthermore, the programmable logic area corresponding to the data channel is clock-aligned based on the delay synchronization clock, aligning the clock within the programmable logic area with the delay synchronization clock. This allows the programmable logic area to issue delay test instructions based on the delay synchronization clock, thus actually executing the delay test process. On this basis, the starting time of the measurement operation is determined according to the rising edge of each cycle of the delay synchronization clock, serving as the measurement start time. It should be noted that since the synchronization pulse clock and the delay synchronization clock have the same clock frequency, the measurement start time corresponds to the rising edge of the synchronization pulse clock, ensuring that the delay test process is synchronized with the delay test clock. This allows delay testing to be performed with the same clock reference signal, improving the synchronization of the data channel during delay testing.

[0072] Furthermore, based on the measurement start time, a delay measurement command is issued through the programmable logic area within the data channel. Using the rising edge of the delay test clock as the measurement reference point, delay measurements are performed on each data channel to obtain the queue delay for each data channel. It is understandable that, under the premise of the same delay test clock, the measurement start time for each data channel is the same, allowing each data channel to start delay testing simultaneously. This reduces the impact of timing errors on the delay test results and improves the accuracy of the queue delay.

[0073] As one embodiment of this application, the synchronization pulse clock is a continuously output periodic signal, and clock calibration is performed after the synchronization pulse clock is received by several data channels and the preset capture conditions are met.

[0074] Specifically, when enabling the clock signal required by the acquisition board, it is necessary to ensure that the synchronization pulse clock is in a periodic and continuous output state to improve the clock stability of the synchronization pulse clock, thereby improving the timing synchronization between data channels when the synchronization pulse clock is used as the reference clock signal. In addition, the periodicity of the synchronization pulse clock also allows the delay test to be repeated multiple times, improving the accuracy of the delay test results.

[0075] Furthermore, the preset acquisition conditions can be that the data channel can stably acquire the synchronization pulse clock, the acquired synchronization pulse clock has little or no clock jitter, the rising edge position of the synchronization pulse clock is predictable, and the period condition is met between adjacent rising edges. Whether the process of the synchronization pulse clock being received by several data channels meets the preset acquisition conditions can be determined by the synchronization state machine within the data channel. If the preset acquisition conditions are not met, clock calibration is not performed until the preset acquisition conditions are met.

[0076] It should be noted that before the synchronization pulse clock is received by the data channels, its path includes the clock source and several other modules. These modules may introduce timing errors in their output synchronization pulse clock due to their own inherent factors or environmental factors, leading to a decrease in the stability of the synchronization pulse clock. By determining whether the process of the synchronization pulse clock being received by several data channels meets the preset capture conditions, the stability of the synchronization pulse clock used for clock calibration can be ensured, reducing the uncertainty caused by unstable clock signals to the on-board synchronization, thereby improving the synchronization between data channels after on-board synchronization.

[0077] Reference Figure 3 As shown, in one embodiment of this application, the queue delay is synchronized and corrected to obtain the synchronization delay boundaries of several data channels, including:

[0078] S310. Perform delay boundary filtering on queue delay, and take the queue delay that meets the preset delay boundary conditions as the optimized delay boundary.

[0079] S320. Perform redundant delay compensation on the optimized delay boundary to obtain the synchronization delay boundary.

[0080] Specifically, the queue delay of each data channel is compared with a preset delay boundary condition. The queue delay that meets the preset delay boundary condition is selected from multiple queue delays and used as the optimized delay boundary. For example, the preset delay boundary condition can be the maximum, minimum, average, or median value of the queue delay, which can be determined according to the actual needs of the scenario.

[0081] Furthermore, to improve the reliability of the optimized delay boundary, redundant delay compensation is performed based on the optimized delay boundary, ensuring that all queue delays are within the range of the synchronization delay boundary, and guaranteeing that the synchronization of the data channel output signal is not affected by queue delay differences. For example, when the preset delay boundary condition is the maximum value in the queue delay, redundant delay compensation can be achieved by adding a delay of multiple clock cycles to the optimized delay boundary; the number of clock cycles can be 16.

[0082] As one embodiment of this application, the preset delay boundary condition is that the queue delay is the maximum value among all queue delays.

[0083] Specifically, when the optimization delay boundary is the maximum value in the queue delay, after passing the synchronization delay boundary, the signal data of all data channels has been read from the FIFO buffer and is ready to be output. This ensures that all data channels can output signal data synchronously, avoiding the situation where data channels with large queue delays and small queue delays cannot output synchronously, and reducing the probability of data loss or data inconsistency.

[0084] Understandably, using the maximum value among all queue delays as the preset delay boundary condition ensures that even if the queue delay of any data channel is too large compared to other data channels, all data channels can still output signal data synchronously, thus improving the stability of the on-board synchronization results.

[0085] As one embodiment of this application, delay synchronization optimization is performed on several data channels based on synchronization delay boundaries, including:

[0086] S410. Use the time delay synchronization clock as the reference clock, and synchronously configure the synchronization time delay boundary to several data channels so that several data channels start synchronous acquisition after the synchronization time delay boundary.

[0087] Specifically, the time-delay synchronization clock, serving as the reference clock signal for the programmable logic area in the data channel, ensures that the synchronous operations of each data channel are performed simultaneously. By synchronously configuring the synchronization delay boundary for each data channel, timing errors caused by configuration lag in any data channel during signal acquisition are avoided. Simultaneously, clock drift and synchronization errors between data channels are reduced, effectively improving the stability of multiple data channels within the acquisition board during synchronous signal acquisition. For example, for Xilinx's RFDC IP core, setting the synchronization delay boundary can be done by calling an API function, such as XRFdc_MultiConverter_Sync.

[0088] Reference Figure 4 As shown, in one embodiment of this application, the following method is used to determine whether the acquisition board is working properly:

[0089] S110. Perform a status check on the acquisition board.

[0090] S120. Determine whether the acquisition board is working properly based on the status check results.

[0091] Specifically, the status checks include module enable status checks, phase-locked loop (PLL) status checks, power-on status checks, and channel enable status checks. Enable status checks can be performed on any module on the acquisition board to determine if it is enabled. PLL status checks can be performed on the PLL on the acquisition board to determine if it is in a phase-locked state or operating normally, thus ensuring the stability of multiple clock signals on the acquisition board. Power-on status checks can be performed on any module on the acquisition board to determine if it is powered on and operating normally. Channel enable status checks can be performed on any data channel on the acquisition board to determine if each data channel is enabled, ensuring that each data channel can participate in synchronization operations during on-board synchronization.

[0092] Furthermore, the status check process includes: checking the module enable status of the acquisition board to obtain its module enable status; if the module enable mode meets the preset module enable mode requirements, checking the phase-locked state of the acquisition board to obtain its phase-locked state; if the phase-locked mode meets the preset phase-locked mode requirements, checking the power-on status of the acquisition board to obtain its power-on status; if the power-on mode meets the preset power-on mode requirements, checking the channel enable status of the acquisition board to obtain its channel enable status; if the channel enable mode meets the preset channel enable mode requirements, determining that the acquisition board can work normally.

[0093] Accordingly, please refer to Figure 5 This application provides an on-board synchronization device without digital functionality based on RFSoC, suitable for acquisition boards containing several data channels; the device includes:

[0094] The self-test initialization module 510 is used to initialize the latency of several data channels in the acquisition board when the acquisition board is working normally.

[0095] The delay test module 520 is used to perform delay tests on several data channels using a synchronization pulse clock and a delay synchronization clock to obtain the queue delay of each data channel.

[0096] The synchronization correction module 530 is used to synchronize and correct the queue delay when there is a difference in the queue delay of each data channel, so as to obtain the synchronization delay boundary of several data channels.

[0097] The delay optimization module 540 is used to optimize the delay synchronization of several data channels based on the synchronization delay boundary, so that the several data channels can achieve synchronous signal acquisition.

[0098] In some alternative implementations, the latency test module 520 includes:

[0099] The clock calibration unit is used to calibrate the clocks of several data channels according to the synchronization pulse clock to obtain the delay test clock.

[0100] The time determination unit is used to determine the measurement start time based on the time delay synchronization clock.

[0101] The delay measurement unit is used to perform delay measurement on any one of several data channels based on the delay test clock and the measurement start time, so as to obtain the queue delay of any one data channel.

[0102] In some optional implementations, in the delay test module 520, the synchronization pulse clock is a continuously output periodic signal, and clock calibration is performed after the synchronization pulse clock is received by several data channels and a preset capture condition is met.

[0103] In some alternative implementations, the synchronization correction module 530 includes:

[0104] The delay boundary filtering unit is used to filter the queue delay boundary and take the queue delay that meets the preset delay boundary conditions as the optimized delay boundary.

[0105] The redundant delay compensation unit is used to perform redundant delay compensation on the optimized delay boundary to obtain the synchronization delay boundary.

[0106] In some optional implementations, in the synchronization correction module 530, the preset delay boundary condition is that the queue delay is the maximum value among all queue delays.

[0107] In some optional implementations, the latency optimization module 540 includes:

[0108] The synchronization configuration unit is used to use the time delay synchronization clock as a reference clock and to synchronously configure the synchronization delay boundary to several data channels so that the several data channels can start synchronous acquisition after the synchronization delay boundary.

[0109] In some optional implementations, the self-test initialization module 510 includes:

[0110] The board status check unit is used to check the status of the acquisition board.

[0111] The working status judgment unit is used to determine whether the acquisition board is working properly based on the results of the status check.

[0112] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0113] In this embodiment, the on-board synchronization device without digital functions based on RFSoC is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0114] This application provides an RFSoC-based data acquisition board without digital functionality, which performs on-board synchronization using the method described in any of the above embodiments.

[0115] Reference Figure 6 As shown, the acquisition board provided in this embodiment is designed with a synchronous clock tree based on a single clock chip. This synchronous clock tree includes a clock chip, a PL MMCM divider, an RF clock chip, and an RFDC IP core. The RFDC IP core contains multiple data channels, represented by ADC tiles. All data channels operate in the same mode and are configured with the same operating parameters. The clock chip, as the foundation of the synchronous clock tree, generates a unified clock signal and sends it to multiple modules on the acquisition board, providing a synchronous clock foundation for each module. It can be understood that a single clock chip outputs a unified clock signal, reducing clock drift and errors between multiple clock signals and improving timing consistency. Furthermore, the single clock chip simplifies the hardware design of the acquisition board, reduces module complexity, and improves the hardware stability and ease of use of the acquisition board.

[0116] The PL MMCM frequency divider is used to divide the clock signal output by the clock chip, generating the ADC parallel data output clock AXIS_clock and the back-end signal processing clock USER_clock to control the output and processing of the acquired signals, ensuring synchronization between different acquired signals in the process. The PL MMCM frequency divider also includes clock frequency conversion, clock phase control, clock division and multiplication, and clock synchronization. It can be understood that the acquired signals are synchronously output to the RFSoCFPGA processing chip on the acquisition board for synchronous signal processing. For example, the frequency of the ADC parallel data output clock AXIS_clock can be 250MHz, and the frequency of the back-end signal processing clock USER_clock can be 350MHz.

[0117] The RF clock chip receives the clock signal sent by the clock chip, derives a synchronous sampling clock based on this clock signal, and synchronously sends it to the RFDC IP core. This provides the synchronous clock basis for the signal acquisition process of the data channels, enabling the data channels to perform synchronous signal acquisition. After receiving the clock signal from the clock chip, the RF clock chip performs clock operations on the clock signal to obtain the synchronous sampling clock for transmission to the RFDC IP core. When the frequency of the synchronous sampling clock is outside the clock frequency range corresponding to the clock chip, the clock chip cannot directly generate the synchronous sampling clock for the RFDC IP core. Therefore, the RF clock chip needs to perform clock operations on the clock signal to generate a synchronous sampling clock that meets the actual requirements. For example, the clock operation can be clock frequency multiplication or clock phase adjustment, etc.

[0118] The RFDC IP core receives the synchronous acquisition signal sent by the RF clock chip and internally distributes the synchronous sampling clock to multiple data channels, enabling all data channels to acquire signals synchronously based on the synchronous sampling clock. Data channels can be analog-to-digital converter (ADC) channels, which convert analog signals into digital signals after acquisition for further signal processing and analysis.

[0119] In some embodiments, the RFDC IP core may have only a single input terminal, which can be the input terminal of the first channel among multiple data channels. After receiving an external input signal, the first channel internally distributes the input signal to the other data channels to operate according to the input signal. It is understood that the first channel serves as the reference channel for all data channels and is active in subsequent synchronous processing and synchronous acquisition. Other data channels are synchronized with the first channel, effectively improving the synchronization between data channels. Furthermore, a single input terminal reduces the hardware resources required to configure the RFDC IP core, lowers the complexity of module connection design on the acquisition board, and improves the integration of the acquisition board.

[0120] Among the aforementioned modules, the output of the clock chip is connected to the input of the RF clock chip, and the outputs of the RF clock chip and the clock chip are respectively connected to the input of the RFDC IP core. The input of the PL MMCM divider is connected to the output of the clock chip. The RFDC IP core receives a synchronous sampling clock from the RF clock chip based on its connection to the RF clock chip, and receives a synchronous pulse clock AMS_SYSREF and a delay synchronization clock PL_SYSREF from the clock chip based on its connection to the clock chip. For example, the frequency of the synchronous sampling clock can be 4 GHz, the frequency of the synchronous pulse clock AMS_SYSREF can be 10 MHz, and the frequency of the delay synchronization clock PL_SYSREF can be 10 MHz.

[0121] Before the data channel begins acquiring synchronization signals, the RFDC IP core receives the synchronization pulse clock AMS_SYSREF and the delay synchronization clock PL_SYSREF, using them as reference clocks. On-board synchronization of the data channel is performed based on AMS_SYSREF and PL_SYSREF to optimize delay synchronization using the obtained synchronization delay boundaries. Furthermore, pulse-triggered synchronization of the data channel is performed based on AMS_SYSREF, eliminating delay and phase errors between different data channels and ensuring timing alignment across multiple data channels, thus improving synchronization consistency. It should be noted that both AMS_SYSREF and PL_SYSREF are generated by the clock chip, have the same clock frequency, and possess a constant phase difference.

[0122] In some embodiments, the pulse-triggered synchronization process includes: turning off the reference signal receivers of each data channel and stopping the reception of the synchronization pulse clock AMS_SYSREF; calling API functions to perform initial phase settings and application configuration updates for each data channel, and setting the mixing trigger source of each data channel to the synchronization pulse clock AMS_SYSREF; turning on the reference signal receivers of each data channel so that each data channel synchronously receives the synchronization pulse clock AMS_SYSREF; capturing multiple cycles of the synchronization pulse clock AMS_SYSREF, using the pulse signal of the synchronization pulse clock AMS_SYSREF in each cycle as a trigger signal to perform phase synchronization on each data channel to align the phases of each data channel; turning off the reference signal receivers of each data channel after the aforementioned multiple cycles of the synchronization pulse clock AMS_SYSREF, stopping the reception of the synchronization pulse clock AMS_SYSREF, to lock the phase settings of each data channel and ensure phase synchronization between data channels.

[0123] This application also provides a phased array radio telescope, including the acquisition board described in any of the above embodiments.

[0124] Please see Figure 7 , Figure 7This is a schematic diagram of a computer device according to an embodiment of this application. As shown in the figure, the computer device includes one or more processors 10, a memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components communicate with each other using different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface). In some alternative embodiments, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 7 Take a processor 10 as an example.

[0125] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0126] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0127] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0128] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0129] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0130] This application also provides a computer-readable storage medium. The methods described in this application can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code downloaded over a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the methods shown in the above embodiments are implemented.

[0131] This application provides a computer program product including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the method of any embodiment of this application.

[0132] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and all such modifications and variations fall within the scope defined by the appended claims.

[0133] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, a computer can be, for example, a personal computer, laptop computer, cellular phone, camera phone, smartphone, personal digital assistant, media player, navigation device, email device, game console, tablet computer, wearable device, or any combination of these devices.

[0134] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0135] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0136] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0137] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

[0138] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. An in-board synchronization method without digital functionality based on RFSoC, characterized in that, The method is suitable for a collection board card comprising a plurality of data channels, and comprises the following steps: In the case that the collection board card is in normal operation, the time delay of the plurality of data channels in the collection board card is initialized; The plurality of data channels are tested for time delay by using a synchronous pulse clock and a time delay synchronous clock, so as to obtain a respective queue time delay of each data channel; wherein the queue time delay is a delay value between the time when signal data enters a first-in-first-out queue and the time when the signal data is read out from the queue, and represents the time delay between the signal collection and the signal output of each of the plurality of channels; In the case that there is a difference between the respective queue time delays of each data channel, the queue time delays are corrected synchronously, so as to obtain a synchronous time delay boundary of the plurality of data channels; The queue time delays of the plurality of data channels are all set to the synchronous time delay boundary, so that the signal data in the plurality of data channels are all output after the synchronous time delay boundary; wherein the synchronous time delay boundary is a same channel time delay setting between the plurality of data channels, and the time length of the synchronous time delay boundary exceeds the queue time delay of any data channel.

2. The method of claim 1, wherein, The step of testing the plurality of data channels for time delay by using a synchronous pulse clock and a time delay synchronous clock, so as to obtain a respective queue time delay of each data channel, comprises the following steps: The plurality of data channels are clocked according to the synchronous pulse clock, so as to obtain a time delay test clock; A measurement start time is determined according to the time delay synchronous clock; Any data channel in the plurality of data channels is measured for time delay according to the time delay test clock and the measurement start time, so as to obtain the queue time delay of the data channel.

3. The method of claim 2, wherein, The synchronous pulse clock is a periodic signal output continuously, and the clocking is performed after the process in which the synchronous pulse clock is received by the plurality of data channels meets a preset capture condition.

4. The method of claim 1, wherein, The step of correcting the queue time delays synchronously, so as to obtain a synchronous time delay boundary of the plurality of data channels, comprises the following steps: The queue time delays are screened for a time delay boundary, and a queue time delay meeting a preset time delay boundary condition is taken as an optimized time delay boundary; The optimized time delay boundary is compensated for redundancy delay, so as to obtain the synchronous time delay boundary.

5. The method of claim 4, wherein, The preset time delay boundary condition is that the queue time delay is the maximum value among all the queue time delays.

6. The method of claim 1, wherein, The step of setting the queue time delays of the plurality of data channels to the synchronous time delay boundary, comprises the following steps: The time delay synchronous clock is taken as a reference clock, and the synchronous time delay boundary is synchronously configured to the plurality of data channels, so that the plurality of data channels start synchronous collection after the synchronous time delay boundary.

7. The method of claim 1, wherein, Whether the collection board card is in normal operation is determined by the following method: The collection board card is checked for state; Whether the collection board card is in normal operation is determined based on the result of the state checking.

8. An in-board synchronization device without digital functionality based on RFSoC, characterized in that, The device is suitable for a collection board card comprising a plurality of data channels, and comprises the following modules: A self-check initialization module, configured to initialize the time delay of the plurality of data channels in the collection board card in the case that the collection board card is in normal operation; a time delay test module, configured to perform time delay test on the plurality of data channels by using the synchronization pulse clock and the time delay synchronization clock to obtain a respective queue time delay of each data channel; wherein the queue time delay is a delay value between when signal data enters a first-in-first-out queue and when the signal data is read out from the queue, and represents a time delay between when the signal data is collected and when the signal data is outputted in each of the plurality of channels; a synchronization correction module, configured to correct the queue time delays synchronously when there is a difference between the respective queue time delays of each data channel to obtain a synchronization time delay boundary of the plurality of data channels; a time delay optimization module, configured to set the queue time delays of the plurality of data channels to be the synchronization time delay boundary, so that the signal data in the plurality of data channels is outputted after the synchronization time delay boundary; wherein the synchronization time delay boundary is a same channel time delay setting between the plurality of data channels, and a time length of the synchronization time delay boundary is longer than the queue time delay of any data channel.

9. An RFSoC-based acquisition board without digital functionality, comprising: In-plate synchronization is performed by the method of any one of claims 1-7.

10. A phased array radio telescope, characterized in that, The acquisition board card of claim 9 is included.

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