Backplane system and storage system

Abstract

The application discloses a backboard system and a storage system, relates to the technical field of backboards, and provides a backboard system which is provided with a plurality of storage device slots, each of the storage device slots is provided with a corresponding signal multiplexing circuit and a protocol switching processor, the storage device slot is used for inserting a first solid state disk or a second solid state disk, the first solid state disk is a solid state disk based on a first communication protocol, the second solid state disk is a solid state disk which is directly connected with a host through an interconnection high-speed bus and is based on a second communication protocol; the signal multiplexing circuit is used for transmitting transmission data of a target communication protocol to the host, the target communication protocol is the first communication protocol or the second communication protocol; and the protocol switching processor is used for switching the communication protocol of the signal multiplexing circuit according to the pin signal of a protocol identification pin of the corresponding storage device slot. The overall efficiency of the storage system can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of backplane, and particularly relates to a backplane system and a storage system. BACKGROUND

[0002] NVMe (Non-Volatile Memory Express) solid state disk (SSD) is an interface specification and hardware product specially designed for high-speed non-volatile storage. Its core advantage lies in the adoption of a PCIe direct connection architecture to directly establish a data channel with a PCIe channel of a CPU.

[0003] In the related art, the hardware logic and the driver program of a redundant array of independent disks (RAID) controller only support SAS / SATA bus transmission and cannot directly configure an NVMe hard disk into a RAID group, schedule reading and writing, and recover faults. If a software RAID solution is used instead, a large amount of CPU computing resources will be occupied, the performance advantage of the NVMe SSD will be offset, and the overall efficiency of the storage system will be reduced. SUMMARY

[0004] The present application provides a backplane system and a storage system to at least solve the problem of reduced overall efficiency of the storage system in the related art.

[0005] In a first aspect, the present application provides a backplane system, which is provided with a plurality of storage device slots, each storage device slot is provided with a corresponding signal multiplexing circuit and a protocol switching processor, the protocol switching processor is connected with the protocol identification pin and the signal multiplexing circuit of the corresponding storage device slot, respectively, and the signal multiplexing circuit of each storage device slot is connected with a host, wherein,

[0006] The storage device slot is used for plugging a first solid state disk or a second solid state disk, the first solid state disk is a solid state disk based on a first communication protocol, and the second solid state disk is a solid state disk directly connected with the host through an interconnection high-speed bus and based on a second communication protocol;

[0007] The signal multiplexing circuit is used for sending transmission data of a target communication protocol to the host, the target communication protocol being the first communication protocol or the second communication protocol;

[0008] The protocol switching processor is used for switching the communication protocol of the signal multiplexing circuit according to the pin signal of the protocol identification pin of the corresponding storage device slot.

[0009] In a second aspect, the application further provides a storage system, comprising the backboard system of any one of the above, a solid state disk corresponding to each storage device slot, and a baseboard management controller, wherein,

[0010] The baseboard management controller is configured to send a notification instruction to each solid state disk via a third communication protocol bypassing the storage logic controller, the notification instruction being configured to instruct the solid state disk to erase or reuse a data block.

[0011] The backboard system and the storage system provided by the application have the following advantages. The backboard system is provided with a plurality of storage device slots and a signal multiplexing circuit, and each storage device slot is provided with a corresponding protocol switching processor. The storage device slot can be connected with a first solid state disk or a second solid state disk. The first solid state disk can be an NVMe hard disk, and the second solid state disk can be a storage device based on SAS / SATA bus transmission. The signal multiplexing circuit can send transmission data of a target communication protocol to a host. The protocol switching processor can switch the communication protocol of the signal multiplexing circuit according to the pin signal of the corresponding storage device slot. The protocol switching processor can support the first solid state disk and the second solid state disk at the same time, retain the performance advantage of the NVMe hard disk, and perform RAID group configuration, read / write scheduling, and fault recovery, thereby improving the overall efficiency of the storage system. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0013] Figure 1 The application scenario provided for the embodiments of the application is shown in the schematic diagram.

[0014] Figure 2 The structure schematic diagram of a backboard system provided for the embodiments of the application is shown.

[0015] Figure 3 The structure schematic diagram of a storage device slot provided for the embodiments of the application is shown.

[0016] Figure 4 The structure schematic diagram of another backboard system provided for the embodiments of the application is shown. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0018] It should be noted that in the description of the present application, the terms "comprise", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms "first", "second" and the like in the present application are used to distinguish similar objects, not to describe a specific order or sequence.

[0019] NVMe protocol: NVMe is a high-performance host controller interface specification designed specifically for solid-state drives, which communicates directly with the CPU through the PCIe bus, bypassing the traditional SATA / SAS controller. The NVMe protocol significantly improves the throughput and IOPS (input / output operations per second) of storage devices, supports multi-queue parallel processing, and reduces latency.

[0020] Solid State Drive (SSD): A hard drive that uses flash memory chips as storage media, which has faster read and write speeds and lower latency than traditional mechanical hard drives, and is the core storage medium of modern high-performance storage systems.

[0021] PCIe bus: PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion bus standard that supports high-bandwidth data transmission. NVMe SSDs are usually connected through PCIe interfaces, and the latest PCIe Gen5 standard has a single-channel bandwidth of up to 32GT / s.

[0022] RAID (Redundant Array of Independent Disks): RAID is a technology that combines multiple disks into a logical unit to improve performance, redundancy, or both. Common RAID levels include: RAID 0: striping, improves performance but has no redundancy. RAID 1: mirroring, provides data redundancy. RAID 5 / 6: striping plus distributed parity, balances performance and redundancy.

[0023] Traditional RAID controller: Traditional hardware RAID cards usually rely on SATA / SAS interfaces to manage hard drives, but cannot directly support the PCIe direct connection architecture of NVMe hard drives.

[0024] Figure 1 The application scenario provided by the embodiment of the present application is shown in the following figure. Please refer to Figure 1 The storage system 100 is a high-performance storage solution with software-defined storage as the core architecture, including a host 101, a hard disk controller 102, and a plurality of solid state disks 103. Each component works together to achieve efficient and reliable data storage and management.

[0025] The host 101 is the computing and control core of the entire system. In addition to bearing the regular business computing tasks, it also integrates a storage logic module. The storage logic module adopts a software RAID (Redundant Array of Independent Disks) architecture and has rich storage management capabilities, bearing core logic such as data striping, check computation, and fault recovery scheduling.

[0026] The hard disk controller 102 is the protocol conversion and data transmission hub between the host 101 and the solid state disks 103. The hard disk controller 102 is connected to the host 101 through a PCIe channel and is responsible for managing NVMe protocol-related operations such as I / O submission queue processing and data transmission scheduling.

[0027] The plurality of solid state disks 103 are solid state disks corresponding to the storage logic module and are connected to the hard disk controller 102. Among them, the solid state disk 103 can be an NVMe hard disk, and the hard disk controller 102 can be an NVMe controller.

[0028] In related technologies, the hardware logic and driver program of the RAID controller only support SAS / SATA bus transmission and cannot directly configure RAID groups, read and write scheduling, and fault recovery for NVMe hard disks. A software RAID module can be used instead, but it will consume a large amount of CPU computing resources, offsetting the performance advantages of NVMe SSDs, and reducing the overall efficiency of the storage system.

[0029] In the embodiment of the present application, a plurality of storage device slots and signal multiplexing circuits are provided on the backplane system, and each storage device slot is provided with its corresponding protocol switching processor. The backplane system is provided with a plurality of storage device slots, each storage device slot is provided with its corresponding signal multiplexing circuit and protocol switching processor, the protocol switching processor is connected with the protocol identification pin and the signal multiplexing circuit of the corresponding storage device slot respectively, and each storage device slot is connected with the host. The storage device slot can be plugged into a first solid state disk or a second solid state disk, the first solid state disk can be an NVMe hard disk, the second solid state disk can be a storage device based on SAS / SATA bus transmission, the signal multiplexing circuit can send transmission data of the target communication protocol to the host, and the protocol switching processor can switch the communication protocol of the signal multiplexing circuit according to the pin signal of the corresponding storage device slot.

[0030] The first solid state disk and the second solid state disk can be supported simultaneously by the protocol switching processor, the performance advantages of the NVMe hard disk are retained, and the RAID group configuration, read-write scheduling and fault recovery are performed, so that the overall efficiency of the storage system can be improved.

[0031] Figure 2 A structural schematic diagram of a backplane system provided by an embodiment of the present application is shown in FIG. 1. Referring to FIG. 1, the backplane system includes a plurality of storage device slots, and each storage device slot is provided with a corresponding signal multiplexing circuit and a protocol switching processor. Figure 2 The protocol switching processor is connected with the protocol identification pin and the signal multiplexing circuit of the corresponding storage device slot, and the signal multiplexing circuit of each storage device slot is connected with the host.

[0032] The storage device slot can be used to plug in the first solid state disk or the second solid state disk.

[0033] The first solid state disk can be a solid state disk based on a first communication protocol. The first communication protocol is the SAS / SATA protocol.

[0034] SAS is the serial attached small computer system interface (Serial Attached SCSI), and the SAS protocol is a high-performance serial interface protocol used to connect storage devices (such as hard disks and solid state disks). The SAS protocol can include three sub-protocols, namely the serial SCSI protocol (SSP), the SCSI management protocol (SMP) and the SATA tunneling protocol (STP). The SSP is used to transmit SCSI commands, the SMP is used for device maintenance and management, and the STP is used to realize data transmission between SAS and SATA devices.

[0035] SATA is the serial advanced technology attachment (Serial Advanced Technology Attachment), and SATA is a hard disk interface standard based on serial technology.

[0036] The SAS interface is downward compatible with the SATA hard disk at the physical layer and the protocol layer (i.e., the SATA hard disk can be directly connected to the SAS environment), but the SATA interface is not compatible with the SAS hard disk.

[0037] The second solid state disk can be a solid state disk directly connected with the host through an interconnection high-speed bus and based on a second communication protocol.

[0038] The interconnection high-speed bus is a Peripheral Component Interconnect Express (PCIe) bus. The PCIe bus is a high-speed serial computer expansion bus standard used to connect CPUs with high-performance peripherals (such as graphics cards, solid-state disks, network cards, etc.).

[0039] The second communication protocol is the NVMe protocol. The NVMe (Non-Volatile Memory Express) protocol is a high-performance storage protocol designed specifically for solid-state disks. Based on the NVMe protocol, the host can be directly connected to the solid-state disk through the PCIe bus.

[0040] The backplane can be used to connect the physical circuit boards of multiple electronic components (such as storage device slots and processors). Its main function is to provide signal transmission paths, power distribution, and mechanical support, replacing traditional cable connections.

[0041] In practical applications, a 12-layer backplane can connect each storage device slot through a differential signal layer to achieve stable signal transmission and device integration, and is the core hardware carrier of a multi-slot storage system. Each layer of the backplane supports 8 storage device slots, and each slot can be configured with an independent power control circuit, a built-in temperature sensor, and an air flow guide device.

[0042] For any storage device slot, the storage device slot includes multiple connection pins, which include multiple first pins for connecting the first solid-state disk, multiple second pins for connecting the second solid-state disk, and common pins. Among them, the common pins can include power pins and ground pins.

[0043] The connection pin is a metal contact on the storage device slot used to achieve "mechanical connection" and "signal / power transmission".

[0044] The first pin can transmit SAS / SATA protocol signals (such as SCSI commands and data) to connect the first solid-state disk; the second pin can transmit PCIe bus signals and NVMe protocol signals to connect the second solid-state disk; and the common pin can be used to transmit power (such as VCC) and ground (GND) signals, which can be shared by the two solid-state disks.

[0045] Each storage device slot is provided with its corresponding protocol switching processor. The protocol switching processor is connected to each pin of the corresponding storage device slot, and the protocol switching processors of multiple storage device slots are connected to the signal multiplexing circuit.

[0046] The protocol switching processor can control the signal multiplexing circuit to switch the communication protocol, so as to ensure that the signals transmitted between the slot and the host computer conform to the protocol standard of the current hard disk (for example, when an NVMe hard disk is identified, the PCIe / NVMe protocol is switched).

[0047] The storage device slot further includes a protocol identification pin, and the protocol switching processor can switch the communication protocol of the signal multiplexing circuit according to the pin signal of the protocol identification pin.

[0048] When solid state disks of different protocols (SAS / SATA vs. NVMe) access the storage device slot, different pin signals will be output from the pin (for example, a SAS / SATA hard disk outputs a low level, and an NVMe hard disk outputs a high level).

[0049] According to the pin signal of the protocol identification pin, it is determined whether the first solid state disk (SAS / SATA) or the second solid state disk (NVMe) is accessed.

[0050] The signal multiplexing circuit can switch the signal path and the protocol type of the circuit under the control of the protocol switching processor (for example, between the SAS / SATA protocol and the NVMe protocol), and can realize multiple storage device slots and multiplex the protocol interface resources of the host computer.

[0051] In the embodiments of the present application, a plurality of storage device slots and signal multiplexing circuits are provided on the backplane system, and each storage device slot is provided with a corresponding protocol switching processor. The storage device slot can be plugged into a first solid state disk or a second solid state disk, the first solid state disk can be an NVMe hard disk, the second solid state disk can be a storage device based on SAS / SATA bus transmission, the signal multiplexing circuit can send transmission data of the target communication protocol to the host computer, and the protocol switching processor can switch the communication protocol of the signal multiplexing circuit according to the pin signal of the corresponding storage device slot. The protocol switching processor can support the first solid state disk and the second solid state disk at the same time, retain the performance advantages of the NVMe hard disk, and perform RAID group configuration, read / write scheduling and fault recovery, so as to improve the overall efficiency of the storage system.

[0052] Specifically, the protocol switching processor can obtain the pin signal of the protocol identification pin corresponding to the storage device slot, and if the pin signal is a first preset pin signal, it is determined that the target solid state disk corresponding to the storage device slot is a first solid state disk; if the pin signal is a second preset pin signal, it is determined that the target solid state disk corresponding to the storage device slot is a second solid state disk.

[0053] High Level is a preset voltage state in digital circuits, representing a specific logic signal (usually "1"). Low Level is the opposite of High Level in digital circuit voltage states, representing another logic signal (usually "0").

[0054] In some possible embodiments, the first preset pin signal can be a high level, and the second preset pin signal can be a low level. The high level can be used as an identification signal of a first solid state disk (SAS / SATA protocol), and when the protocol identification pin detects the voltage, it is determined that the first solid state disk is accessed. The low level can be used as an identification signal of a second solid state disk (NVMe protocol), and when the protocol identification pin detects the voltage, it is determined that the second solid state disk is accessed.

[0055] The first preset level signal and the second preset level signal can be determined based on the specific connection mode of the protocol identification pin and each of the plurality of connection pins, and the application does not make specific limitations, but only gives an example.

[0056] The protocol switching processor is further configured to switch the communication protocol of the signal multiplexing circuit to a target communication protocol corresponding to the target solid state disk, the target solid state disk being the first solid state disk or the second solid state disk.

[0057] If the target solid state disk is the first solid state disk (SAS / SATA protocol), the target communication protocol is the SAS protocol or the SATA protocol; if the target solid state disk is the second solid state disk (NVMe protocol), the target communication protocol is the NVMe protocol (based on the PCIe bus).

[0058] In the present application, the pin signal (high / low) of the protocol identification pin is used to distinguish the type of hard disk, and the protocol identification logic can be sunk from the software layer to the hardware layer, so that the delay of firmware detection or operating system driver in the traditional scheme can be avoided.

[0059] One end of the signal multiplexing circuit can communicate with the host through the PCIe interface, and the other end of the signal multiplexing circuit is connected with the protocol switching processor. The protocol switching processor can process signal switching through the logic gate component.

[0060] For example, when the logic gate component detects that the pin signal is the first preset pin signal, it indicates that the first solid state disk is inserted into the slot, and then the logic gate component connects the first circuit. When the logic gate component detects that the pin signal is the second preset pin signal, it indicates that the second solid state disk is inserted into the slot, and then the logic gate component connects the second circuit.

[0061] The logic gate component can be an AND gate or a NAND gate.

[0062] The following is an example of a logical gate component, which is an AND gate.

[0063] A first AND gate is installed between the first circuit and the protocol identification pin. One input of the first AND gate is connected to the pin signal, and the other input is fixed to a high level "1" (for example, connected to the power supply). When the pin signal is "1", the output is "1", and the first circuit is connected.

[0064] A NOT gate and a second AND gate are installed between the second circuit and the protocol identification pin. The NOT gate is connected to the protocol identification pin, and the NOT gate is connected to the second AND gate. The second AND gate is connected to the second circuit. The NOT gate can invert the pin signal and then connect the second AND gate. When the pin signal is "0", it becomes "1" after inversion, causing the AND gate to output "1" to connect the second circuit.

[0065] The above design ensures that only one circuit is enabled, avoiding conflicts when the first circuit is connected and the second circuit is disconnected, and when the second circuit is connected and the first circuit is disconnected.

[0066] Specifically, one end of the signal multiplexing circuit is connected to the host through the PCIe 4.0 / 5.0 interface, supporting multiple link width configurations such as x4 / x8 / x16, and can dynamically adjust the number of data transmission channels according to the system bandwidth demand.

[0067] For example, in high-performance mode, x16 link is enabled, and the transmission rate can reach 32GB / s (PCIe 4.0) or 64GB / s (PCIe 5.0), ensuring high-speed data interaction between the host and the backend storage device.

[0068] In some possible embodiments, the signal multiplexing circuit can internally integrate a signal buffer and an equalizer, which can effectively compensate for attenuation and noise in high-speed signal transmission and maintain signal integrity.

[0069] The other end of the signal multiplexing circuit is connected to the protocol switching processor, and the signal multiplexing circuit can quickly direct the storage device slot to the host, realizing the sharing of host interface resources by multiple storage device slots. Through the signal multiplexing circuit, the hardware redundancy of separately configuring host interfaces for each storage device slot can be avoided, significantly reducing system cost and wiring complexity.

[0070] Specifically, the protocol switching processor can internally integrate logical gate components (or NOT gates, inverters, NAND gates, etc.) to form hardware-level protocol switching logic. The logical gate components can realize real-time switching control of high-speed signals.

[0071] In some possible embodiments, the protocol switching processor also interacts with the host through a status register to feed back the current signal switching state (such as a link connection state, error alarm information) in real time. When a signal transmission error (such as a CRC check failure) is detected, the processor can quickly generate an interrupt signal through a logic gate combination circuit to trigger an error recovery mechanism (such as link reset, data retransmission) of the host.

[0072] The signal multiplexing circuit can send transmission data of a target communication protocol to the host, and the target communication protocol is the first communication protocol or the second communication protocol.

[0073] Figure 3 A structural diagram of a storage device slot is provided for the embodiments of the present application. Please refer to Figure 3 The signal multiplexing circuit can include a first circuit and a second circuit, the first circuit is provided with a storage logic controller, the storage logic controller is connected with the protocol switching processor and the host through an interconnection high-speed bus respectively, and the second circuit is to directly connect the protocol switching processor and the host through the interconnection high-speed bus.

[0074] The storage logic controller can be a RAID controller, and the storage logic controller can perform storage management on the first solid state disk corresponding to the storage device slot based on a target sub-logic controller.

[0075] The target sub-logic controller can be one of a plurality of sub-logic controllers in the storage logic controller, and the sub-logic controller is used to execute a corresponding storage logic.

[0076] The plurality of sub-logic controllers can include at least two of the following: a stripe unit controller, a mirror redundancy controller, a distributed parity controller, and a double distributed parity controller.

[0077] The stripe unit controller can be a RAID 0, and the storage logic of the RAID 0 is to divide data into fixed-size stripe units (Stripe Size, usually 4K-256K) and poll to write into a disk.

[0078] Stripe Unit: refers to a fixed-size block formed after data is divided, which is a basic unit of data distribution in RAID 0, and the size is usually 4K-256K.

[0079] RAID 0: a non-redundant RAID level, which divides data into stripe units and distributes them into multiple disks (such as disk 1 stores stripe 1, disk 2 stores stripe 2, and so on) through a “polling write” method to improve performance through parallel read and write, but there is no data redundancy, and any disk failure will result in the loss of all data.

[0080] Mirror redundancy controller can be RAID 1, RAID 1: a mirror-based redundancy RAID level, which "100% replicates" data to each member disk (such as disk A and disk B are completely synchronized), forming a mirror relationship. Its advantages are read performance improvement (parallel reading) and strong fault tolerance (data is not lost when a single disk fails), but the storage cost is high (double disk space is required).

[0081] Distributed parity controller can be RAID 5, RAID 5 is a RAID level that balances performance and redundancy, which can stripe data to multiple disks (such as 2 blocks of data stripes and 1 block of parity information in 3 disks), and the parity information is "rotated storage" in each disk (to avoid single disk bottleneck due to storing parity information). Supports single disk failure recovery, and the space utilization rate is (n-1) / n (n is the number of disks).

[0082] Parity: a data checking method that generates parity information by performing XOR operations on multiple data blocks. When a data block is lost, the lost data can be reconstructed from other data blocks and parity information.

[0083] Dual distributed parity controller can be RAID 6, RAID 6 storage logic is an extension of RAID 5 architecture, which uses "two independent parity algorithms" (such as XOR parity + another polynomial parity) to generate two sets of parity information and distribute them. Supports simultaneous tolerance of 2 disk failures, suitable for scenarios with extremely high data security requirements, but with slightly lower write performance (requires calculating two sets of parity), and the space utilization rate is (n-2) / n.

[0084] Among them, the distributed parity controller and the dual distributed parity controller can be FPGA acceleration cards based on FPGA, and the stripe unit controller and the mirror redundancy controller can be ASIC reduction cards based on ASIC.

[0085] RAID controller based on Application-Specific Integrated Circuit (ASIC) to realize the sub-logic controller (for example, stripe unit controller and mirror redundancy controller), ASIC can efficiently process data striping, redundancy checking, fault recovery and other required by RAID technology through customized hardware logic.

[0086] In some possible embodiments, the Field-Programmable Gate Array (FPGA)-based sub-logic controllers (e.g., distributed parity controller and dual distributed parity controller) support real-time burning of hardware logic of different RAID levels.

[0087] The hardware structure of the FPGA is reconfigurable, and the logic function of the FPGA is determined by software configuration, and the configuration process can be completed in the system running (i.e., "real-time burning"), and in the scene where flexible adjustment of hardware logic is required, for example, in the present application, multiple RAID levels are supported.

[0088] The sub-logic controllers of different RAID levels can correspond to configurable hardware modules, and by dynamically loading the configuration files corresponding to the configurable hardware modules corresponding to each sub-logic controller, different configuration files make the FPGA behave as a controller of different RAID levels at different times.

[0089] Specifically, the storage logic controller can include a general logic module and a special logic module, the general logic module is used to implement the general basic functions of each RAID level, and the special logic module is used to implement the special functions of each RAID level.

[0090] The special logic module can switch the RAID level based on the host sending a switching instruction: the host sends a switching instruction (e.g., from RAID 5 to RAID 6); pause the logic running of the initial RAID level (e.g., RAID 5) of the storage logic controller; load the target configuration file of the target RAID level (e.g., RAID 6) corresponding to the switching instruction, and update the logic resources of the special logic module according to the target configuration file, so as to switch the initial RAID level of the storage logic controller to the target RAID level.

[0091] When the logic running of the initial RAID level of the storage logic controller is paused, the necessary intermediate state (e.g., data in the cache, parity information) is saved.

[0092] The protocol switching processor can switch the circuit between the first circuit and the second circuit according to the hard disk type of the inserted solid state disk.

[0093] The first circuit and the second circuit are parallel circuits. The second circuit can be a pass-through card based on a JBOD mode, and the pass-through card can realize direct connection of the solid state disk to the host, bypassing the RAID controller.

[0094] The TRIM instruction is a key ATA instruction for solid state disk garbage collection, and is used to mark invalid data blocks. When the operating system or a management device (such as a BMC) deletes data in the solid state disk, the TRIM instruction informs the solid state disk controller that the data blocks are invalid and the physical storage space occupied by the data blocks can be released in advance. The solid state disk controller can perform background garbage collection based on the instruction to avoid performance degradation caused by the need to clean invalid data before subsequent writing, which is a key instruction for maintaining the long-term read-write performance of the solid state disk, and enables the solid state disk controller to release physical space in advance to avoid write performance degradation.

[0095] The storage logic controller of the hardware cannot generally pass through the TRIM instruction (especially RAID 5 / 6), so that the solid state disk cannot perceive data deletion and the performance drops sharply after a long time.

[0096] The second circuit can enable the second solid state disk to be directly connected to the host, bypassing the RAID controller, and improving the storage performance.

[0097] Please refer to Figure 3 The storage device slot is also provided with an error correction codec, which is connected with the storage logic controller. The error correction codec is used for error correction processing of the storage logic processing, and can realize accelerated verification of the storage.

[0098] The error correction codec can be a Low-Density Parity-Check Code (LDPC) codec. The error correction codec is a forward error correction system based on sparse matrix operation, which can add redundant check bits to the transmitted data to realize efficient detection and correction of errors in the transmission / storage process, and can reduce the amount of calculation to realize accelerated verification of the storage. The error correction codec can include an encoder and a decoder.

[0099] In this application, the storage logic controller is built-in with multiple dedicated sub-logic controllers, each of which independently executes a specific storage logic, and realizes hierarchical management of functions through the storage logic controller and the protocol switching processor, which can increase the reliability of protocol conversion.

[0100] Figure 4 Another structure diagram of a backplane system provided by an embodiment of the present application is provided. Please refer to Figure 4 The backplane system further includes a backplane controller connected with the host and each storage logic controller.

[0101] The user can select a target sub-logic controller corresponding to a target storage logic controller through a management interface, and the host can generate a level switching request. The level switching request can include a processor identifier of the target storage logic controller and a controller identifier corresponding to the target sub-logic controller.

[0102] The backplane controller can generate a replacement instruction according to the level switching request sent by the host, and send the replacement instruction to the target storage logic controller to switch the sub-logic controller corresponding to the target storage logic controller to the target sub-logic controller.

[0103] The switching of each sub-logic controller can be based on a logic gate component. The use of the logic gate component can refer to the switching design of the first and second switching circuits described above, which will not be described here.

[0104] Referring to Figure 4 , the backplane controller includes a hot plug management controller, which can monitor the plug signals of each storage device slot in real time.

[0105] The plug signal is a digital signal used to identify the "inserted" or "removed" state of the storage device. When the signal meets the "inserted" threshold (such as a first preset signal), it means that the device has been connected; when it meets the "removed" threshold (such as a second preset signal), it means that the device has been removed.

[0106] Specifically, if the plug signal is the first preset signal, the plug signal indicates that a solid state disk is inserted into the storage device slot corresponding to the plug signal; if it is the second preset signal, the plug signal indicates that a solid state disk is removed from the storage device slot corresponding to the plug signal.

[0107] In some possible embodiments, the first preset signal can be a high level, and the second preset signal can be a low level.

[0108] Referring to Figure 4 , the hot plug management controller can include a current sensor and a high-speed analog-to-digital converter, the current sensor being connected to the storage device slot, and the high-speed analog-to-digital converter being connected to the current sensor.

[0109] The current sensor is an electronic component for real-time detection of current size in a circuit, which can detect the current analog signal of the hard disk corresponding to the storage device slot. For example, when a solid state disk is inserted, the slot will generate a load current; when it is removed, the current will disappear or drop significantly.

[0110] The current sensor can be connected to the storage device slot through a pin, which can improve the reliability of the current sensor detection.

[0111] The current sensor can be connected to multiple storage device slots through a multiplexer (MUX).

[0112] Multiplexer (MUX) is an electronic switching element that can realize "multiple input, single output". It can connect one current sensor to multiple storage device slots simultaneously. By timing control or signal gating, it can sequentially collect the current analog signals of different slots, without the need to configure one current sensor for each slot, thus simplifying hardware design and reducing cost.

[0113] High-Speed Analog-to-Digital Converter (High-Speed ADC) is an electronic element that can quickly convert continuously changing analog signals (such as current analog signals output by a current sensor) into discrete digital signals (i.e. "plug-in signals").

[0114] In this application, through the current sensor and the high-speed analog-to-digital converter, multiple storage device slots can be detected and monitored simultaneously, saving backplane space.

[0115] In some possible embodiments, the hot plug management controller is further configured to perform update processing on the new hard disk based on log information of the target storage device slot within a period when the historical hard disk is pulled out and the new hard disk is inserted.

[0116] The log information is a detailed record of multiple data operations to be processed within the plug-in period recorded by the system in the storage device plug-in scenario. The log information can include key information such as the source, size, target storage location, and initiation time of the data to be written.

[0117] The hot plug management controller can perform update processing on the new hard disk through log analysis, which can improve the reliability of the storage infrastructure.

[0118] Specifically, the log information within the plug-in period can be obtained to generate hash values of each data block to be written; after the new hard disk is inserted, the difference data blocks are determined based on the hash values of each data block to be written and the hash values of each hard disk data block of the new hard disk; and the difference data blocks are updated in the new hard disk.

[0119] Data block is the smallest unit of data processing and transmission in a storage system (not a single file), which is usually a fixed-size binary data segment (such as several KB or several tens of KB). The system will split files into multiple data blocks for storage, and perform hash calculation, comparison, and writing in units of data blocks, which can improve the efficiency and flexibility of data processing.

[0120] The data block to be written is a data block that should be written to the historical hard disk but has not been successfully written due to the hard disk being pulled out, and is in a "waiting to write state".

[0121] Hash Value is a fixed-length binary or hexadecimal string obtained by converting an input data (for example, a data block) of any size through a hash algorithm. For example, the hash algorithm can be SHA-256 or CRC32.

[0122] Hash values generated by different data blocks are almost impossible to be the same, and the original data cannot be deduced from the hash value.

[0123] Hard disk data block is an existing data segment stored in the new hard disk in the unit of "data block".

[0124] The plug-in period is the period between the time of pulling out the historical hard disk and the time of inserting the new hard disk. During the plug-in period, there may be data blocks to be written. After the new hard disk is inserted, the new hard disk may have written the data blocks to be written, and the hash values of each data block to be written need to be compared with the hash values of each hard disk data block of the new hard disk.

[0125] For any one data block to be written, if the hash value of the data block to be written does not exist in the hash values of each hard disk data block, the data block to be written needs to be written into the new hard disk, and the data block to be written is determined as a difference data block. The difference data block is a data block not written into the new hard disk.

[0126] In this application, after the new hard disk is inserted, the difference data block can be determined according to the hash values of each data block to be written and the hash values of each hard disk data block of the new hard disk, and only the difference data block needs to be transmitted, which can improve the efficiency and stability.

[0127] The hot plug management controller is also used to perform a verification process on the difference data blocks synchronized in the new hard disk, and if the verification fails, the backup storage logical controller is switched to.

[0128] The backup storage logical controller refers to a storage logical control unit additionally deployed in the storage system for redundant backup, which can realize core storage management tasks such as data read-write control and logical processing.

[0129] The backup storage logical controller can immediately take over the work when the main storage logical controller fails (such as data verification failure, hardware exception), re-read or process data, avoid data loss or storage service interruption, and ensure the reliability and continuity of system storage function.

[0130] The check processing can be a cyclic redundancy check (CRC). The CRC can be calculated by a preset mathematical polynomial algorithm (such as CRC-32, CRC-64) on the original data (such as the synchronized differential data block) to generate a fixed-length binary value, that is, a CRC check value. The calculated CRC check value can be compared with a preset check value before data transmission / storage. If the two are consistent, it means that the data has not been corrupted or lost during transmission or storage, and the data is complete. If the two are inconsistent, it means that the data may be damaged or lost due to interference, hardware problems, etc., and needs to be reprocessed (such as re-reading, retransmission).

[0131] When the check fails, it is determined that the current differential data block is unreliable, and the redundant backup storage logical controller can be switched to, and the differential data block is re-read in the backup storage logical controller.

[0132] In this application, through the check processing, the data integrity is monitored in real time, and the backup storage logical controller redundancy is used to realize automatic switching of faults, which can ensure reliable storage services.

[0133] Please refer to Figure 4 The backboard further includes a backboard monitor connected with each storage device slot and the backboard controller. The backboard monitor can monitor the load of each storage device slot to obtain the hard disk load corresponding to each storage device slot, and send the hard disk load corresponding to each storage device slot to the backboard controller.

[0134] The hard disk load can be used as an index to measure the current working pressure of the solid state disk connected in the storage device slot, which is usually quantified by "data transmission amount per unit time", "read / write request number" or "resource occupation rate".

[0135] If the hard disk load is high, the hard disk needs to frequently process a large amount of data read / write (such as continuous transmission of large files), at which time the bandwidth demand of the data transmission channel (such as the interconnection high-speed bus) is high. If the hard disk load is low, the hard disk read / write request is small and the data transmission amount is small (such as only occasionally reading small files), and the bandwidth demand of the transmission channel is low.

[0136] A plurality of storage device slots are provided on the backboard. If the interconnection high-speed bus channel is not evenly distributed, it will cause performance degradation. When the hard disk load corresponding to the storage device slot is large, more data needs to be transmitted, and more interconnection high-speed buses need to be allocated. When the hard disk load corresponding to the storage device slot is small, less data needs to be transmitted, and less interconnection high-speed bus needs to be allocated.

[0137] The backboard controller can assign the interconnection high-speed bus to the storage device slot with a hard disk load greater than a preset load based on the hard disk load of each storage device slot.

[0138] The interconnection high-speed bus can be assigned through an assignment mechanism:

[0139] Trigger condition: at the clock rising edge, compare the current lane request signal (lane_request) with the assigned lane number (current_alloc), when the request number is greater than the assigned number, trigger lane reassignment.

[0140] Assignment rule: read the corresponding configuration from the preset lane priority table (lane_priority_table) according to the request identifier (request_id), and assign the result to the reroute register (reroute_lanes) to realize dynamic allocation of lanes.

[0141] State update: call the update_arbitration function to update the arbitration logic state according to the current active slot (active_slots) information, and prepare for the next lane assignment.

[0142] The preset lane priority table can be a list of storage device slots arranged from high to low according to the hard disk load of each storage device slot.

[0143] Through the comparison of priority table and real-time request, the function of dynamically adjusting PCIe lane resources based on demand is realized, which ensures that high-priority requests can obtain more lane resources.

[0144] The solid state disk corresponding to the storage device slot with a large hard disk load can be realized to preferentially obtain the interconnection high-speed bus lane, realize the dynamic allocation of the high-speed bus lane, so that the solid state disk corresponding to the storage device slot with a large hard disk load can preferentially perform data transmission, and the storage performance can be improved.

[0145] The backboard controller is connected with the backboard monitor through a two-wire communication interface, and the two-wire communication interface is a 2Wire interface, which can include a data transmission line and a clock synchronization line.

[0146] The 2Wire interface can realize data interaction between devices through two physical lines, and the two lines respectively bear the functions of "data transmission" (transferring actual data) and "clock synchronization" (ensuring that the data transmission rhythm of the receiving and transmitting parties is consistent).

[0147] Please refer to Figure 4 , the backboard further includes a preset storage device slot, and the solid state disk corresponding to the preset storage device slot is a preset hot standby hard disk.

[0148] The preset storage slot structure is the same as that of the storage device slot, which can be referred to in the foregoing storage device slot, and will not be described here again.

[0149] The preset storage slot and each storage device slot are powered on at the same time, and do not store data in real time. When the solid state disk corresponding to each storage device slot fails, the preset hot backup hard disk corresponding to the preset storage slot is started.

[0150] The backboard controller can detect the hard disk failure in the solid state disk corresponding to each storage device slot through the backboard monitor, and migrate the data of the hard disk failure to the preset hot backup hard disk.

[0151] The preset hot backup hard disk is a backup solid state disk pre-accessed to the preset storage device slot, and is in a standby ready state, which can cope with other hard disk failures.

[0152] When the backboard monitor detects that the solid state disk in a certain storage device slot fails, the backboard controller can directly migrate the data in the failed hard disk to the preset hot backup hard disk, avoiding data loss, and reducing the "read-modify-write" operation on the failed hard disk, and improving the system recovery efficiency.

[0153] The preset hot backup hard disk can be periodically muted and erased. The mute and erase is a background data cleaning operation for the preset hot backup hard disk. Without affecting the normal standby of the hard disk (without interrupting its ability to receive data migration at any time), the invalid data blocks remaining in the hard disk are automatically erased. The physical storage space of the hard disk can be released in advance to ensure that the hot backup hard disk is always in a "fast read-write" state, and when it needs to receive data migration from the failed hard disk, it can be directly and efficiently written without additional time-consuming space cleaning.

[0154] In some possible embodiments, the backboard monitor monitors the impedance change of the slot in real time. If the sudden change value exceeds 5Ω (AR>5Ω), it is determined that the connection is abnormal. In order to avoid subsequent signal reflection or equipment failure, the system actively switches to a degraded mode (for example, closing part of the function, enabling the redundant preset hot backup hard disk) within 50ms to maintain basic operation and prevent damage.

[0155] In some possible embodiments, for any one storage device slot, a vibration sensor and a temperature sensor are arranged at the storage device slot, the backboard controller can acquire vibration data in a first time length before the current time through the vibration sensor, acquire temperature data in the first time length before the current time through the temperature sensor, determine time sequence data according to the vibration data in the first time length and the temperature data in the first time length, perform data processing on the time sequence data through the hot plug prediction model, and obtain a hot plug probability after the current time; if the hot plug probability is greater than a preset probability, data of the solid state disk corresponding to the storage device slot is migrated to a preset hot standby hard disk.

[0156] The hot plug prediction model can be obtained by pre-training a Long Short-Term Memory (LSTM) model through a training set.

[0157] The first time length can be 2 seconds, 2-second time sequence data can be input into the hot plug prediction model, and a predicted hot plug probability can be output.

[0158] In some possible embodiments, an online learning module can be deployed, that is, each time an actual plug is generated, new data is automatically added to the training set, and the model parameters are updated through incremental gradient descent, for example, the online learning module can be executed in a low load period in the early morning every day.

[0159] Correspondingly, the embodiments of the present application provide a storage system, including the backboard system in the above embodiments, the solid state disks corresponding to the storage device slots, and a baseboard management controller, wherein the baseboard management controller is configured to realize out-of-band management of the solid state disks corresponding to the storage device slots through a third communication protocol.

[0160] The third communication protocol can be an Intelligent Platform Management Interface (IPMI) protocol, which is a hardware-level management protocol independent of an operating system and a CPU, and can realize out-of-band management of a server through a baseboard management controller (BMC) embedded in a motherboard.

[0161] The storage system provided in the embodiments of the present application can realize the backboard system described above, and the implementation principle and technical effects are similar, which will not be described here in detail.

[0162] It should also be noted that the terms "comprising", "comprises" or other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0163] The above embodiments are only used to illustrate the present application, but not to limit it. Instead of the above, various modifications and changes can be made to the application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall fall into the scope of the claims of the application.

Claims

1. A backplane system, characterized in that, The backplane system is provided with multiple storage device slots, each storage device slot having its corresponding signal multiplexing circuit and protocol switching processor. The protocol switching processor is connected to the protocol identification pin and signal multiplexing circuit of its corresponding storage device slot, respectively. The signal multiplexing circuit of each storage device slot is connected to the host. The storage device slot is configured to connect a first solid-state drive or a second solid-state drive. The first solid-state drive is a solid-state drive based on a first communication protocol, and the second solid-state drive is a solid-state drive that is directly connected to the host via an interconnect high-speed bus and is based on a second communication protocol. The signal multiplexing circuit is configured to send transmission data of a target communication protocol to the host, wherein the target communication protocol is either the first communication protocol or the second communication protocol. The protocol switching processor is used to switch the communication protocol of the signal multiplexing circuit according to the pin signal of the protocol identification pin of its corresponding storage device slot. The signal multiplexing circuit includes a first circuit and a second circuit, which are parallel circuits. The first circuit is equipped with a storage logic controller, which is connected to the protocol switching processor and the host respectively through an interconnect high-speed bus. The second circuit directly connects the protocol switching processor and the host through the interconnect high-speed bus.

2. The system according to claim 1, characterized in that, The protocol switching processor is used to obtain the pin signal of the protocol identification pin corresponding to the storage device slot. If the pin signal is a first preset pin signal, the target solid-state drive corresponding to the storage device slot is determined to be a first solid-state drive. If the pin signal is a second preset pin signal, the target solid-state drive corresponding to the storage device slot is determined to be a second solid-state drive. The protocol switching processor is further configured to switch the communication protocol of the signal multiplexing circuit to the target communication protocol corresponding to the target solid-state drive, wherein the target solid-state drive is either the first solid-state drive or the second solid-state drive.

3. The system according to claim 1, characterized in that, The storage logic controller is used to perform storage management on the first solid-state drive corresponding to the storage device slot based on the target sub-logic controller. The target sub-logic controller is one of a plurality of sub-logic controllers in the storage logic controller, and the sub-logic controller is used to execute its corresponding storage logic.

4. The system according to claim 3, characterized in that, The storage device slot is also equipped with an error correction codec, which is connected to the storage logic controller and is used to perform error correction processing on the logic processing of the storage logic controller.

5. The system according to claim 3, characterized in that, The system also includes a backplane controller, which is connected to the host and each storage logic controller. The backplane controller is used to generate a replacement instruction based on the level switching request sent by the host, and send the replacement instruction to the target storage logic controller to switch the sub-logic controller corresponding to the target storage logic controller to the target sub-logic controller. The level switching request includes the processor identifier of the target storage logic controller and the controller identifier corresponding to the target sub-logic controller.

6. The system according to claim 5, characterized in that, The plurality of sub-logic controllers include at least two of the following: a stripe unit controller, a mirrored redundancy controller, a distributed parity check controller, and a dual distributed check controller.

7. The system according to claim 5, characterized in that, The backplane controller includes a hot-swap management controller, which is connected to each of the storage device slots and is used to monitor the insertion and removal signals of each storage device slot in real time. Wherein, if the insertion / removal signal is a first preset signal, the insertion / removal signal indicates that a solid-state drive is inserted into its corresponding storage device slot; if the insertion / removal signal is a second preset signal, the insertion / removal signal indicates that a solid-state drive is removed from its corresponding storage device slot.

8. The system according to claim 7, characterized in that, The hot-swap management controller includes a current sensor and a high-speed analog-to-digital converter, wherein... The current sensor is connected to each of the storage device slots, and the current sensor is used to detect the analog current signal of the hard drive corresponding to each storage device slot; The high-speed analog-to-digital converter is connected to the current sensor. The high-speed analog-to-digital converter is used to convert the analog current signal detected by the current sensor into a plug-in signal, which is a digital signal.

9. The system according to claim 7, characterized in that, The hot-swap management controller is also used to update the new hard drive based on log information from the target storage device slot during the periods when a historical hard drive was removed and a new hard drive was inserted.

10. The system according to claim 9, characterized in that, The hot-swap management controller is used for, Obtain log information during the plug-in / plug-out period and generate hash values ​​for each data block to be written; After a new hard drive is inserted, the difference data blocks are determined based on the hash values ​​of each data block to be written and the hash values ​​of each data block on the new hard drive. In the newly added hard disk, the difference data blocks are updated.

11. The system according to claim 10, characterized in that, The hot-swap management controller is also used to verify the difference data blocks in the newly added hard disk. If the verification fails, the controller switches to the backup storage logic controller.

12. The system according to claim 5, characterized in that, The backplane also includes a backplane monitor, which is connected to each storage device slot and the backplane controller, respectively. The backplane monitor is used to monitor the load of each storage device slot, obtain the hard disk load corresponding to each storage device slot, and send the hard disk load corresponding to each storage device slot to the backplane controller. The backplane controller is also used to allocate high-speed interconnect buses to storage device slots with hard disk loads greater than a preset load, based on the hard disk loads corresponding to each storage device slot.

13. The system according to claim 12, characterized in that, The backplane controller communicates with the backplane monitor via a two-wire communication interface, which includes a data transmission line and a clock synchronization line.

14. The system according to claim 5, characterized in that, The backplane also includes a preset storage device slot, and the solid-state drive corresponding to the preset storage device slot is a preset hot-spare drive. The backplane controller is also used to migrate the data of the faulty solid-state drive to the preset hot spare hard drive after detecting a hard drive failure in the solid-state drive corresponding to each storage device slot through the backplane monitor.

15. A storage system, characterized in that, Includes the backplane system as described in any one of claims 1-14, the solid-state drives corresponding to each storage device slot, and the baseboard management controller, wherein, The baseboard management controller is used to implement out-of-band management of the solid-state drives corresponding to each storage device slot through a third communication protocol.

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