Chip mode control method and device, equipment, medium and product

Abstract

The invention discloses a chip mode control method and device, equipment, a medium and a product, and relates to the technical field of low power consumption of chips, and the method comprises the following steps: after monitoring at least one host wake-up instruction in a sleep mode, firstly determining sleep maintenance time and counting down, and then waking up a chip after timing is ended. The chip is prevented from being awakened too early, so that the chip waits for retransmission preparation of the host in a low-power-consumption state, data can be immediately processed after awakening, and ineffective active power consumption is reduced. Meanwhile, by dynamically adjusting the wake-up time, the energy efficiency management flexibility in a low power consumption mode is improved, the problem of invalid power consumption caused by waiting for retransmission is effectively solved, and the overall power consumption performance of the chip is optimized.

Description

Technical Field

[0001] The present application relates to the field of chip low power consumption technology, and in particular to a chip mode control method, device, equipment, medium and product. Background Art

[0002] Under the current development trend of chip technology, low-power technology is constantly innovating and iterating, which has brought many effective ways to save energy and reduce consumption of chips. Existing chips have formed a relatively mature process in low-power mode management: Figure 1 As shown in the figure, when the sleep enable signal (SLEEP) is asserted, the sleep process (ENTER) is triggered. The CPU ready signal (CPU_RDY) is asserted in response to the sleep request, indicating that the CPU is ready to shut down. The chip clock signal (SYSCLK) disappears / pauses during the sleep phase, completing the clock shutdown process before entering sleep mode. When the chip enters stable sleep mode (SLEEP), the power ready signal (POWER_RDY) enters low-power mode, suspending core modules such as the clock and CPU to maintain minimum power consumption. When the wake / resume signal (RESUME) reaches an active level, POWER_RDY is restored first, preparing for full power consumption. CPU_RDY is then asserted, preparing for a restart, preparing for exiting sleep mode (EXIT). When the SYSCLK clock returns, the chip power supply, CPU, and other modules fully restart, returning to active mode (ACTIVE) and resuming normal task execution. Figure 1 This indicates that the chip turns off unnecessary clocks, reduces power consumption, and lowers standby power consumption when in sleep mode. When awakened, the power, clock, and CPU are restored in sequence to ensure a stable restart of the chip.

[0003] However, existing technologies still have significant shortcomings. After the chip enters low-power mode, when the interface receives a communication request from the host as a slave, it immediately wakes up and then waits for the host to retransmit data. During this process, since data cannot be received in low-power mode, it can only wait for retransmission after waking up, and this wait time can be as long as 5ms. During this 5ms, the chip is in active mode but is not actually executing any tasks. This situation causes the chip to continue consuming power while being unnecessarily active, resulting in wasted energy.

[0004] Furthermore, this inactive state caused by waiting for retransmission not only increases the chip's overall power consumption but can also affect its lifespan and stability. As chip applications increasingly demand low power and energy efficiency, avoiding inactive power consumption while waiting for host retransmissions and improving data transmission efficiency and energy management in low-power mode have become pressing technical challenges. Summary of the Invention

[0005] The present application provides a chip mode control method, device, equipment, medium and product to at least solve the problem of how to avoid invalid power consumption of the chip while waiting for host retransmission, and improve the efficiency of data transmission and energy consumption management level in low power mode.

[0006] The present application provides a mode control method for a chip, comprising: when the chip is in sleep mode, monitoring at least one host wake-up instruction; when at least one host wake-up instruction is monitored, determining the sleep maintenance time; counting down according to the sleep maintenance time; after the countdown ends, controlling the chip to return to active mode.

[0007] As an optional implementation provided in an embodiment of the present application, when at least one host wake-up command is monitored, determining the sleep maintenance time includes:

[0008] When at least one host wake-up command is detected, the control chip enters the wake-up waiting state;

[0009] When the chip is in the wake-up wait state, the sleep maintenance time is determined.

[0010] As an optional implementation provided by an embodiment of the present application, when at least one host wake-up command is monitored, the sleep maintenance time is determined, including: responding to the first host wake-up command, determining the first sleep maintenance time according to the first host retransmission time; if the second host wake-up command is received within the preset time, updating the first sleep maintenance time to the second sleep maintenance time, and the second sleep maintenance time is the second host retransmission time; wherein the preset time is less than the first sleep maintenance time.

[0011] As an optional implementation provided by an embodiment of the present application, when at least one host wake-up instruction is monitored, the sleep maintenance time is determined, including: in response to at least one host wake-up instruction, comparing at least one host retransmission time corresponding to the at least one host wake-up instruction; and determining the shortest host retransmission time from the at least one host retransmission time as the sleep maintenance time.

[0012] As an optional implementation provided by an embodiment of the present application, the method also includes: when at least one host wake-up instruction is not detected, the control chip enters a wake-up waiting state; when the chip is in the wake-up waiting state, a low-power clock is used to accumulate the count; when the count reaches a threshold, the control chip returns to an active mode.

[0013] As an optional implementation provided by an embodiment of the present application, the method also includes: when the chip is in active mode, monitoring at least one host retransmission instruction; when monitoring at least one host retransmission instruction, receiving retransmission data from at least one host.

[0014] The present application also provides a mode control device for a chip, comprising:

[0015] A monitoring module, configured to monitor at least one host wake-up instruction when the chip is in sleep mode;

[0016] A processing module, configured to determine a sleep maintenance time when at least one host wake-up command is monitored;

[0017] A countdown module is used to count down according to the sleep maintenance time;

[0018] The control module is used to control the chip to return to the active mode after the countdown ends.

[0019] As an optional implementation provided in an embodiment of the present application, the processing module is specifically used to: control the chip to enter a wake-up waiting state when at least one host wake-up instruction is monitored; and determine the sleep maintenance time when the chip is in the wake-up waiting state.

[0020] As an optional implementation provided in an embodiment of the present application, the processing module is specifically used to: respond to a first host wake-up instruction, determine a first sleep maintenance time based on the first host retransmission time; if a second host wake-up instruction is received within a preset time, update the first sleep maintenance time to a second sleep maintenance time, and the second sleep maintenance time is the second host retransmission time; wherein the preset time is less than the first sleep maintenance time.

[0021] As an optional implementation provided in an embodiment of the present application, the processing module is specifically used to: respond to at least one host wake-up instruction, compare at least one host retransmission time corresponding to the at least one host wake-up instruction; and determine the shortest host retransmission time from the at least one host retransmission time as the sleep maintenance time.

[0022] As an optional implementation provided in an embodiment of the present application, the processing module is also used to: when at least one host wake-up instruction is not detected, control the chip to enter a wake-up waiting state; when the chip is in the wake-up waiting state, use a low-power clock to accumulate counting; when the count reaches a threshold, control the chip to return to active mode.

[0023] As an optional implementation provided in an embodiment of the present application, the device also includes a retransmission module for monitoring at least one host retransmission instruction when the chip is in active mode; and receiving retransmission data from at least one host when at least one host retransmission instruction is monitored.

[0024] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned chip mode control methods when executing the computer program.

[0025] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of the mode control method of any of the above chips are implemented.

[0026] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned chip mode control methods when executed by a processor.

[0027] When the chip is in sleep mode, the present application does not wake up immediately after listening to the host wake-up command, but first determines the sleep maintenance time. This means that the chip will not rush into active mode simply because it receives a request, reducing unnecessary wake-up operations and avoiding power consumption waste during the no-task period after waking up; through the countdown mechanism, the chip remains in sleep state during the determined sleep maintenance time, and does not return to active mode until the countdown ends. This method enables the chip to wait for the host to be ready for retransmission in a low-power state, or wait for a more appropriate time to wake up, ensuring that valid data can be processed immediately after waking up, rather than wasting power in a no-task state, thereby improving the chip's energy efficiency management level in low-power mode. In this way, by adding sleep maintenance time judgment and countdown mechanism, the technical problem of invalid activity and waste of power consumption caused by waiting for retransmission is solved, invalid power consumption caused by premature wake-up of the chip is avoided, and the efficiency of data transmission and energy consumption management in low-power mode are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0029] Figure 1 This is the sleep-wake timing diagram of the traditional solution;

[0030] Figure 2 A schematic flow chart of a chip mode control method provided in an embodiment of the present application;

[0031] Figure 3 The sleep-wake sequence provided in the embodiment of the present application Figure 1 ;

[0032] Figure 4 The sleep-wake sequence provided in the embodiment of the present application Figure 2 ;

[0033] Figure 5 The sleep-wake sequence provided in the embodiment of the present application Figure 3 ;

[0034] Figure 6A Schematic diagram of chip mode switching between the present application and the traditional solution;

[0035] Figure 6B A comparison chart of the sleep-wake timing between this application and the traditional solution;

[0036] Figure 7 A schematic structural diagram of a mode control device of a chip provided in an embodiment of the present application;

[0037] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0039] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0040] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0041] An embodiment of the present application provides a mode control method for a chip, and the method is described in detail in conjunction with the execution flow of the mode control method for the chip.

[0042] like Figure 2 As shown, Figure 2 A chip mode control method provided in an embodiment of the present application includes the following steps S201 to S204:

[0043] S201: When the chip is in a sleep mode, monitor at least one host wake-up instruction.

[0044] Sleep mode, also known as low-power mode, reduces the overall power consumption of the chip by suspending or shutting down certain chip modules, such as the CPU core, non-essential peripherals, and the clock system. This reduces energy consumption and extends device battery life while the chip is waiting for tasks or events, while retaining the ability to quickly wake up and resume work.

[0045] The at least one host wake-up instruction is a wake-up instruction of at least one host, and the at least one host includes but is not limited to an interface such as an inter-integrated circuit bus (I2C), an enhanced inter-integrated circuit bus (I3C), a serial peripheral interface (SPI), an integrated circuit card interface device (ISO / IEC 7816), or a single wire protocol (SWP). The chip acts as a slave of the interface. The wake-up instruction is a wake-up frame sent by the host.

[0046] like Figure 3 As shown, when the sleep enable signal (SLEEP) is high, the chip enters sleep mode. When the CPU ready signal (CPU_RDY) is high, the CPU is ready and the chip enters sleep mode (ENTER). The CPU must be ready and inactive. The power ready signal (POWER_RDY) reflects the status of the system power module. During sleep mode, the chip enters low-power mode, and exiting sleep (EXIT) requires the power supply to stabilize. The main clock signal (SYSCLK) continuously provides clocks in active mode, stops during sleep mode, and resumes after exiting sleep mode.

[0047] Figure 3 The chip shown in the figure turns off the main clock (SYSCLK) when entering sleep mode (ENTER), but retains I2C monitoring. While in sleep mode (SLEEP), the chip monitors for at least one host wake-up command. For example, the I2C bus clock line signal (SCL_IN) and the I2C bus data line signal (SDA_IN) still have SCL / SDA waveforms during sleep. During sleep, the I2C bus can still monitor external communications. When a wake-up command (such as a wake-up frame) appears on the I2C bus, the I2C wake-up signal (I2C_RESUME) is asserted.

[0048] The above embodiment ensures that the chip enters the wake-up process only when it receives a valid communication request from the target host by monitoring the wake-up instructions of a specific interface, thereby reducing power consumption caused by invalid wake-up; by monitoring the wake-up protocols of host interfaces such as I2C and SPI, it can adapt to the communication requirements of different host devices, ensuring that the chip can interact efficiently with the host in a variety of application scenarios while maintaining the stability of the low-power mode; at the same time, accurate instruction recognition can shorten the invalid waiting time of the wake-up response and further reduce energy consumption in the standby stage; by monitoring the wake-up instructions, the chip can quickly respond to the host request of the corresponding interface, reduce the retransmission delay caused by interface protocol mismatch after wake-up, ensure the timeliness and reliability of data transmission, and optimize the overall balance between power consumption and performance.

[0049] S202: Determine a sleep maintenance time when at least one host wake-up instruction is monitored.

[0050] When at least one host wake-up command is detected, the system does not immediately return to active mode from sleep mode. In some embodiments, the system first enters a wake-up wait state (RESUME_WAIT), such as Figure 3 As shown in Figure 1, when the I2C wake-up signal (I2C_RESUME) is detected, the chip enters RESUME_WAIT. While in RESUME_WAIT, the sleep duration is determined. In this state, the chip waits for the sleep duration to expire before entering EXIT mode and gradually returning to ACTIVE mode.

[0051] In some embodiments, when at least one host wake-up command is monitored (for ease of description, assuming that the at least one host wake-up command includes a first host wake-up command and a second host wake-up command), the process of determining the sleep maintenance time includes: first responding to the first host wake-up command and determining a first sleep maintenance time; if the second host wake-up command is received within a preset time, updating the first sleep maintenance time to a second sleep maintenance time; wherein the preset time is less than the first sleep maintenance time. The retransmission time may vary between different hosts.

[0052] Specifically, if a wake-up command from the first host is received first, the chip first determines the first sleep duration based on the first host's retransmission time. It then records whether a second host wake-up command is received within the preset time. If so, the first sleep duration is updated to the second sleep duration, i.e., the second host's retransmission time. The preset time can be determined based on the difference between the retransmission times of the first and second hosts. This allows for flexible adaptation to the timing requirements of multiple hosts, ensuring the chip maintains low power consumption in multi-host scenarios while promptly responding to communication requests from each host.

[0053] When the first host triggers wake-up, the chip sets the initial sleep maintenance time according to its retransmission time to ensure that it maintains a low power consumption state during this time period. If a wake-up command from the second host is received within the preset time, the sleep maintenance time is promptly updated to the retransmission time of the second host, avoiding the chip waking up due to the end of the first host time and then waking up again due to the second host request, thereby reducing the power consumption waste caused by multiple wake-ups.

[0054] For example, if an I2C wake-up command is received first, assuming the I2C retransmission time is 5ms, the initial value of the timer is set to 5ms. If an SPI wake-up command is received within 1ms, the initial value of the timer is replaced with the SPI retransmission time of 4ms. By dynamically updating the sleep maintenance time, the chip can integrate wake-up requests from multiple hosts before waking up, avoiding frequent wake-up requests or response delays caused by inconsistent retransmission times between different hosts. This improves the continuity and efficiency of data transmission and indirectly reduces the additional power consumption caused by communication interruptions.

[0055] like Figure 4 As shown in the figure, when the chip is in the wake-up waiting state (RESUME_WAIT), it first monitors the wake-up signal (I2C_RESUME) triggered by the I2C bus, and then monitors the wake-up signal (SPI_RESUME) triggered by the SPI bus. Figure 4 The figure shows a rising edge on I2C_RESUME first, triggering TIMER_EN to enable. LP_CLK drives TIMER_CNT to begin counting up from 32'h0, with a target timeout of 5ms. If SPI_RESUME is asserted within 1ms after I2C wakeup, meaning that the rising edge of SPI_RESUME in the figure occurs shortly after I2C wakeup, the count rewrite logic is triggered. The original timer target was 5ms, but because SPI wakeup occurs within 1ms, it needs to be adjusted to 4ms. The TIMER_CNT count value is forcibly rewritten. For example, if the TIMER_CNT value jumps at a certain point in the TIMER_CNT sequence, it is replaced with the 4ms remaining count value, ensuring that the timer ultimately times out 4ms after I2C wakeup.

[0056] The above embodiment monitors wake-up commands from multiple hosts in real time. The chip dynamically adjusts the sleep duration based on the retransmission times of different hosts, allowing the chip to wait in low-power mode until all relevant hosts are ready for data transmission. This prevents the chip from idling after wakeup due to unready hosts, thus reducing inefficient power consumption in active mode. This dynamically adjusts the sleep duration, prioritizing I2C responses. If SPI follows quickly, the remaining wait time is compressed, allowing the chip to more flexibly adapt to multiple bus wake-up requirements.

[0057] Based on the above embodiment, if no second host wake-up command is received within the preset time, the sleep maintenance time is equal to the first host retransmission time and is not updated based on the second host retransmission time. Continuing with the previous example, if an SPI wake-up command is received after 1ms, there is no need to reset the timer's current value. If no second host command is detected within the preset time, the chip does not need to execute the sleep maintenance time update logic, reducing the processor's additional computational overhead in sleep mode, lowering the power consumption increase caused by frequent logic checks, and maintaining the stability of low-power mode.

[0058] like Figure 5 As shown, if SPI_RESUME is set more than 1ms after I2C wakeup, that is, more than 1ms after TIMER_CNT is started, as shown in the figure, the rising edge of SPI_RESUME occurs 1ms after I2C wakeup, triggering the logic of not intervening in the count value. The timer continues to run according to the initial target 5ms timeout, and TIMER_CNT continues to accumulate, unaffected by the SPI wakeup. As shown in the figure, the TIMER_CNT sequence does not jump, maintaining continuous counting. This implements dynamic filtering of invalid interventions, adjusting the timing if the SPI wakeup occurs within 1ms, and maintaining the original process after 1ms. This ensures multi-bus coordination while avoiding logic confusion caused by frequent rewriting of the count value.

[0059] In the above embodiment, when only the first host sends a wake-up command, the chip sets the sleep duration based on its retransmission time and wakes up immediately after the countdown ends. This avoids extending the sleep period while waiting for a command from a non-existent second host, ensuring the timeliness of the first host's data transmission and preventing communication timeouts or data loss due to delays. If multiple hosts are present but the second host does not send a command within the preset time, the chip wakes up at the original time. This avoids missing the first host's valid retransmission window due to a long wait for the second host, prevents confusion in multi-host communication timing, ensures the independent reliability of each host interface, and reduces power consumption caused by repeated wake-ups due to timing conflicts.

[0060] In some embodiments, upon detecting at least one host wake-up command, determining a sleep maintenance time includes: responding to the at least one host wake-up command, comparing at least one host retransmission time corresponding to the at least one host wake-up command; and determining the shortest host retransmission time from the at least one host retransmission time as the sleep maintenance time. Using the shortest retransmission time as the sleep maintenance time allows the chip to minimize the duration of low-power mode while still meeting the fastest host response requirements. This avoids excessive standby time due to long retransmission times, reduces unnecessary low-power state duration, and reduces the additional power consumption associated with switching between active and sleep modes.

[0061] This explanation will still use the first host wake-up command and the second host wake-up command as examples. If both the first host wake-up command and the second host wake-up command are detected simultaneously, the first host retransmission time corresponding to the first host wake-up command is compared with the second host retransmission time corresponding to the second host wake-up command. If the first host retransmission time is less than the second host retransmission time, the first host retransmission time is used as the sleep maintenance time.

[0062] For example, if both I2C_RESUME and SPI_RESUME are detected simultaneously, and the host retransmission time for I2C_RESUME is 5ms, while that for SPI_RESUME is 4ms, the SPI_RESUME host retransmission time is shorter, so it is determined to have higher priority. Therefore, the sleep duration is set to 4ms, and its corresponding timer is started. The I2C timer is not started or is suspended until the SPI timer completes counting, indicating that the chip responds to I2C before processing SPI.

[0063] In the above embodiment, when multiple hosts send wake-up commands at the same time, the chip uses the shortest retransmission time as the sleep maintenance time to ensure that it maintains a low power consumption state during the retransmission cycle of the host, and wakes up immediately after the countdown ends, avoiding the request timeout of the short-cycle host due to the use of a longer retransmission time, thereby ensuring the timeliness of data transmission of the high-frequency communication host.

[0064] In other embodiments, when at least one host wake-up command is not detected, the control chip enters a wake-up wait state; when the chip is in the wake-up wait state, a low-power clock is used to accumulate counts, and when the count reaches a threshold, the control chip returns to active mode. If at least one host wake-up command is not detected, the low-power clock will wake up as a backup to ensure that the system will not be asleep all the time and can execute tasks periodically. The power consumption of the low-power clock is much lower than that of the system main clock (SYSCLK). In the sleep wait state, it is only driven by LP_CLK to count, avoiding high power consumption caused by the operation of the main clock while maintaining the timing function. Among them, by configuring the counting threshold, the backup wake-up period can be customized, such as 1 second, 10 minutes, which not only meets the periodic requirements of different tasks, but also controls the overall energy consumption through the low-power characteristics of LP_CLK, avoiding the increase in power consumption caused by high-frequency wake-up.

[0065] refer to Figure 3As shown in the figure, when the chip enters sleep mode (ENTER), the main clock (SYSCLK) is shut down, while the low-power clock (LP_CLK) remains oscillating to maintain timer counting and ensure the chip can be woken up at scheduled times. The timer enable signal (TIMER_EN) is set in sleep mode to start the timer; the timer counter (TIMER_CNT) starts counting from 32'h0 during sleep mode; the timer wake-up signal (TIMER_RESume) is triggered when the counter reaches the threshold, prompting the system to exit sleep mode (EXIT). This allows automatic wake-up after a specified sleep duration.

[0066] In the above embodiment, when the chip does not receive any host wake-up command, the low-power clock continues to count and forcibly wakes up the chip after reaching the threshold, preventing the system from task stagnation due to long-term sleep, ensuring that the device can still periodically perform basic tasks without external intervention, and improving system robustness.

[0067] In addition, the host wake-up command has a higher priority than the low-power clock backup wake-up. The chip is timed by LP_CLK while listening to the host command. If the host command is triggered first, it will respond immediately. If it times out, LP_CLK will backup it, realizing a wake-up strategy that combines external trigger priority with internal timing guarantee, taking into account both response flexibility and autonomous operation capability.

[0068] S203: Count down according to the sleep duration.

[0069] S204: After the countdown ends, the control chip returns to the active mode.

[0070] After the countdown ends, the control chip exits the wake-up wait state, restores power, restarts the main clock, and the CPU becomes ready again, returning to active mode.

[0071] For example, Figure 4 As shown in the figure, when TIMER_CNT accumulates to the count value corresponding to 4ms, TIMER_RESume is set, pushing the chip to exit the sleep mode (EXIT) from the wake-up wait state (RESUME_WAIT) and finally resume the active mode (ACTIVE).

[0072] Another example is Figure 5 As shown in the figure, when TIMER_CNT accumulates to the count value corresponding to 5ms, TIMER_RESume is set, pushing the chip to exit the sleep mode (EXIT) from the wake-up wait state (RESUME_WAIT) and finally resume the active mode (ACTIVE).

[0073] In some embodiments, after the control chip exits the wake-up wait state, the chip enters an active mode. While in the active mode, the chip monitors at least one host retransmission instruction; and upon receiving the at least one host retransmission instruction, receives retransmitted data from at least one host.

[0074] like Figure 3 As shown, at least one host's retransmission instruction can be a retransmission frame, and the I2C data that was not completed before the chip went to sleep is retransmitted when the chip is in active mode (ACTIVE) to ensure communication integrity.

[0075] In the above embodiment, the chip continuously listens for retransmission commands from at least one host in active mode, allowing it to promptly receive retransmitted data and avoid permanent packet loss due to unresponsiveness. This provides error recovery capabilities for data transmission without increasing power consumption, ensuring both reliability and efficiency.

[0076] The mode control method of the chip provided in the embodiment of the present application adds a wake-up wait state (RESUME_WAIT) compared to the traditional solution, such as Figure 6A As shown, it reflects the waiting for wake-up trigger during sleep; the sleep time is extended, such as Figure 6B Assume that the I2C retransmission time is 5ms, the recovery time after exiting sleep mode (EXIT) is 200us, and the time to configure the I2C register / DMA is 10us. Figure 6B In sleep mode (SLEEP), the chip enters the wake-up wait state (RESUME_WAIT) due to an I2C wake-up command. The sleep duration is equal to I2C retransmission time - exit sleep mode (EXIT) recovery time - I2C register configuration / DMA time. Therefore, the chip stays in the wake-up wait state (RESUME_WAIT) for 4790µs.

[0077] In traditional solutions, the system immediately exits sleep mode (EXIT) after receiving the wake-up command and enters the active state after 200us. However, the host has not yet started retransmitting data at this time, causing the chip to wait in vain for about 5ms in the active state, resulting in significant ineffective power consumption. This application introduces the RESUME_WAIT state, which extends the sleep time to 4790us, allowing the chip to wait in a low-power state until the host is ready to retransmit. The EXIT process (200us) and configuration process (10us) are only started after the countdown ends, ensuring that data transmission begins immediately after wake-up and reducing ineffective waiting time in active mode.

[0078] In summary, when the chip is in sleep mode, the present application does not wake up immediately after listening to the host wake-up command, but first determines the sleep maintenance time. This means that the chip will not rush into active mode simply because it receives a request, reducing unnecessary wake-up operations and avoiding power consumption waste during the no-task period after waking up; through the countdown mechanism, the chip remains in sleep state during the determined sleep maintenance time, and does not return to active mode until the countdown ends. This method enables the chip to wait for the host to be ready for retransmission in a low-power state, or wait for a more appropriate time to wake up, ensuring that valid data can be processed immediately after waking up, rather than wasting power in a no-task state, thereby improving the chip's energy efficiency management level in low-power mode. In this way, by adding sleep maintenance time judgment and countdown mechanism, the technical problem of invalid activity and waste of power consumption caused by waiting for retransmission is solved, invalid power consumption caused by premature wake-up of the chip is avoided, and the efficiency of data transmission and energy consumption management in low-power mode are improved.

[0079] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0080] The embodiment of the present application also provides a mode control device of a chip, such as Figure 7 As shown, the device includes:

[0081] A monitoring module 701 is configured to monitor at least one host wake-up instruction when the chip is in sleep mode;

[0082] The processing module 702 is configured to determine a sleep maintenance time when at least one host wake-up command is detected;

[0083] A countdown module 703 is used to count down according to the sleep maintenance time;

[0084] The control module 704 is configured to control the chip to return to the active mode after the countdown ends.

[0085] As an optional implementation provided in an embodiment of the present application, the processing module 702 is specifically used to: control the chip to enter the wake-up waiting state when at least one host wake-up instruction is monitored; and determine the sleep maintenance time when the chip is in the wake-up waiting state.

[0086] As an optional implementation provided in an embodiment of the present application, the processing module 702 is specifically used to: respond to a first host wake-up instruction, determine a first sleep maintenance time based on the first host retransmission time; if a second host wake-up instruction is received within a preset time, update the first sleep maintenance time to a second sleep maintenance time, and the second sleep maintenance time is the second host retransmission time; wherein the preset time is less than the first sleep maintenance time.

[0087] As an optional implementation provided in an embodiment of the present application, the processing module 702 is specifically used to: respond to at least one host wake-up instruction, compare at least one host retransmission time corresponding to the at least one host wake-up instruction; and determine the shortest host retransmission time from the at least one host retransmission time as the sleep maintenance time.

[0088] As an optional implementation provided in an embodiment of the present application, the processing module 702 is also used to: when at least one host wake-up instruction is not detected, control the chip to enter a wake-up waiting state; when the chip is in the wake-up waiting state, use a low-power clock to accumulate counting; when the count reaches a threshold, control the chip to return to active mode.

[0089] As an optional implementation provided in an embodiment of the present application, the device also includes a retransmission module for monitoring at least one host retransmission instruction when the chip is in active mode; and receiving retransmission data from at least one host when at least one host retransmission instruction is monitored.

[0090] For the description of the features in the embodiment corresponding to the chip mode control device, please refer to the relevant description of the embodiment corresponding to the chip mode control method, which will not be repeated here.

[0091] The embodiment of the present application also provides an electronic device, such as Figure 8 As shown, it includes a memory 801 and a processor 802, wherein the memory 801 stores a computer program, and the processor 802 is configured to run the computer program to execute the steps in any of the above chip mode control method embodiments.

[0092] An embodiment of the present application further provides a computer-readable storage medium, which stores a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned chip mode control method embodiments when running.

[0093] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0094] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned chip mode control method embodiments are implemented.

[0095] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps in any of the above-mentioned chip mode control method embodiments.

[0096] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0097] The above is a detailed introduction to the mode control method, device, equipment, medium and product of a chip provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A chip mode control method, characterized in that: include: When the chip is in sleep mode, monitor at least one host wake-up command; determining a sleep maintenance time when the at least one host wake-up instruction is monitored; Counting down according to the sleep maintenance time; After the countdown ends, the chip is controlled to return to the active mode.

2. The method according to claim 1, characterized in that The step of determining the sleep maintenance time when the at least one host wake-up instruction is monitored includes: When the at least one host wake-up instruction is monitored, controlling the chip to enter a wake-up waiting state; When the chip is in the wake-up waiting state, the sleep maintenance time is determined.

3. The method according to claim 1, characterized in that The step of determining the sleep maintenance time when the at least one host wake-up instruction is monitored includes: In response to a first host wake-up instruction, determining a first sleep maintenance time according to a first host retransmission time; If a second host wake-up command is received within a preset time, the first sleep maintenance time is updated to a second sleep maintenance time, where the second sleep maintenance time is a second host retransmission time; Wherein, the preset time is shorter than the first sleep maintenance time.

4. The method according to claim 1, wherein The step of determining the sleep maintenance time when the at least one host wake-up instruction is monitored includes: In response to the at least one host wake-up instruction, comparing at least one host retransmission time corresponding to the at least one host wake-up instruction; From the at least one host retransmission time, a shortest host retransmission time is determined as the sleep maintenance time.

5. The method according to claim 1, wherein The method further comprises: When the at least one host wake-up instruction is not detected, controlling the chip to enter a wake-up waiting state; When the chip is in the wake-up waiting state, using a low-power clock to perform cumulative counting; When the count reaches a threshold, the chip is controlled to return to active mode.

6. The method according to claim 1 or 5, characterized in that The method further comprises: When the chip is in active mode, monitoring at least one host retransmission instruction; In case of monitoring the at least one host retransmission instruction, receiving the retransmitted data of at least one host.

7. A mode control device for a chip, characterized in that: include: A monitoring module, configured to monitor at least one host wake-up instruction when the chip is in sleep mode; a processing module, configured to determine a sleep maintenance time when monitoring the at least one host wake-up instruction; A countdown module, configured to count down according to the sleep maintenance time; The control module is used to control the chip to return to the active mode after the countdown ends.

8. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the mode control method of the chip according to any one of claims 1 to 6 when executing the computer program.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the mode control method of the chip according to any one of claims 1 to 6.

10. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the mode control method of the chip according to any one of claims 1 to 6 are implemented.

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