In-board synchronization method and device with digital function based on RFSoC, acquisition board card and phased array radio telescope

Abstract

The invention relates to the technical field of signal processing, and discloses an RFSoC-based in-board synchronization method with a digital function, and the method comprises the steps: carrying out the triggering synchronization configuration of a plurality of sampling channels under the condition that the plurality of sampling channels on a collection board card are in a time-delay mismatch state, and if the plurality of sampling channels reach a delay synchronization state through delay distribution synchronization; receiving a plurality of periods of first reference clock signals, and if a preset signal change condition of the first reference clock signals is captured, performing periodic pulse trigger synchronization on a plurality of sampling channels so as to ensure synchronous execution of a digital function; and performing synchronous phase locking on the plurality of sampling channels. The method has the beneficial effects that under the condition that the sampling channels reach a delay synchronization state, periodic pulse trigger synchronization is carried out on the sampling channels by utilizing clock signals, so that each sampling channel is ensured to synchronously execute a digital function, double synchronization of the sampling channels is realized, and the sampling channels are ensured to be in a high-precision synchronization state.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to an intra-board synchronization method and device with digital functions based on RFSoC, an acquisition board, and a phased array radio telescope. Background Art

[0002] Phased array systems are an advanced technology that precisely controls the phase and amplitude of multiple antenna elements in an array, enabling precise control of electromagnetic wave transmission and reception. With its rapid development, phased array systems have played an important role in a variety of fields, including radio astronomy, radar, ultrasonic imaging, and meteorological detection, and have broad application prospects. Each antenna element in a phased array system has a corresponding sampling channel, which is deployed on different acquisition boards. On some specialized acquisition boards, the sampling channels also have certain digital functions for digital signal processing. However, in practice, the digital signal processing within the sampling channels is affected by phase errors, which places higher demands on the synchronization between the sampling channels.

[0003] In the related art, the synchronization accuracy of the intra-board synchronization method for acquisition boards with digital functions still needs to be improved. Summary of the Invention

[0004] The present application provides an intra-board synchronization method, device, acquisition board and phased array radio telescope with digital functions based on RFSoC. When the sampling channel reaches a delayed synchronization state, the sampling channel is periodically pulse-triggered and synchronized using a clock signal, ensuring that each sampling channel executes the digital function synchronously, thereby achieving dual synchronization of the sampling channels and ensuring that the sampling channels are in a high-precision synchronization state.

[0005] In order to achieve the above objectives, the main technical solutions adopted in this application include: In a first aspect, an embodiment of the present application provides an intra-board synchronization method with digital functions based on RFSoC, the method comprising: In a case where multiple sampling channels on an acquisition board are in a time delay mismatch state, if the multiple sampling channels reach a delay synchronization state through delay allocation synchronization, trigger synchronization configuration is performed on the multiple sampling channels so that the multiple sampling channels synchronously receive a first reference clock signal; wherein the delay allocation synchronization is performed based on the first reference clock signal and a second reference clock signal, the first reference clock signal is used to set a delay measurement starting reference for the multiple sampling channels in the delay allocation synchronization, and the second reference clock signal is used to provide a delay measurement observation window for the multiple sampling channels in the delay allocation synchronization; receiving a plurality of cycles of the first reference clock signal, and if a preset signal change of the first reference clock signal is captured, performing periodic pulse triggering synchronization on the plurality of sampling channels to ensure synchronous execution of the digital function; The multiple sampling channels are synchronously phase-locked.

[0006] The embodiment of the present application proposes an intra-board synchronization with digital functions based on RFSoC. First, it determines whether the sampling channel is in a time-delay mismatch state. If so, the sampling channel is delayed and allocated for synchronization so that the sampling channel reaches a delayed synchronization state. Secondly, the sampling channel is triggered and synchronized to control the sampling channel to synchronously receive a first reference clock signal, and the sampling channel is periodically pulse-triggered and synchronized according to the first reference clock signal to repeatedly align the phase of the sampling channel. Finally, the sampling channel is synchronized and phase-locked. Compared with the related art, the present application performs dual synchronization on the sampling channel, which not only ensures that the sampling channel reaches a delayed synchronization state, but also eliminates the phase error between the sampling channels by periodically pulse-triggering the sampling channels, so that the sampling channels are in a stable phase synchronization state. By performing dual synchronization on the sampling channels, the synchronization accuracy between the sampling channels is effectively improved.

[0007] Optionally, the receiving of the first reference clock signal of multiple cycles, and if a preset signal change of the first reference clock signal is captured, performing periodic pulse triggering synchronization on the multiple sampling channels includes: For any sampling channel among the multiple sampling channels, performing signal change detection on the first reference clock signal to obtain a reference clock change state; When the preset signal change condition exists in the reference clock change state, determining that the preset signal change condition of the first reference clock signal is captured, and performing repeated phase initialization on the multiple sampling channels based on the preset signal change condition as a trigger reference; Acquire the phases to be synchronized of each of the multiple sampling channels, and perform phase compensation on each of the multiple sampling channels according to the phases to be synchronized, so that the phases of each of the multiple sampling channels are aligned with the preset initial channel phase; The preset signal change is used as a trigger reference to repeatedly phase align the multiple sampling channels until the number of cycles in which the preset signal change is captured reaches a preset cycle number threshold.

[0008] Optionally, the triggering and synchronously configuring the multiple sampling channels includes: Controlling the plurality of sampling channels to synchronously stop receiving the first reference clock signal; Performing initial phase setting on the plurality of sampling channels according to a preset initial channel phase; The plurality of sampling channels are controlled to synchronously start receiving the first reference clock signal.

[0009] Optionally, before controlling the plurality of sampling channels to synchronously start receiving the first reference clock signal, the method further includes: The trigger signals of the plurality of sampling channels are all set as the first reference clock signal.

[0010] Optionally, after triggering and synchronizing the plurality of sampling channels, the method further includes: When the preset signal change is captured, the channel phases of the multiple sampling channels are initialized according to the preset initial channel phases.

[0011] Optionally, the preset signal change condition is a rising edge of a pulse in the first reference clock signal.

[0012] Optionally, performing synchronous phase locking on the multiple sampling channels includes: The plurality of sampling channels are controlled to synchronously stop receiving the first reference clock signal.

[0013] In a second aspect, an embodiment of the present application provides an intra-board synchronization device with digital functions based on RFSoC, the device comprising: a trigger synchronization preparation module, configured to trigger synchronization configuration for the multiple sampling channels on the acquisition board, when the multiple sampling channels on the acquisition board are in a time delay mismatch state and the multiple sampling channels reach a delay synchronization state through delay allocation synchronization, so that the multiple sampling channels synchronously receive a first reference clock signal; wherein the delay allocation synchronization is performed based on the first reference clock signal and a second reference clock signal, the first reference clock signal being used to set a delay measurement starting reference for the multiple sampling channels in the delay allocation synchronization, and the second reference clock signal being used to provide a delay measurement observation window for the multiple sampling channels in the delay allocation synchronization; a pulse trigger synchronization module, configured to receive a plurality of cycles of the first reference clock signal, and if a preset signal change of the first reference clock signal is captured, perform periodic pulse trigger synchronization on the plurality of sampling channels to ensure synchronous execution of the digital function; The synchronous phase locking module is used to perform synchronous phase locking on the multiple sampling channels.

[0014] In a third aspect, an embodiment of the present application provides an acquisition board with digital functions based on RFSoC, which performs intra-board synchronization through the method described in any one of the above embodiments.

[0015] In a fourth aspect, an embodiment of the present application provides a phased array radio telescope, comprising an acquisition board according to any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1 A diagram showing the steps of an intra-board synchronization method with digital functions based on RFSoC provided in an embodiment of the present application; Figure 2 This is a diagram of the steps of periodic pulse triggering synchronization in an embodiment of the present application; Figure 3 A diagram showing the steps for triggering synchronization configuration in an embodiment of the present application; Figure 4 A module diagram of an intra-board synchronization device with digital functions based on RFSoC provided in an embodiment of the present application; Figure 5 This is a hardware block diagram of an acquisition board with digital functions based on RFSoC in an embodiment of the present application; Figure 6 This is a clock tree structure diagram of an acquisition board with digital functions based on RFSoC in an embodiment of the present application; Figure 7 A schematic structural diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0018] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0019] Phased array systems are an advanced technology that precisely controls the phase and amplitude of multiple antenna elements in an array, enabling precise control of electromagnetic wave transmission and reception. With its rapid development, phased array systems have played an important role in a variety of fields, including radio astronomy, radar, ultrasonic imaging, and meteorological detection, and have broad application prospects. Each antenna element in a phased array system has a corresponding sampling channel, which is deployed on different acquisition boards. On some specialized acquisition boards, the sampling channels also have certain digital functions for digital signal processing. However, in practice, the digital signal processing within the sampling channels is affected by phase errors, which places higher demands on the synchronization between the sampling channels.

[0020] Related technologies usually only use a single synchronization method to synchronize the sampling channels. For example, during the signal acquisition process, the timing asynchrony between the sampling channels may cause timing errors between the sampling signals, thereby affecting the signal quality. Therefore, in this case, it is necessary to ensure that the sampling channels reach a delayed synchronization state to improve the timing consistency between the sampling signals and improve the quality of the sampling signals. In other cases, when the sampling signals are obtained and processed, the phase difference between the sampling channels may have an adverse effect on the signal processing results, resulting in a decrease in signal quality. Therefore, in this case, it is necessary to ensure the phase synchronization of the sampling channels to correctly process the sampling signals and improve the accuracy of the signal processing results. In actual scenarios, timing asynchrony and phase differences may occur between the sampling channels at the same time. It is difficult to achieve stable and accurate synchronization between the sampling channels using only a single synchronization method.

[0021] Based on the above problems, the present application provides an intra-board synchronization method with digital functions based on RFSoC, including: when multiple sampling channels on the acquisition board are in a time delay mismatch state, if the multiple sampling channels reach a delayed synchronization state through delay distribution synchronization, trigger synchronization configuration for the multiple sampling channels; receive a first reference clock signal with multiple cycles, and if the preset signal change of the first reference clock signal is captured, perform periodic pulse trigger synchronization on the multiple sampling channels to ensure the synchronous execution of the digital functions; and synchronize the multiple sampling channels with the phase lock.

[0022] The intra-board synchronization method with digital functions based on RFSoC provided in the present application first determines whether the sampling channel is in a time delay mismatch state. If so, the sampling channel is delayed and allocated for synchronization so that the sampling channel reaches a delayed synchronization state; secondly, the sampling channel is triggered and synchronized to control the sampling channel to synchronously receive a first reference clock signal, and the sampling channel is periodically pulse-triggered and synchronized according to the first reference clock signal to repeatedly align the phase of the sampling channel; finally, the sampling channel is synchronized and phase-locked.

[0023] Compared with related technologies, this application implements dual synchronization of sampling channels, not only ensuring that the sampling channels reach a delayed synchronization state, but also eliminating phase errors between sampling channels by periodically triggering synchronization with pulses, thus ensuring that the sampling channels are in a stable phase synchronization state. By performing dual synchronization of sampling channels, the synchronization accuracy between sampling channels is effectively improved.

[0024] The RFSoC-based intra-board synchronization method with digital functions provided in this specification can be applied to any acquisition board within a phased array system. Phased array systems can be used in a variety of fields, including radio astronomy, radar, ultrasonic detection and imaging, and meteorological detection. In radio astronomy, phased array systems can be used to build phased array radio telescopes, enabling high-speed, real-time, and synchronous acquisition and preprocessing of large-scale, wide-band RF signals. It should be noted that this acquisition board includes digital functions that can perform certain digital signal processing on the sampled signals.

[0025] According to an embodiment of the present application, an embodiment of an intra-board synchronization method with digital functions based on RFSoC is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0026] In this embodiment, a method for synchronizing digital functions on a board based on RFSoC is provided, which can be used for the acquisition board mentioned above. Figure 1 As shown, the method includes: S100. When multiple sampling channels on an acquisition board are in a time delay mismatch state, if the multiple sampling channels reach a delay synchronization state through delay allocation synchronization, trigger synchronization configuration is performed on the multiple sampling channels so that the multiple sampling channels synchronously receive a first reference clock signal; wherein, the delay allocation synchronization is performed based on the first reference clock signal and the second reference clock signal, the first reference clock signal is used to set a delay measurement starting reference for the multiple sampling channels in the delay allocation synchronization, and the second reference clock signal is used to provide a delay measurement observation window for the multiple sampling channels in the delay allocation synchronization.

[0027] S200. Receive a plurality of cycles of a first reference clock signal. If a preset signal change of the first reference clock signal is captured, perform periodic pulse triggering synchronization on a plurality of sampling channels to ensure synchronous execution of digital functions.

[0028] S300. Perform synchronous phase locking on multiple sampling channels.

[0029] The skew mismatch state can occur when the delay values ​​of the sampling channels differ, preventing synchronized signal acquisition across the channels. This can be caused by hardware delays or signal processing delays. The delay synchronization state can occur when the sampling channels share the same target delay value, enabling synchronized signal acquisition across multiple channels.

[0030] Delay allocation synchronization involves assigning target delay values ​​to each sampling channel based on its delay values ​​measured by a first reference clock signal and a second reference clock signal when the sampling channels are in a skew mismatched state. Delay allocation synchronization ensures that the sampling channels share the same target delay value, achieving delay synchronization between the sampling channels and enabling multi-channel synchronous signal acquisition.

[0031] The first reference clock signal can be a reference clock signal with a specific clock frequency, which is used as a global reference clock to perform clock alignment on each sampling channel, so as to set the same delay value measurement benchmark for each sampling channel. The second reference clock signal can be a reference clock signal with the same frequency and a constant phase difference as the first reference clock signal, which is used to perform clock alignment on the programmable logic area corresponding to each sampling channel, and provide the same delay measurement observation window for each sampling channel to synchronously control each sampling channel to perform delay value measurement. It can be understood that based on the coordination between the first reference clock signal and the second reference clock signal, the clock domain deviation that may occur during the delay value measurement process is effectively eliminated, thereby improving the accuracy of the delay value measurement result. In addition, based on the first reference clock signal and the second reference clock signal with the same frequency and a constant phase difference, the delay value measurement of each sampling channel can be repeated, which effectively improves the reliability of the delay value measurement result.

[0032] Specifically, the acquisition board is clock-enabled, and the first reference clock signal, the second reference clock signal, and the sampling reference clock signal are started. It should be noted that the sampling reference clock signal is used as the signal sampling reference clock for the sampling channel after the on-board synchronization is completed, triggering each sampling channel to perform synchronous signal acquisition. Next, a status self-test is performed on the acquisition board to determine whether the acquisition board is operating normally. The status self-test may include a module enable status check, a phase-locked status check, a power-on status check, and a channel enable status check, thereby ensuring that the modules and sampling channels on the acquisition board have a stable initial state, that there are no faults within the acquisition board, and that each sampling channel can start the synchronization process. After completing the clock signal enable and status self-test, the delay value of each sampling channel in the acquisition board is initialized.

[0033] Furthermore, when a sampling channel is in a skew mismatch state, delay allocation synchronization is performed on each sampling channel based on the first reference clock signal and the second reference clock signal, so that each sampling channel has the same target delay value, achieving a delay synchronization state, and realizing multi-channel synchronous signal acquisition. The process of determining whether a sampling channel is in a skew mismatch state may include: measuring the delay value of each sampling channel based on the first reference clock signal and the second reference clock signal to obtain a delay value for each sampling channel; and determining that the sampling channel is in a skew mismatch state if there is a difference between the delay values ​​of the sampling channels.

[0034] The process of measuring the delay value of each sampling channel may include: performing global clock alignment on each sampling channel according to a first reference clock signal, and performing clock alignment on the programmable logic portion of each sampling channel according to a second reference clock signal, so that each sampling channel uses the same reference clock signal as a measurement reference; issuing a delay value test instruction to each sampling channel based on a preset signal change in the second reference clock signal, controlling each sampling channel to perform delay value measurement based on the preset signal change in the first reference clock signal as a reference, and obtaining a delay value for each sampling channel; wherein the preset signal change in the first reference clock signal and the second reference clock signal can be a rising edge or a falling edge of a pulse signal, etc. It can be understood that using the first reference clock signal and the second reference clock signal to perform synchronous delay value measurement on each sampling channel reduces the timing error that may be generated when each sampling channel performs delay value measurement independently, thereby improving the accuracy of the delay value measurement results. In addition, using the first reference clock signal and the second reference clock signal can also realize automatic delay value measurement without manual intervention by an operator, reducing the influence of operator experience on the delay value measurement results, and improving the efficiency and accuracy of delay value measurement.

[0035] On this basis, the delay allocation synchronization process may include: performing a distribution analysis on the delay values ​​of each sampling channel, determining a delay value that meets the preset delay synchronization requirement from all delay values, and performing redundant processing on the delay value to obtain a delay value to be allocated; wherein the preset delay synchronization requirement may be the maximum value, minimum value, average value, or median value of all delay values, and the redundant processing may be adding a redundant delay period on the basis of the delay value. For example, the preset delay synchronization requirement may be the maximum value of all delay values, and the redundant delay period added by the redundant processing may be 16 clock periods; based on the first reference clock signal, synchronously allocating the delay value to be allocated to each sampling channel to set the target delay value of each sampling channel to the delay value to be allocated, so that each sampling channel reaches a delay synchronization state. Through delay allocation synchronization, the sampling channels share the same target delay value, and the sampling channels reach a delay synchronization state, thereby realizing multi-channel synchronous signal acquisition.

[0036] Furthermore, after the sampling channels reach the delayed synchronization state, each sampling channel is triggered and synchronized so that each sampling channel can synchronously receive the first reference clock signal. Next, each sampling channel is controlled to stably receive the first reference clock signal for multiple cycles, and the preset signal change of the first reference clock signal in each cycle is used as a trigger condition to periodically trigger each sampling channel for pulse synchronization so that each sampling channel reaches a phase synchronization state, ensuring that each sampling channel can synchronously execute digital functions and reduce the phase difference between multiple sampling signals. It can be understood that when in the phase synchronization state, the sampling signals in each sampling channel have phase consistency, eliminating the error between the sampling signals of different sampling channels and improving the observation accuracy based on multi-channel sampling signals. In addition, each sampling channel can output the sampling signal with the same phase, so that the sampling signals can be correctly superimposed or interfered with, optimizing the signal strength and accuracy for a specific frequency point, thereby improving the signal quality.

[0037] Furthermore, on the basis that each sampling channel reaches a phase synchronization state, the sampling channels are synchronously phase-locked to prevent the phase synchronization state between the sampling channels from being interfered with by environmental factors or hardware equipment factors, thereby ensuring that the phase synchronization state can be maintained during the subsequent synchronous signal acquisition process and improving the synchronization between the sampling channels.

[0038] The intra-board synchronization method with digital functions based on RFSoC provided in this embodiment first determines whether the sampling channel is in a time delay mismatch state. If so, delay allocation synchronization is performed on the sampling channel so that the sampling channel reaches a delay synchronization state. Secondly, trigger synchronization configuration is performed on the sampling channel to control the sampling channel to synchronously receive a first reference clock signal, and periodic pulse trigger synchronization is performed on the sampling channel based on the first reference clock signal to repeatedly align the phases of the sampling channel. Finally, synchronization phase locking is performed on the sampling channel.

[0039] Compared with related technologies, this application implements dual synchronization of sampling channels, not only ensuring that the sampling channels reach a delayed synchronization state, but also eliminating phase errors between sampling channels by periodically triggering synchronization with pulses, thus ensuring that the sampling channels are in a stable phase synchronization state. By performing dual synchronization of sampling channels, the synchronization accuracy between sampling channels is effectively improved.

[0040] Reference Figure 2 As shown, as an embodiment of the present application, a first reference clock signal with multiple cycles is received, and if a preset signal change of the first reference clock signal is captured, periodic pulse triggering synchronization is performed on multiple sampling channels, including: S210 . For any sampling channel among the multiple sampling channels, perform signal change detection on the first reference clock signal to obtain a reference clock change state.

[0041] S220. When a preset signal change condition exists in the reference clock change state, determine that the preset signal change condition of the first reference clock signal is captured, and use the preset signal change condition as a trigger reference to perform repeated phase initialization on multiple sampling channels.

[0042] S230. Obtain the phases to be synchronized of the plurality of sampling channels, and perform phase compensation on the plurality of sampling channels according to the phases to be synchronized, so that the phases of the plurality of sampling channels are aligned with the preset initial channel phases.

[0043] S240. Using the preset signal change as a trigger reference, repeatedly phase align multiple sampling channels until the number of cycles capturing the preset signal change reaches a preset cycle number threshold.

[0044] The preset signal change condition may be a condition in which a signal characteristic of the first reference clock signal changes, and the signal characteristic may include a signal level, frequency, amplitude, or phase, etc. For example, the preset signal change condition may be a condition in which the level of the first reference clock signal changes from a low level to a high level.

[0045] Specifically, after receiving the first reference clock signal, each sampling channel performs change detection on the corresponding signal characteristics of the first reference clock signal based on the signal characteristics set in the preset signal change situation, and obtains the reference clock change state of the first reference clock signal. The reference clock change state includes the changes of the corresponding signal characteristics in the first reference clock signal over a period of time. The duration of the reference clock change state is shorter than a single clock cycle of the first reference clock signal.

[0046] Furthermore, when a preset signal change condition exists in the reference clock change state, the preset signal change condition of the first reference clock signal is determined to be captured, and the time point of the preset signal change condition is used as the trigger reference for each sampling channel. The initial phase setting of each sampling channel is activated to initialize the phase of each sampling channel. It should be noted that, through multiple cycles of the first reference clock signal, each sampling channel can be repeatedly initialized in phase, ensuring the accuracy of subsequent phase acquisition of each sampling channel. Exemplarily, the number of repetitions of phase initialization can be determined based on a preset cycle number threshold.

[0047] Furthermore, taking into account the possible phase differences between the sampling channels, the phase of each sampling channel is collected to obtain the phase to be synchronized for each sampling channel. Difference calculation is performed based on the phase to be synchronized to determine the phase difference between the sampling channels, and the phase of each sampling channel is individually set based on the phase difference to perform phase compensation on each sampling channel so that the phase of each sampling channel is aligned with the preset initial channel phase. It is understandable that the preset initial channel phase can be the phase value of any sampling channel among all the sampling channels, or it can be a pre-set phase value. By aligning the phase of each sampling channel, it is ensured that the sampling channel will not have a phase misalignment problem when using digital functions for signal processing, thereby ensuring the quality of signal processing and improving the synchronization between the sampling channels. Among them, the digital function can be a function of digitally processing the sampling signal, such as digital orthogonal demodulation.

[0048] Furthermore, a predetermined signal variation of the first reference clock signal occurring over multiple clock cycles is captured. This predetermined signal variation serves as a trigger reference for each sampling channel, and the aligned phase settings of each sampling channel are activated to synchronize all sampling channels, further improving phase synchronization between the sampling channels. When the number of cycles in which the predetermined signal variation is captured reaches a predetermined threshold, it indicates that the phase synchronization between the sampling channels has met the predetermined requirement, and repeated phase alignment is stopped.

[0049] In some embodiments, due to the introduction of digital functions, the signal flow of each sampling channel passes through the analog processing domain and the digital processing domain. The two signal processing domains each correspond to clock signals with different processing frequencies. There may be a phase difference between the analog processing clock corresponding to the analog processing domain and the digital processing clock corresponding to the digital processing domain. When each signal enters the digital processing domain from the analog processing domain, the phase difference between the analog processing clock and the digital processing clock will cause signal delay errors in different sampling channels, affecting the synchronization between the sampling channels. Therefore, when performing on-board synchronization processing, each sampling channel uses the same analog processing clock and digital processing clock, and the relative phase of the analog processing clock and the digital processing clock is determined to ensure that each signal enters the digital processing domain at the same clock position.

[0050] Reference Figure 3 As shown, as an embodiment of the present application, trigger synchronization configuration is performed on multiple sampling channels, including: S110 . Control multiple sampling channels to synchronously stop receiving the first reference clock signal.

[0051] S120. Perform initial phase setting on multiple sampling channels according to a preset initial channel phase.

[0052] S130. Control multiple sampling channels to synchronously start receiving the first reference clock signal.

[0053] Specifically, an API function is called in the programmable logic of each sampling channel to disable the reference signal receiver of each sampling channel, causing the sampling channel to synchronously stop receiving the first reference clock signal. For example, for Xilinx's RFDC IP core, the called API function may be XRFdc_MTS_Sysref_Config. By controlling each sampling channel to synchronously stop receiving the first reference clock signal, false triggering of any sampling channel by the first reference clock signal is avoided, and phase interference between the sampling channels caused by the first reference clock signal is reduced.

[0054] Furthermore, an API function is called to set the initial phase of the sampling channels, setting the initial phase of each sampling channel to a preset initial channel phase to ensure that the initial phase states of each sampling channel are the same before the pulse trigger synchronization. For example, for Xilinx's RFDC IP core, the called API function may be XRFdc_SetMixerSettings.

[0055] Furthermore, an API function is called to enable the reference signal receiver of each sampling channel, allowing the sampling channels to synchronously begin receiving the first reference clock signal. For example, for Xilinx's RFDC IP core, the API function called may be XRFdc_MTS_Sysref_Config. By controlling each sampling channel to synchronously begin receiving the first reference clock signal, the first reference clock signal ensures that each sampling channel can simultaneously trigger pulse triggering synchronization, improving synchronization between the sampling channels.

[0056] As an embodiment of the present application, before controlling the multiple sampling channels to synchronously start receiving the first reference clock signal, the method further includes: S132. Set the trigger signals of the plurality of sampling channels as the first reference clock signal.

[0057] Specifically, an API function is called to set the mixer trigger source for each sampling channel to the first reference clock signal. This allows each sampling channel to detect changes in a preset signal in the first reference clock signal, which serves as a trigger signal, and then be triggered by the preset signal changes to perform periodic pulse trigger synchronization. For example, for Xilinx's RFDC IP core, the API function called may be XRFdc_SetMixerSettings.

[0058] It should be noted that the trigger signals of all sampling channels are set to the first reference clock signal, and when the first reference clock signal is received synchronously, they are synchronously triggered by the first reference clock signal to perform periodic pulse trigger synchronization, thereby reducing the timing error between the sampling channels during the pulse trigger synchronization process and improving the synchronization between the sampling channels.

[0059] As an embodiment of the present application, after triggering and synchronizing the multiple sampling channels, the method further includes: S140. When a preset signal change is captured, initialize the channel phases of multiple sampling channels according to a preset initial channel phase.

[0060] Specifically, after setting the initial phase of each sampling channel to the preset initial channel phase, an API function is further called to make the initial phase setting effective, ensuring that the initial phase states of each sampling channel are the same before the pulse trigger synchronization. For example, for Xilinx's RFDC IP core, the API function called can be XRFdc_ResetNCOPhase to reset the NCO initial phase of each sampling channel.

[0061] As an embodiment of the present application, the preset signal change condition is a rising edge of a pulse in the first reference clock signal.

[0062] Specifically, the preset signal change condition may be a rising edge of a pulse in the first reference clock signal, indicating that the level of the first reference clock signal has changed from a low level to a high level. In other embodiments, the preset signal change condition may be a change in a signal characteristic of the first reference clock signal, where the signal characteristic may include the signal level, frequency, amplitude, or phase. It is understood that the preset signal change condition is obtained by detecting a reference clock change state of the first reference clock signal, where the reference clock change state includes changes in corresponding signal characteristics of the first reference clock signal over a period of time, and the duration of the reference clock change state is shorter than a single clock cycle of the first reference clock signal.

[0063] As an embodiment of the present application, performing synchronous phase locking on multiple sampling channels includes: S310. Control multiple sampling channels to synchronously stop receiving the first reference clock signal.

[0064] Specifically, an API function is called in the programmable logic of each sampling channel to disable the reference signal receiver of each sampling channel, causing the sampling channel to synchronously stop receiving the first reference clock signal and prevent the first reference clock signal from falsely triggering any sampling channel. For example, for Xilinx's RFDC IP core, the called API function may be XRFdc_MTS_Sysref_Config.

[0065] It can be understood that, on the basis of each sampling channel reaching a phase synchronization state, the sampling channels are synchronously phase-locked to prevent the phase synchronization state between the sampling channels from being interfered with by environmental factors or hardware equipment factors, to ensure that the phase synchronization state can be maintained during the subsequent synchronous signal acquisition process, and to improve the synchronization between the sampling channels.

[0066] Accordingly, please refer to Figure 4 The embodiment of the present application provides an intra-board synchronization device with digital functions based on RFSoC, the device comprising: The trigger synchronization preparation module 410 is configured to trigger synchronization configuration for the multiple sampling channels on the acquisition board when the multiple sampling channels are in a time delay mismatch state and reach a delay synchronization state through delay allocation synchronization, so that the multiple sampling channels synchronously receive the first reference clock signal. The delay allocation synchronization is performed based on the first reference clock signal and the second reference clock signal. The first reference clock signal is used to set a delay measurement starting reference for the multiple sampling channels in the delay allocation synchronization, and the second reference clock signal is used to provide a delay measurement observation window for the multiple sampling channels in the delay allocation synchronization. The pulse trigger synchronization module 420 is configured to receive a plurality of cycles of the first reference clock signal and, upon detecting a predetermined signal change of the first reference clock signal, perform periodic pulse trigger synchronization on the plurality of sampling channels to ensure synchronous execution of digital functions. The synchronous phase locking module 430 is used to perform synchronous phase locking on multiple sampling channels.

[0067] In some optional implementations, the pulse trigger synchronization module 420 includes: The signal change detection unit is used to perform signal change detection on the first reference clock signal for any sampling channel among the multiple sampling channels to obtain a reference clock change state.

[0068] The signal capture alignment unit is used to determine the preset signal change situation of the captured first reference clock signal when there is a preset signal change situation in the reference clock change state, and use the preset signal change situation as a trigger reference to perform repeated phase initialization on multiple sampling channels.

[0069] The signal phase compensation unit is used to obtain the phase to be synchronized of each of the multiple sampling channels, and perform phase compensation on the multiple sampling channels according to the phase to be synchronized, so that the phase of each of the multiple sampling channels is aligned with the preset initial channel phase.

[0070] The periodic repetition processing unit is used to repeatedly phase align multiple sampling channels using the preset signal change as a trigger reference until the number of cycles capturing the preset signal change reaches a preset cycle number threshold.

[0071] In some optional implementations, triggering the synchronization preparation module 410 includes: The synchronous stop receiving unit is used to control the multiple sampling channels to synchronously stop receiving the first reference clock signal.

[0072] The initial phase setting unit is used to set the initial phases of the multiple sampling channels according to the preset initial channel phases.

[0073] The synchronous start receiving unit is used to control the multiple sampling channels to synchronously start receiving the first reference clock signal.

[0074] In some optional implementations, the synchronous start receiving unit includes: The trigger signal setting subunit is used to set the trigger signals of the multiple sampling channels as the first reference clock signal.

[0075] In some optional implementations, triggering the synchronization preparation module 410 includes: The phase initialization unit is used to initialize the channel phases of multiple sampling channels according to the preset initial channel phase when the preset signal change is captured.

[0076] In some optional implementations, in the pulse-triggered synchronization module 420 , the preset signal change condition is a rising edge of a pulse in the first reference clock signal.

[0077] In some optional implementations, the synchronization phase locking module 430 includes: The phase locking unit is used to control the multiple sampling channels to synchronously stop receiving the first reference clock signal.

[0078] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0079] The intra-board synchronization device with digital functions based on RFSoC in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0080] Reference Figure 5 As shown, an embodiment of the present application provides an acquisition board with digital functions based on RFSoC, which performs intra-board synchronization through the method described in any one of the above embodiments.

[0081] The acquisition board provided in this embodiment includes an input interface, a clock management module, an RFSoC series FPGA processing chip, a DDR memory module, a power module, and an output interface. The input interface includes an 8-channel RF signal acquisition interface and a 2-channel clock signal interface. The clock management module can be a single clock chip, which is connected to the clock signal interface and generates the various clock signals required for the acquisition board by receiving an external 10MHz reference clock. The RFSoC series FPGA processing chip integrates an RFDCIP core, which can simultaneously perform analog-to-digital conversion or digital processing on the analog signals input by the 8-channel RF signal acquisition interface. The DDR memory module is used to expand the data storage capacity of the acquisition board. The power module includes Core PWR and PWR Conn, which provide the acquisition board with the voltage required during the signal acquisition process. The output interface includes four QSFP28 optical ports and one GE Ethernet port. The QSFP28 optical port has a single-port communication rate of up to 100Gbps.

[0082] Reference Figure 6As shown, the acquisition board provided in this embodiment is designed with a synchronous clock tree based on a single clock chip. The synchronous clock tree includes a clock chip, a PL MMCM divider, a radio frequency clock chip and an RFDC IP core. The RFDC IP core contains multiple sampling channels, represented by ADC Tiles. All sampling channels operate in the same working mode and are configured with the same working parameters. Among them, the clock chip serves as the basis of the synchronous clock tree, is used to generate a homologous clock signal, and sends it to multiple modules on the acquisition board, providing a synchronous clock basis for each of the multiple modules. It can be understood that a single clock chip outputs a clock signal in a unified manner, reduces the clock drift and error between multiple clock signals, and improves the timing consistency between clock signals. In addition, the single clock chip also simplifies the hardware design on the acquisition board, reduces the complexity of the module, and improves the hardware stability and ease of use of the acquisition board.

[0083] The PL MMCM divider is used to divide the clock signal output by the clock chip to generate the ADC parallel data output clock AXIS_clock and the back-end signal processing clock USER_clock to control the output and processing of the sampling signal and ensure the synchronization between different sampling signals in the above process. The PL MMCM divider also includes clock frequency conversion, clock phase control, clock division and multiplication, and clock synchronization. It can be understood that the sampling signal is synchronously output to the RFSoC FPGA processing chip on the acquisition board to perform synchronous signal processing on the sampling signal. For example, the frequency of the ADC parallel data output clock AXIS_clock can be 250MHz, and the frequency of the back-end signal processing clock USER_clock can be 350MHz.

[0084] The RF clock chip is used to receive the clock signal sent by the clock chip, and obtain a sampling reference clock signal based on the clock signal to send it synchronously to the RFDC IP core, providing a synchronous clock basis for the sampling channel in the signal acquisition process, so that the sampling channel can perform synchronous signal acquisition. After receiving the clock signal sent by the clock chip, the RF clock chip performs a clock operation on the clock signal to obtain a sampling reference clock signal for sending to the RFDC IP core. When the frequency of the sampling reference clock signal is outside the clock frequency range corresponding to the clock chip, the clock chip cannot directly generate a sampling reference clock signal for the RFDC IP core, and it is necessary to perform a clock operation on the clock signal through the RF clock chip to generate a sampling reference clock signal that meets actual needs. For example, the clock operation can be clock multiplication or clock phase adjustment.

[0085] The RFDC IP core receives synchronous sampling signals from the RF clock chip and internally distributes the sampling reference clock signal to multiple sampling channels, enabling all sampling channels to perform synchronous signal acquisition based on the sampling reference clock signal. The sampling channels can be analog-to-digital converter (ADC) channels, which convert analog signals obtained through signal acquisition into digital signals for further processing and analysis.

[0086] In some embodiments, the RFDC IP core may have only a single input, which may be the input of a reference channel among multiple sampling channels. After receiving an external input signal, the reference channel distributes the input signal to other sampling channels within the RFDC IP core to operate according to the input signal. It is understood that the reference channel, at this time, serves as the base channel for all sampling channels and is activated during subsequent synchronization processing and synchronous acquisition. The other sampling channels are synchronized with the reference channel, effectively improving the synchronization between the sampling channels. In addition, the single input also reduces the hardware resources required to set up the RFDC IP core, reduces the complexity of the module connection design on the acquisition board, and improves the integration of the acquisition board.

[0087] Between the above modules, the output of the clock chip is connected to the input of the RF clock chip. The output of the RF clock chip and the output of the clock chip are respectively connected to the input of the RFDC IP core. The input of the PL MMCM divider is connected to the output of the clock chip. Based on the connection with the RF clock chip, the RFDC IP core receives a sampling reference clock signal from the RF clock chip. Based on the connection with the clock chip, it receives a first reference clock signal AMS_SYSREF and a second reference clock signal PL_SYSREF from the clock chip. For example, the frequency of the sampling reference clock signal can be 4 GHz, the frequency of the first reference clock signal AMS_SYSREF can be 10 MHz, and the frequency of the second reference clock signal PL_SYSREF can be 10 MHz.

[0088] Before the sampling channels begin synchronous signal acquisition, the RFDC IP core receives the first reference clock signal AMS_SYSREF and the second reference clock signal PL_SYSREF, and uses them as reference clocks. It synchronizes the sampling channels internally based on the first and second reference clock signals AMS_SYSREF and PL_SYSREF, performing delay allocation synchronization on the sampling channels using the resulting delay values ​​to be allocated. Furthermore, the core performs pulse trigger synchronization on the sampling channels based on the first reference clock signal AMS_SYSREF, thereby eliminating delay and phase errors between different sampling channels. This allows multiple sampling channels to be aligned in timing and improves synchronization consistency across the sampling channels. It should be noted that the first and second reference clock signals AMS_SYSREF and PL_SYSREF are both generated by the clock chip, have the same clock frequency, and have a constant phase difference.

[0089] In some embodiments, the process of pulse trigger synchronization includes: turning off the reference signal receiver of each sampling channel and stopping receiving the first reference clock signal AMS_SYSREF; calling the API function to perform initial phase setting and application configuration update on each sampling channel, and setting the mixing trigger source of each sampling channel to the first reference clock signal AMS_SYSREF; turning on the reference signal receiver of each sampling channel so that each sampling channel synchronously receives the first reference clock signal AMS_SYSREF; capturing multiple cycles of the first reference clock signal AMS_SYSREF, using the pulse signal of the first reference clock signal AMS_SYSREF in each cycle as a trigger signal, and performing phase synchronization on each sampling channel to align the phases of each sampling channel; turning off the reference signal receiver of each sampling channel after the above-mentioned multiple cycles of the first reference clock signal AMS_SYSREF, and stopping receiving the first reference clock signal AMS_SYSREF to lock the phase setting of each sampling channel and ensure the phase synchronization state between the sampling channels.

[0090] An embodiment of the present application further provides a phased array radio telescope, comprising an acquisition board according to any one of the above embodiments.

[0091] See also Figure 7 , Figure 71 is a structural diagram of a computer device provided by an embodiment of the present application. As shown in the figure, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are connected to each other using different buses for communication and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the computer device, including instructions stored in or on the memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to an interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 7 A processor 10 is taken as an example.

[0092] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0093] The memory 20 stores instructions that can be executed by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0094] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0095] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0096] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0097] The embodiments of the present application also provide a computer-readable storage medium. The above-mentioned method according to the embodiment of the present application can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0098] An embodiment of the present application provides a computer program product, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a method according to any embodiment of the present application.

[0099] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

[0100] The systems, devices, modules, or units described in the above embodiments may be implemented by computer chips or entities, or by products having certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0101] For the convenience of description, the above devices are described as being divided into various units according to their functions. Of course, when implementing this application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0102] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0103] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the description of the method embodiments.

[0104] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

[0105] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

Claims

1. A method for synchronizing digital functions within a board based on RFSoC, characterized in that: The method comprises: In a case where multiple sampling channels on an acquisition board are in a time delay mismatch state, if the multiple sampling channels reach a delay synchronization state through delay allocation synchronization, trigger synchronization configuration is performed on the multiple sampling channels so that the multiple sampling channels synchronously receive a first reference clock signal; wherein the delay allocation synchronization is performed based on the first reference clock signal and a second reference clock signal, the first reference clock signal is used to set a delay measurement starting reference for the multiple sampling channels in the delay allocation synchronization, and the second reference clock signal is used to provide a delay measurement observation window for the multiple sampling channels in the delay allocation synchronization; receiving a plurality of cycles of the first reference clock signal, and if a preset signal change of the first reference clock signal is captured, performing periodic pulse triggering synchronization on the plurality of sampling channels to ensure synchronous execution of the digital function; The multiple sampling channels are synchronously phase-locked.

2. The method according to claim 1, characterized in that The receiving of the first reference clock signal of multiple cycles and performing periodic pulse triggering synchronization on the multiple sampling channels if a preset signal change of the first reference clock signal is captured includes: For any sampling channel among the multiple sampling channels, performing signal change detection on the first reference clock signal to obtain a reference clock change state; When the preset signal change condition exists in the reference clock change state, determining that the preset signal change condition of the first reference clock signal is captured, and performing repeated phase initialization on the multiple sampling channels based on the preset signal change condition as a trigger reference; Acquire the phases to be synchronized of each of the multiple sampling channels, and perform phase compensation on each of the multiple sampling channels according to the phases to be synchronized, so that the phases of each of the multiple sampling channels are aligned with the preset initial channel phase; The preset signal change is used as a trigger reference to repeatedly phase align the multiple sampling channels until the number of cycles in which the preset signal change is captured reaches a preset cycle number threshold.

3. The method according to claim 1, characterized in that The triggering and synchronously configuring the multiple sampling channels includes: Controlling the plurality of sampling channels to synchronously stop receiving the first reference clock signal; Performing initial phase setting on the plurality of sampling channels according to a preset initial channel phase; The plurality of sampling channels are controlled to synchronously start receiving the first reference clock signal.

4. The method according to claim 3, characterized in that Before controlling the plurality of sampling channels to synchronously start receiving the first reference clock signal, the method further includes: The trigger signals of the plurality of sampling channels are all set as the first reference clock signal.

5. The method according to claim 3, characterized in that After triggering and synchronizing the plurality of sampling channels, the method further includes: When the preset signal change is captured, the channel phases of the multiple sampling channels are initialized according to the preset initial channel phases.

6. The method according to claim 1, characterized in that The preset signal change condition is a rising edge of a pulse in the first reference clock signal.

7. The method according to claim 1, characterized in that The synchronous phase locking of the plurality of sampling channels comprises: The plurality of sampling channels are controlled to synchronously stop receiving the first reference clock signal.

8. An intra-board synchronization device with digital functions based on RFSoC, characterized in that: The device comprises: a trigger synchronization preparation module, configured to trigger synchronization configuration for the multiple sampling channels on the acquisition board, when the multiple sampling channels on the acquisition board are in a time delay mismatch state and the multiple sampling channels reach a delay synchronization state through delay allocation synchronization, so that the multiple sampling channels synchronously receive a first reference clock signal; wherein the delay allocation synchronization is performed based on the first reference clock signal and a second reference clock signal, the first reference clock signal being used to set a delay measurement starting reference for the multiple sampling channels in the delay allocation synchronization, and the second reference clock signal being used to provide a delay measurement observation window for the multiple sampling channels in the delay allocation synchronization; a pulse trigger synchronization module, configured to receive a plurality of cycles of the first reference clock signal, and if a preset signal change of the first reference clock signal is captured, perform periodic pulse trigger synchronization on the plurality of sampling channels to ensure synchronous execution of the digital function; The synchronous phase locking module is used to perform synchronous phase locking on the multiple sampling channels.

9. An acquisition board with digital functions based on RFSoC, characterized in that: Intra-board synchronization is performed by the method according to any one of claims 1 to 7.

10. A phased array radio telescope, characterized in that: Including the acquisition board described in claim 9.

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