Defect detection precision detection method and device, equipment and storage medium

Abstract

The embodiment of the invention provides a defect detection precision detection method and device, equipment and a storage medium, and the method comprises the steps: determining a defect region corresponding to each defect on a target wafer according to the real defect position information corresponding to each defect on the target wafer; and performing defect detection on the detection image corresponding to each defect area, and determining a defect detection result corresponding to each detection image. According to the real defect position information and the defect detection result corresponding to each detection image, defect detection precision detection is carried out, and a defect detection precision detection result representing the defect detection capability is determined. The detection rate of defect detection precision can be effectively improved through detection and precision detection of the defect area, so that the improvement and optimization rate of the defect detection process is improved, and the quality and yield of produced chips are improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor manufacturing technology, and in particular relates to a method, device, equipment and storage medium for inspecting defect detection accuracy. Background Art

[0002] In today's semiconductor industry, defect detection is a crucial step in chip design and production. Accurate and effective defect detection equipment and methods, such as brightfield inspection (BFI) and darkfield inspection (DFI), can accurately and promptly identify defects during chip design and production, enabling timely resolution and avoidance, ultimately improving chip quality and yield.

[0003] When performing defect detection, detection accuracy has a crucial impact on the accuracy of the final test results. Currently, defect detection accuracy is mostly assessed and verified by capturing surface images of the entire test sample wafer, performing defect inspection on each captured image, and then evaluating defect detection accuracy based on the test results. This processing method consumes an extremely large amount of data, significantly reducing the efficiency of defect detection accuracy verification and evaluation. This also impacts subsequent adjustments to defect detection methods or equipment based on the test results, hindering the proper execution of defect detection tasks during actual production. Summary of the Invention

[0004] The embodiments of the present application provide a method, apparatus, device, and storage medium for inspecting defect detection accuracy, which can significantly improve the inspection efficiency for defect detection accuracy.

[0005] In a first aspect, an embodiment of the present application provides a method for inspecting defect detection accuracy, comprising:

[0006] Obtain the actual defect location information of multiple defects on the target wafer;

[0007] For each defect, determine the defect area where the defect is located in the target wafer based on the actual defect location information of the defect;

[0008] Acquire an inspection image of each defect area;

[0009] Perform defect detection on each detection image and determine the defect detection result corresponding to the detection image;

[0010] Based on the actual defect location information and the defect detection results corresponding to each detection image, a defect detection accuracy test is performed to determine the defect detection accuracy test results.

[0011] In a second aspect, an embodiment of the present application provides a device for inspecting defect detection accuracy, comprising:

[0012] A position acquisition unit, used to obtain real defect position information of multiple defects on the target wafer;

[0013] A defect location unit is used to determine, for each defect, a defect area where the defect is located in the target wafer based on the actual defect location information of the defect;

[0014] An image acquisition unit, configured to acquire a detection image of each defect area;

[0015] A defect detection unit, configured to perform defect detection on each detection image and determine a defect detection result corresponding to the detection image;

[0016] The accuracy inspection unit is used to perform defect detection accuracy inspection based on the actual defect position information and the defect detection result corresponding to each detection image, and determine the defect detection accuracy inspection result.

[0017] In a third aspect, an embodiment of the present application provides an electronic device comprising a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein when the program or instruction is executed by the processor, the steps of the defect detection accuracy inspection method of any one of the embodiments of the present application are implemented.

[0018] In a fourth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the steps of the defect detection accuracy inspection method of any embodiment of the present application are implemented.

[0019] In a fifth aspect, an embodiment of the present application provides a computer program product. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device can perform the steps of any defect detection accuracy inspection method of the embodiment of the present application.

[0020] The technical solutions provided by the embodiments of this application bring at least the following beneficial effects:

[0021] An embodiment of the present application provides a method for inspecting defect detection accuracy, comprising: determining a defect area corresponding to each defect on a target wafer based on actual defect position information corresponding to each defect on the target wafer.

[0022] Then, defect detection can be performed on the inspection image corresponding to each defective area to determine the defect detection result for each inspection image. By only inspecting defective wafer areas, the amount of data processing required for defect detection and subsequent defect detection accuracy testing is greatly reduced, significantly improving the efficiency of defect detection accuracy testing.

[0023] Finally, based on the actual defect location information and the defect detection results corresponding to each inspection image, defect detection accuracy can be verified to determine the defect detection accuracy test results that represent the strength of the defect detection capability. By detecting and verifying the accuracy of defect areas, the inspection rate of defect detection accuracy can be effectively improved, thereby effectively improving the improvement rate and optimization effect of the defect detection process, thereby improving the production efficiency and chip quality of the entire chip production and manufacturing process.

[0024] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0026] Figure 1 A flowchart of a method for inspecting defect detection accuracy provided by one embodiment of the present application;

[0027] Figure 2 A schematic diagram of the workflow of a defect detection accuracy inspection system provided in one embodiment of the present application;

[0028] Figure 3 This is a structural diagram of a defect detection accuracy inspection method and device provided by another embodiment of the present application;

[0029] Figure 4 A schematic diagram of the hardware structure of a defect detection accuracy inspection device provided in yet another embodiment of the present application. DETAILED DESCRIPTION

[0030] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating the examples of the present application.

[0031] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0032] Defect detection is a crucial step in today's chip design and production process. It effectively identifies potential issues in chip manufacturing. Accurate and effective defect detection can significantly improve chip quality and yield.

[0033] Detection accuracy during defect detection is a crucial factor in determining the validity of test results. Accurately evaluating and verifying defect detection accuracy can help adjust and optimize the defect detection process, leading to more accurate defect detection. Currently, most defect detection accuracy verification methods primarily capture images of the entire wafer, perform defect detection on all captured images, and then evaluate defect detection accuracy based on the test results.

[0034] Both the defect detection process and the subsequent accuracy assessment based on the test results require processing a large amount of data, significantly reducing the overall efficiency of defect detection accuracy. This reduction in defect detection accuracy can severely impact the efficiency of adjustments and optimizations to the defect detection process, and can even affect the overall chip production efficiency and chip quality.

[0035] To address the above issues, embodiments of the present application provide a method, apparatus, device, and storage medium for inspecting defect detection accuracy. The method specifically includes: first, determining the defect area corresponding to each defect on the target wafer based on the actual defect location information corresponding to each defect on the target wafer.

[0036] Defect detection can be performed on the inspection image corresponding to each defective area, thereby determining the defect detection result corresponding to each inspection image. The embodiment of the present application can only perform defect detection on the defective wafer area. Compared with traditional inspection methods, this greatly reduces the defect detection process and the amount of data processing when inspecting defect detection accuracy, significantly improving the inspection efficiency of defect detection accuracy.

[0037] Based on the actual defect location information and the defect detection results corresponding to each detection image, a defect detection accuracy test is performed to accurately determine the defect detection accuracy test results that can represent the strength of the defect detection process. The technical method provided by the embodiment of the present application can only perform defect detection on the defect area on the wafer with known defect locations, and perform detection accuracy analysis and inspection, effectively improving the inspection rate of defect detection accuracy, so that the subsequent improvement and optimization rate of the detection accuracy of the defect detection process is also effectively improved, and the overall chip production rate and chip quality are also enhanced.

[0038] The execution subject used in the embodiments of the present application may be a terminal device, such as a desktop computer, a laptop computer, or a remote device, such as a server. Furthermore, the execution subject used in the embodiments of the present application may also be an execution subject in the form of software, such as a client installed in a terminal device, a software program, or the like. The specific type of execution subject to which the technical solutions provided in the embodiments of the present application can be applied is not strictly limited here, and can be flexibly selected and applied according to actual application scenarios and actual needs.

[0039] The actual application scenarios corresponding to the defect detection accuracy inspection methods, devices, equipment and storage media provided in the embodiments of the present application are not strictly and specifically limited in this application and can be flexibly adjusted and applied according to actual needs.

[0040] For example, in an actual scenario where periodic accuracy testing is performed on a defect detection process, the technical solution provided by the embodiments of the present application can capture images of wafers with known defect locations during each inspection cycle, and perform defect detection on inspection images containing defects. Based on the defect detection results, the defect detection accuracy test results corresponding to that inspection cycle are determined, thereby accurately evaluating the detection capabilities of the defect detection equipment or method for wafer defects before and after that inspection cycle.

[0041] Applying the technical solutions provided by the embodiments of this application in application scenarios similar to the above can effectively reduce the amount of data to be processed during the defect detection and accuracy verification process, significantly improving the overall processing efficiency of the defect detection accuracy verification process. This effectively improves the efficiency of subsequent adjustments and optimizations of the defect detection process based on the inspection results, further improving the quality and yield of the produced chips.

[0042] It should be noted that the application scenarios described in the above embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. A person skilled in the art will appreciate that, with the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems. The defect detection accuracy inspection method provided in the embodiments of the present application can be applied to various scenarios where defect detection accuracy inspection of defect detection equipment or defect detection methods is required.

[0043] Figure 1 A flowchart of a method for inspecting defect detection accuracy provided in accordance with an embodiment of the present application.

[0044] like Figure 1 As shown in , the defect detection accuracy inspection method provided in the embodiment of the present application includes steps S101 to S105.

[0045] S101: Acquire real defect location information of multiple defects on a target wafer.

[0046] In step S101, the technical solution provided by the embodiment of the present application can obtain the real defect position information corresponding to multiple defects predetermined on the target wafer.

[0047] Among them, the target wafer is a wafer with known specific defect locations. The actual defect location information corresponding to multiple defects on the target wafer can be used to verify the accuracy of defect detection in subsequent steps, and can be understood as the standard value based on which the accuracy inspection of the defect detection process is based.

[0048] The actual defect position information corresponding to each defect on the target wafer is used to represent the position of the defect on the target wafer, and the specific form of expression can be the corresponding coordinate data in a two-dimensional plane rectangular coordinate system established with the center point of the target wafer as the origin.

[0049] The specific data format of the actual defect location information is not strictly limited in the embodiments of this application. In some embodiments, it can be, for example, Klarf (KLA Result File) or comma-separated values ​​(CSV), etc., which can be flexibly selected according to the application scenario and actual needs.

[0050] S102: For each defect, determine the defect area where the defect is located in the target wafer according to the actual defect position information of the defect.

[0051] In step S102, the technical solution provided in the embodiment of the present application can determine the defect region corresponding to each defect in the target wafer based on the actual defect location information corresponding to each defect in the target wafer. The defect region corresponding to each defect is used to represent the corresponding region of the defect in the multiple regions divided according to preset parameters on the target wafer.

[0052] Specifically, in an embodiment provided in the present application, the target wafer can be divided into areas of equal size according to the image acquisition parameters preset when acquiring images of the target wafer, thereby determining multiple corresponding wafer areas on the target wafer, and the corresponding sizes of each wafer area are equal.

[0053] Among them, the specific data content of the image acquisition parameters is not strictly limited in the embodiments of this application, and may include but is not limited to the acquired image size, image acquisition resolution, acquired image magnification, exposure time, light source type, etc., and can be flexibly selected according to actual needs and application scenarios.

[0054] Furthermore, for each wafer region obtained by dividing the target wafer, a corresponding region number may be assigned, and region position information corresponding to each wafer region on the target wafer may be determined.

[0055] The specific method of assigning the region numbers can be to number the wafer regions from left to right and from top to bottom in the order in which they are arranged, or other feasible numbering methods can be used, which can be flexibly selected according to actual needs. The region position information can indicate the position of each wafer region on the target wafer, specifically by the center point or boundary point of the wafer region, or by the coordinate data of all points in the wafer region on the target wafer, which can be flexibly set according to actual needs.

[0056] Then, based on the actual defect location information of each defect on the target wafer and the regional location information of each wafer region on the target wafer, the defects are matched with the wafer regions, so that the wafer region where each defect is located can be accurately determined as the defect region corresponding to the defect. Among them, one defect corresponds to only one defect region, while a defect region may contain multiple defects.

[0057] The defect area determination process of the above embodiment can accurately match and determine the defect area corresponding to each defect on the target wafer, providing a practical basis for subsequent defect detection. This allows subsequent defect detection to be performed only on the defective wafer area, significantly reducing the data processing volume during the defect detection process and subsequent defect detection accuracy verification process, and significantly improving detection and accuracy verification efficiency.

[0058] S103: Acquire a detection image of each defect area.

[0059] In step S103, the technical solution provided in the embodiment of the present application can perform image acquisition based on the defect area corresponding to each defect determined in step S102 on the target wafer, thereby obtaining a detection image corresponding to each defect area.

[0060] Specifically, in one embodiment provided in the present application, image acquisition can be performed for each wafer area in the target wafer to obtain multiple detection images corresponding to each wafer area. The specific image acquisition device is not strictly limited in the embodiment of the present application, and can be, for example, a time delay integration (Time Delay Integration) linear array camera, a high dynamic range area scan CMOS (HDR CMOS) camera, or an electron multiplying charge-coupled device camera (EMCCD), and can be determined according to the application scenario and actual needs.

[0061] Then, based on the region number assigned to each wafer region in step S102, the inspection image corresponding to the defective region can be matched from the multiple inspection images. This matching method can accurately locate and determine the inspection image related to the defect in the target wafer from the numerous inspection images, thereby significantly reducing the data processing volume of the subsequent defect detection process, significantly improving the execution efficiency of the defect detection process, and also reducing the data volume of the subsequent defect detection accuracy inspection process and improving the inspection efficiency.

[0062] Regarding how to specifically determine the test image corresponding to the defective area, in one embodiment provided in this application, the region number corresponding to each wafer region can be used as the region number of the test image corresponding to the wafer region. Then, based on the region number corresponding to the defective region, a test image with the same region number as the region number corresponding to the defective region can be matched from multiple test images to serve as the test image corresponding to the defective region.

[0063] It should be noted that the reason for capturing images before determining the defect area detection image in the above-mentioned embodiments is due to the unique capture mechanism inherent in the camera itself when capturing images using acquisition devices such as time-delayed integration cameras. For example, the time-delayed integration camera's requirement to continuously capture linear images makes it impossible to capture only specific wafer areas within the target wafer, or the captured image may be inaccurate. The above-mentioned matching process based on area numbers allows for precise matching of the detection images corresponding to each defect area on the target wafer, providing a practical basis for subsequent defect detection and accuracy testing.

[0064] In other embodiments, if other image acquisition devices are selected that can ensure image acquisition accuracy and can realize image acquisition of separate wafer areas, images of defective areas on the target wafer can be directly acquired, and the acquired images are the detection images corresponding to the defective areas, thereby significantly improving the image acquisition efficiency and accelerating the processing efficiency of the overall detection accuracy inspection.

[0065] S104: Perform defect detection on each detection image and determine the defect detection result corresponding to the detection image.

[0066] In step S104, the technical solution provided in the embodiment of the present application can perform defect detection on the inspection image corresponding to each defect area determined in step S103, thereby determining a defect detection result corresponding to each inspection image. The defect detection result corresponding to each inspection image is used to indicate whether a wafer defect is detected in the inspection image.

[0067] It should be noted in advance that the embodiments of this application do not limit the specific method of detecting defects in the inspection image, the specific defect detection equipment, and the detection type. The technical solutions provided in the embodiments of this application can effectively and accurately test and evaluate the defect detection accuracy of various defect detection methods or defect detection equipment. They are applicable to any defect detection process and can be flexibly configured according to actual needs and application scenarios.

[0068] In addition, the specific object targeted by the defect detection accuracy inspection results determined by the subsequent accuracy inspection process is the same as the executing entity of the defect detection process in this step, which can be a defect detection device, or a defect detection program, algorithm, etc. The embodiments of this application also do not specify them, and can be flexibly selected according to actual needs and application scenarios.

[0069] S105: Perform a defect detection accuracy test based on the actual defect position information and the defect detection result corresponding to each detection image to determine the defect detection accuracy test result.

[0070] In step S105, the technical solution provided in the embodiment of the present application can perform a defect detection accuracy test on the execution entity that executes the defect detection process based on the actual defect positions corresponding to each defect on the target wafer obtained in step S101, and the defect detection results obtained after the defect detection process of the detection image corresponding to the defect area determined in step S104, to determine the defect detection accuracy test results.

[0071] The defect detection accuracy test result is used to characterize the detection accuracy corresponding to the defect detection process in step S104. The specific data form may be, for example, defect detection accuracy rate, defect detection misjudgment rate, etc.

[0072] In an embodiment provided in the present application, for each detection image, when it is determined that the defect detection result corresponding to the detection image indicates that a defect exists in the detection image, position information corresponding to the detected defect in the detection image is determined.

[0073] Among them, the position information corresponding to each detected defect may include the image position information of the detected defect in the detection image, and the wafer position information of the detected defect in the target wafer, and may also include the chip position information of the detected defect in the chip where it is located.

[0074] Then, based on the position of the detected defect in the inspection image and the actual defect location of the corresponding defect area on the target wafer, the authenticity of the detected defect can be accurately determined. Defect authenticity indicates whether the detected defect is a real defect on the target wafer or a misidentified defect caused by a detection error.

[0075] Finally, the defect detection process may be inspected for detection accuracy based on the authenticity of defects corresponding to the detected defects in all inspection images, and a defect detection accuracy inspection result for the defect detection process in step S104 may be determined.

[0076] Regarding the process of determining the position information corresponding to the detected defect, in one embodiment provided in the present application, the image position information corresponding to the detected defect in each detection image can be determined first.

[0077] The data form of the image position information can specifically be, for example, coordinate data corresponding to a plane rectangular coordinate system with the center point of the detected image as the origin. The specific method for determining the image position information is not strictly limited in the embodiments of this application. For example, it can be through a detection model with image feature positioning, or it can be other feasible image positioning methods, and can be flexibly selected according to actual needs and application scenarios.

[0078] Then, the wafer position information of the detected defect in the target wafer can be calculated based on the area position information corresponding to the detection image to which the detected defect belongs in the target wafer and the image position information corresponding to the detected defect.

[0079] For example, the specific calculation process of wafer position information is as follows: the regional position information can be the coordinate data of the inspection image to which the inspected defect belongs in a coordinate system with the center point of the target wafer as the coordinate origin, and the image position information can be the coordinate data of the inspected defect in a coordinate system with the center point of the inspection image to which it belongs as the coordinate origin. When the coordinate axes of the two coordinate systems are in the same direction, the wafer position information of the inspected defect in the target wafer can be determined by adding and subtracting the coordinate data. Even if the coordinate axes of the coordinate systems are in different directions, the coordinate mapping can be performed based on the positional relationship between the coordinate systems to determine the wafer position information. The specific setting can be flexibly determined according to actual needs.

[0080] Mapping wafer position information provides a strong basis for subsequent defect authenticity assessment, effectively ensuring the accuracy of detected defects. This in turn improves the accuracy of defect detection precision test results, enhancing the effectiveness and practicality of subsequent adjustments and optimizations to the defect detection process based on these results.

[0081] Regarding the specific determination process of the authenticity of the defect corresponding to the detected defect, in an embodiment provided in the present application, based on the wafer position information corresponding to the detected defect and the actual defect position information corresponding to the corresponding detection image in the target wafer, it is determined whether the straight-line distance between the detected defect and the defect corresponding to the detection image in the target wafer is less than a preset distance threshold.

[0082] When it is determined that the distance between the detected defect and the corresponding defect on the target wafer is less than a preset distance threshold, it can be determined that the detected defect is a real defect, and the defect detection process is close to accurate for detecting this defect.

[0083] When it is determined that the distance between the detected defect and the corresponding defect on the target wafer is not less than the preset distance threshold, it can be determined that the detected defect is detected incorrectly and is a misjudged defect, indicating that there is a problem in the defect detection process for detecting this defect.

[0084] This method can accurately classify each detected defect as true or false, providing a practical basis for determining the subsequent defect detection accuracy test results, thereby enabling more effective adjustment and optimization of the defect detection process. This effectively improves wafer defect detection accuracy, thereby enhancing chip production quality and chip yield.

[0085] The defect authenticity corresponding to each detected defect can be used to determine the defect detection accuracy test results. Specifically, in one embodiment provided herein, the defect detection accuracy can be determined based on the number of defects in the target wafer and the defect authenticity of the detected defects, expressed as the number of real defects. The specific calculation process can be the ratio of the number of real defects to the number of defects in the target wafer.

[0086] At the same time, the defect detection misjudgment rate can be determined based on the number of real defects and the number of misjudged defects. The specific calculation process can be the ratio of the number of misjudged defects to the sum of the number of real defects and the number of misjudged defects.

[0087] The calculated defect detection accuracy and defect detection false positive rate can be used as the defect detection precision test results corresponding to the defect detection process. For example, assume that after performing defect detection in step S104 on a target wafer containing 100 defects, the above embodiment determines that the number of detected defects is 80 true defects and the number of detected defects is 10 false positive defects. Accordingly, the defect detection accuracy can be calculated to be 80% (80 / 100) and the defect detection false positive rate to be 11.11% (10 / (80+10)).

[0088] The above-mentioned embodiments can precisely determine the accuracy and false positive rate of the defect detection process, providing a strong reference for subsequent adjustments and optimizations to the defect detection process. This effectively improves the accuracy of defect detection in the overall chip manufacturing process, thereby enhancing chip production quality and yield.

[0089] In addition, regarding misjudged defects and detection images in which no defects are detected, in another embodiment provided in the present application, the position information corresponding to the detected defect that is a misjudged defect and the detection image in which it is located can be recorded and stored as misjudgment record data corresponding to the misjudged defect.

[0090] The stored misjudgment records can be used together with the inspection images that did not detect defects for subsequent defect detection problem analysis, thereby further identifying possible problems in the defect detection process. Adjustments and optimizations to the defect detection methods or equipment are then made to address these issues, eliminating anomalies and improving defect detection accuracy. This allows for accurate and reliable detection of defects on wafers in practical applications, improving chip production quality and yield.

[0091] The above-described embodiment successfully verifies and evaluates the accuracy of the defect detection process in step S104, determining the corresponding defect detection accuracy test results. Furthermore, targeted analysis can be performed on misjudgments and undetected defects, thereby improving subsequent optimization and adjustment of the defect detection process.

[0092] In addition to the above, the defect detection accuracy inspection method provided in the embodiment of the present application can be implemented by a defect detection accuracy inspection system. The system specifically includes: a host computer responsible for sending operation instructions, a machine for placing the target wafer and equipped with an image acquisition device, an image processing module for determining the defect area corresponding to the detection image, a detection module for performing defect detection on the detection image, and an analysis module for performing detection accuracy inspection based on the defect detection results. The specific workflow of the defect detection accuracy inspection system can be referred to Figure 2 As shown in .

[0093] Figure 2 A schematic diagram of a workflow of a defect detection accuracy inspection system provided in one embodiment of the present application includes steps S201 to S206.

[0094] S201: Place the target wafer on the machine platform and establish a coordinate system through the host computer.

[0095] In step S201 , a coordinate system may be constructed for the target wafer placed on the machine, thereby laying a foundation for determining the corresponding area position information of the subsequent wafer area, and mapping the position information of the detected defect image and the wafer position information.

[0096] S202: Switching the system detection mode from normal detection to precision inspection mode via the host computer, and obtaining the real defect position information corresponding to each known defect on the target wafer.

[0097] S203: The image acquisition device of the machine acquires the detection image corresponding to each wafer area according to the preset image acquisition parameters.

[0098] S204: Determine, by means of an image processing module, a detection image corresponding to the defective area on the target wafer from the detection image acquired by the image acquisition device according to the actual defect position information.

[0099] S205: Perform defect detection on the detection image corresponding to the defect area through the detection module to determine the defect detection result.

[0100] S206: The analysis module determines the real defects, misjudged defects, defect detection accuracy, and defect detection misjudgment rate based on the defect detection results, and stores the location information and detection images corresponding to the misjudged defects, as well as the detection images of undetected defects, for subsequent problem analysis.

[0101] Through steps S202 to S206 , the defect detection capability of the detection module can be accurately tested. The specific steps are the same as those in the above steps S101 to S105 , and will not be described in detail here.

[0102] The above is a specific implementation method of the defect detection accuracy inspection method provided in the embodiment of the present application. Specifically, defect detection is performed on the detection image corresponding to each defect area, the defect detection result corresponding to each detection image is determined, and then the detection accuracy is accurately and efficiently inspected based on the detection result corresponding to the defect area.

[0103] By only inspecting defective wafer areas, the amount of data processing required for defect detection and subsequent verification of defect detection accuracy is significantly reduced, significantly improving the efficiency of defect detection accuracy inspection. This effectively increases the inspection rate for defect detection accuracy and also speeds up subsequent improvements and optimizations to the defect detection process, improving the overall production quality and chip yield of the chip manufacturing process.

[0104] Based on the defect detection accuracy inspection method provided in the above embodiment, the present application also provides a specific implementation method of the defect detection accuracy inspection device, please refer to the following embodiment.

[0105] Figure 3 This is a schematic structural diagram of a defect detection accuracy inspection device provided in another embodiment of the present application. The defect detection accuracy inspection device 300 includes:

[0106] A position acquisition unit 301 is used to acquire real defect position information of multiple defects on a target wafer;

[0107] The defect location unit 302 is configured to determine, for each defect, a defect region where the defect is located in the target wafer based on the actual defect location information of the defect;

[0108] An image acquisition unit 303 is used to acquire a detection image of each defect area;

[0109] The defect detection unit 304 is configured to perform defect detection on each detection image and determine a defect detection result corresponding to the detection image;

[0110] The accuracy inspection unit 305 is used to perform defect detection accuracy inspection based on the actual defect position information and the defect detection result corresponding to each detection image, and determine the defect detection accuracy inspection result.

[0111] In some embodiments, the defect location unit 302 is configured to divide the target wafer into regions according to preset image acquisition parameters, and determine multiple wafer regions of the target wafer;

[0112] Assigning a corresponding region number to each wafer region and determining region position information of each wafer region on the target wafer;

[0113] For each defect, based on the actual defect location information of the defect and the regional location information of multiple wafer regions, a wafer region containing the defect is determined from the multiple wafer regions as the defect region of the defect.

[0114] In some embodiments, the image acquisition unit 303 is used to collect multiple detection images corresponding to multiple wafer areas;

[0115] According to the region numbers of the plurality of wafer regions, a detection image corresponding to each defect region is matched from the plurality of detection images.

[0116] In some embodiments, the image acquisition unit 303 is configured to use the region number of each wafer region as the image number of the detection image of the wafer region;

[0117] For each defect area, a detection image having the same image number as the area number of the defect area among the multiple detection images is used as the detection image of the defect area.

[0118] In some embodiments, for each inspection image, a defect detection result corresponding to the inspection image is used to indicate whether a defect is detected from the inspection image;

[0119] The accuracy verification unit 305 is configured to determine, for each inspection image, position information of the detected defect in the inspection image when a defect is detected in the inspection image, where the position information includes image position information of the detected defect in the inspection image and wafer position information of the detected defect in the target wafer;

[0120] Determine the authenticity of the detected defect based on the location information of the detected defect and the actual defect location information of the detected image. The defect authenticity is used to indicate whether the detected defect is a real defect or a falsely determined defect.

[0121] Determine the defect detection accuracy test result based on the defect authenticity of each defect being detected.

[0122] In some embodiments, the accuracy verification unit 305 is used to determine image position information of the detected defect in the detection image;

[0123] Determining wafer position information of the detected defect in the target wafer based on the area position information corresponding to the detection image in the target wafer and the image position information;

[0124] Position information is determined based on the image position information and the wafer position information.

[0125] In some embodiments, the accuracy verification unit 305 is configured to determine whether the distance between the detected defect and the defect corresponding to the detected defect in the detection image on the target wafer is less than a preset distance threshold based on the wafer location information of the detected defect and the actual defect location information of the detection image;

[0126] If so, it is determined that the detected defect is a real defect;

[0127] If not, it is determined that the detected defect is a misjudged defect.

[0128] In some embodiments, the accuracy verification unit 305 is configured to determine and store, for each misjudged defect, misjudged record data corresponding to the misjudged defect based on the position information corresponding to the misjudged defect and the inspection image where the misjudged defect is located;

[0129] Defect detection problem analysis is performed based on the misjudgment record data and the inspection images where defects were not detected.

[0130] In some embodiments, the accuracy verification unit 305 is configured to determine a defect detection accuracy rate based on the number of defects in the target wafer and the number of detected defects that are real defects;

[0131] Determine the defect detection false positive rate based on the number of detected defects that are true defects and the number of detected defects that are false positives;

[0132] Determine the defect detection accuracy test results based on the defect detection accuracy rate and the defect detection misjudgment rate.

[0133] Figure 4 A schematic diagram of the hardware structure of a defect detection accuracy inspection device provided in yet another embodiment of the present application.

[0134] The defect detection accuracy inspection device may include a processor 401 and a memory 402 storing computer program instructions.

[0135] Specifically, the processor 401 may include a central processing unit (CPU), or an application-specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0136] Memory 402 may include a large capacity memory for data or instructions. By way of example and not limitation, memory 402 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive, or a combination of two or more of these. Where appropriate, memory 402 may include removable or non-removable (or fixed) media. Where appropriate, memory 402 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, memory 402 is a non-volatile solid-state memory.

[0137] In certain embodiments, memory 402 includes read-only memory (ROM). The ROM may be mask-programmed ROM, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), electrically alterable ROM (EAROM), or flash memory, or a combination of two or more thereof, where appropriate.

[0138] The processor 401 reads and executes computer program instructions stored in the memory 402 to implement any one of the defect detection accuracy inspection methods in the above embodiments.

[0139] In one example, the defect detection accuracy inspection device may further include a communication interface 403 and a bus 410. Figure 4 As shown, the processor 401 , the memory 402 , and the communication interface 403 are connected via a bus 410 and communicate with each other.

[0140] The communication interface 403 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0141] Bus 410 includes hardware, software or both, and the components of online data flow metering equipment are coupled to each other. For example, but not limitation, bus may include accelerated graphics port (AGP) or other graphics bus, enhanced industry standard architecture (EISA) bus, front side bus (FSB), hypertransport (HT) interconnection, industry standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations. In appropriate cases, bus 410 may include one or more buses. Although the present application embodiment describes and shows a specific bus, the application considers any suitable bus or interconnection.

[0142] In addition, in conjunction with the defect detection accuracy inspection method in the above-mentioned embodiment, the present application embodiment can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by a processor, any of the defect detection accuracy inspection methods in the above-mentioned embodiment is implemented.

[0143] An embodiment of the present application also provides a computer program product, including a computer program, which, when processed and executed, implements any one of the defect detection accuracy inspection methods in the above embodiments.

[0144] It should be understood that the present application is not limited to the specific configurations and processes described above and illustrated in the figures. For the sake of brevity, a detailed description of known methods is omitted here. In the above embodiments, several specific steps are described and illustrated as examples. However, the method process of the present application is not limited to the specific steps described and illustrated. Those skilled in the art can make various changes, modifications, and additions, or change the order of the steps after understanding the spirit of the present application.

[0145] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application specific integrated circuits (ASICs), appropriate firmware, plug-ins, function cards, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium that can store or transmit information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROMs, flash memories, erasable ROMs (EROMs), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0146] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps. In other words, the steps can be performed in the order mentioned in the embodiments, or in a different order, or several steps can be performed simultaneously.

[0147] Aspects of the present disclosure have been described above with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor or a field programmable logic circuit. It is also understood that each box in the block diagram and / or flowchart and the combination of the boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0148] The above description is only a specific embodiment of the present application. Those skilled in the art will clearly understand that for the convenience and brevity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the scope of protection of the present application is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the scope of protection of the present application.

Claims

1. A method for inspecting defect detection accuracy, characterized in that: include: Obtain the actual defect location information of multiple defects on the target wafer; For each defect, determining a defect region where the defect is located in the target wafer according to the actual defect location information of the defect; Acquire a detection image of each defect area; Performing defect detection on each of the detection images to determine a defect detection result corresponding to the detection image; A defect detection accuracy test is performed based on the actual defect position information and the defect detection result corresponding to each of the detection images to determine the defect detection accuracy test result.

2. The method according to claim 1, characterized in that Determining a defect region where the defect is located in the target wafer according to the actual defect location information of the defect includes: Dividing the target wafer into regions according to preset image acquisition parameters to determine multiple wafer regions of the target wafer; Assigning a corresponding area number to each of the wafer areas, and determining area position information of each of the wafer areas on the target wafer; For each defect, based on the actual defect location information of the defect and the regional location information of the multiple wafer regions, a wafer region containing the defect is determined from the multiple wafer regions as the defect region of the defect.

3. The method according to claim 2, characterized in that Acquiring a detection image of each defect area, including: collecting a plurality of detection images corresponding to the plurality of wafer areas; According to the region numbers of the multiple wafer regions, a detection image corresponding to each of the defective regions is matched from the multiple detection images.

4. The method according to claim 3, characterized in that Matching a detection image corresponding to each defective area from the multiple detection images according to the area numbers of the multiple wafer areas includes: Using the region number of each wafer region as the image number of the detection image of the wafer region; For each defect area, a detection image having the same image number as the area number of the defect area among the plurality of detection images is used as the detection image of the defect area.

5. The method according to claim 1, wherein For each of the detection images, a defect detection result corresponding to the detection image is used to indicate whether a defect is detected from the detection image; Performing a defect detection accuracy test based on the actual defect position information and the defect detection result corresponding to each of the detection images to determine a defect detection accuracy test result includes: For each of the inspection images, when it is determined that a defect is detected in the inspection image, determining position information of the detected defect in the inspection image, the position information including image position information of the detected defect in the inspection image and wafer position information of the detected defect in the target wafer; Determining the authenticity of the detected defect based on the position information of the detected defect and the real defect position information of the detected image, wherein the defect authenticity is used to indicate whether the detected defect is a real defect or a falsely determined defect; The defect detection accuracy test result is determined based on the defect authenticity of each detected defect.

6. The method according to claim 5, characterized in that Determining the position information of the detected defect in the inspection image includes: Determining image position information of the detected defect in the detection image; Determining wafer position information of the detected defect in the target wafer based on the area position information corresponding to the detection image in the target wafer and the image position information; The position information is determined according to the image position information and the wafer position information.

7. The method according to claim 6, characterized in that Determining the authenticity of the detected defect based on the position information of the detected defect and the real defect position information of the detected image includes: Determining, based on the wafer position information of the detected defect and the actual defect position information of the detection image, whether the distance between the detected defect and the defect corresponding to the detection image on the target wafer is less than a preset distance threshold; If so, determining that the detected defect is the real defect; If not, it is determined that the detected defect is the misjudged defect.

8. The method according to claim 7, characterized in that After determining that the detected defect is the misjudged defect, the method further includes: For each of the misjudged defects, determining and storing misjudgment record data corresponding to the misjudged defect based on the position information corresponding to the misjudged defect and the inspection image where the misjudged defect is located; Defect detection problem analysis is performed based on the misjudgment record data and the detection images in which no defects are detected.

9. The method according to claim 5, characterized in that Determining the defect detection accuracy test result according to the defect authenticity of each detected defect includes: Determining a defect detection accuracy rate based on the number of defects in the target wafer and the number of detected defects that are real defects; Determining a defect detection misjudgment rate based on the number of detected defects that are true defects and the number of detected defects that are misjudged defects; The defect detection accuracy test result is determined according to the defect detection accuracy rate and the defect detection misjudgment rate.

10. A computer program product, characterized in that When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the defect detection accuracy inspection method according to any one of claims 1 to 9.

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