Display device

Abstract

The invention relates to a display device. The display device includes: a display panel including a display area, a non-display area disposed at a periphery of the display area, and a pad area disposed at a side portion of the non-display area; a data line disposed in the display area of the display panel along a second direction intersecting the first direction; a connection line disposed in the display area of the display panel along the first direction; and a first power supply line disposed in a display area of the display panel along a first direction and receiving a first power supply voltage, in which a first data line of the data lines is connected to a first connection line of the connection lines via a first connection hole located in the display area, and the first connection line overlaps the first power supply line, the first connection hole is disposed in an overlapping region of the first data line and the first power line, in which the pad region protrudes from a long side of the display panel in a direction parallel to a short side of the display panel.

Description

[0001] This application is a divisional application of the invention patent application with an application date of July 16, 2020, application number 202010686340.X, and invention name “Display Device”. Technical Field

[0002] The present disclosure relates to a display device. Background Art

[0003] Due to the growth and continued development of information technology, the demand for display devices for displaying images has been increasing. For example, display devices have been applied to various electronic devices such as smartphones, digital cameras, notebook computers, navigation devices, and smart televisions (TVs). Examples of display devices include flat panel display devices such as liquid crystal display (LCD) devices, field emission display (FED) devices, and organic light emitting diode (OLED) display devices.

[0004] A typical display device may include a display panel including pixels for displaying an image. The display panel may include a display area in which the pixels are formed and a non-display area occupying or corresponding to the remainder of the display panel. A pad connected to a flexible film or circuit board may be formed on one side of the display panel. Therefore, the portion of the non-display area located on one side of the display device may be larger than the portion of the non-display area located on the other side of the display device.

[0005] It will be understood that this background section is intended, in part, to provide a useful context for understanding the technology. However, this background section may also include ideas, concepts, or understandings that are not known or understood by those skilled in the relevant art before the corresponding effective filing date of the subject matter disclosed herein. Summary of the Invention

[0006] The embodiment may provide a display device capable of minimizing a difference in size between portions of a non-display area located on both sides of the display device.

[0007] Additional features of the embodiments will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments described herein.

[0008] According to an embodiment, a display device may include a display panel including a display area, a non-display area disposed at a periphery of the display area, and a pad area disposed at a side of the non-display area. The display device may include data lines disposed in the display area of ​​the display panel along a second direction that may intersect with a first direction, and connection lines disposed in the display area of ​​the display panel along the first direction. A first data line of the data lines may be connected to a first connection line of the connection lines.

[0009] The pad region may protrude from the non-display region in the first direction.

[0010] A length of the display panel in the first direction may be smaller than a length of the display panel in the second direction.

[0011] The display device may include a first power line disposed in the display area of ​​the display panel along the first direction and receiving a first power voltage. The first connection line may overlap with the first power line.

[0012] The first connection line may be connected to the first data line through a first connection hole penetrating at least one insulating film disposed between the first connection line and the first data line.

[0013] The first connection hole may be provided in an overlapping region of the first data line and the first power line.

[0014] The display device may include: a scan line arranged in the display area of ​​the display panel along the first direction; a first gate metal layer including the scan line; a first source metal layer arranged on the first gate metal layer and including the first data line; and a second gate metal layer arranged between the first gate metal layer and the first source metal layer and including the first power line.

[0015] The display device may include: a second source metal layer disposed on the first source metal layer and including the first connection line.

[0016] The display device may include a second power supply line disposed in the display area of ​​the display panel along the second direction and receiving a second power supply voltage that may be higher than the first power supply voltage.

[0017] The first source metal layer may include a second power supply line.

[0018] The display device may include a third source metal layer disposed on the second source metal layer, the third source metal layer may include the first connection line, and the second source metal layer may be disposed on the first source metal layer and include the second power supply line.

[0019] The display device may include a scan driver connected to the scan lines.

[0020] The scan driver may be provided in a portion of the non-display area at a first outer side of the display area.

[0021] The scan driver may include: a first scan driver, which is arranged in a portion of the non-display area located at a first outer side of the display area and connected to the odd scan lines; and a second scan driver, which is arranged in a portion of the non-display area located at a second outer side of the display area and connected to the even scan lines.

[0022] The display device may include: a fan-out line disposed in the pad region of the display panel and connected to the connection line; and a display driver disposed in the pad region of the display panel and connected to the fan-out line.

[0023] The pad region may include: a bending region; and a first sub-pad region, the display driver being disposed in the first sub-pad region, and the fan-out line being disposed in one of the first gate metal layer and the second gate metal layer located in the first sub-pad region. The fan-out line may be disposed in one of the first source metal layer and the second source metal layer located in the bending region, the second source metal layer being disposed on the first source metal layer.

[0024] The scan driver may be disposed in the pad region of the display panel.

[0025] The pad region may include a bending region, a first sub-pad region in which the display driver may be disposed, and a second sub-pad region disposed between the bending region and the first sub-pad region and including a scan driver.

[0026] The fan-out line can be set in: one of the first gate metal layer and the second gate metal layer located in the first sub-pad area; in the second source metal layer on the first source metal layer located in the second sub-pad area; and in one of the first source metal layer and the second source metal layer located in the bending area.

[0027] The first connection line may include: a first sub-connection line disposed along the first direction; and a second sub-connection line disposed along the second direction, and the second sub-connection line may be connected to the first data line.

[0028] The display device may include a demultiplexer connected between the connection line and the fan-out line.

[0029] The number of the connection lines may be greater than the number of the fan-out lines.

[0030] The display device may include: a second power line, arranged in the display area of ​​the display panel along the second direction and receiving a second power voltage that may be higher than the first power voltage; a second source metal layer, arranged on the first source metal layer and including the second power line; and a third source metal layer, arranged on the second source metal layer and including the first connecting line.

[0031] According to an embodiment, a display device may include: a display panel including a display area, a non-display area provided at a periphery of the display area, and a pad area provided at a side of the non-display area; data lines provided in the display area of ​​the display panel along a second direction intersecting with a first direction; and first connection lines provided in the display area of ​​the display panel and including a first sub-connection line provided along the first direction and a second sub-connection line provided along the second direction. A first data line of the data lines may be connected to the second sub-connection line.

[0032] The pad region may protrude from the non-display region in the first direction.

[0033] A length of the display panel in the first direction may be smaller than a length of the display panel in the second direction.

[0034] In the non-display area, the first data line may be connected to the second sub-link line.

[0035] The second sub-link line may be connected to the first data line through a first connection hole penetrating at least one insulating film disposed between the second sub-link line and the first data line.

[0036] The display device may include a first power supply line disposed in the display area of ​​the display panel along the first direction and receiving a first power supply voltage. The first sub-link line may overlap with the first power supply line.

[0037] The display device may include a second power supply line disposed in the display area of ​​the display panel along the second direction and receiving a second power supply voltage that may be higher than the first power supply voltage. The second sub-link line may overlap the second power supply line.

[0038] According to an embodiment, when the pad area protrudes from the non-display area in a direction parallel to the short side of the display panel, the width of the pad area can be greater than when the pad area protrudes from the non-display area in a direction parallel to the long side of the display panel. Therefore, it can be beneficial to design and / or arrange the fan-out line connecting the display area and the pad area. Therefore, the difference between the width of the portion of the non-display area located on the outer left side of the display area and the width of the portion of the non-display area located on the outer right side of the display area can be minimized.

[0039] The connection wiring may overlap the power line in the thickness direction of the display panel. The presence of the power line can prevent the formation of parasitic capacitance between the connection line and the switching transistor. In other words, the power line can prevent coupling between the connection line and the switching transistor. This can reduce or minimize the effect of the data voltage applied to the connection line on the switching transistor.

[0040] In addition, the scan driver can be provided in the pad area rather than the non-display area. Therefore, the difference between the width of the portion of the non-display area located on the outer left side of the display area and the width of the portion of the non-display area located on the outer right side of the display area can be minimized.

[0041] Other features and embodiments may be apparent from the following detailed description, the accompanying drawings, and the present disclosure.

[0042] It is to be understood that neither the foregoing description nor the following detailed description is to be construed as limiting the embodiments described or claimed herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The accompanying drawings, which are included to provide a further understanding of the present disclosure, illustrate embodiments, in which:

[0044] Figure 1 is a perspective view of a display device according to an embodiment;

[0045] Figures 2 to 4 yes Figure 1 A side view of a display device;

[0046] Figure 5 It shows Figure 1 A plan view of a display panel, a display driver, and a scan driver of a display device;

[0047] Figure 6 It shows Figure 5 An enlarged plan view of area A;

[0048] Figure 7 is shown with Figure 6 an enlarged plan view of a sub-pixel where the first data line and the first connection line overlap;

[0049] Figure 8 and Figure 9 According to the embodiment, Figure 7 A cross-sectional view taken along line II' and line II-II';

[0050] Figure 10 and Figure 11 According to the embodiment, Figure 7 A cross-sectional view taken along line II' and line II-II';

[0051] Figure 12 is a plan view showing a display panel, a display driver, and a scan driver of a display device according to another embodiment;

[0052] Figure 13 is a plan view showing a display panel, a display driver, and a scan driver of a display device according to another embodiment;

[0053] Figure 14 is a plan view showing a display panel, a display driver, and a scan driver of a display device according to another embodiment;

[0054] Figure 15 is a plan view showing a display panel, a display driver, and a scan driver of a display device according to another embodiment;

[0055] Figure 16 It shows Figure 15 an enlarged plan view of area B;

[0056] Figure 17 It shows Figure 15 an enlarged plan view of area C;

[0057] Figure 18 is shown with Figure 16 an enlarged plan view of a sub-pixel where the first data line, the first sub-connection line, and the second sub-connection line overlap;

[0058] Figure 19 is shown with Figure 17 an enlarged plan view of a sub-pixel where the first data line and the second sub-connection line overlap;

[0059] Figure 20 and Figure 21 According to the embodiment, Figure 18Line III-III' and Figure 19 A cross-sectional view taken along line IV-IV';

[0060] Figure 22 and Figure 23 According to the embodiment, Figure 18 Line III-III' and Figure 19 A cross-sectional view taken along line IV-IV';

[0061] Figure 24 is a plan view showing a display panel, a display driver, and a scan driver of a display device according to another embodiment;

[0062] Figure 25 It shows Figure 24 A cross-sectional view of an embodiment of a sub-pixel;

[0063] Figure 26 It shows Figure 24 A cross-sectional view of another embodiment of a sub-pixel;

[0064] Figure 27 It shows Figure 24 A cross-sectional view of another embodiment of a sub-pixel;

[0065] Figure 28 It shows Figure 24 A cross-sectional view of another embodiment of a sub-pixel;

[0066] Figure 29 is a plan view showing a display panel, a display driver, and a scan driver of a display device according to another embodiment;

[0067] Figure 30 is a perspective view of a display device according to another embodiment; and

[0068] Figure 31 is a developed view of a display device according to another embodiment. DETAILED DESCRIPTION

[0069] Now, the embodiments will be described more fully below with reference to the accompanying drawings. However, the embodiments may be provided in different forms and should not be construed as limiting. Throughout this disclosure, the same reference numerals represent the same components. In the accompanying drawings, the thickness of layers and regions may be exaggerated for clarity.

[0070] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being “directly on” another element, there may be no intervening elements present.

[0071] In addition, in the specification, the phrase "in a plan view" refers to when the object portion is viewed from above, and the phrase "in a cross-sectional view" refers to when a cross-section taken by vertically cutting the object portion is viewed from the side. In addition, the term "overlapping" or "overlapping" means that the first object can be above or below the second object, and vice versa. The term "facing" or "facing..." means that the first object can be directly or indirectly opposite to the second object. In the case where a third object is interposed between the first and second objects, the first and second objects can be understood as being indirectly opposite to each other, although still facing each other.

[0072] For ease of description, spatially relative terms such as "below," "beneath," "below," "above," or "on" may be used herein to describe the relationship between one element or component and another element or component as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientations depicted in the accompanying drawings. For example, where the device shown in the accompanying drawings is flipped over, a device that is "below" or "beneath" another device may be "above" the other device. Thus, the exemplary term "below" can include both a lower position and an upper position. Devices may also be positioned in other orientations, and therefore, the spatially relative terms may be interpreted differently depending on the orientation.

[0073] Throughout this specification, when an element is referred to as being "connected" to another element, the element may be "directly connected" to the other element, or "electrically connected" to the other element, with one or more intermediate elements interposed therebetween. It will be further understood that when the terms "comprises," "comprising," "containing," and / or "having" are used in this specification, this may indicate the presence of the stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0074] It will be understood that although the terms "first," "second," or "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element or to facilitate description and explanation thereof. For example, when discussing a "first element" in the specification, it may be referred to as a "second element" or a "third element," and the "second element" and "third element" may be named in a similar manner without departing from the teachings herein.

[0075] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0076] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will be further understood that, unless expressly defined in this specification, terms such as those defined in general dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense.

[0077] Figure 1 is a perspective view of a display device 10 according to an embodiment.

[0078] Reference Figures 1 to 4 The display device 10 for displaying images such as moving images and / or still images can be used not only in portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, or ultra-mobile personal computers (UMPCs), but can also be used in various other products such as televisions (TVs), notebook computers, monitors, billboards, or Internet of Things (IoT) devices. The display device 10 can be an organic light emitting diode (OLED) display device, a liquid crystal display (LCD) device, a plasma display device, a field emission display (FED) device, an electrophoretic display (EPD) device, an electrowetting display device, a quantum dot light emitting diode (QLED) display device, and / or a micro light emitting diode (mLED) display device. The display device 10 will be described below as an OLED display device, but the embodiment is not limited thereto.

[0079] The display device 10 may include a display panel 100 , a display driver 200 , and a circuit board 300 .

[0080] As used herein, the terms "above," "top," and "top surface" may refer to an upper direction from the display panel 100, that is, the Z-axis direction, and as used herein, the terms "below," "bottom," and "bottom surface" may refer to a downward direction from the display panel 100, that is, the opposite direction of the Z-axis direction. In addition, as used herein, the terms "left," "right," "up," and "down" may refer to respective directions of the display panel 100 as viewed from above. For example, the term "left" may refer to the opposite direction of the X-axis direction, the term "right" may refer to the X-axis direction, the term "up" may refer to the Y-axis direction, and the term "down" may refer to the opposite direction of the Y-axis direction.

[0081] The display panel 100 may be formed in a rectangular shape in a plan view having a pair of short sides extending in a first direction (or X-axis direction) and a pair of long sides extending in a second direction (or Y-direction) intersecting the first direction (or X-axis direction). The corners where the short and long sides of the display panel 100 intersect may be rounded to have a predetermined curvature or may be right angles. The shape of the display device 10 is not particularly limited, and the display device 10 may be formed in various other polygonal shapes or in a circular or elliptical shape.

[0082] The display panel 100 may include a display area DA, a non-display area NDA, and a pad area PA.

[0083] The display area DA may be an area in which sub-pixels may be arranged to display an image. The non-display area NDA may be an area located outside the display area DA and may not display an image. The non-display area NDA may be arranged to surround the display area DA. The pad area PA may be an area to which the display driver 200 and the circuit board 300 may be attached. The pad area PA may not display an image. The pad area PA may protrude from the non-display area NDA in a first direction (or X-axis direction). The length of the pad area PA in the first direction (or X-axis direction) may be smaller than the length of the display area DA in the first direction (or X-axis direction). The length of the pad area PA in the second direction (or Y-axis direction) may be smaller than the length of the display area DA in the second direction (or Y-axis direction). The display driver 200 and the circuit board 300 may be arranged in the pad area PA.

[0084] The display driver 200 can output signals and voltages for driving the display panel 100. For example, the display driver 200 can output data voltages to data lines. In addition, the display driver 200 can output power voltages to power lines and can output scan control signals to a scan driver. The display driver 200 can be formed as an integrated circuit (IC) and can be provided on the display panel 100 in the first sub-pad area PDA by, for example, chip-on-glass (COG) or chip-on-plastic (COP) or by ultrasonic welding, but the embodiment is not limited thereto. For example, the display driver 200 can be provided on the circuit board 300.

[0085] The circuit board 300 may be attached to the pads via, for example, an anisotropic conductive film. Thus, the conductive lines of the circuit board 300 may be electrically connected to the pads of the display panel 100. The circuit board 300 may be a flexible film such as a flexible printed circuit board, a printed circuit board, or a chip-on-film.

[0086] Figures 2 to 4 yes Figure 1 10 is a side view of the display device 10.

[0087] Reference Figures 2 to 4 The pad area PA may include a bending area BA and a first sub-pad area PDA. The first sub-pad area PDA may be disposed on one side of the bending area BA, and the non-display area NDA may be disposed on the other side of the bending area BA. For example, the first sub-pad area PDA may be disposed on the right side of the bending area BA, and the non-display area NDA may be disposed on the left side of the bending area BA. The display driver 200 and the circuit board 300 may be disposed in the first sub-pad area PDA of the display panel 100.

[0088] The display panel 100 may be formed as a flexible display panel and thus may be bendable in the bending area BA. Figure 2 , before the display panel 100 is bent in the bending area BA, the first surface of the first subpad area PDA of the display panel 100 may face upward. Figure 3 When the display panel 100 is bent in the bending area BA and / or after the display panel 100 is bent in the bending area BA, the first surface of the first sub-pad area PDA of the display panel 100 may face downward. When the display panel 100 is bent in the bending area BA and / or after the display panel 100 is bent in the bending area BA, the first sub-pad area PDA of the display panel 100 may be disposed below the display area DA. When the display panel 100 is bent in the bending area BA and / or after the display panel 100 is bent in the bending area BA, the first sub-pad area PDA of the display panel 100 may overlap with the display area DA in the thickness direction of the display panel 100 (i.e., in the Z-axis direction).

[0089] The display panel 100 may be curved at the boundary between the non-display area NDA and the pad area PA, but the embodiment is not limited thereto. In other embodiments, the display panel 100 may not be curved at the boundary between the non-display area NDA and the pad area PA. For example, the display panel 100 may be curved at a position away from the boundary between the non-display area NDA and the pad area PA. Such a distance may be, for example, in the range of approximately 200 μm to 300 μm.

[0090] Reference Figure 3 The display panel 100 may include a flat portion FA, a first curved portion CA1, and a second curved portion CA2. The first curved portion CA1 may be curved from a first side of the flat portion FA with a first curvature. The second curved portion CA2 may be curved from a second side of the flat portion FA with a second curvature. For example, the first and second sides of the flat portion FA may be the left and right sides of the flat portion FA, respectively. The display area DA of the display panel 100 may be provided not only in the flat portion FA but also in the first and second curved portions CA1 and CA2. Therefore, images may be displayed not only in the flat portion FA but also in the first and second curved portions CA1 and CA2.

[0091] Figure 3 The first curvature of the first curved portion CA1 and the second curvature of the second curved portion CA2 are shown to be substantially the same, but the embodiment is not limited thereto. In other embodiments, the first curvature of the first curved portion CA1 and the second curvature of the second curved portion CA2 may be different from each other. In another embodiment, each of the first curved portion CA1 and the second curved portion CA2 may have a variable curvature rather than a uniform curvature.

[0092] The display panel 100 may include only one of the first and second curved portions CA1 and CA2. In another example, the display panel 100 may not include the first and second curved portions CA1 and CA2, but may include only the flat portion FA.

[0093] Reference Figure 4 The display panel 100 may include a first curved portion CA1, a second curved portion CA2, and a third curved portion CA3. The first curved portion CA1 may be bent from a first side of the third curved portion CA3 at a first curvature. The second curved portion CA2 may be bent from a second side of the third curved portion CA3 at a second curvature. The third curved portion CA3 may be bent at a third curvature. For example, the first side and the second side of the third curved portion CA3 may be the left side and the right side of the third curved portion CA3, respectively.

[0094] The display area DA of the display panel 100 may be disposed in the first, second, and third curved portions CA1, CA2, and CA3, and thus, an image may be displayed in the first, second, and third curved portions CA1, CA2, and CA3.

[0095] Figure 4 The first curvature of the first curved portion CA1 and the second curvature of the second curved portion CA2 are shown to be substantially the same, but the embodiment is not limited thereto. In other embodiments, the first curvature of the first curved portion CA1 and the second curvature of the second curved portion CA2 may be different from each other. In another example, each of the first curved portion CA1 and the second curved portion CA2 may have a variable curvature rather than a uniform curvature. The first curvature of the first curved portion CA1 and the second curvature of the second curved portion CA2 may be greater than the third curvature of the third curved portion CA3.

[0096] The display panel 100 may include only one of the first and second curved portions CA1 and CA2. In another example, the display panel 100 may not include the first and second curved portions CA1 and CA2, but may include only the third curved portion CA3.

[0097] The panel cover bottom 101 may be disposed under the display panel 100. The panel cover bottom 101 may be attached to the bottom surface of the display panel 100 via an adhesive member 102, and the adhesive member may be a pressure sensitive adhesive (PSA).

[0098] The panel bottom cover 101 may include a light absorbing member for absorbing light incident from the outside, a buffering member for absorbing shock from the outside, and a heat dissipating member for effectively releasing heat from the display panel 100 .

[0099] A light absorbing member may be provided below the display panel 100. The light absorbing member may block transmission of light, thereby preventing elements disposed therebelow (such as, for example, the circuit board 300) from becoming visible from above the display panel 100. The light absorbing member may include a light absorbing material such as a black pigment or a black dye.

[0100] A buffer member may be provided below the light absorbing member. The buffer member may absorb external shocks, thereby preventing damage to the display panel 100. The buffer member may be formed as a single-layer film or a multi-layer film. For example, the buffer member may be formed from a polymer resin such as polyurethane, polycarbonate, polypropylene, polyethylene, or a combination thereof. The buffer member may include an elastic material such as rubber, urethane, a sponge made of foamed acrylic material, or a combination thereof. The buffer member may be a cushion layer.

[0101] The heat dissipation member may be disposed below the buffer member. The heat dissipation member may include a first heat dissipation layer and a second heat dissipation layer, the first heat dissipation layer may include graphite or carbon nanotubes, and the second heat dissipation layer may be formed as a metal thin film capable of blocking electromagnetic waves and having excellent thermal conductivity, such as, for example, a metal thin film formed of copper (Cu), nickel (Ni), ferrite, silver (Ag), or a combination thereof.

[0102] In order to make the display panel 100 easily bendable, for example Figure 3 As shown in , the panel bottom cover 101 may not be provided in the curved area BA of the display panel 100. A portion of the panel bottom cover 101 in the flat portion FA of the display panel 100 and a portion of the panel bottom cover 101 in the first sub-pad area PDA of the display panel 100 may be attached together by an adhesive member 102. The first sub-pad area PDA of the display panel 100 may be fixed to the bottom of the flat portion FA of the display panel 100. The adhesive member 102 may be a PSA. In another example, a portion of the panel bottom cover 101 in the first curved portion CA1 of the display panel 100 and a portion of the panel bottom cover 101 in the first sub-pad area PDA of the display panel 100 may be attached together by an adhesive member 102. The first sub-pad area PDA of the display panel 100 may be fixed to the bottom of the first curved portion CA1 of the display panel 100.

[0103] Figure 5 It shows Figure 1 A plan view of a display panel, a display driver, and a scan driver of a display device.

[0104] Reference Figure 5 The display panel 100 may include a display area DA and a non-display area NDA. The display area DA includes sub-pixels and displays an image. The non-display area NDA may be an area located outside the display area DA. Sub-pixels, scan lines, data lines DL, power lines, and connection lines CL may be arranged in the display area DA. The scan driver 400 and the fan-out lines FL may be arranged in the non-display area NDA. For the purpose of convenience of description, Figure 5 The connection lines CL, data lines DL and fan-out lines FL are shown. Figure 5 Sub-pixels, scan lines, and power supply lines are not shown.

[0105] In the display area DA, the connection line CL may extend in a first direction (or X-axis direction), and the data line DL may extend in a second direction (or Y-axis direction). The scan line may be arranged parallel to the connection line CL. For example, the scan line may extend in the first direction (or X-axis direction).

[0106] The power lines may include a first power line and a second power line, a first power voltage may be applied to the first power line, and a second power voltage may be applied to the second power line. The first power voltage may be an initialization voltage for initializing the sub-pixel, and the second power voltage may be a pixel drive voltage for driving the sub-pixel. The second power voltage may be higher than the first power voltage. The first power line may be arranged parallel to the connection line CL. For example, the first power line may extend in a first direction (or an X-axis direction). The second power line may be arranged parallel to the data line DL. For example, the second power line may extend in a second direction (or a Y-axis direction).

[0107] The connection lines CL may be connected to the data lines DL through the connection holes CT. The data lines DL may be connected to the connection lines CL through the connection holes CT. The connection lines CL may be connected to the data lines DL. For example, each connection line CL may be connected to a corresponding one of the data lines DL.

[0108] The pad area PA includes a bending area BA and a first sub-pad area PDA, and the display driver 200 and the pad PAD can be disposed in the first sub-pad area PDA. The display driver 200 can be formed as an IC and can be disposed on the display panel 100 in the first sub-pad area PDA, for example, in a COG or COP manner or by ultrasonic welding. The circuit board 300 can be attached to the pad PAD, for example, via an anisotropic conductive film. Thus, the conductive lines of the circuit board 300 can be electrically connected to the pad PAD.

[0109] The fan-out lines FL may be disposed in the bending area BA and the first sub-pad area PDA. The fan-out lines FL may include a first fan-out line FL1 and a second fan-out line FL2. The first fan-out line FL1 may be disposed in the first sub-pad area PDA and may be connected to the display driver 200. In a portion of the first sub-pad area PDA adjacent to the bending area BA, the first fan-out line FL1 may be connected to the second fan-out line FL2 via a first wiring connection hole FCT1. The second fan-out line FL2 may be disposed in the bending area BA. In the non-display area NDA, the second fan-out line FL2 may be connected to the connection line CL via a second wiring connection hole FCT2.

[0110] Figure 5 It is shown that the second wiring connection hole FCT2 may be provided between the scan driver 400 and the pad area PA, but the embodiment is not limited thereto. In other embodiments, the second wiring connection hole FCT2 may be provided between the scan driver 400 and the display area DA.

[0111] The scan driver 400 may be disposed in a portion of the non-display area NDA located at an outer right side of the display area DA. The scan driver 400 may be disposed between the display area DA and the bending area BA of the pad area PA.

[0112] The scan driver 440 may include thin film transistors (TFTs). The TFTs of the scan driver 440 may be formed in the same layer as the TFTs of the sub-pixels in the display area DA.

[0113] according to Figure 5 In an embodiment, the pad area PA, in which the display driver 200 may be provided, protrudes from the non-display area NDA in a first direction (or X-axis direction), the first direction (or X-axis direction) intersecting the direction in which the data lines DL extend (i.e., the second direction (or Y-axis direction). Therefore, the data lines DL extending in the second direction (or Y-axis direction) may receive data voltages from the display driver 200 via the connection lines CL extending in the first direction (or X-axis direction).

[0114] and Figure 5 Compared to the embodiment of the present invention, the embodiment may include a pad area PA protruding from the non-display area NDA in the second direction (or Y-axis direction), in which the display driver 200 may be disposed. In the embodiment in which the pad area PA protrudes from the non-display area NDA in the second direction (or Y-axis direction), the length of the pad area PA in the first direction (or X-axis direction) needs to be less than the length of the display area DA in the first direction (or X-axis direction). Therefore, due to the presence of the fan-out line FL connecting the display area DA and the pad area PA, a difference inevitably occurs between the width of the portion of the non-display area NDA located on the outer upper side of the display area DA and the width of the portion of the non-display area NDA located on the outer lower side of the display area DA.

[0115] Return to reference Figure 5, the pad area PA may protrude from the non-display area NDA in a first direction (or X-axis direction), and the length of the pad area PA in a second direction (or Y-axis direction) may be less than the length of the display area DA in the second direction (or Y-axis direction). When the pad area PA protrudes from the non-display area NDA in the first direction (or X-axis direction), the length of the pad area PA in the second direction (or Y-axis direction) (i.e., the width of the pad area PA) may be greater than the length of the pad area PA in the first direction (or X-axis direction) (i.e., the width of the pad area PA) when the pad area PA protrudes from the non-display area NDA in the second direction (or Y-axis direction). Therefore, the design and / or arrangement of the fan-out line FL connecting the display area DA and the pad area PA can be facilitated. Therefore, the difference between the width of the portion of the non-display area NDA located on the outer left side of the display area DA and the width of the portion of the non-display area NDA located on the outer right side of the display area DA can be minimized.

[0116] Figure 6 It shows Figure 5 Specifically, Figure 6 Illustrated are first, second, and third data lines DL1, DL2, and DL3, and first, second, and third connection lines CL1, CL2, and CL3 that may be connected to the first, second, and third data lines DL1, DL2, and DL3, respectively.

[0117] Reference Figure 6 , the first connection line CL1, the second connection line CL2, and the third connection line CL3 can extend in the first direction (or the X-axis direction). The first data line DL1, the second data line DL2, and the third data line DL3 can extend in the second direction (or the Y-axis direction). The first power line VIL, to which the first power supply voltage can be applied, can extend in the first direction (or the X-axis direction). The second power line VDDL, to which the second power supply voltage can be applied, can extend in the second direction (or the Y-axis direction). The first power supply voltage can be an initialization voltage for initializing the sub-pixel, and the second power supply voltage can be a pixel driving voltage for driving the sub-pixel. The second power supply voltage can be higher than the first power supply voltage.

[0118] The first, second, and third connection lines CL1, CL2, and CL3 and the first power line VIL extending in the first direction (or X-axis direction) may intersect the first, second, and third data lines DL1, DL2, and DL3 and the second power line VDDL extending in the second direction (or Y-axis direction).

[0119] The first connection line CL1, the second connection line CL2, and the third connection line CL3 may overlap with the first power line VIL in the thickness direction of the display panel 100 (i.e., in the third direction (or Z-axis direction)). The first connection line CL1 may be connected to the first data line DL1 via a first connection hole CT1, which may be formed in the overlapping region of the first data line DL1 and the first power line VIL. The second connection line CL2 may be connected to the second data line DL2 via a second connection hole CT2, which may be formed in the overlapping region of the second data line DL2 and the first power line VIL. The third connection line CL3 may be connected to the third data line DL3 via a third connection hole CT3, which may be formed in the overlapping region of the third data line DL3 and the first power line VIL.

[0120] The first dummy pattern DM1 may be spaced apart from the first connection line CL1 in the first direction (or X-axis direction) and may overlap with the first power line VIL in the third direction (or Z-axis direction), with the first power line VIL overlapping the first connection line CL1. The second dummy pattern DM2 may be spaced apart from the second connection line CL2 in the first direction (or X-axis direction) and may overlap with the first power line VIL in the third direction (or Z-axis direction), with the first power line VIL overlapping the second connection line CL2. The third dummy pattern DM3 may be spaced apart from the third connection line CL3 in the first direction (or X-axis direction) and may overlap with the first power line VIL in the third direction (or Z-axis direction), with the first power line VIL overlapping the third connection line CL3. The first, second, and third dummy patterns DM1, DM2, and DM3 may be formed as islands and may be electrically floating. That is, no voltage is applied to the first, second, and third dummy patterns DM1, DM2, and DM3.

[0121] In the case where the first, second, and third dummy patterns DM1, DM2, and DM3 may not be formed, the amount of external light reflected in the region where the first, second, and third connection lines CL1, CL2, and CL3 may be provided is different from the amount of external light reflected in the region where the first, second, and third connection lines CL1, CL2, and CL3 may not be provided, and thus the connection lines CL1, CL2, and CL3 may be visible to the user. However, if the first, second, and third dummy patterns DM1, DM2, and DM3 may be provided in the region where the first, second, and third connection lines CL1, CL2, and CL3 may not be provided, the amount of external light reflected in the region where the first, second, and third connection lines CL1, CL2, and CL3 may be provided is not significantly different from the amount of external light reflected in the region where the first, second, and third connection lines CL1, CL2, and CL3 may not be provided, and thus the first, second, and third connection lines CL1, CL2, and CL3 may be prevented from becoming visible to the user.

[0122] according to Figure 6 In an embodiment of the present invention, the first connection line CL1, the second connection line CL2, and the third connection line CL3 may be connected to the first data line DL1, the second data line DL2, and the third data line DL3, respectively, through the first connection hole CT1, the second connection hole CT2, and the third connection hole CT3. Therefore, the first data line DL1, the second data line DL2, and the third data line DL3 extending in the second direction (or the Y-axis direction) may receive a data voltage from the display driver 200 via the first connection line CL1, the second connection line CL2, and the third connection line CL3 extending in the first direction (or the X-axis direction).

[0123] Figure 7 is shown with Figure 6 An enlarged plan view of a sub-pixel where the first data line and the first connection line overlap.

[0124] Reference Figure 7 , sub-pixels may include, for example, Figure 8 The driving transistor DT, the first to sixth transistors ST1 to ST6 and the capacitor C1 are shown in FIG.

[0125] The driving transistor DT may include an active layer DT_ACT, a gate electrode DT_G, a first electrode DT_S, and a second electrode DT_D. The active layer DT_ACT of the driving transistor DT may overlap with the gate electrode DT_G of the driving transistor DT. The gate electrode DT_G of the driving transistor DT may be connected to the first connection electrode BE1 through a first contact hole CNT1. The first connection electrode BE1 may be connected to the first electrode S1-1 of the (1-1)th transistor ST1-1 through a second contact hole CNT2. The first connection electrode BE1 may intersect with the kth scan line Sk. For example, as in Figure 8 As shown in , the first electrode DT_S of the driving transistor DT may be connected to the first electrode S2 of the second transistor ST2. The second electrode DT_D of the driving transistor DT may be connected to the first electrode S3-1 of the (3-1)th transistor ST3-1 and the first electrode S6 of the sixth transistor ST6.

[0126] The first transistor ST1 may be formed as a double transistor. The first transistor ST1 may include a (1-1)th transistor ST1-1 and a (1-2)th transistor ST1-2.

[0127] The (1-1)th transistor ST1-1 may include an active layer ACT1-1, a gate electrode G1-1, a first electrode S1-1, and a second electrode D1-1. The gate electrode G1-1 of the (1-1)th transistor ST1-1 may correspond to a portion of the (k-1)th scan line Sk-1, specifically, may correspond to a portion of the (k-1)th scan line Sk-1 that overlaps with the active layer ACT1-1 of the (1-1)th transistor ST1-1. The first electrode S1-1 of the (1-1)th transistor ST1-1 may be connected to the first connection electrode BE1 of the drive transistor DT through a second contact hole CNT2. The second electrode D1-1 of the (1-1)th transistor ST1-1 may be connected to the first electrode S1-2 of the (1-2)th transistor ST1-2.

[0128] The (1-2)th transistor ST1-2 may include an active layer ACT1-2, a gate electrode G1-2, a first electrode S1-2, and a second electrode D1-2. The gate electrode G1-2 of the (1-2)th transistor ST1-2 may correspond to a portion of the (k-1)th scan line Sk-1, specifically, may correspond to a portion of the (k-1)th scan line Sk-1 that overlaps with the active layer ACT1-2 of the (1-2)th transistor ST1-2. The first electrode S1-2 of the (1-2)th transistor ST1-2 may be connected to the second electrode D1-1 of the (1-1)th transistor ST1-1. The second electrode D1-2 of the (1-2)th transistor ST1-2 may be connected to the second connection electrode VIE through a fourth contact hole CNT4. The first power line VIL may be connected to the second connection electrode VIE through a fifth contact hole CNT5. The second connection electrode VIE may be disposed to intersect the (k-1)th scan line Sk-1.

[0129] The second transistor ST2 may include an active layer ACT2, a gate electrode G2, a first electrode S2, and a second electrode D2. The gate electrode G2 of the second transistor ST2 may correspond to a portion of the k-th scan line Sk, specifically, may correspond to a portion of the k-th scan line Sk that overlaps with the active layer ACT2 of the second transistor ST2. For example, Figure 8 As shown in FIG, the first electrode S2 of the second transistor ST2 may be connected to the first electrode DT_S of the driving transistor DT. The second electrode D2 of the second transistor ST2 may be connected to the j-th data line Dj through the third contact hole CNT3.

[0130] The third transistor ST3 may be formed as a double transistor. The third transistor ST3 may include a (3-1)th transistor ST3-1 and a (3-2)th transistor ST3-2.

[0131] The (3-1)th transistor ST3-1 may include an active layer ACT3-1, a gate electrode G3-1, a first electrode S3-1, and a second electrode D3-1. The gate electrode G3-1 of the (3-1)th transistor ST3-1 may correspond to a portion of the kth scan line Sk, specifically, may correspond to a portion of the kth scan line Sk that overlaps with the active layer ACT3-1 of the (3-1)th transistor ST3-1. The first electrode S3-1 of the (3-1)th transistor ST3-1 may be connected to the second electrode DT_D of the drive transistor DT. The second electrode D3-1 of the (3-1)th transistor ST3-1 may be connected to the first electrode S3-2 of the (3-2)th transistor ST3-2.

[0132] The (3-2)th transistor ST3-2 may include an active layer ACT3-2, a gate electrode G3-2, a first electrode S3-2, and a second electrode D3-2. The gate electrode G3-2 of the (3-2)th transistor ST3-2 may correspond to a portion of the k-th scan line Sk, specifically, may correspond to a portion of the k-th scan line Sk that overlaps with the active layer ACT3-2 of the (3-2)th transistor ST3-2. The first electrode S3-2 of the (3-2)th transistor ST3-2 may be connected to the second electrode D3-1 of the (3-1)th transistor ST3-1. The second electrode D3-2 of the (3-2)th transistor ST3-2 may be connected to the first connection electrode BE1 through the second contact hole CNT2.

[0133] The fourth transistor ST4 may include an active layer ACT4, a gate electrode G4, a first electrode S4, and a second electrode D4. The gate electrode G4 of the fourth transistor ST4 may correspond to a portion of the k-th emission line Ek, specifically, a portion of the k-th emission line Ek that overlaps with the active layer ACT4 of the fourth transistor ST4. The first electrode S4 of the fourth transistor ST4 may be connected to the second power line VDDL via a seventh contact hole CNT7. The second electrode D4 of the fourth transistor ST4 may be connected to the first electrode DT_S of the drive transistor DT. The second power line VDDL may be connected to the second electrode CE12 of the capacitor C1 via an eighth contact hole CNT8. The second power line VDDL may be arranged parallel to the j-th data line Dj.

[0134] The fifth transistor ST5 may include an active layer ACT5, a gate electrode G5, a first electrode S5, and a second electrode D5. The gate electrode G5 of the fifth transistor ST5 may correspond to a portion of the k-th emission line Ek, specifically, a portion of the k-th emission line Ek that overlaps with the active layer ACT5 of the fifth transistor ST5. The first electrode S5 of the fifth transistor ST5 may be connected to the second electrode DT_D of the drive transistor DT. The second electrode D5 of the fifth transistor ST5 may be connected to the first anode connection electrode ANDE1 via a sixth contact hole CNT6.

[0135] The sixth transistor ST6 may include an active layer ACT6, a gate electrode G6, a first electrode S6, and a second electrode D6. The gate electrode G6 of the sixth transistor ST6 may correspond to a portion of the k-th scan line Sk, specifically, a portion of the k-th scan line Sk that overlaps with the active layer ACT6 of the sixth transistor ST6. The first electrode S6 of the sixth transistor ST6 may be connected to the second connection electrode VIE via a fourth contact hole CNT4. The second electrode D6 of the sixth transistor ST6 may be connected to the first anode connection electrode ANDE1 via a sixth contact hole CNT6.

[0136] The first anode connection electrode ANDE1 may be connected to the first electrode S6 of the sixth transistor ST6 through the sixth contact hole CNT6. Figure 8 As shown in , the second anode connection electrode ANDE2 may be connected to the first anode connection electrode ANDE1 through the first anode contact hole AND_CNT1. Figure 8 , the first electrode 171 of the light emitting element may be connected to the first anode connection electrode ANDE1 through the second anode contact hole AND_CNT2 .

[0137] A first electrode CE11 of the capacitor C1 may correspond to a portion of the gate electrode DT_G of the driving transistor DT, and a second electrode CE12 of the capacitor C1 may overlap with the gate electrode DT_G of the driving transistor DT.

[0138] The first connection line CL1 may overlap the first power line VIL in the third direction (or Z-axis direction). The first connection hole CT1 may be provided in the overlapping region of the first data line DL1 and the first connection line CL1. The first connection line CL1 may be connected to the first data line DL1 through the first connection hole CT1.

[0139] Reference Figure 9 , the first connection line CL1 may overlap with the second electrode D1-1 of the (1-1)th transistor ST1-1 and the first electrode S1-2 of the (1-2)th transistor ST1-2. The first connection line CL1 may overlap with the second connection electrode VIE and the second electrode D5 of the fifth transistor ST5. The first connection line CL1 may overlap with the fifth contact hole CNT5. The first power line VIL may be provided between the first connection line CL1 and the second electrode D1-1 of the (1-1)th transistor ST1-1, between the first connection line CL1 and the first electrode S1-2 of the (1-2)th transistor ST1-2, and between the first connection line CL1 and the second electrode D5 of the fifth transistor ST5. Due to the presence of the first power line VIL, coupling can be prevented between the first connection line CL1 and the second electrode D1-1 of the (1-1)th transistor ST1-1, between the first connection line CL1 and the first electrode S1-2 of the (1-2)th transistor ST1-2, and between the first connection line CL1 and the second electrode D5 of the fifth transistor ST5. Therefore, the influence of the first connection line CL1 on the second electrode D1-1 of the (1-1)th transistor ST1-1, the first electrode S1-2 of the (1-2)th transistor ST1-2, and the second electrode D5 of the fifth transistor ST5 may be reduced or minimized.

[0140] Figure 8 and Figure 9 According to the embodiment, Figure 7 Cross-sectional views taken along line II' and line II-II'.

[0141] Reference Figure 8 and Figure 9 , a TFT layer TFTL, a light emitting element layer EML, and an encapsulation layer TFE may be sequentially formed on the first substrate SUB1.

[0142] The TFT layer TFTL includes a light shielding layer BML, a buffer film BF, an active layer ACT (DT_ACT, ACT1, ACT2, ACT3, ACT4, ACT5, ACT6), a first gate layer GTL1, a second gate layer GTL2, a first source metal layer DTL1, a second source metal layer DTL2, a gate insulating film 130, a first interlayer insulating film 141, a second interlayer insulating film 142, a passivation film 150, a first planarization film 160 and a second planarization film 180.

[0143] A light shielding layer BML may be formed on one surface of the first substrate SUB1 and disposed to overlap the active layer DT_ACT of the driving transistor DT to prevent leakage current from being generated when light may be incident on the active layer DT_ACT of the driving transistor DT. Figure 11 The light shielding layer BML is shown as overlapping only the active layer DT_ACT of the driving transistor DT, but the embodiment is not limited thereto. The light shielding layer BML may overlap not only the active layer DT_ACT of the driving transistor DT, but also the active layers ACT1 to ACT6 of the first to sixth transistors ST1 to ST6. The light shielding layer BML may be formed as a single layer or a multilayer film including molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), Ni, neodymium (Nd), Cu, or alloys thereof.

[0144] A buffer film BF may be formed on the light shielding layer BML. The buffer film may be formed on the first substrate SUB1 to protect the TFT 120 and the organic light-emitting layer 172 of the light-emitting element layer EML from moisture that may penetrate through the first substrate SUB1 into the TFT 120 and the organic light-emitting layer 172. The buffer film BF may include alternately stacked inorganic films. For example, the buffer film BF may be formed as a multilayer film in which at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer may be alternately stacked. In another example, the buffer film BF may not be provided.

[0145] The active layer ACT may be formed on the first substrate SUB1 or on the buffer film BF. The active layer ACT may include polycrystalline silicon, single crystal silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor. When the active layer ACT is formed of polycrystalline silicon, the active layer ACT may be conductive. Therefore, the active layer ACT may include not only the active layer DT_ACT of the drive transistor DT and the active layers ACT1, ACT2, ACT3, ACT4, ACT5, and ACT6 of the first to sixth transistors ST1 to ST6, but may also include the source electrode DT_S and the drain electrode DT_D of the drive transistor DT, and the source electrodes S1, S2-1, S2-2, S3-1, S3-2, S4, S5, and S6 and the drain electrodes D1, D2-1, D2-2, D3-1, D3-2, D4, D5, and D6 of the first to sixth transistors ST1 to ST6.

[0146] The gate insulating film 130 may be formed on the active layer ACT. The gate insulating film 130 may be formed as an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0147] The first gate layer GTL1 may be formed on the gate insulating film 130. The first gate layer GTL1 may include not only the gate electrode DT_G of the drive transistor DT and the gate electrodes G1 to G6 of the first to sixth transistors ST1 to ST6, but may also include the (k-1)th scan line Sk-1 and the kth scan line Sk, and the kth emission line Ek. The scan lines may be formed of a first gate metal layer. The first gate layer GTL1 may be formed as a single layer or a multilayer film including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or alloys thereof.

[0148] A first interlayer insulating film 141 may be formed on the first gate layer GTL1. The first interlayer insulating film 141 may be formed as an inorganic film such as, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating film 141 may include an inorganic film.

[0149] The second gate layer GTL2 may be formed on the first interlayer insulating film 141. The second gate layer GTL2 may include the first power line VIL and the second electrode CE2 of the capacitor C1. The second gate layer GTL2 may be formed as a single layer or a multilayer film including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or alloys thereof.

[0150] The second interlayer insulating film 142 may be formed on the second gate layer GTL2. The second interlayer insulating film 142 may be formed as an inorganic film such as, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating film 142 may include an inorganic film.

[0151] A first source metal layer DTL1 may be formed on the second interlayer insulating film 142. The first source metal layer DTL1 may include a first data line DL1, a second power line VDDL, a first connection electrode BE1, a first anode connection electrode ANDE1, and a second connection electrode VIE. The first data line DL1 may be formed from the first source metal layer DTL1. The first source metal layer DTL1 may be formed as a single layer or a multilayer film including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or alloys thereof.

[0152] The first planarization film 160 may be formed on the first source metal layer DTL1 to planarize the height difference formed by the active layer ACT, the first gate layer GTL1, the second gate layer GTL2, and the first source metal layer DTL1. The first planarization film 160 may be formed as an organic film including acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0153] The passivation film 150 may be formed between the first source metal layer DTL1 and the first planarization film 160. For example, the passivation film 150 may be formed as an inorganic film such as, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0154] The second source metal layer DTL2 may be formed on the first planarization film 160. The second source metal layer DTL2 may include a second anode connection electrode ANDE2 and a first connection line CL1. The second source metal layer DTL2 may be formed as a single layer or a multilayer film including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or alloys thereof.

[0155] The second planarization film 180 may be formed on the second source metal layer DTL2 . The second planarization film 180 may be formed as an organic film including acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin.

[0156] The driving transistor DT and the first to sixth transistors ST1 to ST6 may be top-gate transistors in which the gate electrode may be disposed above the active layer, but the embodiment is not limited thereto. In other embodiments, the driving transistor DT and the first to sixth transistors ST1 to ST6 may be bottom-gate transistors in which the gate electrode is disposed below the active layer or dual-gate transistors in which the gate electrodes may be disposed above and below the active layer.

[0157] The first contact hole CNT1 may be a hole penetrating the first and second interlayer insulating films 141 and 142 and exposing the gate electrode DT_G of the driving transistor DT. The first connection electrode BE1 may be connected to the gate electrode DT_G of the driving transistor DT through the first contact hole CNT1.

[0158] The second contact hole CNT2 may be a hole exposing the second electrode D3-1 of the (3-1)th transistor ST3-1 through the gate insulating film 130 and the first and second interlayer insulating films 141 and 142. The second connection electrode BE2 may be connected to the second electrode D3-1 of the (3-1)th transistor ST3-1 through the second contact hole CNT2.

[0159] The third contact hole CNT3 may be a hole exposing the first electrode S2 of the second transistor ST2 through the gate insulating film 130 and the first and second interlayer insulating films 141 and 142. The j-th data line Dj may be connected to the first electrode S2 of the second transistor ST2 through the third contact hole CNT3.

[0160] The fourth contact hole CNT4 may be a hole exposing the second electrode D1 of the first transistor ST1 and the second electrode D4 of the fourth transistor ST4 through the gate insulating film 130 and the first and second interlayer insulating films 141 and 142. The second connection electrode VIE may be connected to the (1-2)th electrode of the (1-2)th transistor ST1-2 and the second electrode D4 of the fourth transistor ST4 through the fourth contact hole CNT4.

[0161] The fifth contact hole CNT5 may be a hole exposing the first power line VIL through the second interlayer insulating film 142. The second link electrode VIE may be connected to the first power line VIL through the fifth contact hole CNT5.

[0162] The sixth contact hole CNT6 may be a hole exposing the second electrode D6 of the sixth transistor ST6 through the gate insulating film 130 and the first and second interlayer insulating films 141 and 142. The first anode connection electrode ANDE1 may be connected to the sixth transistor ST6 through the sixth contact hole CNT6.

[0163] The seventh contact hole CNT7 may be a hole exposing the first electrode S5 of the fifth transistor ST5 through the gate insulating film 130 and the first and second interlayer insulating films 141 and 142. The second power line VDDL may be connected to the first electrode S4 of the fourth transistor ST4 through the seventh contact hole CNT7.

[0164] The eighth contact hole CNT8 may be a hole exposing the second electrode CE12 of the capacitor C1 through the second interlayer insulating film 142. The second power line VDDL may be connected to the second electrode CE12 of the capacitor C1 through the eighth contact hole CNT8.

[0165] The first anode contact hole AND_CNT1 may be a hole exposing the first anode connection electrode ANDE1 through the passivation film 150 and the first planarization film 160. The second anode contact hole AND_CNT2 may be a hole exposing the second anode connection electrode ANDE2 through the second planarization film 180.

[0166] The first connection hole CT1 may be a hole exposing the first data line DL1 through the first planarization film 160. The second and third connection holes CT2 and CT3 may be holes exposing the second and third data lines DL2 and DL3 through the first planarization film 160, respectively.

[0167] A light emitting element layer EML may be formed on the TFT layer TFTL. The light emitting element layer EML includes a light emitting element 170 and a pixel defining film 190.

[0168] The light emitting elements 170 and the pixel defining film 190 may be formed on the planarization film 160. Each of the light emitting elements 170 may include a first electrode 171, an organic light emitting layer 172, and a second electrode 173.

[0169] The first electrode 171 may be formed on the second planarization film 180. The first electrode 171 may be connected to the second anode connection electrode ANDE2 through a second anode contact hole AND_CNT2 penetrating the second planarization film 180.

[0170] In a top emission structure that emits light in a direction from the organic light-emitting layer 172 to the second electrode 173, the first electrode 171 can be formed of a metal material with high reflectivity, such as a stack of Al and Ti (e.g., Ti / Al / Ti), a stack of Al and indium tin oxide (ITO) (e.g., ITO / Al / ITO), a silver-palladium-copper (APC) alloy, or a stack of an APC alloy and ITO (e.g., ITO / APC / ITO).

[0171] The pixel defining film 190 may be formed to define the first electrode 171 above the second planarization film 180, thereby defining the emission area EA. The pixel defining film 190 may be formed to cover the edge of the first electrode 171. The pixel defining film 190 may be formed as an organic film including acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0172] The emission area EA refers to a region where the first electrode 171, the organic light emitting layer 172, and the second electrode 173 may be sequentially stacked so that holes from the first electrode 171 and electrons from the second electrode 173 may be combined together in the organic light emitting layer 172 to emit light.

[0173] The organic light emitting layer 172 may be formed on the first electrode 171 and the pixel defining film 190. The organic light emitting layer 172 may include an organic material and may emit light of a predetermined color. For example, the organic light emitting layer 172 may include a hole transport layer, an organic material layer, and an electron transport layer.

[0174] The second electrode 173 may be formed on the organic light emitting layer 172. The second electrode 173 may be formed to cover the organic light emitting layer 172. The second electrode 173 may be a common layer formed for all sub-pixels. A covering layer may be formed on the second electrode 173.

[0175] In a top emission structure, the second electrode 173 may be formed of a transparent conductive oxide (TCO) material such as ITO or IZO, or a semi-transparent metal material such as magnesium (Mg), Ag, or an alloy of Mg and Ag. When the second electrode 173 is formed of a semi-transparent metal material, the emission efficiency of the light-emitting element layer EML may be improved due to a microcavity effect.

[0176] The encapsulation layer TFE may be formed on the light emitting element layer EML. The encapsulation layer TFE may include at least one inorganic film for preventing oxygen or moisture from penetrating into the light emitting element layer EML. In addition, the encapsulation layer TFE may include at least one organic film for protecting the light emitting element layer EML from foreign substances such as dust.

[0177] A second substrate may be provided on the light-emitting element layer EML instead of the encapsulation layer TFE. The space between the light-emitting element layer EML and the second substrate may be hollow in a vacuum, or a filling film may be provided in the space between the light-emitting element layer EML and the second substrate. The filling film may be an epoxy resin filling film or a silicone filling film.

[0178] according to Figures 7 to 9In an embodiment of the present invention, the first connection line CL1 may overlap with the first power line VIL in the thickness direction of the display panel 100 (i.e., in the third direction (or Z-axis direction)). Due to the presence of the first power line VIL, parasitic capacitances may be prevented from being formed between the first connection line CL1 and the second electrode D1-1 of the (1-1)th transistor ST1-1, between the first connection line CL1 and the first electrode S1-2 of the (1-2)th transistor ST1-2, and between the first connection line CL1 and the second electrode D5 of the fifth transistor ST5. That is, due to the presence of the first power line VIL, coupling may be prevented from being generated between the first connection line CL1 and the second electrode D1-1 of the (1-1)th transistor ST1-1, between the first connection line CL1 and the first electrode S1-2 of the (1-2)th transistor ST1-2, and between the first connection line CL1 and the second electrode D5 of the fifth transistor ST5. Therefore, the influence of the data voltage applied to the first connection line CL1 on the second electrode D1-1 of the (1-1)th transistor ST1-1, the first electrode S1-2 of the (1-2)th transistor ST1-2, and the second electrode D5 of the fifth transistor ST5 can be reduced or minimized.

[0179] Figure 5 The first fan-out lines FL1 may be alternately disposed in the first gate metal layer GTL1 and the second gate metal layer GTL2 . Figure 5 The second fan-out lines FL2 may be alternately arranged in the first source metal layer DTL1 and the second source metal layer DTL2. The first wiring connection hole FCT1 may be a hole that passes through the first planarization film 160, the passivation film 150, and the second interlayer insulating film 142, or a hole that passes through the passivation film 150, the second interlayer insulating film 142, and the first interlayer insulating film 141. In an embodiment, the second wiring connection hole FCT2 may not be provided. The second fan-out line FL2 may be provided in the same layer as the layer in which the connection line CL is provided. The second fan-out line FL2 may be connected to (or directly connected to) the connection line CL.

[0180] Figure 10 and Figure 11 According to the embodiment, Figure 7 Cross-sectional views taken along line II' and line II-II'.

[0181] exist Figure 10 and Figure 11 In an embodiment, the second source metal layer DTL2 may include a second power line VDDL, a third source metal layer DTL3 including a third anode connection electrode ANDE3 and a first connection electrode CE1 may be disposed on the second planarization film 180, and a third planarization film 181 may be disposed on the third source metal layer DTL3.

[0182] Reference Figure 10 and Figure 11 , a second source metal layer DTL2 may be formed on the first planarization film 160. The second source metal layer DTL2 may include a second anode connection electrode ANDE2 and a second power supply line VDDL. The second source metal layer DTL2 may be formed as a single layer or a multilayer film including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or alloys thereof.

[0183] The second planarization film 180 may be formed on the second source metal layer DTL2 . The second planarization film 180 may be formed as an organic film including acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin.

[0184] The third source metal layer DTL3 may be formed on the second planarization film 180. The third source metal layer DTL3 may include a third anode connection electrode ANDE3 and a first connection line CL1. The third source metal layer DTL3 may be formed as a single layer or a multilayer film including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or alloys thereof.

[0185] The third planarization film 181 may be formed on the third source metal layer DTL3 . The third planarization film 181 may be formed as an organic film including acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin.

[0186] The second anode contact hole AND_CNT2 may be a hole exposing the third anode connection electrode ANDE3 through the third planarization film 181. The third anode contact hole AND_CNT3 may be a hole exposing the second anode connection electrode ANDE2 through the second planarization film 180.

[0187] The first connection hole CT1 may be a hole exposing the first data line DL1 through the first planarization film 160. The second and third connection holes CT2 and CT3 may be holes exposing the second and third data lines DL2 and DL3 through the first planarization film 160, respectively.

[0188] Figure 5 The first fan-out lines FL1 may be alternately disposed in the first gate metal layer GTL1 and the second gate metal layer GTL2 . Figure 5 The second fan-out lines FL2 may be alternately arranged in the first source metal layer DTL1 and the second source metal layer DTL2. The first wiring connection hole FCT1 may be a hole penetrating the first planarization film 160, the passivation film 150, and the second interlayer insulating film 142, or a hole penetrating the passivation film 150, the second interlayer insulating film 142, and the first interlayer insulating film 141. The second wiring connection hole FCT2 may be a hole penetrating the second planarization film 180.

[0189] Figure 12 is a plan view illustrating a display panel, a display driver, and a scan driver of a display device according to another embodiment.

[0190] exist Figure 12 In the embodiment of FIG. 5 , the scan driver 400 may be disposed in a portion of the non-display area NDA located at an outer left side of the display area DA.

[0191] Reference Figure 12 If the scan driver 400 is disposed at the outer right side of the display area DA, the complexity of wiring in the portion of the non-display area NDA located at the outer right side of the display area DA may be excessively high due to the presence of the fan-out lines FL and the scan driver 400. Conversely, if the scan driver 400 is disposed at the outer left side of the display area DA, the complexity of wiring in the portion of the non-display area NDA located at the outer right side of the display area DA can be reduced due to the presence of the scan driver 400.

[0192] Figure 13 is a plan view illustrating a display panel, a display driver, and a scan driver of a display device according to another embodiment.

[0193] exist Figure 13 In an embodiment, two scan drivers 401 and 402 may be provided in the non-display area NDA at the outer left and outer right sides of the display area DA, respectively.

[0194] Reference Figure 13 , each of the scan drivers 401 and 402 may include a scan signal output portion that can be connected to a scan line and an emission signal output portion that can be connected to an emission line. The scan signal output portion may be provided in a portion of the non-display area NDA located at a first outer side of the display area DA, and the emission signal output portion may be provided in a portion of the non-display area NDA located at a second outer side of the display area DA. The scan signal output portion may be provided in a portion of the non-display area NDA located at an outer left side of the display area DA, and the emission signal output portion may be provided in a portion of the non-display area NDA located at an outer right side of the display area DA. In another example, the scan signal output portion may be provided in a portion of the non-display area NDA located at an outer right side of the display area DA, and the emission signal output portion may be provided in a portion of the non-display area NDA located at an outer left side of the display area DA.

[0195] In another example, a portion of the scan signal output portion and a portion of the emission signal output portion may be provided in a portion of the non-display area NDA located at a first outer side of the display area DA, and the remaining portion of the scan signal output portion and the remaining portion of the emission signal output portion may be provided in a portion of the non-display area NDA located at a second outer side of the display area DA. For example, an odd-numbered scan signal output portion that may be connected to an odd-numbered scan line may be provided in a portion of the non-display area NDA located at a first outer side of the display area DA, and an even-numbered scan signal output portion that may be connected to an even-numbered scan line may be provided in a portion of the non-display area NDA located at a second outer side of the display area DA.

[0196] Figure 14 is a plan view illustrating a display panel, a display driver, and a scan driver of a display device according to another embodiment.

[0197] exist Figure 14 In the embodiment of the present invention, the scan driver 400 may be disposed in the pad area PA instead of in the non-display area NDA.

[0198] Reference Figure 14 The pad area PA may include a bending area BA, a first sub-pad area PDA, and a second sub-pad area SDA. The second sub-pad area SDA may be disposed between the bending area BA and the first sub-pad area PDA. The scan driver 400 may be disposed in the second sub-pad area SDA.

[0199] The fan-out lines FL may be arranged in the bending area BA and the first sub-pad area PDA. The fan-out lines FL may include a first fan-out line FL1, a second fan-out line FL2, and a third fan-out line FL3. The first fan-out line FL1 may be arranged in the first sub-pad area PDA and may be connected to the display driver 200. The first fan-out line FL1 may be connected to the third fan-out line FL3 through a first wiring connection hole FCT1 in a portion of the first sub-pad area PDA adjacent to the second sub-pad area SDA. The third fan-out line FL3 may be arranged in the second sub-pad area SDA. The third fan-out line FL3 may be connected to the second fan-out line FL2 through a third wiring connection hole FCT3 in a portion of the second sub-pad area SDA adjacent to the bending area BA. The second fan-out line FL2 may be arranged in the bending area BA. The second fan-out line FL2 may be connected to the connection line CL through a second wiring connection hole FCT2 in the non-display area NDA.

[0200] The first fan-out lines FL1 may be alternately arranged in the first gate metal layer GTL1 and the second gate metal layer GTL2. The third fan-out lines FL3 may be arranged in the second source metal layer DTL2. In another example, the third fan-out lines FL3 may be alternately arranged in the second source metal layer DTL2 and the third source metal layer DTL3. The second fan-out lines FL2 may be alternately arranged in the first source metal layer DTL1 and the second source metal layer DTL2. In this case, the first wiring connection hole FCT1 may be a hole that passes through the second planarizing film 180, the first planarizing film 160, the passivation film 150, and the second interlayer insulating film 142, or a hole that passes through the first planarizing film 160, the passivation film 150, the second interlayer insulating film 142, and the first interlayer insulating film 141. In addition, the third wiring connection hole FCT3 may be a hole that passes through the first planarizing film 160 or a hole that passes through the second planarizing film 180. Alternatively, the second wiring connection hole FCT2 may not be provided, and the second fan-out line FL2 may be provided in the same layer as the connection line CL and connected (or directly connected) to the connection line CL. Alternatively, the second wiring connection hole FCT2 may be a hole penetrating the second planarization film 180 .

[0201] according to Figure 14 In an embodiment, since the scan driver 400 can be set in the pad area PA instead of the non-display area NDA, the difference between the width of the portion of the non-display area NDA located at the outer left side of the display area DA and the width of the portion of the non-display area NDA located at the outer right side of the display area DA can be minimized.

[0202] Figure 15 is a plan view illustrating a display panel, a display driver, and a scan driver of a display device according to another embodiment.

[0203] exist Figure 15 In an embodiment of the present invention, the connection line CL may be connected to the data line DL in the non-display area NDA instead of in the display area DA.

[0204] Reference Figure 15 , the connection lines CL may include horizontal connection lines HCL extending in a first direction (or X-axis direction) and vertical connection lines VCL extending in a second direction (or Y-axis direction).

[0205] In the non-display area NDA, the horizontal connection line HCL may be connected to the second fan-out line FL2 through the second wiring connection hole FCT2. The vertical connection line VCL may be connected to the data line DL through the connection hole CT. The data line DL may be connected to the vertical connection line VCL through the connection hole CT. The vertical connection line VCL may be connected to the data line DL one-to-one.

[0206] In the non-display area NDA, the vertical connection line VCL may be connected to the data line DL through the connection hole CT. That is, the connection hole CT may be provided in the non-display area NDA. Figure 15 The vertical connection line VCL is shown to be disposed in a portion of the non-display area NDA located at the outer lower side of the display area DA, but the embodiment is not limited thereto. For example, the vertical connection line VCL may be disposed in a portion of the non-display area NDA located at the outer upper side of the display area DA.

[0207] according to Figure 15 In an embodiment, the pad area PA, in which the display driver 200 may be disposed, may protrude from the non-display area NDA in a first direction (or X-axis direction), the first direction (or X-axis direction) intersecting the direction in which the data lines DL extend (i.e., the second direction (or Y-axis direction). Therefore, the data lines DL extending in the second direction (or Y-axis direction) may receive data voltages from the display driver 200 via the horizontal connection lines HCL extending in the first direction (or X-axis direction) and the vertical connection lines VCL extending in the second direction (or Y-axis direction).

[0208] In addition, according to Figure 15 In an embodiment, when the pad area PA protrudes from the non-display area NDA in the first direction (or the X-axis direction), the length of the pad area PA in the second direction (or the Y-axis direction) can be greater than the length of the pad area PA in the first direction (or the X-axis direction). This can facilitate the design and / or arrangement of the fan-out line FL connecting the display area DA and the pad area PA. Therefore, the difference between the width of the portion of the non-display area NDA located on the outer left side of the display area DA and the width of the portion of the non-display area NDA located on the outer right side of the display area DA can be minimized.

[0209] Figure 16 It shows Figure 15 An enlarged plan view of area B. Figure 17 It shows Figure 15 Specifically, Figure 16 and Figure 17 Illustrated are first, second, and third connection lines CL1, CL2, and CL3 that may be connected to the first, second, and third data lines DL1, DL2, and DL3, respectively.

[0210] exist Figure 16 and Figure 17 In the embodiment of the present invention, each of the first connection line CL1, the second connection line CL2, and the third connection line CL3 includes a horizontal connection line and a vertical connection line.

[0211] Reference Figure 16 and Figure 17 The first connection line CL1 includes a first sub-connection line HCL1 and a second sub-connection line HCL2. The second connection line CL2 includes a second horizontal connection line HCL2 and a second vertical connection line VCL2. The third connection line CL3 includes a third horizontal connection line HCL3 and a third vertical connection line VCL3.

[0212] The first sub-connection line HCL1, the second horizontal connection line HCL2, and the third horizontal connection line HCL3 may extend in the first direction (or X-axis direction), and the second sub-connection line VCL1, the second vertical connection line VCL2, and the third vertical connection line VCL3 may extend in the second direction (or Y-axis direction).

[0213] The first sub-connection line HCL1, the second horizontal connection line HCL2, and the third horizontal connection line HCL3 may overlap with the first power line VIL in the third direction (or the Z-axis direction). The second sub-connection line VCL1, the second vertical connection line VCL2, and the third vertical connection line VCL3 may overlap with the second power line VDDL in the third direction (or the Z-axis direction).

[0214] The first sub-connection line HCL1 can be connected to the second sub-connection line VCL1 in an overlapping area between the first sub-connection line HCL1 and the second power line VDDL. The first sub-connection line HCL1 and the second sub-connection line VCL1 can be arranged in the same layer. In the non-display area NDA, the second sub-connection line VCL1 can be bent in the first direction (or the X-axis direction) and can be connected to the first data line DL1 through the first connection hole CT1'. That is, in the display area DA, the first connection line CL1 can extend in the first direction (or the X-axis direction) and can be bent to extend in the second direction (or the Y-axis direction), and in the non-display area NDA, the first connection line CL1 can be bent again to extend back in the first direction (or the X-axis direction).

[0215] The second horizontal connection line HCL2 can be connected to the second vertical connection line VCL2 in the overlapping area of ​​the second horizontal connection line HCL2 and the second power line VDDL. The second horizontal connection line HCL2 and the second vertical connection line VCL2 can be arranged in the same layer. In the non-display area NDA, the second vertical connection line VCL2 can be bent in the first direction (or X-axis direction) and can be connected to the second data line DL2 through the second connection hole CT2'. That is, in the display area DA, the second connection line CL2 can extend in the first direction (or X-axis direction) and can be bent to extend in the second direction (or Y-axis direction), and in the non-display area NDA, the second connection line CL2 can be bent again to extend back in the first direction (or X-axis direction).

[0216] The third horizontal connection line HCL3 can be connected to the third vertical connection line VCL3 in the overlapping area of ​​the third horizontal connection line HCL3 and the second power line VDDL. The third horizontal connection line HCL3 and the third vertical connection line VCL3 can be arranged in the same layer. In the non-display area NDA, the third vertical connection line VCL3 can be bent in the first direction (or the X-axis direction) and can be connected to the third data line DL3 through the third connection hole CT3'. That is, in the display area DA, the third connection line CL3 can extend in the first direction (or the X-axis direction) and can be bent to extend in the second direction (or the Y-axis direction). In the non-display area NDA, the third connection line CL3 can be bent again to extend back in the first direction (or the X-axis direction).

[0217] The first dummy pattern DM1 may be spaced apart from the first sub-connection line HCL1 in the first direction (or the X-axis direction) and may overlap with the first power line VIL in the third direction (or the Z-axis direction). The first power line VIL may overlap with the first sub-connection line HCL1. The second dummy pattern DM2 may be spaced apart from the second connection line CL2 in the first direction (or the X-axis direction) and may overlap with the first power line VIL in the third direction (or the Z-axis direction). The first power line VIL may overlap with the second horizontal connection line HCL2. One of the second dummy patterns DM2 may be positioned to the left of the second sub-connection line VCL1, and another of the second dummy patterns DM2 may be positioned to the right of the second sub-connection line VCL1. The third dummy pattern DM3 may be spaced apart from the third connection line CL3 in the first direction (or the X-axis direction) and may overlap with the first power line VIL in the third direction (or the Z-axis direction). The first power line VIL may overlap with the third horizontal connection line HCL3. One of the third dummy patterns DM3 may be disposed on the left side of the second sub connection line VCL1, another of the third dummy patterns DM3 may be disposed between the second sub connection line VCL1 and the second vertical connection line VCL2, and still another of the third dummy patterns DM3 may be disposed on the right side of the second vertical connection line VCL2.

[0218] The fourth dummy pattern DM4 may be spaced apart from the second sub-connection line VCL1 in the second direction (or Y-axis direction) and may overlap the second power line VDDL in the third direction (or Z-axis direction). The second power line VDDL may overlap the second sub-connection line VCL1. The fifth dummy pattern DM5 may be spaced apart from the second vertical connection line VCL2 in the second direction (or Y-axis direction) and may overlap the second power line VDDL in the third direction (or Z-axis direction). The second power line VDDL may overlap the second vertical connection line VCL2. One of the fifth dummy patterns DM5 may be positioned above the first sub-connection line HCL1, and another of the fifth dummy patterns DM5 may be positioned below the first sub-connection line HCL1. The sixth dummy pattern DM6 may be spaced apart from the third vertical connection line VCL3 in the second direction (or Y-axis direction) and may overlap the second power line VDDL in the third direction (or Z-axis direction). The second power line VDDL may overlap the third vertical connection line VCL3. One of the sixth dummy patterns DM6 may be disposed on an upper side of the first sub-connection line HCL1, another of the sixth dummy patterns DM6 may be disposed between the first sub-connection line HCL1 and the second horizontal connection line HCL2, and still another of the sixth dummy patterns DM6 may be disposed on a lower side of the second horizontal connection line HCL2.

[0219] The seventh dummy pattern DM7 may overlap with one of the first power lines VIL. One of the seventh dummy patterns DM7 may be disposed to the left of the second sub-connection line VCL1, another of the seventh dummy patterns DM7 may be disposed between the second sub-connection line VCL1 and the second vertical connection line VCL2, yet another of the seventh dummy patterns DM7 may be disposed between the second vertical connection line VCL2 and the third vertical connection line VCL3, and yet another of the seventh dummy patterns DM7 may be disposed to the right of the third vertical connection line VCL3. The eighth dummy pattern DM8 may overlap with the first power line VIL below (or directly below) the first power line VIL, and the first power line VIL may overlap with the seventh dummy pattern DM7. One of the eighth dummy patterns DM8 may be positioned to the left of the second sub-connection line VCL1, another of the eighth dummy patterns DM8 may be positioned between the second sub-connection line VCL1 and the second vertical connection line VCL2, yet another of the eighth dummy patterns DM8 may be positioned between the second vertical connection line VCL2 and the third vertical connection line VCL3, and yet another of the eighth dummy patterns DM8 may be positioned to the right of the third vertical connection line VCL3. The ninth dummy pattern DM9 may overlap the first power line VIL below (or directly below) the first power line VIL, and the first power line VIL may overlap the eighth dummy pattern DM8. One of the ninth dummy patterns DM9 may be positioned to the left of the second sub-connection line VCL1, another of the ninth dummy patterns DM9 may be positioned between the second sub-connection line VCL1 and the second vertical connection line VCL2, yet another of the ninth dummy patterns DM9 may be positioned between the second vertical connection line VCL2 and the third vertical connection line VCL3, and yet another of the ninth dummy patterns DM9 may be positioned to the right of the third vertical connection line VCL3.

[0220] The first dummy pattern DM1, the second dummy pattern DM2, the third dummy pattern DM3, the fourth dummy pattern DM4, the fifth dummy pattern DM5, the sixth dummy pattern DM6, the seventh dummy pattern DM7, the eighth dummy pattern DM8, and the ninth dummy pattern DM9 may be formed as islands and may be electrically floating. That is, no specific voltage may be applied to the first dummy pattern DM1, the second dummy pattern DM2, the third dummy pattern DM3, the fourth dummy pattern DM4, the fifth dummy pattern DM5, the sixth dummy pattern DM6, the seventh dummy pattern DM7, the eighth dummy pattern DM8, and the ninth dummy pattern DM9.

[0221] In a case where the first dummy pattern DM1, the second dummy pattern DM2, the third dummy pattern DM3, the fourth dummy pattern DM4, the fifth dummy pattern DM5, the sixth dummy pattern DM6, the seventh dummy pattern DM7, the eighth dummy pattern DM8 and the ninth dummy pattern DM9 may not be formed, the amount of external light reflected in the area where the first connection line CL1, the second connection line CL2 and the third connection line CL3 may be set is different from the amount of external light reflected in the area where the first connection line CL1, the second connection line CL2 and the third connection line CL3 may not be set, and therefore, the connection lines CL1, CL2 and CL3 may be visible to the user. However, if the first dummy pattern DM1, the second dummy pattern DM2, the third dummy pattern DM3, the fourth dummy pattern DM4, the fifth dummy pattern DM5, the sixth dummy pattern DM6, the seventh dummy pattern DM7, the eighth dummy pattern DM8 and the ninth dummy pattern DM9 can be set in an area where the first connection line CL1, the second connection line CL2 and the third connection line CL3 can be not set, then because the amount of external light reflected in the area where the first connection line CL1, the second connection line CL2 and the third connection line CL3 can be set is not significantly different from the amount of external light reflected in the area where the first connection line CL1, the second connection line CL2 and the third connection line CL3 can be not set, the first connection line CL1, the second connection line CL2 and the third connection line CL3 can be prevented from becoming visible to the user.

[0222] according to Figure 16 and Figure 17 In an embodiment of the present invention, the first connection line CL1, the second connection line CL2, and the third connection line CL3 can be connected to the first data line DL1, the second data line DL2, and the third data line DL3 through the first connection hole CT1', the second connection hole CT2', and the third connection hole CT3', respectively. Therefore, the first data line DL1, the second data line DL2, and the third data line DL3 extending in the second direction (or the Y-axis direction) can receive data voltages from the display driver 200 via the horizontal connection lines HCL1, HCL2, and HCL3 extending in the first direction (or the X-axis direction) and the vertical connection lines VCL1, VCL2, and VCL3 extending in the second direction (or the Y-axis direction).

[0223] Figure 18 is shown with Figure 16 An enlarged plan view of a sub-pixel where a first data line, a first sub-connection line, and a second sub-connection line overlap. Figure 19 is shown with Figure 17 An enlarged plan view of a sub-pixel where a first data line and a second sub-connection line overlap.

[0224] exist Figure 18 and Figure 19In the embodiment of FIG. 5 , the first connection line CL1 includes a first sub-connection line HCL1 and a second sub-connection line VCL1 .

[0225] Reference Figure 18 and Figure 19 , the first sub-connection line HCL1 may overlap with the first power line VIL in the third direction (or Z-axis direction). The first sub-connection line HCL1 may overlap with the second electrode D1-1 of the (1-1)th transistor ST1-1 and the first electrode S1-2 of the (1-2)th transistor ST1-2. The first sub-connection line HCL1 may overlap with the second connection electrode VIE and the second electrode D5 of the fifth transistor ST5. The first sub-connection line HCL1 may overlap with the fifth contact hole CNT5. The first power line VIL may be provided between the first sub-connection line HCL1 and the second electrode D1-1 of the (1-1)th transistor ST1-1, between the first sub-connection line HCL1 and the first electrode S1-2 of the (1-2)th transistor ST1-2, and between the first sub-connection line HCL1 and the second electrode D5 of the fifth transistor ST5. Due to the presence of the first power supply line VIL, coupling can be prevented from occurring between the first sub-connection line HCL1 and the second electrode D1-1 of the (1-1)th transistor ST1-1, between the first sub-connection line HCL1 and the first electrode S1-2 of the (1-2)th transistor ST1-2, and between the first sub-connection line HCL1 and the second electrode D5 of the fifth transistor ST5. Therefore, the influence of the first sub-connection line HCL1 on the second electrode D1-1 of the (1-1)th transistor ST1-1, the first electrode S1-2 of the (1-2)th transistor ST1-2, and the second electrode D5 of the fifth transistor ST5 can be reduced or minimized.

[0226] The second sub-connection line VCL1 may overlap with the second power line VDDL in the third direction (or Z-axis direction). The second sub-connection line VCL1 may overlap with the active layer ACT1-1, gate electrode G1-1, and first electrode S1-1 of the (1-1)th transistor ST1-1, the active layer ACT2, gate electrode G2, first electrode S2, and second electrode D2 of the second transistor ST2, and the active layer ACT4, gate electrode G4, first electrode S4, and second electrode D4 of the fourth transistor ST4. The second power line VDDL may be provided between the second sub-connection line VCL1 and the (1-1)th transistor ST1-1, between the second sub-connection line VCL1 and the second transistor ST2, and between the second sub-connection line VCL1 and the fourth transistor ST4. Due to the presence of the second power line VDDL, coupling can be prevented between the second sub-connection line VCL1 and the (1-1)th transistor ST1-1, between the second sub-connection line VCL1 and the second transistor ST2, and between the second sub-connection line VCL1 and the fourth transistor ST4. Therefore, the influence of the second sub-connection line VCL1 on the active layer ACT1-1, gate electrode G1-1 and first electrode S1-1 of the (1-1) transistor ST1-1, the active layer ACT2, gate electrode G2, first electrode S2 and second electrode D2 of the second transistor ST2, and the active layer ACT4, gate electrode G4, first electrode S4 and second electrode D4 of the fourth transistor ST4 can be reduced or minimized.

[0227] Figure 20 and Figure 21 According to the embodiment, Figure 18 Line III-III' and Figure 19 A cross-sectional view taken along line IV-IV'.

[0228] exist Figure 20 and Figure 21 In the embodiment of FIG. 5 , the first connection line CL1 includes a first sub-connection line HCL1 and a second sub-connection line VCL1 .

[0229] Reference Figure 20 and Figure 21 The first and second sub-connection lines HCL1 and VCL1 may be formed of the second source metal layer DTL2. The first connection hole CT1' may be a hole exposing the first data line DL1 through the first planarization film 160. The second sub-connection line VCL1 may be connected to the first data line DL1 via the first connection hole CT1'.

[0230] Figure 22 and Figure 23 According to the embodiment, Figure 18 Line III-III' and Figure 19 A cross-sectional view taken along line IV-IV'.

[0231] exist Figure 22 and Figure 23 In the embodiment of FIG. 5 , the first connection line CL1 includes a first sub-connection line HCL1 and a second sub-connection line VCL1 .

[0232] Reference Figure 22 and Figure 23 The first and second sub-connection lines HCL1 and VCL1 may be formed from the third source metal layer DTL3. The second power line VDDL may be formed from the second source metal layer DTL2. The first connection hole CT1' may be a hole that exposes the first data line DL1 through the first and second planarization films 160 and 180. The second sub-connection line VCL1 may be connected to the first data line DL1 via the first connection hole CT1'.

[0233] Figure 24 is a plan view illustrating a display panel, a display driver, and a scan driver of a display device according to another embodiment.

[0234] exist Figure 24 In an embodiment, the data lines may be arranged in pairs such that each sub-pixel overlaps with a pair of data lines DLO and DLE, and the display device 10 further includes a demultiplexer 410 .

[0235] Reference Figure 24 , the odd data lines DLO and the even data lines DLE can be connected to the connection lines CL via the connection holes CT. The odd data lines DLO and the even data lines DLE can extend in the second direction (or Y-axis direction). The odd data lines DLO can be arranged to be adjacent to their respective even data lines DLE in the first direction (or X-axis direction). For example, the first odd data line and the first even data line can be arranged to be adjacent to each other in the first direction (or X-axis direction), and the second odd data line and the second even data line can be arranged to be adjacent to each other in the first direction (or X-axis direction). The distance between the first odd data line and the first even data line in the first direction (or X-axis direction) can be smaller than the distance between the first even data line and the second odd data line in the first direction (or X-axis direction).

[0236] The scan driver 400 may be disposed in a portion of the non-display area NDA located on the outer left side of the display area DA. The demultiplexer 410 may be disposed in a portion of the non-display area NDA located on the outer right side of the display area DA. The area of ​​the demultiplexer 410 may be smaller than that of the scan driver 400. Therefore, the length of the demultiplexer 410 in the second direction (or Y-axis direction) may be smaller than the length of the scan driver 400 in the second direction (or Y-axis direction).

[0237] The demultiplexer 410 can distribute the data voltage applied to each fan-out line FL among the connection lines CL. The number of fan-out lines FL connected to the demultiplexer 410 can be smaller than the number of connection lines CL connected to the demultiplexer 410. Because the number of fan-out lines FL provided in the pad area PA can be reduced by half or more, the distance between the fan-out lines FL can be widened. In other words, the complexity of the wiring in the pad area PA can be reduced.

[0238] The third fan-out line FL3 may be provided in a portion of the non-display area NDA located at the outer right side of the display area DA. In the portion of the non-display area NDA located at the outer right side of the display area DA, the third fan-out line FL3 may be connected to the second fan-out line FL2 via a second wiring connection hole FCT2.

[0239] Figure 25 It shows Figure 24 Specifically, Figure 25 Sub-pixels overlapping the first odd data line DLO1 , the first even data line DLE1 , and the first connection line CL1 are shown.

[0240] Reference Figure 25 The second power line VDDL may be formed from the first source metal layer DTL1, the first odd data line DLO1 and the first even data line DLE1 may be formed from the second source metal layer DTL2, and the first connection line CL1 may be formed from the third source metal layer DTL3. The first connection line CL1 may be connected to one of the first odd data line DLO1 and the first even data line DLE1. The first connection line CL1, the first odd data line DLO1, and the first even data line DLE1 may overlap with the second power line VDDL.

[0241] The second power line VDDL may be provided between the first connection line CL1 and the driving transistor DT, between the first connection line CL1 and the sixth transistor ST6, between the first odd data line DLO1 and the driving transistor DT, and between the first even data line DLE2 and the sixth transistor ST6. Due to the presence of the second power line VDDL, the first connection line CL1, the first odd data line DLO1, and the first even data line DLE1 may overlap with the second power line VDDL. The second power line VDDL may prevent coupling between the first connection line CL1 and the driving transistor DT, between the first connection line CL1 and the sixth transistor ST6, between the first odd data line DLO1 and the driving transistor DT, and between the first even data line DLE2 and the sixth transistor ST6.

[0242] Figure 26 It shows Figure 24 A cross-sectional view of another embodiment of a sub-pixel. Specifically, Figure 26 Sub-pixels overlapping the first odd data line DLO1 , the first even data line DLE1 , and the first connection line CL1 are shown.

[0243] exist Figure 26 In an embodiment, the first odd data line DLO1 and the first even data line DLE1 may be formed of the first source metal layer DTL1, and the second power line VDDL may be formed of the second source metal layer DTL2.

[0244] Figure 27 It shows Figure 24 A cross-sectional view of another embodiment of a sub-pixel. Specifically, Figure 27 Sub-pixels overlapping the first odd data line DLO1 , the first even data line DLE1 , and the first connection line CL1 are shown.

[0245] exist Figure 27 In an embodiment, the first connection line CL1 may be formed of the second source metal layer DTL2, and the first odd data line DLO1 and the first even data line DLE1 may be formed of the third source metal layer DTL3.

[0246] Figure 28 It shows Figure 24 A cross-sectional view of another embodiment of a sub-pixel. Specifically, Figure 28 Sub-pixels overlapping the first odd data line DLO1 , the first even data line DLE1 , and the first connection line CL1 are shown.

[0247] exist Figure 28 In an embodiment, the first connection line CL1 may be formed of a first source metal layer DTL1, the second power line VDDL may be formed of a second source metal layer DTL2, and the first odd data line DLO1 and the first even data line DLE1 may be formed of a third source metal layer DTL3.

[0248] Figure 29 is a plan view illustrating a display panel, a display driver, and a scan driver of a display device according to another embodiment.

[0249] exist Figure 29 In an embodiment, the data lines may be arranged in pairs such that each sub-pixel overlaps with a pair of data lines DLO and DLE, and the display device 10 further includes a demultiplexer 410 .

[0250] Reference Figure 29, the odd data lines DLO and the even data lines DLE can be connected to the vertical connection line VCL via the connection hole CT'. The odd data lines DLO and the even data lines DLE can extend in the second direction (or Y-axis direction). The odd data lines DLO can be arranged to be adjacent to their respective even data lines DLE in the first direction (or X-axis direction). For example, the first odd data line and the first even data line can be arranged to be adjacent to each other in the first direction (or X-axis direction), and the second odd data line and the second even data line can be arranged to be adjacent to each other in the first direction (or X-axis direction). The distance between the first odd data line and the first even data line in the first direction (or X-axis direction) can be smaller than the distance between the first even data line and the second odd data line in the first direction (or X-axis direction).

[0251] The scan driver 400 may be disposed in a portion of the non-display area NDA located on the outer left side of the display area DA. The demultiplexer 410 may be disposed in a portion of the non-display area NDA located on the outer right side of the display area DA. The area of ​​the demultiplexer 410 may be smaller than that of the scan driver 400. Therefore, the length of the demultiplexer 410 in the second direction (or Y-axis direction) may be smaller than the length of the scan driver 400 in the second direction (or Y-axis direction).

[0252] The demultiplexer 410 can distribute the data voltage applied to each fan-out line FL among the connection lines CL. The number of fan-out lines FL connected to the demultiplexer 410 can be smaller than the number of connection lines CL connected to the demultiplexer 410. Because the number of fan-out lines FL provided in the pad area PA can be reduced by half or more, the distance between the fan-out lines FL can be widened. In other words, the complexity of the wiring in the pad area PA can be reduced.

[0253] The third fan-out line FL3 may be provided in a portion of the non-display area NDA located at the outer right side of the display area DA. In the portion of the non-display area NDA located at the outer right side of the display area DA, the third fan-out line FL3 may be connected to the second fan-out line FL2 via a second wiring connection hole FCT2.

[0254] As mentioned above Figures 25 to 28 As described, the connection line CL, the odd data line DLO, and the even data line DLE may be disposed in two of the first source metal layer DTL1, the second source metal layer DTL2, and the third source metal layer DTL3.

[0255] Figure 30 is a perspective view of a display device according to another embodiment. Figure 31 is a developed view of a display device according to another embodiment.

[0256] exist Figure 30 and Figure 31 In the embodiment of FIG. 5 , the display device 10 includes a plane portion PS and four side portions, ie, a first side portion SS1 , a second side portion SS2 , a third side portion SS3 , and a fourth side portion SS4 .

[0257] Reference Figure 30 and Figure 31 The display panel 100 may include a plane portion PS, a first side portion SS1, a second side portion SS2, a third side portion SS3, and a fourth side portion SS4, a first edge portion ES1, a second edge portion ES2, a third edge portion ES3, and a fourth edge portion ES4, and a first corner portion CS1, a second corner portion CS2, a third corner portion CS3, and a fourth corner portion CS4.

[0258] The planar portion PS may be a flat surface that is not curved. The planar portion PS may be a rectangular surface having a pair of short sides extending in a first direction (or the X-axis direction) and a pair of long sides extending in a second direction (or the Y-axis direction). The corners where the short and long sides of the planar portion PS intersect may be rounded to have a predetermined curvature. The planar portion PS may be the top surface of the display panel 100.

[0259] The first edge portion ES1 may extend from a first side of the planar portion PS. The first edge portion ES1 may extend from a left side of the planar portion PS. The first edge portion ES1 may be disposed between the planar portion PS and the first side portion SS1. The first edge portion ES1 may be a surface curved with a predetermined curvature between the first bending line BL1 and the fifth bending line BL5. The first bending line BL1 may be a boundary between the planar portion PS and the first edge portion ES1, and the fifth bending line BL5 may be a boundary between the first side portion SS1 and the first edge portion ES1.

[0260] The first side portion SS1 may extend from the first side of the first edge portion ES1. The first side portion SS1 may be the left side of the display panel 100. The first side portion SS1 may be a rectangular surface having a pair of short sides extending in the third direction (or Z-axis direction) and a pair of long sides extending in the second direction (or Y-axis direction).

[0261] The second edge portion ES2 may extend from the second side of the planar portion PS. The second edge portion ES2 may extend from the left side of the planar portion PS. The second edge portion ES2 may be disposed between the planar portion PS and the second side portion SS2. The second edge portion ES2 may be a surface curved with a predetermined curvature between the second bending line BL2 and the sixth bending line BL6. The second bending line BL2 may be a boundary between the planar portion PS and the second edge portion ES2, and the sixth bending line BL6 may be a boundary between the second side portion SS2 and the second edge portion ES2.

[0262] The second side portion SS2 may extend from the first side of the second edge portion ES2. The second side portion SS2 may be the lower side of the display panel 100. The second side portion SS2 may be a rectangular surface having a pair of short sides extending in the third direction (or Z-axis direction) and a pair of long sides extending in the first direction (or X-axis direction).

[0263] The third edge portion ES3 may extend from the third side of the plane portion PS. The third edge portion ES3 may extend from the upper side of the plane portion PS. The third edge portion ES3 may be disposed between the plane portion PS and the third side portion SS3. The third edge portion ES3 may be a surface curved with a predetermined curvature between the third bending line BL3 and the seventh bending line BL7. The third bending line BL3 may be a boundary between the plane portion PS and the third edge portion ES3, and the seventh bending line BL7 may be a boundary between the third side portion SS3 and the third edge portion ES3.

[0264] The third side portion SS3 may extend from the first side of the third edge portion ES3. The third side portion SS3 may be an upper side of the display panel 100. The third side portion SS3 may be a rectangular surface having a pair of short sides extending in the third direction (or Z-axis direction) and a pair of long sides extending in the first direction (or X-axis direction).

[0265] The fourth edge portion ES4 may extend from the fourth side of the plane portion PS. The fourth edge portion ES4 may extend from the right side of the plane portion PS. The fourth edge portion ES4 may be disposed between the plane portion PS and the fourth side portion SS4. The fourth edge portion ES4 may be a surface curved with a predetermined curvature between the fourth bending line BL4 and the eighth bending line BL8. The fourth bending line BL4 may be a boundary between the plane portion PS and the fourth edge portion ES4, and the eighth bending line BL8 may be a boundary between the fourth side portion SS4 and the fourth edge portion ES4.

[0266] The fourth side portion SS4 may extend from the first side of the fourth edge portion ES4. The fourth side portion SS4 may be an upper side of the display panel 100. The fourth side portion SS4 may be a rectangular surface having a pair of short sides extending in the third direction (or Z-axis direction) and a pair of long sides extending in the second direction (or Y-axis direction).

[0267] The first corner portion CS1 may be disposed between the first edge portion ES1 and the second edge portion ES2. Because the first corner portion CS1 may not be disposed between the first side portion SS1 and the second side portion SS2, an empty space may be provided between the first side portion SS1 and the second side portion SS2. The width of the first corner portion CS1 may be smaller than the width of the first edge portion ES1 and the width of the second edge portion ES2. Therefore, as viewed from above the plane portion PS, a first dead space may be disposed outside the first corner portion CS1. The first dead space may be defined as an empty space in the region between the first edge portion ES1 and the second edge portion ES2, where the first corner portion CS1 may not be disposed.

[0268] The second corner portion CS2 may be disposed between the first edge portion ES1 and the third edge portion ES3. Because the second corner portion CS2 may not be disposed between the first side portion SS1 and the third side portion SS3, an empty space may be provided between the first side portion SS1 and the third side portion SS3. The width of the second corner portion CS2 may be smaller than the width of the first edge portion ES1 and the width of the third edge portion ES3. Therefore, as viewed from above the planar portion PS, a second dead zone may be provided outside the second corner portion CS2. The second dead zone may be defined as an empty space provided in the region between the first edge portion ES1 and the third edge portion ES3, where the second corner portion CS2 may not be provided.

[0269] The third corner CS3 may be disposed between the second edge portion ES2 and the fourth edge portion ES4. Because the third corner CS3 may not be disposed between the second side portion SS2 and the fourth side portion SS4, an empty space may be provided between the second side portion SS2 and the fourth side portion SS4. The width of the third corner CS3 may be smaller than the width of the second edge portion ES2 and the width of the fourth edge portion ES4. Therefore, as viewed from above the planar portion PS, a third dead zone may be disposed outside the third corner CS3. The third dead zone may be defined as an empty space provided in the region between the second edge portion ES2 and the fourth edge portion ES4, where the third corner CS3 may not be provided.

[0270] The fourth corner portion CS4 may be disposed between the third edge portion ES3 and the fourth edge portion ES4. Since the fourth corner portion CS4 may not be disposed between the third side portion SS3 and the fourth side portion SS4, an empty space may be provided between the third side portion SS3 and the fourth side portion SS4. The width of the fourth corner portion CS4 may be smaller than the width of the third edge portion ES3 and the width of the fourth edge portion ES4. Therefore, as viewed from above the plane portion PS, the fourth dead zone DS4 may be disposed outside the fourth corner portion CS4. The fourth dead zone DS4 may be defined as an empty space provided in the region between the third edge portion ES3 and the fourth edge portion ES4, wherein the fourth corner portion CS4 may not be provided.

[0271] A first intersection point CP1 between the first bending line BL1 and the second bending line BL2 may overlap with the first corner CS1. A second intersection point CP2 between the first bending line BL1 and the seventh bending line BL7 may overlap with the second corner CS2. A third intersection point CP3 between the second bending line BL2 and the fourth bending line BL4 may overlap with the third corner CS3. A fourth intersection point CP4 between the fourth bending line BL4 and the seventh bending line BL7 may overlap with the fourth corner CS4.

[0272] The display area DA may be provided in the plane portion PS, the first side portion SS1, the second side portion SS2, the third side portion SS3, and the fourth side portion SS4, the first edge portion ES1, the second edge portion ES2, the third edge portion ES3, and the fourth edge portion ES4, and the first corner portion CS1, the second corner portion CS2, the third corner portion CS3, and the fourth corner portion CS4. The non-display area NDA may occupy an area located at the periphery of the first side portion SS1, the second side portion SS2, the third side portion SS3, and the fourth side portion SS4, the first edge portion ES1, the second edge portion ES2, the third edge portion ES3, and the fourth edge portion ES4, and the first corner portion CS1, the second corner CS2, the third corner CS3, and the fourth corner CS4.

[0273] The pad area PA is shown as protruding from the right side of the fourth side portion SS4, but the embodiment is not limited thereto. In other embodiments, the pad area PA may protrude from the left side of the first side portion SS1.

[0274] Although exemplary embodiments have been described above, it is not intended that these embodiments describe all possible forms thereof. Rather, the words used in the specification are descriptive rather than restrictive, and it should be understood that various changes may be made without departing from the spirit and scope of the present disclosure. The features of the various embodiments may be combined to form further embodiments.

Claims

1. A display device, wherein: The display device includes: The display panel includes a display area, a non-display area provided at a periphery of the display area, and a pad area provided at a side of the non-display area; a data line arranged in the display area of ​​the display panel along a second direction intersecting the first direction; a connecting line, arranged in the display area of ​​the display panel along the first direction; and a first power line, arranged in the display area of ​​the display panel along the first direction and receiving a first power voltage; wherein a first data line among the data lines is connected to a first connection line among the connection lines via a first connection hole located in the display area, and the first connection line overlaps with the first power line; Wherein, the first connection hole is provided in an overlapping area of ​​the first data line and the first power line. The pad area protrudes from the long side of the display panel in a direction parallel to the short side of the display panel.

2. The display device according to claim 1, wherein The pad area protrudes from the non-display area in the first direction.

3. The display device according to claim 1, wherein A length of the display panel in the first direction is smaller than a length of the display panel in the second direction.

4. The display device according to claim 1, wherein The first connection hole penetrates at least one insulating film disposed between the first connection line and the first data line.

5. The display device according to claim 1, wherein The display device further includes: a scan line, arranged in the display area of ​​the display panel along the first direction; a first gate metal layer, comprising the scan line; a first source metal layer disposed on the first gate metal layer, wherein the first source metal layer includes the first data line; and The second gate metal layer is disposed between the first gate metal layer and the first source metal layer, and the second gate metal layer includes the first power line. The display device according to claim 5 , wherein: The display device further includes a second source metal layer disposed on the first source metal layer, and the second source metal layer includes the first connection line.

7. The display device according to claim 5, wherein: The display device further includes: The second power line is arranged in the display area of ​​the display panel along the second direction and receives a second power voltage higher than the first power voltage.

8. The display device according to claim 7, wherein: The first source metal layer includes the second power line.

9. The display device according to claim 7, wherein: The display device further includes: The third source metal layer is provided on the second source metal layer, wherein: The third source metal layer includes the first connecting line, and The second source metal layer is disposed on the first source metal layer and includes the second power line.

10. The display device according to claim 5, wherein The display device further includes: A scan driver is connected to the scan lines.

11. The display device according to claim 10, wherein: The scan driver is disposed in a portion of the non-display area at a first outer side of the display area.

12. The display device according to claim 10, wherein: The scanning driver comprises: a first scan driver provided in a portion of the non-display area located at a first outer side of the display area and connected to the odd-numbered scan lines; and A second scan driver is provided in a portion of the non-display area located at a second outer side of the display area and connected to the even-numbered scan lines.

13. The display device according to claim 10, wherein: The display device further includes: a fan-out line disposed in the pad region of the display panel and connected to the connection line; and A display driver is disposed in the pad region of the display panel and connected to the fan-out line.

14. The display device according to claim 13, wherein: The pad area includes: curved areas; and a first sub-pad region, wherein the display driver is disposed in the first sub-pad region, and The fan-out line is disposed in one of the first gate metal layer and the second gate metal layer located in the first sub-pad region.

15. The display device according to claim 14, wherein The fan-out line is provided in one of the first source metal layer and the second source metal layer located in the bending region, and The second source metal layer is disposed on the first source metal layer.

16. The display device according to claim 13, wherein The scan driver is disposed in the pad region of the display panel.

17. The display device according to claim 16, wherein: The pad area includes: bending area; a first sub-pad region, wherein the display driver is disposed in the first sub-pad region; and The second sub-pad region is disposed between the bending region and the first sub-pad region, and the second sub-pad region includes the scan driver.

18. The display device according to claim 17, wherein: The fan-out lines are set at: in one of the first gate metal layer and the second gate metal layer in the first sub-pad region; provided in a second source metal layer on the first source metal layer in the second sub-pad region; as well as In one of the first source metal layer and the second source metal layer in the bending region.

19. The display device according to claim 1, wherein The first connecting line includes: a first sub-connection line, arranged along the first direction; and The second sub-connection line is arranged along the second direction, Wherein, the second sub-connection line is connected to the first data line.

20. The display device according to claim 13, wherein The display device further includes: A demultiplexer is connected between the connection line and the fan-out line.

21. The display device according to claim 20, wherein The number of the connection lines is greater than the number of the fan-out lines.

22. The display device according to claim 20, wherein The display device further includes: a second power line, arranged in the display area of ​​the display panel along the second direction and receiving a second power voltage higher than the first power voltage; a second source metal layer disposed on the first source metal layer, wherein the second source metal layer includes the second power line; and The third source metal layer is disposed on the second source metal layer, and the third source metal layer includes the first connecting line.

23. A display device, wherein: The display device includes: The display panel includes a display area, a non-display area provided at a periphery of the display area, and a pad area provided at a side of the non-display area; a data line arranged in the display area of ​​the display panel along a second direction intersecting the first direction; a first connection line disposed in the display area of ​​the display panel and including a first sub-connection line disposed along the first direction and a second sub-connection line disposed along the second direction; and a first power line, arranged in the display area of ​​the display panel along the first direction and receiving a first power voltage; wherein a first data line among the data lines is connected to the second sub-connection line via a first connection hole located in the non-display area, and the first sub-connection line overlaps with the first power line; The pad area protrudes from the long side of the display panel in a direction parallel to the short side of the display panel.

24. The display device according to claim 23, wherein The pad area protrudes from the non-display area in the first direction.

25. The display device according to claim 23, wherein A length of the display panel in the first direction is smaller than a length of the display panel in the second direction.

26. The display device according to claim 23, wherein In the non-display area, the first data line is connected to the second sub-link line.

27. The display device according to claim 26, wherein: The first connection hole penetrates at least one insulating film disposed between the second sub-connection line and the first data line.

28. The display device according to claim 23, wherein The display device further includes: a second power line disposed in the display area of ​​the display panel along the second direction and receiving a second power voltage higher than the first power voltage; Wherein, the second sub-connection line overlaps with the second power line.

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