Battery management system fault processing method, AFE chip and battery management system

Abstract

The application provides a battery management system fault processing method, an AFE chip and a battery management system, and relates to the field of circuit devices or systems for power supply or power distribution. The battery management system fault processing method provided by the application comprises the following steps: when the battery management system is in a low-power consumption mode, an abnormal signal is received by a bridge chip, and a microcontroller unit is woken up; the bridge chip wakes up an AFE chip; each AFE chip detects its own state, generates its own state signal in combination with the state signal of the previous AFE chip, and sends the state signal to the next AFE chip; it is determined that a single-point disconnection occurs, and the topology structure is divided into two parts by the single-point disconnection; the address of each AFE chip, the state signal transmission direction and whether the state signal of other AFE chips needs to be waited for are re-determined. The method provided by the application can still perform regular autonomous diagnosis in the low-power consumption mode after a single-point disconnection fault occurs, and the microcontroller unit can be woken up in time for processing when the fault occurs.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of power supply or power distribution circuit devices or systems, in particular to a battery management system fault processing method, an AFE chip and a battery management system. BACKGROUND

[0002] Abnormal conditions such as overcharge, overdischarge, overheating of the battery are extremely easy to cause thermal runaway and even explosion, which puts strict requirements on the real-time monitoring and protection capability of the battery management system (BMS). As the core component of the BMS, the analog front-end chip (AFE) bears the functions of collecting and diagnosing key parameters such as battery voltage, temperature and current, and its reliability directly affects the safety of the entire system.

[0003] In low-power application scenarios (such as new energy vehicles), the BMS is often in sleep mode to reduce power consumption. However, during sleep, the battery may enter an abnormal state due to self-discharge, changes in ambient temperature or internal short circuit, etc. If the system cannot be awakened in time for intervention, irreversible damage or safety accidents will occur. In addition, the AFE chip itself may experience hardware aging or transient faults (such as register flip, clock drift) due to long-term operation, and its functional integrity needs to be ensured through regular diagnosis. SUMMARY

[0004] To solve the problems in the prior art, the present application provides a battery management system fault processing method, the battery management system comprising a plurality of AFE chips in a topological structure electrically connected through a bridge chip at the head and tail, and a microcontroller unit electrically connected with the bridge chip, characterized in that the method comprises: when the microcontroller unit in the battery management system is in a shutdown mode, the bridge chip is in a sleep mode or a shutdown mode, and the plurality of AFE chips are in a sleep mode, the bridge chip wakes up the microcontroller unit when receiving an abnormal signal from the last AFE chip in the topological structure; the bridge chip sends a wake-up command to the AFE chips in the topological structure; each AFE chip in the topological structure is configured to detect its own state, and to generate its own state signal in combination with the state signal received from the previous AFE chip and send it to the next AFE chip; when only one AFE chip in the topological structure does not receive a normal signal or an abnormal signal, it is determined that a single-point disconnection occurs between the AFE chip and its previous AFE chip, and the topological structure is divided into a first topological structure and a second topological structure by the single-point disconnection; according to the number of AFE chips in the first topological structure and the second topological structure and the positions of the AFE chips, the addresses of the AFE chips, the transmission directions of the state signals and whether the AFE chips need to wait for the state signals of other AFE chips to generate their own state signals are re-determined.

[0005] In particular, the battery management system fault processing method provided in the application sends a normal signal to the next AFE chip when the AFE chip itself is not faulty and a normal signal from the previous AFE chip is received; sends an abnormal signal to the next AFE chip when the AFE chip itself is not faulty and an abnormal signal from the previous AFE chip is received; sends an abnormal signal to the next AFE chip when the AFE chip itself is faulty and a normal signal from the previous AFE chip is received; sends an abnormal signal to the next AFE chip when the AFE chip itself is faulty and an abnormal signal from the previous AFE chip is received; and sends an abnormal signal to the next AFE chip when the AFE chip does not receive a normal signal or an abnormal signal from the previous AFE chip.

[0006] In particular, the battery management system fault processing method provided in the application determines that there is no disconnection fault in the topology structure but a first type of fault of the AFE chip when all the AFE chips in the topology structure except the AFE chip that does not need to wait for a state signal from another AFE chip receive a state signal from the previous AFE chip.

[0007] In particular, the battery management system fault processing method provided in the application determines that a multi-point disconnection fault occurs in the topology structure when two or more AFE chips in the topology structure do not receive a normal signal or an abnormal signal.

[0008] In particular, the battery management system fault processing method provided in the application detects the state of the previous AFE chip of the AFE chip that does not receive a normal signal or an abnormal signal to determine whether the previous AFE chip itself has a second type of fault when only one AFE chip in the topology structure does not receive a normal signal or an abnormal signal.

[0009] The application further provides an AFE chip, characterized in that it comprises: a normal signal register configured to set a value stored therein as valid when a normal signal from a previous AFE chip is received; an abnormal signal register configured to set a value stored therein as valid when an abnormal signal from the previous AFE chip is received; a direction register in which a value stored therein represents a propagation direction of a state signal; a waiting register in which a value stored therein represents whether the AFE chip needs to wait for a state signal from the previous AFE chip to generate a state signal of the AFE chip; and a disconnection register configured to set a value stored therein as valid when a state signal from the previous AFE chip is not received within a specified time.

[0010] In particular, the AFE chip provided in the application further comprises an address register configured to store an address of the AFE chip.

[0011] In particular, the AFE chip proposed in the present application further comprises a top register configured to mark whether the AFE chip is the top of the topology structure in which the AFE chip is located.

[0012] The present application further proposes a battery management system comprising a plurality of AFE chips connected in a topology structure through a bridge chip, and a microcontroller unit electrically connected with the bridge chip, characterized in that when the microcontroller unit in the battery management system is in a shutdown mode, the bridge chip is in a sleep mode or a shutdown mode, and the plurality of AFE chips are in a sleep mode, the bridge chip is configured to receive a state signal from the last AFE chip in the topology structure, and when the state signal is an abnormal signal, the bridge chip is configured to wake up the microcontroller unit; and configured to send a wake-up command to the AFE chips in the topology structure in two directions respectively; each AFE chip in the topology structure is configured to detect its own state and receive a state signal from the previous AFE chip, to generate its own state signal and send it to the next AFE chip; the microcontroller unit is configured to read the register values of each AFE chip in the topology structure to determine whether a single-point disconnection occurs between the AFE chip and its previous AFE chip; when a single-point disconnection occurs, the topology structure is divided into a first topology structure and a second topology structure by the single-point disconnection, and the values of the registers of the AFE chips in the first topology structure and the second topology structure are reset.

[0013] In particular, the battery management system proposed in the present application, the AFE chip comprises a normal signal register configured to set the value stored therein as valid when a normal signal from the previous AFE chip is received; an abnormal signal register configured to set the value stored therein as valid when an abnormal signal from the previous AFE chip is received; a direction register in which the value stored therein represents the propagation direction of the state signal; a waiting register in which the value stored therein represents whether the AFE chip needs to wait for the state signal from the previous AFE chip to generate the state signal of the AFE chip; and a disconnection register configured to set the value stored therein as valid when the state signal from the previous AFE chip is not received within a specified time.

[0014] In particular, the battery management system proposed in the present application, the microcontroller unit reads the values of the normal signal register, the abnormal signal register and the disconnection register of each AFE chip in the topology structure to determine whether a single-point disconnection occurs.

[0015] In particular, the battery management system proposed in the present application, the microcontroller unit resets the values of the direction register and the waiting register of the AFE chips in the first topology structure and the second topology structure.

[0016] The application further provides an electronic device comprising the battery management system.

[0017] The method, AFE chip, battery management system and electronic device provided by the application can perform periodic autonomous diagnosis in a low-power mode after a single-point disconnection fault occurs, and can wake up a microcontroller unit in time to perform processing when a new fault occurs. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a state diagram of a battery management system according to an embodiment of the application when no fault occurs;

[0019] Figure 2 is a state diagram of a battery management system according to an embodiment of the application after a single-point disconnection fault occurs and after configuration;

[0020] Figure 3 is a state diagram of a battery management system according to an embodiment of the application after a single-point disconnection fault occurs and without configuration;

[0021] Figure 4 is a configuration flowchart after a single-point disconnection fault according to an embodiment of the application. DETAILED DESCRIPTION

[0022] To make the objects, technical solutions and advantages of the embodiments of the application clearer, the technical solutions in the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only some of the embodiments of the application, but not all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the application.

[0023] In the following detailed description, reference can be made to the various drawings that form a part of the present description and are used to illustrate certain embodiments of the application. In the drawings, like numerals describe generally similar components throughout the several views. Each of the various embodiments of the application is described in enough detail to enable those skilled in the art to implement the application. It is to be understood that other embodiments can be utilized and structural, logical, and electrical changes can be made without departing from the scope of the present application.

[0024] Techniques, methods, and apparatus known to those of ordinary skill in the relevant art(s) can not be discussed in any detail in order to avoid obscuring the present description. For the avoidance of doubt, the number of lines of communication between elements in the drawings is indicative only of the minimum number of signals required to be communicated between the elements, and does not limit the elements to the minimum number of signals. Further, the number of lines of communication between two elements is not intended to limit the communication to only the signals illustrated in the drawing.

[0025] The present application provides a mechanism that can autonomously wake up in low power mode and perform diagnosis, and wake up the master after discovering a fault. In addition, in order to reduce the user's use cost or ensure safety during the repair process, when a single-point disconnection fault occurs in the entire topology, the present application provides a method that can continue to perform low-power periodic diagnosis and reverse wake-up of the entire BMS system, so that the user can continue to use normally without maintenance, or ensure that the state of the battery can still be continuously monitored during the repair process.

[0026] Figure 1 is a state diagram of a battery management system without a fault according to an embodiment of the present application.

[0027] According to an embodiment, the battery management system can include a microcontroller unit 101.

[0028] According to an embodiment, the battery management system can further include a bridge chip 102 electrically connected to the microcontroller unit 101 and receiving commands from the microcontroller unit 101. According to an embodiment, the bridge chip 102 can include two interfaces, an L interface and an H interface. According to an embodiment, the bridge chip 102 can further include an interface register configured to control the forwarding interface of the command. When the value of the interface register is 0, the command is forwarded from the H interface; when the value of the interface register is 1, the command is forwarded from the L interface. When a single-point disconnection fault occurs, the entire topology is divided into two parts. When configuring one of the two parts, the value of the interface register of the bridge chip 102 needs to be set to 1. When configuring the other part, the value of the interface register of the bridge chip 102 needs to be set to 0.

[0029] According to an embodiment, the bridge chip 102 can further include a power control pin configured to reverse wake up the microcontroller unit 101 to process the fault when the fault occurs.

[0030] According to an embodiment, the battery management system can further include a plurality of analog front-end chips (AFEs), hereinafter referred to as AFE chips. Figure 1For example, the battery management system includes a plurality of AFE chips, for example, 7 AFE chips. The battery management system can also include other number of AFE chips. According to an embodiment, as shown in Figure 1 , the plurality of AFE chips are connected in series, and the first and the last are electrically connected to the bridge chip.

[0031] According to an embodiment, the battery management system as shown in Figure 1 may be in a low power consumption mode. The low power consumption mode means that the microcontroller unit 101 is in a shutdown mode, all AFE chips are in a sleep mode, and the bridge chip 102 is in a shutdown mode or a sleep mode.

[0036] According to an embodiment, the AFE chip can include two interfaces, L interface and H interface. According to an embodiment, the L interface of the AFE chip 103 is electrically connected to the H interface of the bridge chip 102. The H interface of the AFE chip 109 is electrically connected to the L interface of the bridge chip 102. The L interface of other AFE chips is electrically connected to the H interface of the previous AFE chip.

[0037] According to an embodiment, the AFE chip can periodically perform self-diagnosis on its own functions and cell voltages. According to an embodiment, the status signal includes two types, normal signal and abnormal signal.

[0038] According to an embodiment, when the battery management system is fault-free, the transmission direction of the status signal is from the AFE chip 103 to the AFE chip 109, as shown in

[0039] . Therefore, when the battery management system is fault-free, the previous AFE chip means the AFE chip closer to the AFE chip 103 in the transmission direction of the status signal, and the next AFE chip means the AFE chip farther away from the AFE chip 103 in the transmission direction of the status signal. For example, the previous AFE chip of the AFE chip 105 is the AFE chip 104, and the next AFE chip is the AFE chip 106.

[0040] According to an embodiment, the fault of the AFE chip itself can include a first type of fault and a second type of fault. The AFE chip with the first type of fault can send the abnormal signal. The AFE chip with the second type of fault cannot send the status signal. In the following, the "fault" of the AFE chip refers to the first type of fault. When the second type of fault is involved, it will be specially stated as "second type of fault".

[0041] According to one embodiment, when the AFE chip itself is not faulty, and a normal signal is received from the previous AFE chip, a normal signal is sent to the next AFE chip; when the AFE chip itself is not faulty, and an abnormal signal is received from the previous AFE chip, an abnormal signal is sent to the next AFE chip; when the AFE chip itself is faulty, and a normal signal is received from the previous AFE chip, an abnormal signal is sent to the next AFE chip; when the AFE chip itself is faulty, and an abnormal signal is received from the previous AFE chip, an abnormal signal is sent to the next AFE chip; when the AFE chip does not receive a normal signal or an abnormal signal from the previous AFE chip, an abnormal signal is sent to the next AFE chip.

[0037] According to one embodiment, the AFE chip can further include a normal signal register. Initially, the value of the normal signal register is 0. When the AFE chip receives a normal signal from the previous AFE chip, the value of the normal signal register is set to 1. When a fault occurs, the microcontroller unit 101 reads the value of the normal signal register of each AFE chip, and in combination with the values of other registers, determines the type of fault. If the type of fault is a single-point open circuit fault, it can also be used to determine the location of the single-point open circuit fault.

[0038] According to one embodiment, the AFE chip can further include an abnormal signal register. Initially, the value of the abnormal signal register is 0. When the AFE chip receives an abnormal signal from the previous AFE chip, the value of the abnormal signal register is set to 1. When a fault occurs, the microcontroller unit 101 reads the value of the abnormal signal register of each AFE chip, and in combination with the values of other registers, determines the type of fault. If the type of fault is a single-point open circuit fault, it can also be used to determine the location of the single-point open circuit fault. According to one embodiment, the AFE chip can further include a period register, the value of which is the period of autonomous diagnosis of the AFE chip. By setting the value of the register, the period of autonomous diagnosis of the AFE chip can be changed.

[0039] According to one embodiment, the AFE chip can further include a direction register configured to control the propagation direction of the status signal in sleep mode. When the value of the direction register is 1, the AFE chip sends the status signal from the L interface and receives the status signal from the H interface. When the value of the direction register is 0, the AFE chip sends the status signal from the H interface and receives the status signal from the L interface. When a single-point open circuit fault occurs, the entire topology is divided into two parts. In one of the parts, the propagation direction of the status signal is opposite to that when no fault occurs, so the value of the direction register of each AFE chip in this part needs to be changed.

[0040] According to one embodiment, the AFE chip can further comprise an address register configured to store the address of the AFE chip.

[0041] According to one embodiment, the AFE chip can further comprise a wait register configured to control whether the AFE chip sends a status signal to a neighboring AFE chip according to the direction defined by the direction register, or waits for a status signal from the neighboring AFE chip. When the value of the wait register is 1, the AFE chip sends a status signal to a neighboring AFE chip without waiting for a status signal from the neighboring AFE chip. When the value of the wait register is 0, the AFE chip waits for a status signal from a neighboring AFE chip.

[0042] According to one embodiment, the AFE chip can further comprise a broken wire register. Initially, the value of the broken wire register is 0. When an AFE chip does not receive a normal signal or an abnormal signal within a specified time, and the value of the wait register of the AFE chip is 0, the value of the broken wire register of the AFE chip is set to 1. In this case, the AFE chip also sends an abnormal signal to the next AFE chip.

[0043] According to one embodiment, when a fault occurs, the microcontroller unit 101 reads the value of the broken wire register of each AFE chip, and combines the values of other registers to determine the type of fault. If the type of fault is a single-point broken wire fault, the location of the single-point broken wire fault can also be determined.

[0044] According to one embodiment, the AFE chip can further comprise a top register configured to mark whether the AFE chip is the top of the topology, i.e., the AFE chip with the largest address in the topology. When the value of the top register is 1, the AFE chip is the top of the topology. When the value of the top register is 0, the AFE chip is not the top of the topology.

[0045] According to one embodiment, the working state of the battery management system when there is no fault is as shown in FIG. 1. Figure 1 At this time, the AFE chips 103-109 and the bridge chip 102 together form a topology that is connected head to tail. The values of the direction registers of the AFE chips 103-109 are all 0, and the AFE chips 103-109 send status signals from the H interface and receive status signals from the L interface. Because the bridge chip 102 is in the shutdown mode, the value of the wait register of the AFE chip 103 is 1, and the AFE chip 103 does not need to wait for a status signal from a neighboring chip. The AFE chip 109 is at the top of the topology, so the value of the top register of the AFE chip 109 is 1. The status signals are transmitted in the direction shown in the figure.

[0046] Figure 2is a state diagram of the battery management system according to an embodiment of the present application after a single point wire breakage fault occurs.

[0047] According to an embodiment, Figure 2 In the working state shown, the battery management system is in a low power consumption mode. The low power consumption mode means that the microcontroller unit 201 is in a shutdown mode, all the AFE chips are in a sleep mode, and the bridge chip 202 is in a shutdown mode or a sleep mode.

[0048] According to an embodiment, after a single point fault occurs in the battery management system, the battery management system is configured by using the method proposed in the present application, so that the battery management system can still perform autonomous periodic diagnosis in the low power consumption mode. The configured battery management system is shown in Figure 2 .

[0049] According to an embodiment, Figure 2 For example, the battery management system containing 7 AFE chips can also contain other numbers of AFE chips.

[0050] According to an embodiment, Figure 2 For example, the single point wire breakage fault between the AFE chip 206 and the AFE chip 207. Of course, the single point wire breakage fault in the battery management system can also be located at other positions.

[0051] According to an embodiment, as Figure 2 shown, when the single point wire breakage fault occurs between the AFE chip 206 and the AFE chip 207, the original complete topology is divided into two parts, i.e., a first topology and a second topology. The first topology connects the AFE chip 203 to the AFE chip 206, and the second topology connects the AFE chip 207 to the AFE chip 209.

[0052] According to an embodiment, because the original complete topology is divided into two parts, the address registers of the AFE chips are modified. In the first topology, the value of the address register of the AFE chip 203 is 001, the value of the address register of the AFE chip 204 is 010, the value of the address register of the AFE chip 205 is 011, and the value of the address register of the AFE chip 206 is 100. In the second topology, the value of the address register of the AFE chip 209 is 001, the value of the address register of the AFE chip 208 is 010, and the value of the address register of the AFE chip 207 is 011.

[0053] According to one embodiment, because of a disconnection between AFE chip 206 and AFE chip 207, AFE chip 206 becomes the endpoint for the transmission of the first topology status signal, and its wait register value is 1. AFE chip 207 becomes the endpoint for the transmission of the second topology status signal, and its wait register value is 1. The wait register values ​​of the remaining AFE chips are 0.

[0054] According to one embodiment, AFE chip 206 is at the top of the first topology, and its top register has a value of 1. AFE chip 207 is at the top of the second topology, and its top register has a value of 1. The top registers of the remaining AFE chips have a value of 0.

[0055] According to one embodiment, in the first topology, the transmission direction of the status signal is from AFE chip 206 to AFE chip 203, so the value of the direction register of AFE chip 203, AFE chip 204, AFE chip 205, and AFE chip 206 in the first topology is 1. According to one embodiment, in the second topology, the transmission direction of the status signal is from AFE chip 207 to AFE chip 209, so the value of the direction register of AFE chip 207, AFE chip 208, and AFE chip 209 in the second topology is 0.

[0056] According to one embodiment, after a single point of failure occurs in the battery management system and configuration is performed, the transmission direction of the status signal in the first and second topologies is as described above. Therefore, in the first topology, the previous AFE chip refers to the AFE chip closer to AFE chip 206 in the status signal transmission direction, and the next AFE chip refers to the AFE chip further away from AFE chip 206 in the status signal transmission direction. For example, the previous AFE chip for AFE chip 205 is AFE chip 206, and the next AFE chip is AFE chip 204. In the second topology, the previous AFE chip refers to the AFE chip closer to AFE chip 207 in the status signal transmission direction, and the next AFE chip refers to the AFE chip further away from AFE chip 207 in the status signal transmission direction. For example, the previous AFE chip for AFE chip 208 is AFE chip 207, and the next AFE chip is AFE chip 209.

[0057] According to one embodiment, such as Figure 2 As shown, even after a disconnection between AFE chips 206 and 207, the battery management system can still perform periodic autonomous diagnostics in low-power mode. This autonomous diagnostics is initiated by the AFE chips, with status signals flowing along... Figure 2The direction transmission is shown, without the participation of the microcontroller unit 201. Therefore, the whole battery management system can continue to maintain normal use without repair when a single-point line breakage fault occurs.

[0058] Figure 3 is a state diagram of the battery management system according to an embodiment of the present application after a single-point line breakage fault occurs.

[0059] According to an embodiment, Figure 3 The battery management system can also include other numbers of AFE chips, taking the battery management system including 7 AFE chips as an example.

[0060] According to an embodiment, Figure 3 The single-point line breakage fault in the battery management system can also be located at other positions, taking the single-point line breakage fault between the AFE chip 306 and the AFE chip 307 as an example.

[0061] According to an embodiment, as Figure 3 shown, when the single-point line breakage fault between the AFE chip 306 and the AFE chip 307 occurs, the AFE chip 307 does not receive a normal signal or an abnormal signal, and the value of the waiting register of the AFE chip 307 is 0 at this time, so the value of the line breakage register of the AFE chip 307 is set to 1. And the AFE chip 307 sends an abnormal signal to the AFE chip 308. The AFE chip 308 receives the abnormal signal, sets the value of its own abnormal signal register to 1, and sends an abnormal signal to the AFE chip 309. The AFE chip 309 receives the abnormal signal, sets the value of its own abnormal signal register to 1, and sends an abnormal signal to the bridge chip 302. Therefore, when the single-point line breakage fault between the AFE chip 306 and the AFE chip 307 occurs, the value of the line breakage register of the AFE chip 307 is 1, and the values of the abnormal signal registers of the AFE chip 308 and the AFE chip 309 are 1.

[0062] Figure 4 is a configuration flowchart after a single-point line breakage fault according to an embodiment of the present application.

[0063] Step 401: The bridge chip 302 receives an abnormal signal and reversely wakes up the microcontroller unit 301 through the power supply control pin.

[0064] Step 402: Wake up all AFE chips. The values of the interface registers of the bridge chip 302 are set to 0 and 1 respectively and the corresponding commands are sent to wake up all AFE chips.

[0065] Step 403: Determine the type of fault. The microcontroller unit 301 reads the values of the normal signal register, the abnormal signal register and the disconnection register of each AFE chip, and determines the type of fault according to the read values.

[0066] When the values of the disconnection registers of all AFE chips are 0, the type of fault is determined to be AFE chip fault.

[0067] When the value of the disconnection register of only one AFE chip is 1, for example, the value of the disconnection register of the AFE chip 307 is 1, it is necessary to further determine the state of the AFE chip 306.

[0068] According to an embodiment, the AFE chip can be unable to send any abnormal signal due to its own second type of fault, in which case it is necessary to determine whether the AFE chip 306 has the second type of fault, and if not, the type of fault is determined to be single-point disconnection fault. According to an embodiment, any known method can be used to determine whether the AFE chip is unable to send a state signal due to its own second type of fault.

[0069] When the values of the disconnection registers of two or more AFE chips are 1, the type of fault is determined to be multi-point disconnection fault.

[0070] Step 404: When the type of fault is AFE chip fault, maintenance is required.

[0071] Step 406: When the type of fault is multi-point disconnection fault, maintenance is required.

[0072] Step 405: When the type of fault is single-point disconnection fault, the location of the single-point disconnection fault is determined, and the topology is divided into two parts. Since the value of the disconnection register of the AFE chip 307 is 1, and the AFE chip 306 does not have the second type of fault described above, it can be determined that the location of the single-point disconnection fault is between the AFE chip 306 and the AFE chip 307. The AFE chips 303 to 306 form a first topology, and the AFE chips 307 to 309 form a second topology.

[0073] Step 407: Re-allocate addresses to all AFE chips. According to the number of AFE chips in the first topology and the second topology, re-allocate the addresses. For example, set the value of the address register of AFE chip 303 to 001, the value of the address register of AFE chip 304 to 010, the value of the address register of AFE chip 305 to 011, and the value of the address register of AFE chip 306 to 100. For example, set the value of the address register of AFE chip 309 to 001, the value of the address register of AFE chip 308 to 010, and the value of the address register of AFE chip 307 to 011. According to an embodiment, the operation of re-allocating the addresses of the AFE chips in the two topologies can be performed according to the values of the bridge chip interface registers in sequence.

[0074] Step 408: Set the values of the top register and the wait register. Set the values of the top register and the wait register of the two AFE chips adjacent to the single-point broken-line fault to 1, and set the values of the top register and the wait register of the remaining AFE chips to 0. For example, AFE chip 306 becomes the top in the first topology. Moreover, AFE chip 306 will not wait for the status signals of other AFE chips after entering the sleep mode later, but actively send its own status signal, so the value of its wait register is set to 1.

[0075] Step 409: Set the value of the direction register of all AFE chips in the first topology to 1. Thereafter, each AFE chip in the first topology will send the status signal from the L interface and receive the status signal from the H interface. For example, AFE chip 306 will send the status signal to AFE chip 305 instead of AFE chip 307 when no fault occurs.

[0076] Step 410: Make the entire system enter the low-power mode. Configure all AFE chips in the first topology and the second topology to enter the sleep mode and perform the periodic autonomous diagnosis. Configure bridge chip 302 to enter the sleep mode or the shutdown mode, configure microcontroller unit 301 to enter the shutdown mode, so that the entire battery management system enters the low-power mode again.

[0077] After the above configuration process, the working state of the battery management system is as shown in FIG. 6. Figure 2 After the above configuration process, the working state of the battery management system is as shown in FIG. 6.

[0078] According to one embodiment, referring to Figure 1 , the battery management system can set the autonomous wake-up time according to the low-power strategy of the microcontroller. After the autonomous wake-up, the microcontroller wakes up the bridge chip 102 and all the AFE chips, and judges whether the connection between the bridge chip and the AFE chip 109 is normal by sending a command. When it is found that the AFE chip 109 and the bridge chip are disconnected, the values of the registers of each AFE chip are configured to make the AFE chip 109 actively send its status signal, and make the status signal pass from the AFE chip 109 to the AFE chip 103. The AFE chip 103 sends the status signal to the bridge chip 102.

[0079] According to one embodiment, referring to Figure 1 When a single-point disconnection occurs between the AFE chip 103 and the bridge chip 102, the bridge chip 102 can still receive the status signal from the AFE chip 109. Therefore, the single-point disconnection fault between the AFE chip 103 and the bridge chip 102 does not affect the autonomous diagnosis of the entire battery management system.

[0080] The above method is only one embodiment of the present application, and the sequence numbers of the steps do not limit the execution order of the operations. Based on the disclosure of the present application, the method with adjusted execution order of different operations still belongs to the scope of the present application.

[0081] The present application also provides an electronic device comprising the above battery management system.

[0082] In low-power application scenarios (such as new energy vehicles and energy storage devices), the battery management system is often in a low-power mode to reduce energy consumption. However, during the low-power mode, the battery may enter an abnormal state due to self-discharge, changes in environmental temperature, internal short circuit, etc. If the microcontroller unit cannot be woken up in time for intervention, irreversible damage or safety accidents will occur. In addition, the AFE chip itself may experience hardware aging or transient faults (such as register flipping and clock drift) due to long-term operation, and needs to be diagnosed regularly to ensure its functional integrity. The method, AFE chip, battery management system and electronic device provided by the present application can still perform regular autonomous diagnosis in the low-power mode after a single-point disconnection fault occurs, and can wake up the microcontroller unit in time to handle new faults.

[0083] The above embodiments are only used to illustrate the present application, and are not intended to limit the present application. Those skilled in the art can make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also belong to the scope of the present application.

Claims

1. A battery management system fault handling method, the battery management system comprising a plurality of AFE chip topologies electrically connected end-to-end via bridging chips, and a microcontroller unit electrically connected to the bridging chips, characterized in that, The method includes: when the microcontroller unit in the battery management system is in a power-off mode, the bridge chip is in a sleep mode or a power-off mode, and multiple AFE chips are in a sleep mode... When the bridging chip receives an abnormal signal from the last AFE chip in the topology, it wakes up the microcontroller unit. The bridging chip sends a wake-up command to the AFE chip in the topology; Each AFE chip in the topology is configured to detect its own state, combine the state signal it receives from the previous AFE chip to generate its own state signal, and send it to the next AFE chip. The status signals include normal signals and abnormal signals, wherein When the AFE chip itself is fault-free and receives a normal signal from the previous AFE chip, it sends a normal signal to the next AFE chip. When the AFE chip itself is not faulty, and it receives an abnormal signal from the previous AFE chip, it sends an abnormal signal to the next AFE chip; or When the AFE chip itself malfunctions, upon receiving a normal signal from the previous AFE chip, it sends an abnormal signal to the next AFE chip; or When the AFE chip itself malfunctions and receives an abnormal signal from the previous AFE chip, it sends an abnormal signal to the next AFE chip; or When the AFE chip does not receive a normal or abnormal signal from the previous AFE chip, it sends an abnormal signal to the next AFE chip. When only one AFE chip in the topology does not receive a normal or abnormal signal, it is determined that a single-point disconnection has occurred between that AFE chip and the AFE chip above it, and the topology is divided into a first topology and a second topology by the single-point disconnection. Based on the number of AFE chips and the location of each AFE chip in the first and second topologies, the address, status signal transmission direction, and whether it is necessary to wait for the status signals of other AFE chips to generate its own status signal are re-determined. When the microcontroller unit is in power-off mode, the two adjacent AFE chips at the single-point disconnection point are designated as endpoint AFE chips. The endpoint AFE chips are configured to actively send their own status signals to the next AFE chip in their respective topology along the propagation direction of the status signal.

2. The battery management system fault handling method according to claim 1, characterized in that, The step of re-determining the address of each AFE chip includes setting the address of the AFE chip that is closest to the bridging chip in the first topology and the second topology to 1, and setting the addresses of the remaining AFE chips to increment sequentially according to the distance between the AFE chip and the bridging chip.

3. The battery management system fault handling method according to claim 1, characterized in that, When all AFE chips in the topology, except for those that do not need to wait for status signals from other AFE chips, have received status signals from the previous AFE chip, it is determined that there is no open circuit fault in the topology, but rather that the AFE chips have experienced a type 1 fault.

4. The battery management system fault handling method according to claim 1, characterized in that, When two or more AFE chips in the topology do not receive normal or abnormal signals, it is determined that a multi-point disconnection fault has occurred in the topology.

5. The battery management system fault handling method according to claim 1, characterized in that, When only one AFE chip in the topology fails to receive a normal or abnormal signal, the status of the AFE chip preceding that AFE chip is checked to confirm whether the failure to send a status signal is due to a Type II fault in the preceding AFE chip itself.

6. An AFE chip applied to the method of claim 1, characterized in that, include: The normal signal register is configured to have its stored value set to valid when a normal signal is received from the previous AFE chip; The exception signal register is configured to have its stored value set to valid when an exception signal is received from the previous AFE chip. The direction register stores values ​​that represent the direction of propagation of the status signal; The wait register stores a value indicating whether the AFE chip needs to wait for a status signal from the previous AFE chip in order to generate its own status signal. The disconnection register is configured to have its stored value set to valid if no status signal is received from the previous AFE chip within a specified time.

7. The AFE chip according to claim 6, characterized in that, It also includes an address register configured to store the address of the AFE chip.

8. The AFE chip according to claim 6, characterized in that, It also includes a top register, configured to mark whether the AFE chip is at the top of its topology.

9. A battery management system, characterized in that, The system includes an AFE chip topology that is electrically connected end-to-end via a bridging chip, and a microcontroller unit electrically connected to the bridging chip. When the microcontroller unit in the battery management system is in power-off mode, the bridging chip is in sleep mode or power-off mode, and the multiple AFE chips are in sleep mode... The bridging chip is configured to receive a status signal from the last AFE chip in the topology. When the status signal is an abnormal signal, the bridging chip is configured to wake up the microcontroller unit and send wake-up commands to the AFE chips in the topology in two directions respectively. Each AFE chip in the topology is configured to detect its own state and receive a state signal from the previous AFE chip to generate its own state signal and send it to the next AFE chip. The status signal includes a normal signal and an abnormal signal. When the AFE chip itself is fault-free and receives a normal signal from the previous AFE chip, it sends a normal signal to the next AFE chip. When the AFE chip itself is not faulty, it sends an abnormal signal to the next AFE chip when it receives an abnormal signal from the previous AFE chip. or When the AFE chip itself malfunctions and receives a normal signal from the previous AFE chip, it sends an abnormal signal to the next AFE chip. or When the AFE chip itself malfunctions and receives an abnormal signal from the previous AFE chip, it sends an abnormal signal to the next AFE chip. or When the AFE chip does not receive a normal or abnormal signal from the previous AFE chip, it sends an abnormal signal to the next AFE chip. The microcontroller unit is configured to read the register value of each AFE chip in the topology to determine whether a single point of disconnection has occurred between the AFE chip and the AFE chip above it. When a single point of disconnection occurs, the configuration is set to divide the topology into a first topology and a second topology by the single point of disconnection, and the register values ​​of the AFE chips in the first topology and the second topology are reset. The two adjacent AFE chips at the single point of disconnection are designated as endpoint AFE chips. When the microcontroller unit is in power-off mode, the endpoint AFE chips are configured to actively send their own status signals to the next AFE chip in their respective topology along the propagation direction of the status signal.

10. The battery management system according to claim 9, characterized in that, The AFE chip includes: The normal signal register is configured to have its stored value set to valid when a normal signal is received from the previous AFE chip; The exception signal register is configured to set its stored value to valid when an exception signal is received from the previous AFE chip; The direction register stores values ​​that represent the direction of propagation of the status signal; The wait register stores a value indicating whether the AFE chip needs to wait for a status signal from the previous AFE chip in order to generate its own status signal. The disconnection register is configured to have its stored value set to valid if no status signal is received from the previous AFE chip within a specified time.

11. The battery management system according to claim 10, characterized in that, The microcontroller unit is configured to read the values ​​of the normal signal register, abnormal signal register, and disconnection register of each AFE chip in the topology to determine whether a single-point disconnection has occurred.

12. The battery management system according to claim 10, characterized in that, The microcontroller unit is configured to reset the values ​​of the direction register and wait register of the AFE chip in the first topology and the second topology.

13. An electronic device, characterized in that, Includes the battery management system as described in any one of claims 9-12.

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