Real-time optical fiber communication protocol with synchronization function

Abstract

The invention belongs to the technical field of power electronic control, and particularly relates to a real-time optical fiber communication protocol with a synchronization function. The protocol comprises a sending end and a receiving end, wherein the sending end comprises a time synchronization coding module, a data area packaging module and a retransmission mechanism module; the receiving end comprises a time synchronization decoding module, a data area decoding module, a data area multiple voting decoding module and a decoding retransmission response module; according to the invention, the synchronous clock signal and the data stream are subjected to time division multiplexing coding, so that the system can complete multi-node accurate synchronous control and data transmission only by a pair of optical fibers. According to the scheme, the number of optical fiber links is effectively reduced to 1 / Q of that of a traditional architecture, Q is the number of nodes, the use amount of high-speed optical fibers is reduced, meanwhile, the system construction cost and topology complexity are remarkably reduced, and a solution with higher expansibility is provided for networking of large-scale power electronic devices.

Description

Technical Field

[0001] The present invention belongs to the field of power electronic control technology. Specifically, it relates to a real-time fiber optic communication protocol with synchronization function, which is used to resolve the contradiction between high-speed real-time performance and low cost requirements of fiber optic communication systems and improve the reliability and economy of power electronic equipment control. Background Art

[0002] With the widespread application of power electronics in renewable energy generation, smart grids, and industrial control, high-speed, real-time communication systems between master and slave controllers face the dual challenges of synchronization accuracy and hardware cost. In high-precision control scenarios such as converters and DC transmission valve control systems, communication latency must be strictly controlled to the nanosecond level, meeting the dual requirements of high reliability and low cost. However, existing fiber-optic communication technologies face significant bottlenecks in protocol architecture and physical layer implementation, hindering further improvements in the performance of power electronics.

[0003] Currently, synchronization between the master and slave FPGAs primarily utilizes two technical approaches. The first utilizes an independent synchronous fiber architecture, transmitting synchronization trigger signals via dedicated fiber channels while maintaining a separate channel for data communication. While this approach achieves precise clock alignment, it requires the deployment of additional synchronization optical modules and supporting circuitry, exponentially increasing system hardware complexity, particularly in multi-point topologies. The second approach utilizes high-speed serial communication coupled with clock recovery technology, relying on high-speed transceivers such as Xilinx GTX / GTH for simultaneous data and clock transmission. This necessitates the use of costly optical modules and is sensitive to fiber link attenuation, requiring the deployment of relay compensation circuitry.

[0004] The dual demands of power electronics control systems for real-time and cost-effective communication conflict with the inherent limitations of existing technologies, such as high baud rate constraints, multi-fiber architecture costs, and protocol processing overhead. Therefore, there is an urgent need to develop a new fiber-optic communication device that, through protocol stack reconstruction and physical layer optimization, can achieve full-duplex real-time transmission on a single fiber while reducing communication costs and providing reliable support for high-precision power electronics control. Summary of the Invention

[0005] In order to overcome the defects and shortcomings of the above-mentioned prior art and solve the technical problems of high-precision instruction synchronization, reliable data transmission in strong interference environments and millisecond-level fault recovery in distributed power electronic equipment group control systems, the present invention proposes a real-time fiber optic communication protocol with synchronization function.

[0006] To achieve the above technical effects, the present invention is implemented through the following technical solutions: A real-time optical fiber communication protocol with synchronization function, including a sending end and a receiving end, The transmitting end includes a time synchronization encoding module, a data area encapsulation module and a retransmission mechanism module; The time synchronization encoding module adopts a dual-edge trigger mechanism and a dynamically adjustable frame header mechanism to enable clock synchronization between master and slave devices in long-distance optical fiber communication; The data area encapsulation module adopts a multi-structure encapsulation and verification mechanism to achieve high real-time industrial communication; The retransmission mechanism module adopts a dual judgment mechanism of link interruption retransmission and response timeout retransmission.

[0007] The receiving end includes a time synchronization decoding module, a data area decoding module, a data area multiple voting decoding module and a decoding retransmission response module; The time synchronization decoding module parses the time synchronization code start frame header and the time synchronization code end frame header according to the time synchronization encoding module of the sending end, realizes the timing alignment between the receiving end and the sending end, and provides a stable synchronization benchmark for data analysis; The data area decoding module sequentially decodes the address, function code, frame sequence number, data area and additional code of the data frame according to the communication protocol, wherein the data area verifies the complete data packet through the check code; The data area multi-voting decoding module adopts a majority voting mechanism combined with CRC check and closed-loop check of instruction status feedback to achieve high anti-interference data transmission and ensure the reliability of instruction execution; The decoding and retransmission response module adopts a dual judgment strategy of real-time monitoring of link interruption and control of response timeout threshold to build a retransmission system with rapid response to physical layer anomalies and reliable communication guarantee at the logical layer, ensuring the effective delivery of key instructions in unreliable channels.

[0008] Furthermore, the time synchronization encoding module at the transmitting end is configured with dynamically adjustable time synchronization code start frame header and end frame header.

[0009] Furthermore, the starting frame header is composed of N1 bytes, where N1≥32 bits, and N1×T is pre-calculated. CLK Generates the rising edge of the synchronization signal, where T CLK It is a single clock cycle that generates the rising edge of the synchronization signal in advance to compensate for the delay of optical fiber transmission and signal processing.

[0010] Furthermore, the end frame header adopts a fixed width of N5 bytes, where N5≥32bit, and N5 adopts a fixed clock cycle width as a falling edge identification code to ensure alignment of the dual-edge trigger windows and realize clock-embedded data transmission between the N1 pre-synchronization segment and the N5 falling edge segment.

[0011] Furthermore, the data area encapsulation module of the sending end includes an address, a function code, a frame counter, a data area greater than or equal to 64 bytes, an additional code and a check code, and its total length is N3 bytes.

[0012] Furthermore, the data area structure of the data area encapsulation module includes idle bits, start bits, data bits, check bits and stop bits.

[0013] Furthermore, the retransmission mechanism module of the transmitting end includes two fault determination situations: a) Link interruption retransmission: When the slave detects signal loss for two consecutive clock cycles during data reception, it immediately sends a NAK frame to trigger the master to retransmit; b) Response timeout retransmission: After the main control unit sends the command, if 6TCLK If no response data packet is received from the target slave node within the window period, the original data frame will be automatically resent. 6TCLK For the time that has not been returned.

[0014] Furthermore, the time synchronization decoding module of the receiving end includes a time synchronization code start frame header detection part, a time synchronization code end frame header detection part and a dual-edge trigger part. The time synchronization code start frame header detection part is used to identify the time synchronization code start frame header composed of N1 bytes, and its detection window width is dynamically configured as N1×T according to the received N1 value. CLK The end frame header detection part of the time synchronization code is composed of N5 bytes. The dual-edge trigger part generates a synchronous clock signal according to the rising edge of the start frame header and the falling edge of the end frame header to achieve timing alignment of the trigger window.

[0015] Furthermore, the data area multi-voting decoding module of the receiving end adopts a majority voting mechanism, and the receiving end samples each data bit R times continuously, and takes the level with a number of occurrences exceeding R / 2 as the final sampling result of the single bit; the structured data packet includes a CRC check code and an instruction execution status feedback code, which are used for data transmission integrity verification in the closed-loop verification mechanism.

[0016] Working process: In the first step, the master control unit uses the time synchronization encoding module at the sending end and the time synchronization decoding module at the receiving end to realize the clock alignment with the FPGA of the controlled unit; In the second step, the data area encapsulation module at the transmitter and the data area multi-voting decoding module at the receiver use redundant transmission and majority decision mechanisms to address transient interference in the fiber channel. The data area multi-voting decoding module samples each data bit R times in a row and takes the level that occurs more than R / 2 times as the final single-bit sampling result. In the third step, the retransmission mechanism uses a dual-security strategy to deal with communication link anomalies. The retransmission mechanism module on the sending end performs two fault determinations: a) Link interruption retransmission: When the controlled unit detects the loss of two consecutive clock cycle signals during data reception, it immediately sends a NAK frame to trigger the master unit to resend the time synchronization encoding module and data area encapsulation module; b) Response timeout retransmission: After the main control unit sends the command, if 6TCLK If no response data packet is received from the target slave node within the window period, the original data frame, i.e., the data area encapsulation module, will be automatically resent.

[0017] The advantages of the present invention are: Traditional interconnected systems for multiple power electronic devices typically use point-to-point fiber-optic communication for hard synchronization control to achieve drive synchronization. However, this architecture requires a separate high-speed fiber link for each node. As the system scales up, not only does this require the deployment of a large number of high-speed fibers, but it also significantly increases the hardware investment cost and wiring complexity. To overcome this drawback, the present invention uses time-division multiplexing encoding of synchronous clock signals and data streams, enabling the system to achieve precise synchronization control and data transmission for multiple nodes with just one pair of optical fibers. This solution effectively reduces the number of fiber links to 1 / Q of the traditional architecture (Q is the number of nodes). While reducing the amount of high-speed fiber used, it significantly reduces system construction costs and topology complexity, providing a more scalable solution for large-scale power electronic device networking. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a flow chart for the implementation of a real-time fiber optic communication protocol with synchronization capabilities.

[0019] Figure 2 This is a principle block diagram of the time synchronization encoding module of the present invention.

[0020] Figure 3 This is a format diagram of the data area encapsulation module of the present invention. DETAILED DESCRIPTION

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0022] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0023] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0024] In the description of this application, it should be noted that the terms "upper," "vertical," "inner," "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is typically placed when in use, or are the orientations or positional relationships commonly understood by those skilled in the art. These terms are intended only to facilitate the description of this application and simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting this application. Furthermore, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0025] It should also be noted that, in the description of this application, unless otherwise expressly specified or limited, the terms "disposed," "installed," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0026] Example 1 A real-time optical fiber communication protocol with synchronization function, including a sending end and a receiving end, The sending end includes a time synchronization encoding module, a data area encapsulation module and a retransmission mechanism module; The time synchronization encoding module adopts a dual-edge trigger mechanism and a dynamically adjustable frame header mechanism to enable low-latency and high-reliability clock synchronization between master and slave devices in long-distance optical fiber communications. The data area encapsulation module adopts a multi-structure encapsulation and verification mechanism to achieve high real-time industrial communication; The retransmission mechanism module adopts a dual judgment mechanism of link interruption retransmission and response timeout retransmission to ensure the accurate execution of instructions in complex environments.

[0027] The receiving end includes a time synchronization decoding module, a data area decoding module, a data area multiple voting decoding module and a decoding retransmission response module; The time synchronization decoding module parses the time synchronization code start frame header and the time synchronization code end frame header according to the time synchronization encoding module of the sending end, achieving high-precision timing alignment between the receiving end and the sending end, and providing a stable synchronization benchmark for data analysis; The data area decoding module decodes the address, function code, frame sequence number, data area and additional code of the data frame in sequence according to the communication protocol, wherein the data area verifies the complete data packet through the check code; The data area multi-voting decoding module adopts a majority voting mechanism combined with CRC check and closed-loop check of instruction status feedback to achieve highly anti-interference data transmission and ensure the reliability of instruction execution. The decoding and retransmission response module adopts a dual judgment strategy of real-time monitoring of link interruption and control of response timeout threshold to build a retransmission system with rapid response to physical layer anomalies and reliable communication guarantee at the logical layer, ensuring the effective delivery of key instructions in unreliable channels.

[0028] Traditional interconnected systems for multiple power electronic devices typically use point-to-point fiber-optic communication for hard synchronization control to achieve drive synchronization. However, this architecture requires a separate high-speed fiber link for each node. As the system scales up, not only does this require the deployment of a large number of high-speed fibers, but it also significantly increases the hardware investment cost and wiring complexity. To overcome this drawback, the present invention uses time-division multiplexing encoding of synchronous clock signals and data streams, enabling the system to achieve precise synchronization control and data transmission for multiple nodes with just one pair of optical fibers. This solution effectively reduces the number of fiber links to 1 / Q of the traditional architecture (Q is the number of nodes). While reducing the amount of high-speed fiber used, it significantly reduces system construction costs and topology complexity, providing a more scalable solution for large-scale power electronic device networking.

[0029] Example 2 A real-time optical fiber communication protocol with synchronization function, including a sending end and a receiving end, The sending end includes a time synchronization encoding module, a data area encapsulation module and a retransmission mechanism module; The time synchronization encoding module adopts a dual-edge trigger mechanism and a dynamically adjustable frame header mechanism to enable low-latency and high-reliability clock synchronization between master and slave devices in long-distance optical fiber communications. The data area encapsulation module adopts a multi-structure encapsulation and verification mechanism to achieve high real-time industrial communication; The retransmission mechanism module adopts a dual judgment mechanism of link interruption retransmission and response timeout retransmission to ensure the accurate execution of instructions in complex environments.

[0030] The receiving end includes a time synchronization decoding module, a data area decoding module, a data area multiple voting decoding module and a decoding retransmission response module; The time synchronization decoding module parses the time synchronization code start frame header and the time synchronization code end frame header according to the time synchronization encoding module of the sending end, achieving high-precision timing alignment between the receiving end and the sending end, and providing a stable synchronization benchmark for data analysis; The data area decoding module decodes the address, function code, frame sequence number, data area and additional code of the data frame in sequence according to the communication protocol, wherein the data area verifies the complete data packet through the check code; The data area multi-voting decoding module adopts a majority voting mechanism combined with CRC check and closed-loop check of instruction status feedback to achieve highly anti-interference data transmission and ensure the reliability of instruction execution. The decoding and retransmission response module adopts a dual judgment strategy of real-time monitoring of link interruption and control of response timeout threshold to build a retransmission system with rapid response to physical layer anomalies and reliable communication guarantee at the logical layer, ensuring the effective delivery of key instructions in unreliable channels.

[0031] The above modules are executed in parallel through FPGA hardware logic, combined with dynamic node address allocation and closed-loop verification mechanism to achieve full-node instruction distribution, execution and status feedback within a single control cycle.

[0032] The time synchronization encoding module at the sending end is configured with dynamically adjustable time synchronization code start frame header and end frame header.

[0033] The starting frame header consists of N1 bytes, where N1 ≥ 32 bits. By pre-calculating N1×T CLK Generates the rising edge of the synchronization signal, where T CLK It is a single clock cycle that generates the rising edge of the synchronization signal in advance to compensate for the delay of optical fiber transmission and signal processing.

[0034] The end frame header uses a fixed width of N5 bytes, where N5 ≥ 32 bits. N5, as the falling edge identification code, uses a fixed clock cycle width to ensure precise alignment of the dual-edge trigger windows and implement clock-embedded data transmission between the N1 pre-synchronization segment and the N5 falling edge segment.

[0035] The data area encapsulation module at the sending end includes an address, a function code, a frame counter, a data area greater than or equal to 64 bytes, an additional code, and a check code, with a total length of N3 bytes.

[0036] The data area structure of the data area encapsulation module includes idle bits, start bits, data bits, check bits and stop bits.

[0037] The retransmission mechanism module at the sending end includes two fault judgment situations: a) Link interruption retransmission: When the slave detects signal loss for two consecutive clock cycles during data reception, it immediately sends a NAK frame to trigger the master to retransmit; b) Response timeout retransmission: After the main control unit sends the command, if 6TCLK If no response data packet is received from the target slave node within the window period, the original data frame will be automatically resent. 6TCLK For the time that has not been returned.

[0038] The time synchronization decoding module at the receiving end includes a time synchronization code start frame header detection part, a time synchronization code end frame header detection part and a dual-edge trigger part. The time synchronization code start frame header detection part is used to identify the time synchronization code start frame header composed of N1 bytes. The detection window width is dynamically configured as N1×T according to the received N1 value. CLK The end frame header detection part of the time synchronization code is composed of N5 bytes. The dual-edge trigger part generates a synchronous clock signal according to the rising edge of the start frame header and the falling edge of the end frame header to achieve timing alignment of the trigger window.

[0039] The data area multi-voting decoding module at the receiving end adopts a majority voting mechanism. The receiving end samples each data bit R times continuously and takes the level that occurs more than R / 2 times as the final single-bit sampling result. The structured data packet contains a CRC checksum and an instruction execution status feedback code, which are used to verify the data transmission integrity in the closed-loop verification mechanism.

[0040] Working process: In the first step, the master control unit uses the time synchronization encoding module at the sending end and the time synchronization decoding module at the receiving end to realize the clock alignment with the FPGA of the controlled unit; In the second step, the data area encapsulation module at the transmitter and the data area multi-voting decoding module at the receiver use redundant transmission and majority decision mechanisms to address transient interference in the fiber channel. The data area multi-voting decoding module samples each data bit R times in a row and takes the level that occurs more than R / 2 times as the final single-bit sampling result. In the third step, the retransmission mechanism uses a dual-security strategy to deal with communication link anomalies. The retransmission mechanism module on the sending end performs two fault determinations: a) Link interruption retransmission: When the controlled unit detects the loss of two consecutive clock cycle signals during data reception, it immediately sends a NAK frame to trigger the master unit to resend the time synchronization encoding module and data area encapsulation module; b) Response timeout retransmission: After the main control unit sends the command, if 6TCLK If no response data packet is received from the target slave node within the window period, the original data frame, i.e., the data area encapsulation module, will be automatically resent.

[0041] Traditional interconnected systems for multiple power electronic devices typically use point-to-point fiber-optic communication for hard synchronization control to achieve drive synchronization. However, this architecture requires a separate high-speed fiber link for each node. As the system scales up, not only does this require the deployment of a large number of high-speed fibers, but it also significantly increases the hardware investment cost and wiring complexity. To overcome this drawback, the present invention uses time-division multiplexing encoding of synchronous clock signals and data streams, enabling the system to achieve precise synchronization control and data transmission for multiple nodes with just one pair of optical fibers. This solution effectively reduces the number of fiber links to 1 / Q of the traditional architecture (Q is the number of nodes). While reducing the amount of high-speed fiber used, it significantly reduces system construction costs and topology complexity, providing a more scalable solution for large-scale power electronic device networking.

[0042] Example 3 Aiming at the real-time and reliability requirements of power electronic control scenarios, the present invention is composed of a transmitter and a receiver: The sending end includes a time synchronization encoding module, a data area encapsulation module and a retransmission mechanism module; The receiving end includes a time synchronization decoding module, a data area decoding module, a data area multiple voting decoding module and a decoding retransmission response module.

[0043] Each module is executed in parallel through FPGA hardware logic, combined with dynamic node address allocation and closed-loop verification mechanism to achieve full-node instruction distribution, execution and status feedback within a single control cycle.

[0044] The transmitter time synchronization encoding module uses a dual-edge trigger mechanism and is configured with dynamically adjustable time synchronization code start and end frame headers: The start frame header consists of N1 bytes, where the N1 value is dynamically configured according to the system delay (for example, N1 ≥ 32 bits). CLK (T CLK Generate the rising edge of the synchronization signal in advance (the module clock cycle), avoiding the delay accumulation caused by signal propagation and detection in traditional synchronization methods; The end frame header uses a fixed width of N5 bytes (N5 ≥ 32 bits). N5, as the falling edge identifier, uses a fixed clock cycle width to ensure precise alignment of the dual-edge trigger windows and implement clock-embedded data transmission between the N1 pre-synchronization segment and the N5 falling edge segment. By sending synchronization signals in advance and using a dynamic compensation mechanism, the timing uncertainty of traditional synchronization schemes is effectively avoided, ensuring master and slave clock alignment and providing a stable timing reference for subsequent data transmission.

[0045] The data area encapsulation module at the sender end includes the address, function code, frame counter, data area greater than or equal to 64 bytes, additional code and check code, with a total length of N3 bytes. Its data area structure consists of idle bits, start bits, data bits, check bits and stop bits.

[0046] The retransmission mechanism module at the sending end uses a dual protection strategy to deal with communication link anomalies: First, if it detects that the data packet interval has timed out or the data has not been received in the soft synchronization mode during the reception process, it immediately pulls up the timeout signal and sends an ACK frame to request the sending end to retransmit at the breakpoint; second, the sending end starts the response timer N after sending the data. 7TCLK If no ACK feedback is received after the timeout, the link is considered broken, and the cumulative code is automatically appended and the complete data packet is resent. To optimize efficiency, the sender uses a priority queue to respond to breakpoint retransmission requests first, with a maximum retry count of 3. If continuous failures occur, the sender switches to the backup channel and logs the failure.

[0047] In the time synchronization decoding module at the receiving end, the time synchronization code start frame header detection part is used to identify the time synchronization code start frame header composed of N1 bytes. Its detection window width is dynamically configured as N1×T according to the received N1 value. CLK The end frame header detection part of the time synchronization code is composed of N5 bytes. The dual-edge trigger part generates a synchronous clock signal according to the rising edge of the start frame header and the falling edge of the end frame header to achieve timing alignment of the trigger window.

[0048] The receiving end data area multiple voting decoding module solves the problem of bit errors caused by on-site electromagnetic interference in actual industrial applications. The specific implementation method is as follows: the receiving end performs N decoding on each data bit. j Continuous sampling, take the number of occurrences exceeding N j The level of / 2 is used as the final single-bit sampling result. The data validity is confirmed by combining it with the CRC check result. If the check passes, it is stored in the buffer and a reception success signal is fed back. If there are more than two error bits or the CRC check fails, the retransmission mechanism is triggered.

[0049] In addition, it should be noted that the above content described in this specification is merely an example of the structure of the present invention. Any equivalent changes made based on the structure, features and principles described in the patent concept of the present invention are included in the scope of protection of the patent of the present invention. Those skilled in the art of the present invention can make various modifications, supplements or replace the specific embodiments described in a similar manner. As long as they do not deviate from the structure of the present invention or exceed the scope defined by the claims, they should fall within the scope of protection of the present invention.

Claims

1. A real-time optical fiber communication protocol with synchronization function, characterized in that: Including the sending end and the receiving end, The transmitting end includes a time synchronization encoding module, a data area encapsulation module and a retransmission mechanism module; The time synchronization encoding module adopts a dual-edge trigger mechanism and a dynamically adjustable frame header mechanism to enable clock synchronization between master and slave devices in long-distance optical fiber communication; The data area encapsulation module adopts a multi-structure encapsulation and verification mechanism to achieve high real-time industrial communication; The retransmission mechanism module adopts a dual judgment mechanism of link interruption retransmission and response timeout retransmission. The receiving end includes a time synchronization decoding module, a data area decoding module, a data area multiple voting decoding module and a decoding retransmission response module; The time synchronization decoding module parses the time synchronization code start frame header and the time synchronization code end frame header according to the time synchronization encoding module of the sending end, realizes the timing alignment between the receiving end and the sending end, and provides a stable synchronization benchmark for data analysis; The data area decoding module sequentially decodes the address, function code, frame sequence number, data area and additional code of the data frame according to the communication protocol, wherein the data area verifies the complete data packet through the check code; The data area multi-voting decoding module adopts a majority voting mechanism combined with CRC check and closed-loop check of instruction status feedback to achieve high anti-interference data transmission and ensure the reliability of instruction execution; The decoding and retransmission response module adopts a dual judgment strategy of real-time monitoring of link interruption and control of response timeout threshold to build a retransmission system with rapid response to physical layer anomalies and reliable communication guarantee at the logical layer, ensuring the effective delivery of key instructions in unreliable channels.

2. A real-time optical fiber communication protocol with synchronization function according to claim 1, characterized in that: The time synchronization encoding module at the sending end is configured with dynamically adjustable time synchronization code start frame header and end frame header.

3. A real-time optical fiber communication protocol with synchronization function according to claim 2, characterized in that: The starting frame header consists of N1 bytes, where N1≥32 bits, and N1×T is pre-calculated. CLK Generates the rising edge of the synchronization signal, where T CLK It is a single clock cycle that generates the rising edge of the synchronization signal in advance to compensate for the delay of optical fiber transmission and signal processing.

4. A real-time optical fiber communication protocol with synchronization function according to claim 3, characterized in that: The end frame header adopts a fixed width of N5 bytes, where N5≥32 bits, and N5 adopts a fixed clock cycle width as a falling edge identification code to ensure alignment of the double-edge trigger windows and realize clock-embedded data transmission between the N1 pre-synchronization segment and the N5 falling edge segment.

5. A real-time optical fiber communication protocol with synchronization function according to claim 1, characterized in that: The data area encapsulation module of the transmitting end includes an address, a function code, a frame counter, a data area greater than or equal to 64 bytes, an additional code and a check code, and its total length is N3 bytes.

6. A real-time optical fiber communication protocol with synchronization function according to claim 1, characterized in that: The data area structure of the data area encapsulation module includes idle bits, start bits, data bits, check bits and stop bits.

7. A real-time optical fiber communication protocol with synchronization function according to claim 1, characterized in that: The retransmission mechanism module of the sending end includes two fault judgment situations: a) Link interruption retransmission: When the slave detects signal loss for two consecutive clock cycles during data reception, it immediately sends a NAK frame to trigger the master to retransmit; b) Response timeout retransmission: After the main control unit sends the command, if 6TCLK If no response data packet is received from the target slave node within the window period, the original data frame will be automatically resent. 6TCLK For the time that has not been returned.

8. A real-time optical fiber communication protocol with synchronization function according to claim 1, characterized in that: The time synchronization decoding module of the receiving end includes a time synchronization code start frame header detection part, a time synchronization code end frame header detection part and a double-edge trigger part. The time synchronization code start frame header detection part is used to identify the time synchronization code start frame header composed of N1 bytes. The detection window width is dynamically configured as N1×T according to the received N1 value. CLK The end frame header detection part of the time synchronization code is composed of N5 bytes. The dual-edge trigger part generates a synchronous clock signal according to the rising edge of the start frame header and the falling edge of the end frame header to achieve timing alignment of the trigger window.

9. A real-time optical fiber communication protocol with synchronization function according to claim 1, characterized in that: The data area multi-voting decoding module at the receiving end adopts a majority voting mechanism. The receiving end samples each data bit R times continuously and takes the level that appears more than R / 2 times as the final single-bit sampling result; the structured data packet contains a CRC check code and an instruction execution status feedback code, which are used for data transmission integrity verification in the closed-loop verification mechanism.

10. A real-time optical fiber communication protocol with synchronization function according to claim 1, characterized in that: The working process is as follows: In the first step, the master control unit uses the time synchronization encoding module at the sending end and the time synchronization decoding module at the receiving end to realize the clock alignment with the FPGA of the controlled unit; In the second step, the data area encapsulation module at the transmitter and the data area multi-voting decoding module at the receiver use redundant transmission and majority decision mechanisms to address transient interference in the fiber channel. The data area multi-voting decoding module samples each data bit R times in a row and takes the level that occurs more than R / 2 times as the final single-bit sampling result. In the third step, the retransmission mechanism uses a dual-security strategy to deal with communication link anomalies. The retransmission mechanism module on the sending end performs two fault determinations: a) Link interruption retransmission: When the controlled unit detects the loss of two consecutive clock cycle signals during data reception, it immediately sends a NAK frame to trigger the master unit to resend the time synchronization encoding module and data area encapsulation module; b) Response timeout retransmission: After the main control unit sends the command, if 6TCLK If no response data packet is received from the target slave node within the window period, the original data frame, i.e., the data area encapsulation module, will be automatically resent.

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