Method and device for assembling and transmitting confused network data packets based on multiple buffers

Abstract

The invention discloses an obfuscated network data packet assembling and transmitting method and device based on multiple buffer areas, and the method comprises a data packet assembling step and a cached data sending step. A data packet assembling step: setting a plurality of buffer areas for the queue to be sent of the data packets, extracting one data packet from the queue to be sent each time, sequentially judging whether the idle load space of each buffer area can accommodate the data packet or not according to a preset sequence, if so, storing the data packet, and continuing to extract the next data packet; when all the buffer areas cannot accommodate the data, entering a waiting state until the data in the buffer areas are read and sent, and re-executing storage; a cache data sending step: locking a plurality of buffer areas at a preset sending moment, reading data of the first buffer area, filling the data to a set load size, and forwarding the data to the confusion network; and after forwarding is completed, buffer area pointer switching is executed, a buffer area is unlocked, repeated sending at the next sending moment is waited, and the effective load utilization rate is increased by optimizing data packet assembling and sending logic.

Description

Technical Field

[0001] The present invention relates to the field of obfuscated network communication technology, and in particular to a method and device for assembling and transmitting obfuscated network data packets based on multiple buffers. Background Art

[0002] As the core infrastructure for anonymous communication, the obfuscation network eliminates traffic statistical characteristics through traffic normalization and time synchronization strategies to combat traffic correlation analysis and tracing. Traffic normalization requires shaping (e.g., assembly and padding) packets to a fixed size for transmission, while time synchronization imposes delay interference on forwarding behavior.

[0003] There are two main methods for obfuscating network packet transmission: First, assemble multiple data packets within the forwarding time window. If the total size does not reach the set specification value, fill it with invalid data to a fixed size. This method results in low payload utilization because invalid data occupies payload space.

[0004] Second, encapsulate the original data packet with a custom protocol (including headers such as the session ID, fragment sequence number, and offset), trim the padding, and transmit it. However, this protocol header takes up extra payload space and can even reduce payload utilization, making it unsuitable for obfuscated networks.

[0005] Both of the above methods have the problem of low payload space utilization, which seriously restricts the improvement of the bandwidth performance of the obfuscated network. Summary of the Invention

[0006] In view of the above problems, the present invention provides a method and device for assembling and transmitting obfuscated network data packets based on multiple buffers, which improves the payload utilization by optimizing the data packet assembly and sending logic.

[0007] In a first aspect, an embodiment of the present invention provides a method for assembling and transmitting obfuscated network data packets based on multiple buffers, comprising: a data packet assembling step and a buffered data sending step, wherein: The data packet assembling step includes: setting a plurality of buffers for a data packet queue to be sent, extracting a data packet from the queue to be sent each time, determining in a predetermined order whether the free load space of each buffer can accommodate the data packet; if any buffer can accommodate the data packet, storing the data packet in the corresponding buffer and continuing to extract the next data packet from the queue to be sent; if all buffers cannot accommodate the data packet, entering a waiting state until a data packet in a buffer is read and sent, and then re-performing the above-mentioned storage operation; The cached data sending step includes: at a preset sending time, locking the multiple buffers, reading all data in the first buffer, filling the read data to the set payload size and then forwarding it to the obfuscation network; after the forwarding is completed, performing a buffer pointer switching operation, and sequentially advancing the subsequent buffers of the previous sending time window as the preceding buffers of the current sending time window, and switching the original first buffer to the last buffer; after the pointer switching is completed, unlocking the multiple buffers, waiting for the next sending time and repeating the cached data sending step.

[0008] In some embodiments, the plurality of buffer zones are three buffer zones and are physically isolated.

[0009] In some embodiments, the preset order in the data packet assembly step includes: proceeding in sequence according to the logical sequence number of each buffer, first determining the free payload space of the first buffer, and if it cannot accommodate, determining subsequent buffers in sequence.

[0010] In some embodiments, the waiting state in the data packet assembling step includes: pausing the extraction of data packets from the queue to be sent until it is detected that at least one buffer generates new idle payload space due to data being read and sent.

[0011] In some embodiments, locking multiple buffers in the cache data sending step includes: prohibiting new data from being written to the multiple buffers during data reading and pointer switching; unlocking the multiple buffers in the cache data sending step includes: allowing new data to be written to the multiple buffers after switching.

[0012] In some embodiments, the position of the unsent data stored in each buffer remains unchanged during the buffer pointer switching operation, and the logical sequence number of each buffer is updated through the pointer mark.

[0013] In some embodiments, in the cache data sending step, filling the read data to the set payload size includes: if the total size of the read data is less than the set payload size, using invalid data to fill it to the set payload size; if the total size of the read data is equal to the set payload size, directly forwarding it without filling.

[0014] In a second aspect, an embodiment of the present invention provides a multi-buffer-based obfuscated network data packet assembly and transmission device, the multi-buffer-based obfuscated network data packet assembly and transmission device comprising: A data packet assembly module is configured to set up multiple buffers for a queue of data packets to be sent, extract a data packet from the queue each time, and sequentially determine, in a preset order, whether the free payload space of each buffer can accommodate the data packet. If any buffer can accommodate the data packet, the data packet is stored in the corresponding buffer and the next data packet is extracted from the queue to be sent. If all buffers cannot accommodate the data packet, the module enters a waiting state until a data packet in a buffer is read and sent, and then performs the above-mentioned storage operation again. The cache data sending module is used to lock the multiple buffers at a preset sending time, read all the data in the first buffer, fill the read data to the set payload size, and then forward it to the obfuscation network; after the forwarding is completed, a buffer pointer switching operation is performed, and the subsequent buffers of the previous sending time window are successively advanced as the preceding buffers of the current sending time window, and the original first buffer is switched to the last buffer; after the pointer switching is completed, the multiple buffers are unlocked, and the next sending time is waited for and the cache data sending step is repeated.

[0015] In a third aspect, an embodiment of the present application provides an electronic device comprising a memory and a processor, wherein the memory stores program code that can be run on the processor, and when the program code is executed by the processor, the multi-buffer-based obfuscated network data packet assembly and transmission method as described in any one of the implementation methods of the first aspect is implemented.

[0016] In a fourth aspect, an embodiment of the present application provides a computer storage medium storing one or more programs, which can be executed by an electronic device as described in the third aspect to implement the multi-buffer-based obfuscated network data packet assembly and transmission method as described in any implementation method of the first aspect.

[0017] Embodiments of the present invention provide a method, device, electronic device, and storage medium for assembling and transmitting obfuscated network data packets based on multiple buffers. The method comprises a data packet assembly step and a cached data sending step, wherein: the data packet assembly step comprises: setting multiple buffers for a data packet queue to be sent, extracting a data packet from the queue to be sent each time, and determining in sequence in a preset order whether the free payload space of each buffer can accommodate the data packet; if any buffer can accommodate the data packet, storing the data packet in the corresponding buffer and continuing to extract the next data packet from the queue to be sent; if all buffers cannot accommodate the data packet, entering a waiting state until a data packet in a buffer is read and sent, and then re-performing the above-mentioned storage operation; the cached data sending step comprises: at a preset sending time, locking multiple buffers, reading all data from the first buffer, filling the read data to a set payload size, and then forwarding it to the obfuscated network; after the forwarding is completed, performing a buffer pointer switching operation, and sequentially advancing the subsequent buffers of the previous sending time window to the preceding buffers of the current sending time window, and switching the original first buffer to the last buffer; after the pointer switching is completed, unlocking the multiple buffers, waiting for the next sending time, and repeating the cached data sending step, thereby improving the payload utilization rate by optimizing the data packet assembly and sending logic.

[0018] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Hereinafter, the present invention will be described in more detail based on embodiments with reference to the accompanying drawings.

[0020] Figure 1 A schematic flow chart of an exemplary method for assembling and transmitting obfuscated network data packets based on multiple buffers according to an embodiment of the present invention is shown; Figure 2 FIG2 shows a schematic diagram of an exemplary buffer area for setting a queue for sending data packets proposed in one embodiment of the present invention; Figure 3 An exemplary buffer data packet assembly flow chart proposed in one embodiment of the present invention is shown; Figure 4 A schematic diagram of assembling an exemplary buffer data packet according to an embodiment of the present invention is shown; Figure 5 Another exemplary schematic diagram of assembling a buffer data packet according to an embodiment of the present invention is shown; Figure 6 A schematic diagram of assembling another exemplary buffer data packet according to an embodiment of the present invention is shown; Figure 7 A schematic diagram of assembling another exemplary buffer data packet according to an embodiment of the present invention is shown; Figure 8 An exemplary buffer area data packet sending flow chart proposed in one embodiment of the present invention is shown; Figure 9 A schematic diagram of an exemplary cache pointer switching proposed in one embodiment of the present invention is shown; Figure 10 A schematic diagram of an exemplary typical obfuscated network data packet assembly solution proposed in one embodiment of the present invention is shown; Figure 11 A schematic diagram of an exemplary data packet clipping and reassembly solution proposed in one embodiment of the present invention is shown; Figure 12 The present invention shows a block diagram of a multi-buffer-based obfuscated network data packet assembly and transmission device according to an embodiment of the present invention; Figure 13 A structural block diagram of an electronic device for executing the multi-buffer-based obfuscated network data packet assembly and transmission method according to an embodiment of the present application is shown; Figure 14 A computer-readable storage medium for storing or carrying the multi-buffer-based obfuscated network data packet assembly and transmission method implemented in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0021] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with examples and drawings. The exemplary embodiments of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0022] Obfuscation networks are currently the mainstream anonymous communication infrastructure. Typical obfuscation networks eliminate traffic statistical signatures through traffic normalization and time synchronization strategies, thereby hindering traffic correlation analysis and tracing. Traffic normalization requires packet shaping, primarily through assembly and padding techniques to assemble packets to a fixed size. Time synchronization requires proactively applying delay interference to packet forwarding.

[0023] The current obfuscation network mainly adopts a packet organization method based on invalid data filling. This method assembles multiple packets together as much as possible within each forwarding time window, but the total size of the assembled packets cannot exceed the set standard value. The remaining space is filled to keep each packet at a fixed size. Figure 10The schematic diagram of the exemplary typical obfuscated network data packet assembly scheme shown in the figure shows that within the current time window, data packets 1, 2, 3, and 4 are assembled from the queue to be sent. If 5 is continued to be assembled, the total capacity exceeds the set load capacity upper limit, and the assembled data packets can only be filled to the set capacity and forwarded to the obfuscated network.

[0024] A study has proposed a packet reassembly method based on a custom protocol. This method designs an application layer packet transmission protocol, implements a transmission protocol encapsulation on each original packet, trims and fills it to the set payload capacity before sending it to the obfuscated network. After receiving the payload, the other end decapsulates and restores the packet according to the custom transmission protocol. This solution requires adding a segmentation and reassembly protocol header to each packet, including tags such as the packet session ID, total length, fragment sequence number, payload interval, and payload offset. Figure 11 The diagram below shows an exemplary packet trimming and reassembly scheme. Packet 5 is trimmed and reassembled into the payload space to be sent. However, for effective reassembly, a trimming and reassembly protocol header must be appended to each fragment of packet 5. Furthermore, the complete packet also requires this header for integrity verification and effective reassembly at the peer end. This scheme's additional protocol headers for each packet occupy additional payload space, resulting in limited or even reduced payload space utilization. Therefore, this scheme is not suitable for packet assembly and transmission in obfuscated networks. More efficient assembly methods are needed.

[0025] The applicant's research found that the current obfuscated network data packet transmission mainly adopts a data packet assembly method based on invalid data filling and a data packet reassembly method based on a custom protocol. Both methods have the problem of low payload space utilization, which seriously restricts the improvement of the obfuscated network bandwidth performance indicators.

[0026] In response to the above problems, the applicant proposed a method and device for assembling and transmitting obfuscated network data packets based on multiple buffers: a packet waiting to be sent queue is provided with multiple buffer areas, wherein the embodiment of the application takes three buffer areas as an example for explanation, the data packets to be sent are assembled in the buffer area using the sending time window, and then the data is read from the buffer area at the sending time and sent to the obfuscated network, such as Figure 2 The following figure shows an exemplary diagram of a buffer zone for setting up a queue for sending packets. Sending packets to an obfuscated network involves a packet assembly process and a buffered data transmission process. The following describes the packet assembly logic and buffered data transmission logic in detail through a flowchart and a specific transmission example.

[0027] The data packet assembly logic includes the following steps: See Figure 3An exemplary buffer area data packet assembly flow chart, each time a data packet is extracted from the queue to be sent, attempts are made to store this data packet in buffer area 1, buffer area 2 and buffer area 3 in sequence. If the free load space of the buffer area can accommodate this data packet, then the storage is successful and the next data packet is extracted from the queue to be sent; if there is no space in any of the three buffer areas to accommodate this data packet, then the sending process will enter a waiting state, waiting for the buffer area data packet to be read and sent, and then repeat the above process.

[0028] The following example further illustrates the process of assembling data packets in the three buffer areas. Figure 4 An exemplary buffer area data packet assembly diagram is shown, where data packets numbered 1, 2, 3, and 4 are stored in buffer area 1. At this time, the remaining space in buffer area 1 is insufficient to accommodate data packet 5. According to the assembly logic, an attempt is made to store data packet 5 in buffer area 2. At this time, buffer area 2 has sufficient space, so data packet 5 is stored in buffer area 2. Next, data packets 5 and 6 are stored in the remaining space in buffer area 1. Figure 5 Another exemplary schematic diagram of buffer area data packet assembly is shown.

[0029] like Figure 6 As shown in another exemplary cache data packet assembly diagram, data packets 8, 9, and 10 are successfully stored in cache 2, but the remaining space in cache 2 is not enough to accommodate data packet 11, so data packet 11 is stored in cache 3.

[0030] According to this logic, data packets are continuously extracted into the buffer area until data packet 17 cannot find any storage space in the buffer area. Figure 7 Another exemplary buffer area data packet assembly diagram is shown, in which the buffer area is locked, the data packet assembly behavior is suspended, and the data packet assembly operation is continued after the buffer area data is read and sent.

[0031] The cache data sending logic includes the following steps: The data sending process of the buffer area is as follows Figure 8 An exemplary buffer area data packet sending flowchart is shown. Every time a sending time is reached, the buffer area is first locked, and then all data is read directly from buffer area 1. After that, another process is started to fill the read data to the set payload size, and then sent to the obfuscated network.

[0032] In the buffer area, a pointer switching operation is required after reading data from buffer area 1, such as Figure 9An exemplary buffer pointer switching diagram is shown below. This pointer switching shifts buffers 2 and 3 within the previous send window upward, switching them to buffers 1 and 2, respectively. The original buffer 1 is switched to buffer 3. After the pointer switching operation is complete, the buffers are unlocked, allowing data to be written. The process then repeats itself until the next send window arrives.

[0033] The data packet waiting queue in this application sets multiple buffers, which can be summarized as follows: Data packet extraction and storage judgment: Each time a data packet is extracted from the queue to be sent, it is judged in a preset order whether the free load space of each buffer can accommodate the data packet.

[0034] Store and continue operation: If any buffer can accommodate the data packet, store the data packet in the corresponding buffer and continue to extract the next data packet from the queue to be sent.

[0035] Waiting mechanism: If all buffers cannot accommodate the current data packet, the system enters the waiting state and suspends the data packet extraction and storage operations until a data packet in the buffer is read and sent (free space is released), and then re-executes the above storage judgment and storage operations.

[0036] The steps for sending cached data can be summarized as follows. Based on the time synchronization strategy, the following sending logic is executed at the preset sending time: Buffer lock: Lock all buffers and prohibit writing new data during data reading and pointer switching to ensure data integrity.

[0037] Data reading and forwarding: Read all data in the first buffer. If the total data size is less than the set payload size, use invalid data to fill it to the set size; if it is equal to the set size, forward it directly to the obfuscation network.

[0038] Pointer switching: After forwarding is completed, the buffer pointer switching operation is performed - the subsequent buffers of the previous sending time window are successively advanced to the preceding buffers of the current sending time window, and the original first buffer is switched to the last buffer (during the switching process, the physical position of the unsent data in each buffer remains unchanged, only the logical sequence number is updated through the pointer mark).

[0039] Unlock and wait: After the pointer switching is completed, unlock all buffers (allowing new data to be written), wait for the next preset sending time, and repeat the above sending steps.

[0040] Among them, the buffer preset order is: judge in sequence according to the logical sequence number, that is, judge the free load space of the first buffer first, if it cannot be accommodated, judge the subsequent buffers in sequence, that is, judge the free load space of buffer 1 first, if it cannot be accommodated, judge buffer 2, and finally judge buffer 3.

[0041] The storage example is: Extract data packet 1 from the queue to be sent, determine whether there is enough free space in buffer 1 to accommodate it, and store it in buffer 1; continue to extract data packet 2 and store it in buffer 1 in the same way.

[0042] When the remaining space in the buffer 1 cannot accommodate the data packet 5, it is determined that the free space in the buffer 2 can accommodate the data packet, and the data packet 5 is stored in the buffer 2.

[0043] If there is no free space in buffers 1, 2, and 3 after data packet 17 is extracted, the system enters a waiting state (suspending the extraction of data packets from the queue to be sent until at least one buffer is detected to have new free payload space due to data being read and sent). The system then suspends the extraction of data packets until the next sending moment, when buffer 1 is sent (space is freed up), and then re-determines the storage.

[0044] Waiting state trigger condition: It is triggered only when all buffers cannot accommodate the current data packet, and waits until at least one buffer releases free space due to data sending and then recovers.

[0045] In the embodiment of the present application, the cache data sending step is specifically implemented as follows: Preset sending time trigger: Set the sending time according to the time synchronization strategy.

[0046] Lock operation: After the sending time arrives, buffers 1, 2, and 3 are locked (new data is prohibited from being written to the multiple buffers during data reading and pointer switching), and new data writing is prohibited to ensure that data is not modified during reading and pointer switching.

[0047] Data reading and filling: Read all data in buffer 1. If the total size is the set payload size, fill it with invalid data until it reaches the set size and then forward it. If it is equal to the set size, forward it directly.

[0048] Pointer switching operation (in the buffer pointer switching operation, the position of the unsent data stored in each buffer remains unchanged, and the logical sequence number of each buffer is updated through the pointer mark): After the forwarding is completed, buffer 2 is progressively promoted to the first new buffer 1, buffer 3 is progressively promoted to the subsequent new buffer 2, and the original buffer 1 is switched to the last new buffer 3; After the switch, the unsent data packets in the original buffer 2 still maintain their physical storage location, and are only marked with their logical sequence number as buffer 1 through the pointer.

[0049] Unlock operation: After the pointer switching is completed, all buffers are unlocked (new data can be written to the multiple buffers after switching), new data packets can be written into the new buffers 1, 2, and 3, and wait for the next sending time.

[0050] In the embodiment of the present application, the number of buffers is preferably 3, which can be adjusted according to the actual load size and data packet frequency, but it is necessary to ensure that the number is met to achieve progressive switching.

[0051] Among them, the filling rule only fills the first buffer data when sending, and only fills invalid data to avoid occupying the payload space.

[0052] Pointer switching enables buffer recycling by updating logical sequence numbers, eliminating the need for physical data migration and reducing operational overhead.

[0053] In summary, compared with the prior art, this application has at least the following beneficial effects: This application reduces the amount of invalid data filling through dynamic assembly of multiple buffers; there is no need to attach an additional reorganization protocol header to each data packet, thus avoiding waste of payload space and effectively improving payload space utilization.

[0054] Based on the assembly and pointer switching logic of multiple buffers, the payload space is maximized within the time synchronization window, the bandwidth occupied by invalid data is reduced, and the bandwidth performance of the obfuscated network is significantly improved.

[0055] Data packet assembly and transmission are achieved through lightweight operations such as preset order storage and pointer switching, without the need for complex protocol encapsulation, adapting to the needs of obfuscated networks for lightweight transmission.

[0056] See also Figure 12 , Figure 12 The structure block diagram of the multi-buffer-based obfuscated network data packet assembly and transmission device 300 provided by the present invention includes: a data packet assembly module 310 and a cached data sending module 320, wherein: The data packet assembly module 310 is configured to set up multiple buffers for the data packet queue to be sent. Each time a data packet is extracted from the queue to be sent, the module determines in a predetermined order whether the free payload space of each buffer can accommodate the data packet. If any buffer can accommodate the data packet, the module stores the data packet in the corresponding buffer and continues to extract the next data packet from the queue to be sent. If all buffers cannot accommodate the data packet, the module enters a waiting state until a data packet in a buffer is read and sent, and then performs the above storage operation again. The cache data sending module 320 is used to lock the multiple buffers at a preset sending time, read all the data in the first buffer, fill the read data to the set payload size, and then forward it to the obfuscation network; after the forwarding is completed, the buffer pointer switching operation is performed, and the subsequent buffers of the previous sending time window are successively advanced as the preceding buffers of the current sending time window, and the original first buffer is switched to the last buffer; after the pointer switching is completed, the multiple buffers are unlocked, and the next sending time is waited for and the cache data sending step is repeated.

[0057] It should be noted that the device embodiment of the present invention corresponds to the aforementioned method embodiment. The specific principles in the device embodiment can be found in the contents of the aforementioned method embodiment, which will not be repeated here.

[0058] In several embodiments provided in this embodiment, the coupling between modules may be electrical, mechanical or other forms of coupling.

[0059] In addition, the functional modules in various embodiments of the present invention may be integrated into a single processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module. The aforementioned integrated modules may be implemented in the form of hardware or software functional modules.

[0060] See also Figure 13 , Figure 13 The present application provides a structural block diagram of an electronic device 200 that can execute the above-mentioned multi-buffer-based obfuscated network data packet assembly and transmission method. The electronic device 200 can be a smart phone, tablet computer, computer, portable computer or other device.

[0061] The electronic device 200 further includes a processor 202 and a memory 204 . The memory 204 stores a program that can execute the contents of the aforementioned embodiments, and the processor 202 can execute the program stored in the memory 204 .

[0062] The processor 202 may include one or more cores for processing data and a message matrix unit. The processor 202 utilizes various interfaces and circuits to connect various components within the electronic device 200. It executes instructions, programs, code sets, or instruction sets stored in the memory 204, and accesses data stored in the memory 204 to perform various functions and process data within the electronic device 200. Optionally, the processor 202 may be implemented in hardware using at least one of a digital signal processing (DSP), a field-programmable gate array (FPGA), and a programmable logic array (PLA). The processor 202 may integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), and a modem (decoder). The CPU primarily handles the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing display content; and the modem handles wireless communications. It is understood that the modem (decoder) may also be implemented independently of the processor using a separate communications chip.

[0063] Memory 204 may include random access memory (RAM) or read-only memory (ROM). Memory 204 may be used to store instructions, programs, code, code sets, or instruction sets. Memory 204 may include a program storage area and a data storage area. The program storage area may store instructions for implementing an operating system, instructions for implementing at least one function (e.g., instructions for a user to obtain a random number), instructions for implementing the various method embodiments described below, and the like. The data storage area may also store data (e.g., random numbers) generated by the terminal during use.

[0064] The electronic device 200 may also include a network module and a screen. The network module is used to receive and transmit electromagnetic waves, converting them into electrical signals, thereby communicating with a communications network or other devices, such as an audio playback device. The network module may include various existing circuit components for performing these functions, such as an antenna, a radio frequency transceiver, a digital signal processor, an encryption / decryption chip, a subscriber identity module (SIM) card, memory, and the like. The network module can communicate with various networks such as the Internet, an intranet, or a wireless network, or with other devices via a wireless network. These wireless networks may include cellular telephone networks, wireless local area networks, or metropolitan area networks. The screen can display interface content and facilitate data exchange.

[0065] Please refer to Figure 14 , Figure 14 The computer-readable storage medium 400 stores program code 410, which can be called by a processor to execute the method described in the above method embodiment.

[0066] Computer-readable storage medium 400 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM, hard disk, or ROM. Alternatively, the computer-readable storage medium includes a non-transitory computer-readable storage medium. Computer-readable storage medium 400 has storage space for program code 410 for executing any of the method steps described above. This program code 410 can be read from or written to one or more computer program products. Program code 410 may be compressed, for example, in a suitable format.

[0067] The present application also provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the multi-buffer-based obfuscated network data packet assembly and transmission method described in the various optional implementations above.

[0068] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not drive the essence of the corresponding technical solutions away from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for assembling and transmitting obfuscated network data packets based on multiple buffers, characterized in that: The method comprises: a data packet assembling step and a buffered data sending step, wherein: The data packet assembling step includes: setting a plurality of buffers for a data packet queue to be sent, extracting a data packet from the queue to be sent each time, determining in a predetermined order whether the free load space of each buffer can accommodate the data packet; if any buffer can accommodate the data packet, storing the data packet in the corresponding buffer and continuing to extract the next data packet from the queue to be sent; if all buffers cannot accommodate the data packet, entering a waiting state until a data packet in a buffer is read and sent, and then re-performing the above-mentioned storage operation; The cached data sending step includes: at a preset sending time, locking the multiple buffers, reading all data in the first buffer, filling the read data to the set payload size and then forwarding it to the obfuscation network; after the forwarding is completed, performing a buffer pointer switching operation, and sequentially advancing the subsequent buffers of the previous sending time window as the preceding buffers of the current sending time window, and switching the original first buffer to the last buffer; after the pointer switching is completed, unlocking the multiple buffers, waiting for the next sending time and repeating the cached data sending step.

2. The method for assembling and transmitting obfuscated network data packets based on multiple buffers according to claim 1, characterized in that: The plurality of buffer zones are three buffer zones and are physically isolated.

3. The method for assembling and transmitting obfuscated network data packets based on multiple buffers according to claim 1, characterized in that: The preset sequence in the data packet assembly step includes: proceeding in sequence according to the logical sequence number of each buffer zone, giving priority to determining the free load space of the first buffer zone, and if it cannot accommodate, determining subsequent buffer zones in sequence.

4. The method for assembling and transmitting obfuscated network data packets based on multiple buffers according to claim 1, characterized in that: The waiting state in the data packet assembling step includes: pausing the extraction of data packets from the queue to be sent until it is detected that new idle payload space is generated in at least one buffer due to data being read and sent.

5. The method for assembling and transmitting obfuscated network data packets based on multiple buffers according to claim 1, characterized in that: Locking the multiple buffers in the cache data sending step includes: prohibiting new data from being written to the multiple buffers during data reading and pointer switching; unlocking the multiple buffers in the cache data sending step includes: allowing new data to be written to the multiple buffers after switching.

6. The method for assembling and transmitting obfuscated network data packets based on multiple buffers according to claim 1, characterized in that: During the buffer pointer switching operation, the position of the unsent data stored in each buffer remains unchanged, and the logical sequence number of each buffer is updated through the pointer mark.

7. The method for assembling and transmitting obfuscated network data packets based on multiple buffers according to claim 1, characterized in that: In the cache data sending step, filling the read data to the set payload size includes: if the total size of the read data is less than the set payload size, using invalid data to fill it to the set payload size; if the total size of the read data is equal to the set payload size, directly forwarding it without filling.

8. A multi-buffer based obfuscated network data packet assembly and transmission device, characterized in that: The device comprises: A data packet assembly module is configured to set up multiple buffers for a queue of data packets to be sent, extract a data packet from the queue each time, and sequentially determine, in a preset order, whether the free payload space of each buffer can accommodate the data packet. If any buffer can accommodate the data packet, the data packet is stored in the corresponding buffer and the next data packet is extracted from the queue to be sent. If all buffers cannot accommodate the data packet, the module enters a waiting state until a data packet in a buffer is read and sent, and then performs the above-mentioned storage operation again. The cache data sending module is used to lock the multiple buffers at a preset sending time, read all the data in the first buffer, fill the read data to the set payload size, and then forward it to the obfuscation network; after the forwarding is completed, a buffer pointer switching operation is performed, and the subsequent buffers of the previous sending time window are successively advanced as the preceding buffers of the current sending time window, and the original first buffer is switched to the last buffer; after the pointer switching is completed, the multiple buffers are unlocked, and the next sending time is waited for and the cache data sending step is repeated.

9. An electronic device, characterized in that: The electronic device includes a memory and a processor, wherein the memory stores program code that can be run on the processor. When the program code is executed by the processor, the multi-buffer-based obfuscated network data packet assembly and transmission method as described in any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores program code, and the program code can be called by one or more processors to execute the multi-buffer-based obfuscated network data packet assembly and transmission method according to any one of claims 1 to 7.

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