Method and apparatus for assembling and transmitting obfuscated network packets based on multiple buffers

Abstract

The application discloses a kind of based on multiple buffer's obfuscated network packet assembly transmission method and device, the method, including, data packet assembly step and cache data sending step;Data packet assembly step: multiple buffer is set for data packet to be sent queue, extract a data packet from to-be-sent queue each time, whether the idle load space of each buffer can accommodate the data packet in turn according to preset order is judged, can accommodate then store and continue to extract next;When all buffer cannot accommodate, enter waiting state until the data of buffer is read and sent, and then re-execute storage;Cache data sending step: multiple buffer is locked at preset sending time, read first buffer data and fill to the size of set load after forwarding to obfuscated network;After forwarding is completed, execute buffer pointer switching, unlock buffer and wait for the next sending time to repeat sending, improve payload utilization by optimizing data packet assembly and sending logic.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of obfuscated network communication, and in particular to an obfuscated network data packet assembly and transmission method and device based on multiple buffers. BACKGROUND

[0002] As the core infrastructure of anonymous communication, obfuscated networks eliminate traffic statistical characteristics through traffic normalization and time synchronization strategies to resist traffic correlation analysis tracing. Traffic normalization requires shaping (such as assembly, padding) of data packets for fixed-size transmission, and time synchronization requires imposing delay interference on forwarding behavior.

[0003] Existing obfuscated network data packet transmission mainly adopts two methods:

[0004] I. Assemble multiple data packets within a forwarding time window, and if the total size does not reach the specified specification value, fill with invalid data to a fixed size. This method occupies payload space with invalid data, resulting in low payload utilization.

[0005] II. Encapsulate a custom protocol (including session ID, fragment sequence number, offset, etc. packet header) on the original data packet, and transmit after trimming and padding. However, the protocol header occupies additional payload space, even reducing payload utilization, which is not suitable for obfuscated networks.

[0006] Both of the above methods have the problem of low payload space utilization, which seriously restricts the improvement of obfuscated network bandwidth performance. SUMMARY

[0007] In view of the above problems, the present application provides an obfuscated network data packet assembly and transmission method and device based on multiple buffers, which optimizes the data packet assembly and sending logic to improve the payload utilization.

[0008] In a first aspect, the present application embodiment provides an obfuscated network data packet assembly and transmission method based on multiple buffers, comprising a data packet assembly step and a buffered data sending step, wherein:

[0009] The data packet assembly step includes setting multiple buffers for a data packet to-be-sent queue, extracting one data packet from the to-be-sent queue each time, and sequentially judging whether each buffer can accommodate the data packet in a predetermined order. If any buffer can accommodate the data packet, the data packet is stored in the corresponding buffer and the next data packet is extracted from the to-be-sent queue. If all buffers cannot accommodate the data packet, the system enters a waiting state until the data packet in a buffer is read and sent, and then the above storage operation is performed again.

[0010] The cache data sending step comprises: locking the plurality of buffers at a preset sending time, reading all data of the first buffer, filling the read data to a set load size, and forwarding the filled data to the obfuscation network; after the forwarding is completed, performing a buffer pointer switching operation, sequentially advancing the subsequent buffers of the previous sending time window to the preceding buffers of the current sending time window, and switching the original first buffer to the last buffer; after the pointer switching is completed, unlocking the plurality of buffers, waiting for the next sending time, and repeating the cache data sending step.

[0011] In some embodiments, the plurality of buffers are three buffers and are physically isolated.

[0012] In some embodiments, the preset order in the data packet assembling step comprises: sequentially performing according to the logical serial numbers of the buffers, preferentially judging the free load space of the first buffer, and sequentially judging the subsequent buffers if the first buffer cannot accommodate.

[0013] In some embodiments, the waiting state in the data packet assembling step comprises: suspending the extraction of data packets from the to-be-sent queue until at least one buffer generates a new free load space due to the reading and sending of data.

[0014] In some embodiments, the locking of the plurality of buffers in the cache data sending step comprises: prohibiting the writing of new data to the plurality of buffers during the data reading and pointer switching; and the unlocking of the plurality of buffers in the cache data sending step comprises: allowing the writing of new data to the plurality of buffers after the switching.

[0015] In some embodiments, in the buffer pointer switching operation, the positions of the stored unsent data in each buffer remain unchanged, and the logical serial numbers of the buffers are updated by pointer marking.

[0016] In some embodiments, in the cache data sending step, the filling of the read data to the set load size comprises: if the total size of the read data is smaller than the set load size, filling invalid data to the set load size; and if the total size of the read data is equal to the set load size, directly forwarding without filling.

[0017] In a second aspect, an embodiment of the present application provides a multi-buffer-based obfuscation network data packet assembling and transmitting device, which comprises:

[0018] The data packet assembling module is configured to set a plurality of buffer areas for a data packet to-be-sent queue, extract one data packet from the to-be-sent queue each time, and determine in a preset order whether each buffer area can accommodate the data packet. If any buffer area can accommodate the data packet, the data packet is stored in the corresponding buffer area, and the next data packet is extracted from the to-be-sent queue. If all buffer areas cannot accommodate the data packet, a waiting state is entered until the data packet in a buffer area is read and sent, and the above storage operation is performed again.

[0019] The cache data sending module is configured to lock the plurality of buffer areas at a preset sending time, read all data in the first buffer area, fill the read data to a set load size, and then forward the filled data to the obfuscation network. After the forwarding is completed, a buffer pointer switching operation is performed, the subsequent buffer areas of the previous sending time window are sequentially advanced to the previous buffer areas of the current sending time window, and the original first buffer area is switched to the last buffer area. After the pointer switching is completed, the plurality of buffer areas are unlocked, the next sending time is waited, and the cache data sending step is repeated.

[0020] In a third aspect, an electronic device is provided, which includes a memory and a processor. The memory stores program code executable on the processor. When the program code is executed by the processor, the program code implements the method for assembling and transmitting data packets of an obfuscation network based on multiple buffer areas as introduced in any of the embodiments of the first aspect.

[0021] In a fourth aspect, a computer storage medium is provided, which stores one or more programs. The one or more programs can be executed by the electronic device as introduced in the third aspect to implement the method for assembling and transmitting data packets of an obfuscation network based on multiple buffer areas as introduced in any of the embodiments of the first aspect.

[0022] The embodiment of the application provides a multi-buffer-based obfuscated network packet assembly transmission method, device, electronic equipment and storage medium, the multi-buffer-based obfuscated network packet assembly transmission method comprises a packet assembly step and a cache data sending step, wherein: the packet assembly step comprises the following steps: a plurality of buffer areas are set for a data packet to-be-sent queue, one data packet is extracted from the to-be-sent queue each time, whether the idle load space of each buffer area can accommodate the data packet is judged in a preset order in sequence, if any buffer area can accommodate, the data packet is stored in the corresponding buffer area, and the next data packet is continuously extracted from the to-be-sent queue; if all buffer areas cannot accommodate, a waiting state is entered, and the above storage operation is re-executed after the data packet of the buffer area is read and sent; the cache data sending step comprises the following steps: at a preset sending moment, a plurality of buffer areas are locked, all data of the first buffer area is read, the read data is filled to a set load size, and then forwarded to an obfuscated network; after the forwarding is completed, a buffer pointer switching operation is performed, the subsequent buffer area of the last sending time window is sequentially advanced to the previous buffer area of the current sending time window, and the original first buffer area is switched to the last buffer area; after the pointer switching is completed, the plurality of buffer areas are unlocked, the cache data sending step is repeated at the next sending moment, and the effective load utilization rate is improved by optimizing the data packet assembly and sending logic.

[0023] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the application, nor is it used to limit the scope of the application. Other features of the application will become apparent through the following description. BRIEF DESCRIPTION OF DRAWINGS

[0024] The application will be described in more detail below based on embodiments and with reference to the drawings.

[0025] Figure 1 An exemplary multi-buffer-based obfuscated network packet assembly transmission method flow diagram proposed in an embodiment of the application is shown;

[0026] Figure 2 An exemplary data packet to-be-sent queue buffer area setting diagram proposed in an embodiment of the application is shown;

[0027] Figure 3 An exemplary cache area data packet assembly flow diagram proposed in an embodiment of the application is shown;

[0028] Figure 4 An exemplary cache area data packet assembly diagram proposed in an embodiment of the application is shown;

[0029] Figure 5 Another exemplary cache area data packet assembly diagram proposed in an embodiment of the application is shown;

[0030] Figure 6 Figure 6 shows another exemplary buffer data packet assembly diagram proposed in an embodiment of the present application;

[0031] Figure 7 Figure 7 shows still another exemplary buffer data packet assembly diagram proposed in an embodiment of the present application;

[0032] Figure 8 Figure 8 shows an exemplary buffer data packet sending flow chart proposed in an embodiment of the present application;

[0033] Figure 9 Figure 9 shows an exemplary buffer pointer switching diagram proposed in an embodiment of the present application;

[0034] Figure 10 Figure 10 shows an exemplary typical obfuscated network data packet assembly scheme diagram proposed in an embodiment of the present application;

[0035] Figure 11 Figure 11 shows an exemplary data packet assembly scheme diagram after data packet pruning proposed in an embodiment of the present application;

[0036] Figure 12 Figure 12 shows a structural block diagram of an obfuscated network data packet assembly and transmission device based on multiple buffers proposed in an embodiment of the present application;

[0037] Figure 13 Figure 13 shows a structural block diagram of an electronic device for performing the obfuscated network data packet assembly and transmission method based on multiple buffers according to an embodiment of the present application;

[0038] Figure 14 Figure 14 shows a computer readable storage medium for storing or carrying the obfuscated network data packet assembly and transmission method based on multiple buffers according to an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to make the objectives, technical solutions and advantages of the present application clearer, further detailed description will be given below in combination with embodiments and drawings. The exemplary embodiments of the present application and the description thereof are only used to explain the present application and do not limit the present application.

[0040] An obfuscated network is a current mainstream anonymous communication infrastructure. A typical obfuscated network eliminates traffic statistical characteristics through traffic normalization and time synchronization strategies, thereby resisting traffic correlation analysis tracing. The traffic normalization strategy requires data packet shaping, mainly using assembly and padding technical means to assemble data packets into a fixed size. The time synchronization strategy requires actively imposing delay interference on data packet forwarding behavior.

[0041] Current confusion network mainly adopts a data packet organization method based on invalid data padding. In this method, as many data packets as possible are assembled together within each forwarding time window, but the total size of the assembled data packets cannot exceed the specified specification value. The remaining space is filled by padding means to keep each data packet at a fixed size. The data packet assembly scheme based on invalid data padding is shown in the example typical confusion network data packet assembly scheme diagram of Figure 10 As shown in the example, in the current time window, data packets 1, 2, 3, and 4 are assembled from the to-be-sent queue. If data packet 5 is continued to be assembled, the total capacity exceeds the upper limit of the set load capacity, and only the assembled data packet can be padded to the set capacity and forwarded to the confusion network.

[0042] Some studies have proposed a data packet reassembly method based on a custom protocol. This method designs an application layer data packet transmission protocol, encapsulates each original data packet with the transmission protocol, and trims and pads the data packet to the set load capacity before sending it to the confusion network. The receiving end receives the load and performs data packet unencapsulation and recovery according to the custom transmission protocol. This scheme requires adding a segmentation and reassembly protocol header to each data packet, including data packet session id, total length, fragment number, payload interval, and payload offset. As shown in Figure 11 As shown in the example, data packet 5 is assembled into the to-be-sent load space after being trimmed. However, in order to effectively reassemble, the fragments of data packet 5 need to be appended with a trimming and reassembly protocol header. In addition, the complete data packet also needs to be appended with this header to perform integrity verification and effective reassembly at the receiving end. This scheme occupies additional load space for each data packet with the protocol header, which limits the improvement of load space utilization and even reduces it. Therefore, it is not suitable for confusion network data packet assembly and transmission, and other more efficient assembly methods need to be designed.

[0043] Applicant's research has found that current confusion network data packet transmission mainly uses a data packet assembly method based on invalid data padding and a data packet reassembly method based on a custom protocol. Both methods have low load space utilization, which severely restricts the improvement of confusion network bandwidth performance indicators.

[0044] To solve the above problems, the applicant proposes a confusion network data packet assembly and transmission method and device based on multiple buffer areas. In this method, a plurality of buffer areas are set in the to-be-sent queue. In this embodiment, three buffer areas are used as an example to illustrate the assembly of data packets in the buffer areas using the sending time window, and then reading the data from the buffer area at the sending time and sending it to the confusion network. As shown in Figure 2 An example of a data packet to-be-sent queue setting buffer area diagram is shown. Data packet transmission to the confusion network involves data packet assembly and cache data transmission processes. The data packet assembly logic and cache data transmission logic are described in detail below through flowcharts and specific transmission examples.

[0045] The data packet assembly logic includes the following steps:

[0046] See Figure 3 An exemplary flowchart of buffer data packet assembly shows that after each data packet is retrieved from the queue to be sent, the data packet is sequentially attempted to be stored in buffer 1, buffer 2, and buffer 3. If the free payload space of the buffer can accommodate the data packet, the storage is successful, and the next data packet is retrieved from the queue to be sent. If none of the three buffers have space to accommodate the data packet, the sending process will enter a waiting state, waiting for the data packet in the buffer to be read and sent before repeating the above process.

[0047] The following example further illustrates the packet assembly process across the three buffers. (See also...) Figure 4 A schematic diagram of an exemplary buffer packet assembly shows that packets numbered 1, 2, 3, and 4 are saved to buffer 1. At this point, the remaining space in buffer 1 is insufficient to accommodate packet 5. Following the assembly logic, an attempt is made to store packet 5 in buffer 2. Since buffer 2 has sufficient space, packet 5 is stored there. Next, packets 5 and 6 are saved to the remaining space in buffer 1. (See attached diagram.) Figure 5 Another exemplary diagram of buffer packet assembly is shown.

[0048] like Figure 6 The diagram shows another exemplary buffer packet assembly. Next, packets 8, 9, and 10 are successfully stored in buffer 2. However, the remaining space in buffer 2 is insufficient to accommodate packet 11, so packet 11 is stored in buffer 3.

[0049] This logic continues to extract data packets into the buffer until data packet 17 can no longer find any storage space in the buffer. Figure 7 The diagram shows another exemplary buffer packet assembly diagram. In this case, the buffer is locked, the packet assembly behavior is paused, and the packet assembly operation will continue after the buffer data is read and sent.

[0050] The logic for sending cached data includes the following steps:

[0051] The data sending process of the buffer is as follows Figure 8 The diagram shows an exemplary buffer packet sending flowchart. At each sending time, the buffer is first locked, and then all data is read directly from buffer 1. After that, another process is started to fill the read data into the set payload size and then send it to the obfuscated network.

[0052] Within the buffer, after reading data from buffer 1, a pointer switch operation is required, such as...Figure 9 An exemplary buffer pointer switching diagram is shown. The pointer switching moves the buffer 2 and buffer 3 in the last sending time window upward, respectively switching to buffer 1 and buffer 2, and the original buffer 1 switches to buffer 3. After the pointer switching operation is completed, the buffer is unlocked, allowing data to be written, waiting for the next sending time window, and repeating the process.

[0053] The data packet to be sent queue in the present application sets multiple buffers, which are summarized as implementing data packet assembly through the following logic:

[0054] Data packet extraction and storage judgment: each time a data packet is extracted from the to-be-sent queue, it is judged in turn whether each buffer can accommodate the data packet according to the preset order.

[0055] Storage and continue operation: if any buffer can accommodate, the data packet is stored in the corresponding buffer, and the next data packet is extracted from the to-be-sent queue.

[0056] Waiting mechanism: if all buffers cannot accommodate the current data packet, enter the waiting state, suspend the data packet extraction and storage operation, until the data packet in the buffer is read and sent (freeing the idle space), and then re-execute the storage judgment and storage operation.

[0057] The cache data sending step is summarized as the following logic, based on the time synchronization strategy, the following sending logic is executed at the preset sending time:

[0058] Buffer locking: lock all buffers, prohibit writing new data during data reading and pointer switching, and ensure data integrity.

[0059] Data reading and forwarding: read all data in the first buffer, if the total size of the data is less than the set load size, fill the set size with invalid data; if it is equal to the set size, directly forward to the confusion network.

[0060] Pointer switching: after forwarding, perform the buffer pointer switching operation —— sequentially advance the subsequent buffers of the last sending time window to the previous buffers of the current sending time window, and switch the original first buffer to the last buffer (during the switching process, the physical position of the unsent data in each buffer does not change, only the logical sequence number is updated by pointer marking).

[0061] Unlocking and waiting: after the pointer switching is completed, all buffers are unlocked (allowing new data to be written), and waiting for the next preset sending time, repeating the above sending step.

[0062] The preset order of the buffer area is: judging in logical sequence, that is, judging in logical sequence of each buffer area, preferentially judging the free load space of the first buffer area, if it cannot be accommodated, then judging the subsequent buffer area, that is, preferentially judging the free load space of the buffer area 1, if it cannot be accommodated, then judging the buffer area 2, and finally judging the buffer area 3.

[0063] The storage example is:

[0064] The data packet 1 is extracted from the to-be-sent queue, it is judged that the free space of the buffer area 1 can be accommodated, and is stored in the buffer area 1; the data packet 2 is continuously extracted, and is stored in the buffer area 1 in the same way.

[0065] When the remaining space of the buffer area 1 cannot accommodate the data packet 5, it is judged that the free space of the buffer area 2 can be accommodated, and the data packet 5 is stored in the buffer area 2.

[0066] If the data packet 17 is extracted, the buffer areas 1, 2 and 3 all have no free space, and the waiting state is entered (the extraction of the data packet from the to-be-sent queue is paused until at least one buffer area generates a new free load space due to data being read and sent) - the extraction of the data packet is paused until the data in the buffer area 1 is sent (space is released) at the next sending time, and the storage is re-judged.

[0067] The waiting state triggering condition is that the waiting state is triggered only when all the buffer areas cannot accommodate the current data packet, and the waiting state is restored after at least one buffer area releases the free space due to data sending.

[0068] In the embodiment of the application, the cache data sending step is specifically implemented as:

[0069] The preset sending time trigger is set according to a time synchronization strategy.

[0070] The locking operation is that after the sending time arrives, the buffer areas 1, 2 and 3 are locked (new data is prohibited from being written into the buffer areas during the data reading and pointer switching processes), new data writing is prohibited, and it is ensured that the data is not modified during the data reading and pointer switching processes.

[0071] The data reading and filling are that all the data in the buffer area 1 is read, if the total size is a set load size, then invalid data is filled to the set size and is forwarded, and if the total size is equal to the set size, then the data is directly forwarded.

[0072] The pointer switching operation (in the buffer area pointer switching operation, the positions of the stored unsent data in each buffer area remain unchanged, and the logical sequence numbers of the buffer areas are updated through the pointer mark):

[0073] After the forwarding is completed, the buffer area 2 is advanced to the first new buffer area 1, the buffer area 3 is advanced to the subsequent new buffer area 2, and the original buffer area 1 is switched to the last new buffer area 3.

[0074] After switching, the data packets not sent in the original buffer 2 still keep the physical storage location, and only the logical sequence number is marked by the pointer for the buffer 1.

[0075] Unlocking operation: after the pointer switching is completed, all the buffers are unlocked (allowing new data to be written to the switched multiple buffers), allowing new data packets to be written to the new buffers 1, 2, and 3, and waiting for the next sending time.

[0076] In the embodiment of the application, the number of buffers is preferably 3, which can be adjusted according to the actual load size and data packet frequency, but needs to be ensured to meet the number to realize progressive switching.

[0077] Among them, the filling rule only fills the first buffer data when sending, and only fills invalid data to avoid occupying the payload space.

[0078] The pointer switching realizes the cyclic utilization of the buffer through the logical sequence number update, without the need for physical data migration, reducing the operation overhead.

[0079] In summary, the application has at least the following beneficial effects compared with the prior art:

[0080] The application reduces the amount of invalid data filling through dynamic assembly of multiple buffers; without the need for adding an additional recombination protocol packet header for each data packet, avoiding the waste of payload space, and effectively improving the payload space utilization.

[0081] Based on the assembly of multiple buffers and the pointer switching logic, the payload space is maximized within the time synchronization window, the invalid data occupies less bandwidth, and the performance of the obfuscation network is significantly improved.

[0082] Through the lightweight operations such as preset order storage and pointer switching, data packet assembly and sending are realized without complex protocol encapsulation, which meets the needs of the obfuscation network for lightweight transmission.

[0083] Please refer to Figure 12 , Figure 12 The structure block diagram of the obfuscation network data packet assembly and transmission device 300 based on multiple buffers provided by the application comprises a data packet assembly module 310 and a cache data sending module 320, wherein:

[0084] The data packet assembly module 310 is used to set multiple buffers for a data packet to-be-sent queue, extract one data packet from the to-be-sent queue each time, and judge whether the idle payload space of each buffer can accommodate the data packet in turn according to the preset order. If any buffer can accommodate the data packet, the data packet is stored in the corresponding buffer, and the next data packet is extracted from the to-be-sent queue; if all the buffers cannot accommodate the data packet, the storage operation is re-executed after the data packet in the buffer is read and sent.

[0085] The cache data sending module 320 is configured to, at a preset sending moment, lock the plurality of buffer areas, read all data of the first buffer area, and fill the read data to a set load size and then forward the data to the obfuscation network; after the forwarding is completed, perform a buffer area pointer switching operation, sequentially advance the subsequent buffer areas of the previous sending time window to the previous buffer areas of the current sending time window, and switch the original first buffer area to the last buffer area; after the pointer switching is completed, unlock the plurality of buffer areas, wait for the next sending moment, and repeat the cache data sending step.

[0086] It should be noted that the device embodiments in the present application correspond to the foregoing method embodiments, and the specific principles in the device embodiments can be referred to the content in the foregoing method embodiments, which will not be described here again.

[0087] In several embodiments provided in the present embodiment, the coupling between the modules can be electrical, mechanical or other forms of coupling.

[0088] In addition, each functional module in each embodiment of the present application can be integrated in one processing module, or each module can exist physically alone, or two or more modules can be integrated in one module. The integrated module can be realized in the form of hardware or in the form of a software functional module.

[0089] Please refer to Figure 13 , Figure 13 A structural block diagram of an electronic device 200 that can execute the foregoing obfuscation network packet assembly and transmission method based on multiple buffer areas is provided for the embodiments of the present application. The electronic device 200 can be a smart phone, a tablet computer, a computer, a portable computer or the like.

[0090] The electronic device 200 further includes a processor 202 and a memory 204. The memory 204 stores a program that can execute the content in the foregoing embodiments, and the processor 202 can execute the program stored in the memory 204.

[0091] The processor 202 can include one or more cores for processing data and a message matrix unit. The processor 202 connects various parts within the entire electronic device 200 by various interfaces and lines, executes various functions of the electronic device 200 and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 204, and calling data stored in the memory 204. Alternatively, the processor 202 can be implemented in at least one of a hardware form of a digital signal processing (DSP), a field-programmable gate array (FPGA), a programmable logic array (PLA). The processor 202 can be integrated with one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. Among them, the CPU mainly processes an operating system, a user interface, and an application program; the GPU is responsible for rendering and drawing display content; and the modem is used for processing wireless communication. It can be understood that the above-mentioned modem can also not be integrated into the processor, but can be implemented by a separate communication chip.

[0092] The memory 204 can include a random access memory (RAM) and can also include a read-only memory (ROM). The memory 204 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 204 can include a program storage area and a data storage area, wherein the program storage area can store instructions for implementing an operating system, instructions for implementing at least one function (such as instructions for obtaining a random number by a user), and instructions for implementing various method embodiments described below. The data storage area can also store data created by the terminal in use (such as random numbers) and the like.

[0093] The electronic device 200 can also include a network module for receiving and sending electromagnetic waves, converting electromagnetic waves and electrical signals to each other, and thus communicating with a communication network or other devices, such as an audio playing device. The network module can include various existing circuit elements for performing these functions, such as an antenna, a radio frequency transceiver, a digital signal processor, an encryption / decryption chip, a subscriber identity module (SIM) card, a memory, and the like. The network module can communicate with various networks, such as the Internet, an intranet, a wireless network, or other devices through the wireless network. The wireless network can include a cellular phone network, a wireless local area network, or a metropolitan area network. The screen can display interface content and interact with data.

[0094] Reference is made to Figure 14 , Figure 14 A structure block diagram of a computer readable storage medium provided by an embodiment of the present application is shown. The computer readable storage medium 400 stores program codes 410, which can be invoked by a processor to execute the methods described in the above method embodiments.

[0095] The computer readable storage medium 400 can be an electronic storage such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk, or a ROM. Alternatively, the computer readable storage medium includes a non-transitory computer readable medium. The computer readable storage medium 400 has a storage space for the program codes 410 for executing any of the above methods. These program codes 410 can be read from or written to one or more computer program products. The program codes 410 can be compressed in an appropriate form, for example.

[0096] The embodiments of the present application also provide a computer program product or a computer program, which includes computer instructions stored in a computer readable storage medium. A processor of a computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to make the computer device perform the multi-buffer based obfuscated network packet assembly and transmission method described in the various optional implementation manners.

[0097] The above examples are only used to illustrate the technical solutions of the present application, and are not intended to limit the present application; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art will understand that the technical solutions recorded in the foregoing examples can be modified, or some technical features can be replaced by equivalent features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A multi-buffer based obfuscated network packet assembly transmission method, characterized in that, The method comprises a data packet assembling step and a cache data sending step, wherein: the data packet assembling step comprises: setting multiple buffer areas for a data packet to-be-sent queue, wherein the multiple buffer areas are three buffer areas and are physically isolated, extracting one data packet from the to-be-sent queue each time, judging whether the idle load space of each buffer area can accommodate the data packet in a preset order in sequence, if any buffer area can accommodate the data packet, storing the data packet to the corresponding buffer area and continuing to extract the next data packet from the to-be-sent queue, and if all buffer areas cannot accommodate the data packet, entering a waiting state until the data packet of a buffer area is read and sent to re-execute the above storage operation; the cache data sending step comprises: locking the multiple buffer areas at a preset sending time, including: prohibiting writing new data to the multiple buffer areas in the data reading and pointer switching process, reading all data of the first buffer area, filling the read data to a set load size and then forwarding the read data to a confusion network, wherein filling the read data to the set load size comprises: if the total size of the read data is smaller than the set load size, filling invalid data to the set load size; if the total size of the read data is equal to the set load size, directly forwarding without filling; after the forwarding is completed, performing a buffer area pointer switching operation, in which the positions of the stored unsent data in each buffer area remain unchanged, the logical serial numbers of the buffer areas are updated by a pointer mark, the subsequent buffer areas of the last sending time window are sequentially advanced to the previous buffer areas of the current sending time window, and the original first buffer area is switched to the last buffer area; and after the pointer switching is completed, unlocking the multiple buffer areas, including: allowing writing new data to the switched multiple buffer areas, waiting for the next sending time and repeating the cache data sending step.

2. The multi-buffer based obfuscated network packet assembly transmission method of claim 1, wherein, The preset order in the data packet assembling step comprises: judging the idle load space of the first buffer area in priority in sequence according to the logical serial numbers of the buffer areas, and judging the idle load space of the subsequent buffer areas in sequence if the first buffer area cannot accommodate the data packet.

3. The multi-buffer based obfuscated network packet assembly transmission method of claim 1, wherein, The waiting state in the data packet assembling step comprises: suspending the extraction of the data packet from the to-be-sent queue until at least one buffer area produces a new idle load space due to the reading and sending of data.

4. A multi-buffer based obfuscated network packet assembly transmission apparatus, comprising: The device comprises: a data packet assembling module, configured to set multiple buffer areas for a data packet to-be-sent queue, wherein the multiple buffer areas are three buffer areas and are physically isolated, extract one data packet from the to-be-sent queue each time, judge whether the idle load space of each buffer area can accommodate the data packet in a preset order in sequence, if any buffer area can accommodate the data packet, store the data packet to the corresponding buffer area and continue to extract the next data packet from the to-be-sent queue, and if all buffer areas cannot accommodate the data packet, enter a waiting state until the data packet of a buffer area is read and sent to re-execute the above storage operation; The cache data sending module is configured to, at a preset sending time, lock the plurality of buffer areas, including: prohibiting writing new data to the plurality of buffer areas during data reading and pointer switching, reading all data of a first buffer area, filling the read data to a set load size, and then forwarding the read data to a confusion network, wherein filling the read data to the set load size includes: if the total size of the read data is less than the set load size, filling invalid data to the set load size; if the total size of the read data is equal to the set load size, directly forwarding without filling; after forwarding is completed, performing a buffer area pointer switching operation, in which the position of the stored unsent data in each buffer area remains unchanged, the logical serial number of each buffer area is updated by a pointer mark, the subsequent buffer areas of the previous sending time window are sequentially advanced to the previous buffer areas of the current sending time window, including: allowing writing new data to the plurality of buffer areas after switching, and switching the original first buffer area to the last buffer area; after the pointer switching is completed, unlocking the plurality of buffer areas, waiting for the next sending time, and repeating the cache data sending step.

5. An electronic device, comprising: The electronic device includes a memory and a processor, and the memory stores program code that can be run on the processor. When the program code is executed by the processor, the program code implements the multi-buffer area-based confusion network packet assembly transmission method of any one of claims 1-3.

6. A computer-readable storage medium, characterized in that, The computer readable storage medium stores program code, and the program code can be called and executed by one or more processors to implement the multi-buffer area-based confusion network packet assembly transmission method of any one of claims 1-3.

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