Video line field self-recovery method based on FPGA

Abstract

The invention discloses a video line field self-recovery method based on an FPGA (Field Programmable Gate Array), which adopts a system architecture consisting of an FPGA processing chip, an image detector and a power management circuit, and is externally provided with video display equipment. Therefore, the problem that video signals cannot be displayed due to line and field signal loss caused by signal crosstalk, insufficient hardware interfaces, hardware design errors and the like is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of image and video processing, and in particular to a video line and field self-recovery method based on FPGA. Background Art

[0002] Video signals are generally divided into two categories: one is a video signal with an embedded code, which can be received and displayed by a display device without matching the corresponding horizontal and vertical signals; the other is a conventional video signal, which must match the corresponding horizontal and vertical signals to be received and displayed by a conventional display device. For conventional video signals, during the video acquisition process of the front-end image detector, the horizontal and vertical signals are often missing due to signal crosstalk, insufficient hardware interfaces, or hardware design errors, making the video signal unreceivable by the display device. Summary of the Invention

[0003] In view of the above problems, the purpose of the invention is to provide a video line field self-recovery method based on FPGA, which uses FPGA debugging visibility to recover video signals with missing lines and fields.

[0004] To achieve the above objectives, the present invention adopts the following technical solution: a FPGA-based video line and field self-recovery method, which uses a system architecture consisting of an FPGA processing chip, an image detector, and a power management circuit, and is externally equipped with a video display device. The specific implementation steps of the self-recovery method are as follows: S0 provides power input to the system, and the power management module supplies power to each chip; S1, FPGA processing chip configures the image detector; S2, the image detector collects the light signal and converts it into an electrical signal and outputs it to the FPGA processing chip; S3, the FPGA processing chip parses and aligns the received video image signal and determines whether the line or field signal in the video data is missing through the FPGA visual debugging window; S4, the FPGA processing chip recovers the missing line or field signals in the video data; S5, the FPGA processing chip outputs the restored video signal to the video display device for display.

[0005] Furthermore, the determination of whether the line or field signal of the video data is missing in step S3 is achieved by setting the line and field count in the FPGA processing chip and using the ILA observation core. The specific implementation steps are as follows: Two counters are set to record the number of pixels in each row and the number of rows in each field respectively. If the count of each row does not meet the corresponding pixel count or there is no row signal, the video row signal is missing; if it does not meet the corresponding row or there is no field signal, the video field signal is missing.

[0006] Furthermore, the method for restoring missing line or field signals in the video data in step S4 is implemented by the following steps: (1) Determine the total number of pixels and total number of lines in each frame of video based on the data output by the image detector; (2) determining, based on the ILA observation core in the FPGA processing chip, whether the video data in step (1) is missing a line signal, a field signal, or both; (3) If the line signal is missing, the counter counts based on the start of the field signal. The upper limit of the line count is the total number of pixels in each line of the image detector. When the upper limit is reached within the effective field range, the counter is reset to zero. Then, based on the relative position difference between the start position of the line signal and the start position of the field signal described in the image detector data sheet, the start and end positions of the line signal are determined until the end of the field signal. (4) If the field signal is missing, the pixel counter is counted based on the line signal start, the counter is reset to zero, and the upper limit of the pixel counter is 2 times or more of the number of line pixels; when the pixel counter reaches the upper limit, it is assigned the original value until the line signal starts; at the same time, the number of video lines is counted based on the line signal start, the field signal start is the start of the line signal when the counter upper limit is reached, and the field signal end is the position where the line counter reaches the valid line and the line signal ends; (5) When both the line signal and the field signal are missing, if the image detector outputs video data containing training words, the position where the training words appear is the invalid line position, otherwise the position without training words is the line signal, and then the video data is restored according to the missing field signal; if the image detector has no training words, the detector must be set to external synchronization mode, and an external synchronization signal must be generated using FPGA to ensure the output timing of the image detector. A counter and a pixel counter are manufactured based on the external synchronization signal, and the amount of light entering the image detector is changed so that it varies between the minimum and maximum values. The position of the counter corresponding to the photosensitivity change of the video data is observed through the FPGA observation core, and the position corresponding to the valid line signal of the video data is then restored according to the missing field signal.

[0007] Compared with the existing technology, the advantages of the present invention are: using FPGA algorithm and visual debugging window to solve the problem of missing line and field signals caused by signal crosstalk, insufficient hardware interface, hardware design errors, etc., which causes the video signal to be unable to be displayed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of the imaging system of the present invention; Figure 2 It is a workflow diagram of the present invention; Figure 34 is a flow chart of the implementation of the self-recovery method of the present invention. DETAILED DESCRIPTION

[0009] The technical solutions in the embodiments of the present invention are described clearly and completely below with reference to the accompanying drawings.

[0010] Reference Figure 1 ,This implementation of a video line and field self-recovery method based on FPGA adopts a system architecture consisting of FPGA processing chip, image detector, and power management circuit, and is equipped with an external video display device; Among them, FPGA is the core processing chip, responsible for completing video input acquisition, determining whether the video signal is missing lines and fields, restoring the missing lines and fields of the video signal, and outputting and displaying the video signal; The image detector is the system's video input source. The image detector can also be an imaging core. This embodiment uses the image detector as an example to describe the implementation process. The image detector is connected to the I / O pin of the FPGA processing chip. The FPGA processing chip provides configuration information to the image detector and transmits it to the image detector through the I / O port to drive the image detector to work normally. The image detector collects raw video image information and transmits it to the FPGA processing chip through the I / O port, completing the video image acquisition function. The power management circuit is composed of multiple power conversion chips and corresponding peripheral circuits, providing power for the FPGA processing chip, image detector, and serial communication circuit; The display device is an external observation device of the system, used to observe whether the system video signal is displayed normally.

[0011] Reference Figure 2 , a video line field self-recovery method based on FPGA, its workflow is as follows: S0 provides power input to the system, and the power management module supplies power to each chip; S1, FPGA processing chip configures the image detector; S2, the image detector collects video image data, converts it into video image signals and outputs it to the FPGA processing chip; S3, FPGA processing chip analyzes video image signals; S4, setting the row and field count in the FPGA processing chip and using the ILA observation core to determine whether the video is missing a row or field signal; Taking 1920×1080 resolution as an example, its row valid signal protects 1920 pixels and its field valid signal protects 1080 rows. Two counters can be set to record the number of pixels in each row and the number of rows in each field respectively. If the count of each row does not meet 1920 pixels or there is no row signal, the video row signal is missing; if it does not meet 1080 rows or there is no field signal, the video field signal is missing.

[0012] S5, if the video data lacks a line or field signal, the FPGA processing chip performs video recovery on the missing line or field signal; S6, the FPGA processing chip outputs the restored video signal to the video display device for display.

[0013] Reference Figure 3 The specific implementation process of the FPGA-based video line field self-recovery method is as follows: (1) Determine the total number of pixels and total number of lines in each frame of video based on the data output by the image detector; Taking the 1920×1080 resolution as an example, assuming the total number of pixels is 2048×2048, then each row has 1920 valid pixels and 128 invalid pixels, the valid rows are 1080 and the invalid rows are 968.

[0014] (2) Based on the ILA observation window detection step (1) in the FPGA processing chip, the type of missing line and field signals is determined, such as missing line signals, missing field signals, or both.

[0015] (3) If the line signal is missing, the counter counts based on the start of the field signal. The upper limit of the line count is the total number of pixels in each line of the image detector. When the upper limit is reached within the effective field range, the counter is reset to zero. Then, based on the relative position difference between the start position of the line signal and the start position of the field signal described in the image detector data sheet, the start and end positions of the line signal are determined until the end of the field signal. For ease of understanding, let's use an example. Assume that the image detector's data sheet indicates that the detector outputs a total valid data frame of 2640×1125, with effective data of 1920×1080. The first valid pixel begins 30 clock cycles from the start of the field signal. Therefore, the total number of pixels in a row is 2640. The upper limit of the row count described above should be set to 2640. When the field signal is high, the counter returns to 0 and restarts counting upon reaching 2640. Since the first valid pixel begins 30 clock cycles from the start of the field signal, the row valid signal is every 30 to 1949 segments of the counter until the field signal goes low, thus forming a complete row signal.

[0016] (4) If the field signal is missing, the pixel counter is counted based on the line signal start, the counter is reset to zero, and the upper limit of the pixel counter is 2 times or more of the number of line pixels; when the pixel counter reaches the upper limit, it is assigned the original value until the line signal starts; at the same time, the number of video lines is counted based on the line signal start, the field signal start is the start of the line signal when the counter upper limit is reached, and the field signal end is the position where the line counter reaches the valid line and the line signal ends; Let's assume, for example, that the image detector's data sheet indicates that the total valid data output per frame is 2640 × 1125, with the effective data being 1920 × 1080. In this case, the upper limit of the pixel counter is 2640 × 2 = 5280. When the pixel counter reaches 5280, it stops incrementing until the row signal goes high, at which point the counter is reset to 0 and then increments with the clock. When the pixel counter reaches 5280, the row counter is reset to 0. When the row signal transitions from low to high, the row counter increments by 1, remaining unchanged at all other times. Thus, when the pixel counter reaches 5280 and the row signal transitions from low to high, the field signal is set to 1. When the row counter reaches 1080 and the pixel counter reaches 1920, the field signal is reset to 0, completing the reconstruction of the field signal.

[0017] (5) When both the line signal and the field signal are missing, if the image detector outputs video data containing training words, the position where the training words appear is the invalid line position, otherwise the position without training words is the line signal, and then the video data is restored according to the missing field signal; taking a 10-bit wide detector as an example, assuming that its training word is 0x060, the data displayed at all positions where the line signal is low level is 0x060; otherwise, it can be determined based on the data whether the line signal is high level, and then the line signal is reconstructed, and then the field signal is reconstructed according to the missing field signal in step (3).

[0018] If the image detector does not have a training word, the detector must be set to external synchronization mode. An external synchronization signal must be generated using FPGA to ensure the output timing of the image detector. A row counter and a pixel counter are manufactured based on the external synchronization signal. The amount of light entering the image detector is changed so that it varies between the minimum value (usually 0) and the maximum value (usually the upper limit of the bit width). The position of the counter corresponding to the light sensitivity change of the video data is observed through the FPGA observation core to reconstruct the row field signal. Assuming the total data volume of a frame is 2640×1125, it's impossible to set the counter's starting point without a line-field signal as a reference. Therefore, a reference is required. External synchronization is used to introduce such a reference. The triggering of the external synchronization is in an absolute time relationship with the first pixel output by the image detector, so the external synchronization trigger serves as the counter's starting reference. Furthermore, since the total data volume of a frame is 2640×1125, the external synchronization trigger period is set to 2640×1125. A line counter and a pixel counter are set. When the external synchronization triggers, both the pixel counter and the line counter are reset to 0. The pixel counter increments according to the clock. When the pixel counter reaches 2639, the pixel counter is reset to 0. The line counter increments when the pixel counter reaches 2639, and otherwise maintains its original value. By varying the amount of light entering the image detector from darkest to brightest, the FPGA monitors the image data segments in the row and pixel counters where changes occur. For example, if image data changes in pixel counters 300 to 2219 in rows 2 to 1081, the high-level field signal starts at pixel 300 in row 2 and ends at pixel 2219 in row 1081. The high-level row signal corresponds to pixels 300 to 2219 in rows 2 to 1081. This completes the construction.

[0019] (6) Outputting the recovered video data to an external display device for video observation.

[0020] The above description is only a preferred embodiment of the present invention and the technical principles used. The present invention is not limited to the above specific embodiment, and similar methods for recovering video line and field signals are all within the scope of protection of the appended claims of the present invention.

Claims

1. A video line field self-recovery method based on FPGA, characterized in that: The system architecture is composed of an FPGA processing chip, an image detector, and a power management circuit, and is equipped with an external video display device. The specific implementation steps of the self-recovery method are as follows: S0 provides power input to the system, and the power management module supplies power to each chip; S1, FPGA processing chip configures the image detector; S2, the image detector collects the light signal and converts it into an electrical signal and outputs it to the FPGA processing chip; S3, the FPGA processing chip parses and aligns the received video image signal and determines whether the line or field signal in the video data is missing through the FPGA visual debugging window; S4, the FPGA processing chip recovers the missing line or field signals in the video data; S5, the FPGA processing chip outputs the restored video signal to the video display device for display.

2. The FPGA-based video line field self-recovery method according to claim 1, characterized in that: The determination of whether the line or field signal of the video data is missing in step S3 is achieved by setting the line and field count in the FPGA processing chip and using the ILA observation core. The specific implementation steps are as follows: Two counters are set to record the number of pixels in each row and the number of rows in each field respectively. If the count of each row does not meet the corresponding pixel count or there is no row signal, the video row signal is missing; if it does not meet the corresponding row or there is no field signal, the video field signal is missing.

3. The FPGA-based video line field self-recovery method according to claim 2, characterized in that: The method for restoring missing line or field signals in the video data in step S4 is implemented by the following steps: (1) Determine the total number of pixels and total number of lines in each frame of video based on the data output by the image detector; (2) determining, based on the ILA observation core in the FPGA processing chip, whether the video data in step (1) is missing a line signal, a field signal, or both; (3) If the line signal is missing, the counter counts based on the start of the field signal. The upper limit of the line count is the total number of pixels in each line of the image detector. When the upper limit is reached within the effective field range, the counter is reset to zero. Then, based on the relative position difference between the start position of the line signal and the start position of the field signal described in the image detector data sheet, the start and end positions of the line signal are determined until the end of the field signal. (4) If the field signal is missing, the pixel counter is counted based on the line signal start, the counter is reset to zero, and the upper limit of the pixel counter is 2 times or more of the number of line pixels; when the pixel counter reaches the upper limit, it is assigned the original value until the line signal starts; at the same time, the number of video lines is counted based on the line signal start, the field signal start is the start of the line signal when the counter upper limit is reached, and the field signal end is the position where the line counter reaches the valid line and the line signal ends; (5) When both the line signal and the field signal are missing, if the video data output by the image detector contains a training word, the position where the training word appears is the invalid position of the line, otherwise the position without the training word is the line signal, and then the video data is restored based on the missing field signal; If the image detector has no training words, the detector must be set to external synchronization mode, and an external synchronization signal must be generated using FPGA to ensure the output timing of the image detector. A counter and a pixel counter are manufactured based on the external synchronization signal, and the amount of light entering the image detector is changed so that it varies between the minimum and maximum values. The FPGA observation core observes the position of the counter corresponding to the photosensitivity change of the video data. The position corresponds to the valid line signal of the video data, and then the video data is restored according to the missing field signal.

4. The FPGA-based video line field self-recovery method according to claim 3, characterized in that: The FPGA processing chip completes video input acquisition, judgment of whether a video signal is missing a line or field, recovery of a missing line or field video signal, and video signal output and display.

5. The FPGA-based video line field self-recovery method according to claim 4, characterized in that: The image detector is connected to the I / O pin of the FPGA processing chip. The FPGA processing chip provides configuration information for the image detector and transmits it to the image detector through the I / O port to drive the image detector to work normally; the image detector collects raw video image information and transmits it to the FPGA processing chip through the I / O port to complete the video image acquisition function.

6. The FPGA-based video line and field self-recovery method according to claim 5, characterized in that: The power management circuit consists of multiple power conversion chips and corresponding peripheral circuits, providing power for the FPGA processing chip, image detector, and serial communication circuit.

7. The FPGA-based video line and field self-recovery method according to claim 6, characterized in that: The display device is an external observation device of the system, used to observe whether the system video signal is displayed normally.

Images