A preparation method of an ultra-low junction capacitance TVS protection device

Abstract

The present application relates to the technical field of semiconductor device manufacturing, in particular to a preparation method of an ultra-low junction capacitance TVS protection device. The present application relates to the technical field of semiconductor device manufacturing, in particular to a preparation method of an ultra-low junction capacitance TVS protection device. + A gradient intrinsic layer-N + Doped structure, through a continuous concentration slope, an electric field distribution is optimized, and a problem of early breakdown caused by a peak electric field concentration is solved; an air bridge electrode process is innovated, a suspended interconnection isolated by air medium is formed by using a sacrifice layer release, and parasitic capacitance is completely eliminated; a multi-ring field limiting terminal and a pulse laser local annealing are combined, edge electric field suppression and lattice integrity control are realized. The method makes the device have ultra-low junction capacitance, nanosecond-level response and high robustness, and provides a revolutionary electrostatic protection solution for a high-speed communication system.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and more specifically, to a method for preparing an ultra-low junction capacitance TVS protection device. Background Technology

[0002] Transient voltage suppressors (TVS), as critical circuit protection components, face severe challenges in high-speed communication scenarios. Traditional planar PIN TVS, limited by its two-dimensional structure, exhibits a junction capacitance of 0.82 pF at 5V bias, leading to significant attenuation during signal transmissions above 5Gbps. Simultaneously, the SiO2 dielectric layer (dielectric constant k=3.9) between the metal electrodes introduces additional parasitic capacitance, further degrading high-frequency performance. Existing improvements, such as trench-type TVS, can reduce capacitance, but are limited by aspect ratio; at an aspect ratio ≤3:1, the junction capacitance only drops to 0.28 pF, failing to achieve a significant order-of-magnitude breakthrough. Even with low-k SiCOH dielectrics (k=2.2-3.0), an additional 0.09 pF is introduced in experiments. More critically, the concentrated electric field in the high-concentration doped region easily triggers premature breakdown, creating a triangular contradiction between junction capacitance, withstand voltage, and response speed, becoming the core bottleneck restricting ESD protection in high-speed circuits. Summary of the Invention

[0003] The purpose of this invention is to provide a method for fabricating an ultra-low junction capacitance TVS protection device, which solves the problems mentioned in the background art by integrating three-dimensional structure modification, dielectric improvement and doping engineering.

[0004] To achieve the above objectives, on the one hand, the present invention provides a method for fabricating an ultra-low junction capacitance TVS protection device, comprising the following steps:

[0005] First, a fin array with an aspect ratio ≥ 5:1 (depth 10 μm / line width 0.8 μm) is formed on a gallium arsenide (GaAs) substrate by reactive ion deep etching process, and the sidewall tilt angle is precisely controlled to 88°±0.5% to suppress carrier surface recombination, thus constructing a vertical fin PIN junction framework.

[0006] Secondly, a three-dimensional gradient doping technique was achieved using multi-energy tilted ion implantation (15° tilt angle × 4 rotations): P was sequentially formed on the sidewalls of the fin trench. + District (Be + Injection, peak concentration 5×10 18 cm -3 Intrinsic buffer layer (gradient concentration 1×10⁻⁶) 15 -1×10¹⁷cm -3 ) and N + District (Si) + Injection, peak concentration 1×10 19 cm -3The electric field distribution is optimized by using a concentration gradient.

[0007] Subsequently, an innovative air-bridge electrode process was implemented: polyimide was used as a sacrificial layer to fill the fin trenches, Ti / Al / Ti / Au multilayer metal was sputtered and photolithographically formed, and then the sacrificial layer was released by O2 plasma ashing to form a suspended electrode structure isolated by air medium (k=1), completely eliminating parasitic capacitance. Finally, polysilicon field confinement rings (5 rings with a gradient spacing of 1.2-2.5 μm) and Si3N4 / SiO2 stacked layers were constructed at the device edge for passivation, and pulsed laser annealing (950℃ / 30ns) was used to activate doping and suppress diffusion.

[0008] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0009] By expanding the depletion region volume by 8 times through a three-dimensional fin structure and combining it with an air dielectric electrode, the overall capacitance is reduced by orders of magnitude: the junction capacitance is 0.048pF at 5V bias (compared to the traditional 0.82pF, a reduction of 94%), and the electrode parasitic capacitance is only 0.02pF (a reduction of 87%).

[0010] In terms of dynamic performance, the three-dimensional fin structure enables a response time of 0.048 ns (compared to the traditional 0.35 ns), supporting high-speed signal protection up to 40 Gbps. The clamping ratio is significantly optimized to 1.15 (8 / 20 μs waveform), and it passes the IEC 61000-4-2 Level 4 8kV contact discharge test. Reliability improvements are demonstrated by gradient doping reducing the peak electric field to 2.2 × 10⁻⁶. 5 V / cm (a decrease of 37%), pulsed laser annealing process ensures stable operation of the device in a wide temperature range of -55℃ to 175℃.

[0011] The core innovation lies in combining finned trench PIN junctions with air bridge electrodes, overcoming the physical limitations of two-dimensional planar structures: the three-dimensional depletion region design solves the problem of excessive capacitance per unit area, the air dielectric achieves near-zero parasitic capacitance, and gradient doping balances the contradiction between withstand voltage and response speed. The overall figure of merit (FOM = Cj × Vbr / Ipp) is improved by more than 8 times, providing a revolutionary protection solution for scenarios such as 5G / 6G communication and high-speed SerDes interfaces. Attached Figure Description

[0012] Figure 1 This is an overall flowchart of Embodiment 1 of the present invention. Detailed Implementation

[0013] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0014] The following provides a systematic explanation of the technical terms, abbreviations, and concepts used in the embodiments to ensure that the technical solutions are fully disclosed and easy to understand:

[0015] Table 1: Material-related

[0016]

[0017] Table 2: Process-related

[0018]

[0019] Table 3: Device Structure

[0020]

[0021] Table 4: Doping and Band Engineering

[0022]

[0023] The following are embodiments of the present invention.

[0024] Example 1: This embodiment of the invention provides a method for fabricating a GaAs-based three-dimensional fin-type TVS protection device, comprising the following steps:

[0025] Step 1: Substrate fabrication and hard mask formation

[0026] Choose n + -GaAs substrate (carrier mobility >5000 cm⁻¹) 2 / V·s) ensures a low-resistance path, and its (100) crystal orientation can optimize the anisotropy of subsequent etching;

[0027] After RCA cleaning of the substrate, the native oxide layer was removed by immersion in HF dilution (0.5%) for 30s. A 100nm SiN hard mask was deposited by LPCVD (stress control ±50MPa), and the fin groove pattern was defined by photolithography.

[0028] The high selectivity of SiN (GaAs:SiN=30:1) prevents etching through-through, and the thickness of 100nm has been verified by simulation to withstand an etching depth of ≥15μm.

[0029] Step 2: High aspect ratio fin groove etching

[0030] Main etching: ICP-RIE (Cl2 / BCl3=30 / 10 sccm, RF power 300W / bias 20V), achieving a perpendicularity of 88°±0.3° (angle deviation >1° will result in P...). + / N + (area overlap);

[0031] Passivation repair: C4F8 (5s, 10mTorr) is introduced to form a 10nm polymer to repair sidewall defects;

[0032] Parameter basis: A depth-to-width ratio of 5:1 (10μm depth / 2μm width) has been confirmed by Sentaurus simulation to increase the volume of the depletion region by 7.8 times.

[0033] The etching byproduct GaCl3 (boiling point 201℃) forms a retained layer on the sidewall. The ·CF2 free radical generated by the dissociation of C4F8 plasma reacts with it to generate volatile GaF3 (reaction formula: 2GaCl3 + 6·CF2 → 2GaF3↑ + 3C2Cl4↑).

[0034] Step 3: Three-dimensional gradient doping

[0035] Perform layered injection:

[0036] P + Be ion implantation zone + Energy 80keV / 1×10 15 cm -2 The tilt angle is 15° and it rotates 4 times. Its function is to avoid the channeling effect and the concentration gradient ensures the hole injection efficiency.

[0037] I-region implantation of Be ions + / Si + Gradient energy 30-120keV, tilt angle 7°, forming 1×10 15 -1×10 17 cm -3 Concentration slope, widening the depletion zone.

[0038] Si+ ions were implanted into the N+ region at an energy of 150 keV / 5 × 10⁻⁶. 15 cm -2 The tilt angle is 0°, which is used to reduce ohmic contact resistance.

[0039] Immediately after injection, the crystal lattice damage was repaired by thermal annealing at 300°C (60s).

[0040] Step 4: Air bridge electrode construction

[0041] Sacrificial layer filling: spin-coated polyimide (PI-2610, viscosity 3500cP), cured at 250℃ to form a 3μm smooth layer (thickness error <5%).

[0042] Electrode forming: sputtering Ti / Al / Ti / Au (50 / 300 / 50 / 100nm), photolithography lift-off to form a cantilever beam structure (span 15μm).

[0043] Release mechanism: O2 plasma (300W, 200sccm) ashing for 60min, PI decomposition rate 0.05μm / min (ensuring no residue);

[0044] Support and reinforcement: Anchor point structure (5μm in diameter, 20μm in spacing) is designed at the beam ends to resist mechanical vibration.

[0045] The goal is to minimize the dielectric constant (k=1), maximize the electrode spacing, and ensure mechanical stability.

[0046] Step 5: Terminal Protection and Passivation

[0047] Field limiting ring: LPCVD polycrystalline silicon ring (0.8μm width, spacing gradient 1.8-2.5μm) reduces the edge electric field by 40%;

[0048] Passivation layer: PECVD deposited Si3N4 (100nm) / SiO2 (200nm), interface state density <1×10 10 cm -2 ·eV -1 ;

[0049] Annealing activation: Nd:YAG pulsed laser (wavelength 1064nm, pulse width 30ns), peak temperature 950℃ (substrate temperature rise <150℃) to suppress doping diffusion.

[0050] The purpose is to suppress edge breakdown, control surface leakage, and achieve environmental isolation.

[0051] Example 2: This example provides a method for fabricating an aspect ratio-enhanced (suitable for 40GHz applications) TVS protection device, the purpose of which is to increase the cutoff frequency, reduce RF loss, and enhance thermal stability; the difference between this example and Example 1 is:

[0052] Fin slot structure optimization: The depth-to-width ratio is 15:1 (15μm / 1.0μm). The depth-to-width ratio is achieved through Bosch technology. For every doubling of the depth-to-width ratio, the capacitance per unit area decreases by 35% (measured capacitance 0.03pF@5V).

[0053] Thermal management design:

[0054] Electrode material: AuSn solder bumps (40μm in diameter) directly connected to the heat sink substrate;

[0055] Thermal pathway: Microchannels (0.5μm wide, 2μm deep) are pre-placed at the bottom of the fin groove and filled with thermally conductive adhesive.

[0056] Example 3: This example provides a method for fabricating a high-voltage industrial-grade TVS protection device, aiming to optimize electric field distribution, suppress avalanche breakdown, and control leakage current. The difference between this example and Example 1 is:

[0057] Composite terminal structure:

[0058] Main junction region: JTE extended ring (width 12 μm, dose gradient 2 × 10⁻⁶) 12 -1×10 13 cm -2 );

[0059] Auxiliary ring: Level 3 floating field ring (spacing 3 / 4 / 5μm);

[0060] TCAD shows a surface electric field <2×10⁻⁶. 5 V / cm (below the avalanche threshold of 3×10) 5 V / cm).

[0061] Innovative buffer layer: Insert an AlGaAs transition layer (Al composition gradually changes from 0.2 to 0), and suppress hot carrier injection with a 0.3 eV step in the conduction band.

[0062] Example 4: This example provides a method for fabricating an integrated TVS array protection device, aiming to ensure signal integrity, minimize packaging parasitic parameters, and achieve multi-channel matching; the difference between this example and Example 1 is:

[0063] Interconnect design:

[0064] Copper pillar bumps: 30μm diameter / 20μm height (aspect ratio 0.67 to ensure electromigration tolerance >10). 7 A / cm 2 );

[0065] Wiring rules: Coplanar waveguide structure (impedance 50Ω±5%, line width / spacing = 40μm / 30μm).

[0066] Experiment 1: Junction capacitance comparison test, the purpose of which is to verify the capacitance reduction effect of the three-dimensional fin structure and the air bridge electrode.

[0067] Test group:

[0068] Group A: Planar PIN structure, dielectric material SiO2, electrode type is planar electrode;

[0069] Group B: Trench TVS structure, dielectric material SiCOH, aspect ratio 3:1, electrode type is filled electrode;

[0070] Group C: Fin-type PIN structure, air dielectric material, aspect ratio 5:1, electrode type is air bridge;

[0071] Test conditions:

[0072] Test instrument: Keysight B1505A capacitance analyzer; bias range: 0-10V@1MHz; test standard: JESD22-C101F.

[0073] Table 5: Test Results

[0074]

[0075] As shown in Table 5, the air bridge electrode reduces parasitic capacitance by 87% (k=1 vs. k=3.9); the fin structure with a depth-to-width ratio of 5:1 reduces junction capacitance by 94% (the volume of the three-dimensional depletion region is increased by 8 times).

[0076] Experiment Example 2: Gradient Doping Electric Field Optimization Experiment, the purpose of which is to verify the effect of gradient doping on improving the electric field distribution.

[0077] Test method:

[0078] Sample preparation:

[0079] Control group: Uniformly doped (Be + (80keV monoenergetic injection);

[0080] Experimental group: Gradient doping (Be + (30-120keV multi-energy injection).

[0081] Testing techniques: Scanning Kelvin probe microscopy (SKPM) to measure surface potential; Sentaurus TCAD to simulate electric field distribution.

[0082] Table 6: Test Results

[0083]

[0084] As shown in Table 6, gradient doping creates a linear concentration ramp:

[0085]

[0086] Doping concentration distribution function: A function describing the change in doping concentration with location. It represents the distribution of doping concentration at a distance from a reference point (usually P). + The bulk concentration of electroactive impurities (acceptors or donors) at x micrometers from the boundary of the region;

[0087] Initial / surface doping concentration: Doping concentration at position x = 0 (i.e., the starting point of the gradient doping region);

[0088] : Position coordinates, from the starting point of the doped region (e.g., P) + The depth or distance calculated starting from the interface of zone I;

[0089] Concentration gradient (slope) represents the rate or slope at which the doping concentration changes with distance.

[0090] Increase the width of the depletion region:

[0091]

[0092] Depletion region width: The total width of the region near a PN junction or PIN junction lacking mobile carriers under zero bias or reverse bias conditions. W is a key parameter for measuring junction capacitance and breakdown voltage; the wider W is, the smaller the junction capacitance.

[0093] The dielectric constant of a semiconductor material is a physical quantity that represents the material's ability to store electrical energy.

[0094] Electron charge, a fundamental physical constant;

[0095] : P-type region doping concentration, electroactive acceptor impurities (such as Be) on the P-type semiconductor side + The concentration of ) in the body;

[0096] : N-type region doping concentration, electroactive donor impurities (such as Si) on the N-type semiconductor side + The concentration of ) in the body;

[0097] Built-in potential is the potential difference that naturally forms when a P-type semiconductor and an N-type semiconductor come into contact due to the alignment of their Fermi levels. It is determined by the bandgap and doping concentration of the materials.

[0098] The measured W increased from 1.2 μm to 2.8 μm.

[0099] Gradient doping technology reduced the peak electric field intensity from 3.5 × 10⁻⁶ to 3.5 × 10⁻⁶. 5 V / cm decreased to 2.2×10 5 V / cm (reduction of 37%), leakage current reduced by 84% (0.75μA vs 4.8μA@10V); linear concentration gradient achieved through band engineering (slope 0.5×10⁻⁶). 18 cm -3 / μm), solving the problem of concentrated edge electric field caused by traditional uniform doping.

[0100] Test Example 3: High-frequency dynamic response test, the purpose of which is to verify the protection capability of 40Gbps signal.

[0101] Test system: Signal source and ESD gun are used for the TVS under test, and connected to the receiver via a transmission line.

[0102] Test conditions:

[0103] Signal source: Tektronix AWG70002A (56Gbps PRBS31);

[0104] ESD waveform: IEC 61000-4-2 8kV contact discharge;

[0105] Test metrics: signal distortion rate, clamping response time.

[0106] Table 7: Test Results

[0107]

[0108] As shown in Table 7, the three-dimensional fin structure reduces the response time to 0.048 ns (compared to 0.35 ns for traditional TVS); the distortion rate of the 40Gbps signal is reduced from 23% to 4.8%. The theoretical carrier transit time is reduced by 86%, enabling real-time and precise clamping of high-speed interfaces above 40Gbps, meeting the protection requirements of 802.3ck 200G Ethernet.

[0109] Experiment 4: Thermal stability comparison test, the purpose of which is to verify the reliability advantages of pulsed laser annealing.

[0110] Test Design:

[0111] Comparison of annealing processes:

[0112] Control group: conventional RTA annealing (800℃ / 30s);

[0113] Experimental group: Pulsed laser annealing (950℃ / 30ns).

[0114] Aging test:

[0115] Temperature cycling: -55℃↔175℃ (1000 cycles);

[0116] High temperature bias: 175℃@10V (1000h).

[0117] Table 8: Test Results

[0118]

[0119] Secondly, through microscopic analysis, TEM revealed the presence of a dislocation network (density > 10) in the RTA sample. 7 cm -2 Laser-annealed samples have intact crystal lattices (dislocation density < 10). 5 cm -2 Interfacial oxygen content: 8.2 at% for the RTA group and 2.3 at% for the laser group.

[0120] As shown in Table 8, pulsed laser annealing technology reduced the oxygen content at the high-temperature interface from 8.2 at% to 2.3 at%, and decreased the failure rate by more than 90% (Vbr drift < 2%, compared to 32%); through nanosecond-level localized annealing (thermal budget < 10⁻⁶), J / μm 2 This addresses the challenge of interface state proliferation caused by high-temperature GaAs processing.

[0121] Experimental Example 5: Limiting Aspect Ratio Optimization Experiment, the purpose of which is to determine the quantitative relationship between aspect ratio and capacitance.

[0122] Experimental Design:

[0123] Five groups of samples with different aspect ratios were prepared:

[0124] D1: 3:1 (Depth 6μm / Width 2μm)

[0125] D2: 5:1 (10μm / 2μm)

[0126] D3: 8:1 (16μm / 2μm)

[0127] D4: 12:1 (24μm / 2μm)

[0128] D5: 15:1 (30μm / 2μm)

[0129] Table 9: Test Results

[0130]

[0131] As shown in Table 9, when the aspect ratio is >10:1, the sidewall steepness is >89.5°, leading to a decrease in breakdown voltage. The optimal range is 5:1 to 8:1, achieving: a capacitance of 0.05pF (90% reduction), maintaining a breakdown voltage >18V; explaining the physical mechanism of the breakdown voltage decrease caused by an aspect ratio >10:1 (sidewall steepness >89.5° triggering edge avalanche), correcting the industry's misconception of blindly pursuing high aspect ratios.

[0132] Test Example 6: ESD protection limit test, the purpose of which is to verify the pressure resistance of the composite terminal structure.

[0133] Test subject:

[0134] Example 3 Device (JTE + Field Confinement Ring)

[0135] Comparative example: No terminal protection device

[0136] Test method:

[0137] TLP test: 100ns square wave, 0.1A step;

[0138] UIS test: L=0.5mH, I=5A;

[0139] Failure determination: Leakage current > 1mA.

[0140] Table 10: Test Results

[0141]

[0142] According to Table 10. No terminal: Edge electric field > 4 × 10⁻⁶ 5 V / cm (avalanche threshold); Example 3: Field limiting loop reduces peak electric field to 1.8 × 10⁻⁶ 5 V / cm.

[0143] The composite terminal structure of this invention enables ESD tolerance of 28kV (compared to 12kV for conventional structures) and increases avalanche energy density to 3.5mJ / μm. 2 (Industry average 0.8 mJ / μm2); By using JTE and field limiting loops, the edge electric field strength was reduced from 4 × 10 5 V / cm decreased to 1.8×10 5 V / cm (below the avalanche threshold of 2.5 × 10⁻⁶) 5 V / cm), solving the problem of premature failure of high-voltage TVS.

[0144] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely preferred examples and are not intended to limit the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for fabricating an ultra-low junction capacitance TVS protection device, characterized in that, The method comprises the following steps: S1, forming a fin slot array with a depth-width ratio of ≥5:1 on a GaAs substrate by reactive ion deep etching, and controlling the side wall angle to be 88±0.5%; S2, using multi-energy oblique ion implantation on the fin slot sidewall, sequentially forming P + region, gradient concentration intrinsic buffer layer and N + region, thereby constructing PIN junction on three-dimensional sidewall; S3, filling the fin slot with a polyimide as a sacrificial layer, sputtering metal, and releasing the sacrificial layer by O2 plasma ashing to form an air bridge electrode; S4, constructing a field limiting ring and a passivation layer at the edge of the device; S5, and activating the doping by pulse laser annealing.

2. The method of claim 1, wherein the method further comprises: In the S1, the etching parameters of the fin slot array satisfy: The depth-width ratio is 5:1-15:1, the depth is 10-30 μm, and the width is 0.8-2 μm; The etching gas is Cl2 / BCl3 mixed gas, the radio frequency power is 300 W, and the bias voltage is 20 V; The side wall defects are periodically repaired by C4F8 plasma.

3. The method of claim 1, wherein the method further comprises: The S2 comprises: P + Zone implantation: Be + Ions, energy 80 keV, dose 1 x 10 15 cm -2 , tilt angle 15° x 4 rotations; Intrinsic buffer implant: Be + / Si + ions, energy gradient 30-120 keV, concentration gradient 1 x 10 15 -1 x 10 17 cm -3 ; N + Zone implant: Si + Ions, energy 150 keV, dose 5x1013cm-2 15 cm -2 .

4. The method of claim 1, wherein the method further comprises: In the S3, the sacrificial layer is polyimide PI-2610 with a solidified thickness of 3 μm±5%, the metal layer has a thickness of Ti(50 nm) / Al(300 nm) / Ti(50 nm) / Au(100 nm), and the O2 plasma release parameters are: power 300 W, gas flow rate 200 sccm, and time 60 min.

5. The method of claim 1, wherein the method further comprises: In the S4, the field limiting ring has a 5-ring gradient spacing structure with a ring width of 0.8 μm and a spacing of 1.8-2.5 μm, and the passivation layer is composed of 100 nm Si3N4 and 200 nm SiO2.

6. The method of manufacturing an ultra-low junction capacitance TVS protection device according to claim 1, wherein, In the S5, the pulse laser is Nd:YAG laser with a wavelength of 1064 nm and a pulse width of 30 ns, the peak temperature is 950 ℃, and the substrate temperature rise is less than 150 ℃.

7. The method of manufacturing an ultra-low junction capacitance TVS protection device according to claim 1, wherein, In the S1, the depth-width ratio of the fin slot is increased to 15:1, a microchannel with a width of 0.5 μm and a depth of 2 μm is pre-set at the bottom of the fin slot, and the microchannel is filled with heat-conducting glue; The electrode is connected to an AuSn solder bump with a diameter of 40 μm.

8. The method of claim 1, wherein the method further comprises: In the S4, the JTE extension ring is added, with a width of 12 μm and a dopant dose gradient of 2 x 10 12 -1 x 10 13 cm -2 The 3-stage floating field ring is added, with a spacing of 3 μm, 4 μm and 5 μm, respectively; and the AlGaAs layer with a gradual change in Al composition from 0.2 to 0 is inserted between the P + region and the intrinsic buffer layer.

9. The method of claim 1, wherein the method further comprises: After the S3, a copper pillar bump with a diameter of 30 μm and a height of 20 μm is formed; the wiring adopts a coplanar waveguide structure with a characteristic impedance of 50 Ω±5%, a line width of 40 μm, and a line spacing of 30 μm.

Images