Fan-out packaging structure of CIS chip and manufacturing method of fan-out packaging structure

Abstract

The invention provides a fan-out packaging structure of a CIS (Contact Image Sensor) chip, which improves the reliability and the integration level of system-level packaging and is low in packaging cost. The present invention comprises: glass; the cofferdam layer comprises a cofferdam cavity; the CIS chip comprises a silicon layer and a photosensitive device; a functional chip; and solder balls; a cofferdam layer is arranged on the upper surface of the glass, the CIS chip is bonded on the upper surface of the cofferdam layer, a photosensitive device of the CIS chip is arranged in a cofferdam cavity domain, a groove is etched in the upper surface of a silicon layer of the CIS chip, a functional chip is arranged in the groove, the silicon layer of the CIS chip is further provided with a connecting straight hole, and the connecting straight hole is communicated with the cavity domain of the cofferdam layer. The connection straight hole is connected to a lower layer PAD of the CIS chip, the connection straight hole and the upper surface of the silicon layer are provided with an RDL, the RDL connects the functional chip and the CIS chip, the upper surface of the silicon layer is provided with a solder mask layer, only the position of a bonding pad of the RDL is exposed, and the solder ball is arranged at the position of the bonding pad.

Description

Technical Field

[0001] The present invention relates to the technical field of CIS chip packaging, and in particular to a fan-out packaging structure of a CIS chip. The present invention also provides a corresponding manufacturing method. Background Art

[0002] With the rapid development of semiconductor technology, integrated circuit performance improvements are gradually shifting from a single reliance on process scaling to multi-dimensional innovation. Advanced packaging technology has become a key path to continuing Moore's Law. Traditional packaging technology, limited by physical space and interconnect density, faces bottlenecks in addressing high-density I / O requirements, heterogeneous integration, and miniaturized applications. In particular, mobile terminals, IoT devices, and autonomous driving are placing higher demands on chip miniaturization, high reliability, low power consumption, and high signal integrity, driving the evolution of packaging technology toward system-level integration and functional diversification.

[0003] Fan-out packaging, an extension of wafer-level packaging (WLP), achieves the "fan-out" expansion of I / O pins from the chip surface to the package's epitaxial area by embedding the chip within a reconstructed wafer and rewiring the circuits. Its core advantage lies in enabling high-density interconnection without a substrate, significantly reducing package thickness. It also supports heterogeneous multi-chip integration, providing improved electrical performance and heat dissipation for high-performance computing and RF devices. However, issues such as warpage control and multi-material interface stress matching in ultra-thin fan-out packaging still require further optimization.

[0004] Existing CIS packaging mostly uses chip-scale packaging (CSP) or ceramic packaging. However, with the stringent requirements of applications such as smartphones and medical imaging on pixel density, module thickness and resistance to environmental noise, existing packaging solutions face challenges in narrow-bezel design, stacked sensor integration (such as 3D stacked CIS) and thermal management.

[0005] In order to be able to reliably package highly integrated CIS chips, it is urgent to develop a packaging structure for CIS chips corresponding to fan-out packaging, thereby reducing packaging costs. Summary of the Invention

[0006] In response to the above problems, the present invention provides a fan-out packaging structure for a CIS chip, which improves the reliability and integration of system-level packaging and has low packaging costs.

[0007] A fan-out packaging structure for a CIS chip, characterized in that it comprises:

[0008] Glass;

[0009] a cofferdam layer, comprising a cofferdam cavity;

[0010] CIS chip, which includes a silicon layer and a photosensitive device;

[0011] Functional chips;

[0012] and solder balls;

[0013] A dam layer is provided on the upper surface of the glass, the CIS chip is bonded to the upper surface of the dam layer, and the photosensitive device of the CIS chip is placed in the dam cavity. A groove is etched on the upper surface of the silicon layer of the CIS chip, and a functional chip is placed in the groove. The silicon layer of the CIS chip is also provided with a connecting straight hole, and the connecting straight hole is connected to the lower PAD of the CIS chip. The connecting straight hole and the upper surface of the silicon layer are provided with RDL, and the RDL connects the functional chip and the CIS chip. A solder mask layer is provided on the upper surface of the silicon layer, and only the pad position of the RDL is exposed, and the solder ball is placed at the pad position.

[0014] It is further characterized by:

[0015] After the CIS chip and the dam layer are bonded, the upper layer of the silicon layer away from the glass is thinned;

[0016] The CIS chip is bonded to the upper convex surface of the dam layer via bonding glue;

[0017] The groove corresponding to the functional chip is placed directly above the photosensitive device. The functional chip is placed above the photosensitive device in the photosensitive area of ​​the CIS chip, which can effectively help the photosensitive device of the CIS chip block visible light from the silicon surface and improve the imaging problem of the CIS chip.

[0018] After the DAF film is pasted in the groove, the functional chip is placed in the groove, with the PAD of the functional chip exposed;

[0019] Preferably, the functional chip is a computing power chip.

[0020] A method for manufacturing a fan-out packaging structure of a CIS chip, characterized in that it comprises the following steps:

[0021] S1. Make a cofferdam layer on the glass. The cofferdam cavity of the cofferdam layer corresponds to the position of the photosensitive device of the CIS chip. Bond the CIS chip and the cofferdam layer on the glass to form a closed cavity.

[0022] S2, thinning the upper silicon layer of the CIS chip;

[0023] S3, making a groove in the silicon layer above the photosensitive area of ​​the CIS chip;

[0024] S4, placing the functional chip in the groove with the PAD of the functional chip exposed;

[0025] S5, performing straight hole etching on the silicon layer corresponding to the CIS chip PAD position and the cutting street position to form the cutting street straight hole and the connecting straight hole;

[0026] S6 forms RDL on the upper surface of the silicon layer and the connecting straight holes, and leads the PAD of the CIS chip from the straight holes to the upper surface of the silicon layer through the RDL, so that the PAD of the functional chip is interconnected with the relevant functional pins of the CIS chip through the RDL, and the RDL reserves the pad position on the upper surface of the silicon layer;

[0027] S7. A solder resist layer is provided on the upper surface of the silicon layer of the CIS chip to expose the solder pad position;

[0028] S8. Solder balls are placed at the pad position, and then the straight holes are cut along the cutting paths to obtain the fan-out packaging structure of a single CIS chip.

[0029] It is further characterized by:

[0030] In step S1, the dam layer is obtained by coating, planing and developing, and the CIS chip is bonded to the dam layer by bonding adhesive;

[0031] In step S2, the upper silicon layer of the CIS chip is thinned by grinding and dry etching;

[0032] In step S4, a DAF film is attached to the groove of the silicon layer. The material of the DAF film is epoxy resin or polyimide. Then, the functional chip is placed in the inner cavity of the DAF film, and the PAD of the functional chip is exposed.

[0033] In step S7, a layer of positive photoresist is applied on the upper surface of the silicon layer of the CIS chip by spin coating or spray coating as a solder resist layer, and then exposed and developed to expose the pad position.

[0034] After adopting the present invention, two chips, namely the CIS chip and the functional chip, can be set in the same CIS packaging volume, thereby improving the chip integration, making full use of the area, saving the space of the subsequent PCB board, improving the PCB board utilization rate, and reducing the packaging cost. In addition, burying the functional chip on the upper side of the photosensitive device in the photosensitive area of ​​the CIS chip can effectively help the CIS block visible light from the silicon surface and improve the imaging problem of the chip. It improves the reliability and integration of the system-level packaging and has a low packaging cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of step S8 of a method for manufacturing a cross-sectional schematic diagram of a package structure according to a specific embodiment of the present invention;

[0036] Figure 2 Schematic diagram of step S1 of a method for manufacturing a packaging structure according to a specific embodiment of the present invention;

[0037] Figure 3 Schematic diagram of step S2 of the method for manufacturing a packaging structure according to a specific embodiment of the present invention;

[0038] Figure 4 Schematic diagram of step S3 of the method for manufacturing a packaging structure according to a specific embodiment of the present invention;

[0039] Figure 5 Schematic diagram of step S4 of the method for manufacturing a packaging structure according to a specific embodiment of the present invention;

[0040] Figure 6 Schematic diagram of step S5 of the method for manufacturing a packaging structure according to a specific embodiment of the present invention;

[0041] Figure 7 Schematic diagram of step S6 of the method for manufacturing a packaging structure according to a specific embodiment of the present invention;

[0042] Figure 8 Schematic diagram of step S7 of the method for manufacturing a packaging structure according to a specific embodiment of the present invention; the names corresponding to the serial numbers in the figure are as follows:

[0043] Glass 10, cofferdam layer 11, cofferdam cavity 111, bonding glue 12, CIS chip 13, silicon layer 131, groove 1311, connecting straight hole 1312, cutting straight hole 1313, photosensitive device 132, DAF film 14, functional chip 15, RDL16 tin, ball 17, solder mask layer 18. DETAILED DESCRIPTION

[0044] A fan-out packaging structure for CIS chips, see Figure 1 , which includes glass 10; a bank layer 11, a CIS chip 13, a functional chip 15, and solder balls 17;

[0045] The cofferdam layer 11 includes a cofferdam cavity 111;

[0046] The CIS chip 13 includes a silicon layer 131 and a photosensitive device 132;

[0047] A dam layer 11 is provided on the upper surface of the glass 10, the CIS chip 13 is bonded to the upper surface of the dam layer 11, and the photosensitive device 132 of the CIS chip 13 is placed in the dam cavity 111, and a groove 1311 is etched on the upper surface of the silicon layer 131 of the CIS chip 13, and the functional chip 15 is placed in the groove 1311. The silicon layer 131 of the CIS chip 13 is also provided with a connecting straight hole 1312, and the connecting straight hole 1312 is connected to the lower layer PAD of the CIS chip 13. The connecting straight hole 1312 and the upper surface of the silicon layer 131 are provided with RDL16, and RDL16 connects the functional chip 15 and the CIS chip 13. The upper surface of the silicon layer 131 is provided with a solder resist layer 18, and only the pad position of the RDL is exposed, and the solder ball 17 is placed at the pad position.

[0048] In a specific embodiment, after the CIS chip 13 and the bank layer 11 are bonded, the upper layer of the silicon layer 131 away from the glass 10 is thinned;

[0049] The CIS chip 13 is bonded to the upper convex surface of the dam layer 11 via the bonding adhesive 12;

[0050] The groove 1311 corresponding to the functional chip 15 is placed directly above the photosensitive device 132. The functional chip 15 is placed above the photosensitive device 132 in the photosensitive area of ​​the CIS chip 13, which can effectively help the photosensitive device 132 of the CIS chip 13 block visible light from the silicon surface, thereby improving the imaging problem of the CIS chip 13.

[0051] After the DAF film 14 is pasted in the groove 1311, the functional chip 15 is placed in the groove 1311, and the PAD of the functional chip 13 is exposed;

[0052] In a specific embodiment, the functional chip 15 is a computing power chip.

[0053] A method for manufacturing a fan-out packaging structure of a CIS chip, see Figures 1-8 , which includes the following steps:

[0054] S1. A cofferdam layer 11 is formed on the glass 10 by coating, planing, and developing. The cofferdam cavity 111 of the cofferdam layer 11 corresponds to the position of the photosensitive device 132 of the CIS chip 13. The CIS chip 13 and the cofferdam layer 11 on the glass 10 are bonded by bonding adhesive 12 to form a closed cavity.

[0055] S2. The upper silicon layer 131 of the CIS chip 13 is thinned by grinding and dry etching;

[0056] S3, forming a groove 1311 in the silicon layer above the photosensitive device 132 in the photosensitive area of ​​the CIS chip 13 through photolithography and dry etching processes;

[0057] S4. Paste a DAF film 14 in the groove 1311. The material of the DAF film 14 is epoxy resin or polyimide (PI). Embed a functional chip 15 in the groove 1311 with the PAD of the functional chip 15 exposed. The functional chip 15 is a computing chip.

[0058] S5. Dry etching is performed on the silicon layer 131 at the PAD position and the cutting street position corresponding to the CIS chip 13 to form a cutting street straight hole 1313 and a connecting straight hole 1312.

[0059] S6 forms RDL16 on the upper surface of the silicon layer 131 and the connecting straight holes 1312 by PVD, electroplating, and photolithography. The PAD of the CIS chip 13 is led out from the straight holes to the upper surface of the silicon layer 131 through the RDL16, so that the PAD of the functional chip 15 is interconnected with the relevant functional pins of the CIS chip 13 through the RDL16. The RDL16 reserves a pad position on the upper surface of the silicon layer;

[0060] S7, coating the upper surface of the silicon layer 131 of the CIS chip 13 with a layer of positive photoresist as the solder resist 18 by spin coating or spray coating, and then exposing and developing to expose the pad position;

[0061] S8. Solder balls 17 are formed at the pad positions. The process is not limited to ball planting and printing. The solder balls 17 are then cut along the cutting paths and straight holes 1313 to obtain a fan-out package structure of a single CIS chip.

[0062] With the same CIS package volume, two chips, a CIS chip and a functional chip, can be set up, which improves the chip integration, fully utilizes the area, saves space on subsequent PCB boards, improves PCB board utilization, and reduces packaging costs. Burying the functional chip on the upper side of the photosensitive device in the photosensitive area of ​​the CIS chip can effectively help the CIS block visible light from the silicon surface and improve the imaging problem of the chip. It improves the reliability and integration of the system-level packaging, and the packaging cost is low.

[0063] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0064] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A fan-out packaging structure for a CIS chip, characterized in that: It includes: Glass; a cofferdam layer, comprising a cofferdam cavity; CIS chip, which includes a silicon layer and a photosensitive device; Functional chips; and solder balls; A dam layer is provided on the upper surface of the glass, the CIS chip is bonded to the upper surface of the dam layer, and the photosensitive device of the CIS chip is placed in the dam cavity. A groove is etched on the upper surface of the silicon layer of the CIS chip, and a functional chip is placed in the groove. The silicon layer of the CIS chip is also provided with a connecting straight hole, and the connecting straight hole is connected to the lower PAD of the CIS chip. The connecting straight hole and the upper surface of the silicon layer are provided with RDL, and the RDL connects the functional chip and the CIS chip. A solder mask layer is provided on the upper surface of the silicon layer, and only the pad position of the RDL is exposed, and the solder ball is placed at the pad position.

2. The fan-out packaging structure of a CIS chip according to claim 1, wherein: After the CIS chip and the dam layer are bonded, the upper layer of the silicon layer away from the glass is thinned.

3. The fan-out packaging structure of a CIS chip according to claim 2, wherein: The CIS chip is bonded to the upper convex surface of the dam layer via bonding glue.

4. The fan-out packaging structure of a CIS chip according to claim 3, wherein: The groove corresponding to the functional chip is placed directly above the photosensitive device, and the functional chip is placed above the photosensitive device in the photosensitive area of ​​the CIS chip.

5. The fan-out packaging structure of a CIS chip according to claim 1, wherein: After the DAF film is pasted in the groove, the functional chip is placed in the groove, and the PAD of the functional chip is exposed.

6. The fan-out packaging structure of a CIS chip according to claim 1, wherein: The functional chip is a computing power chip.

7. A method for manufacturing a fan-out package structure of a CIS chip, which is used to manufacture a fan-out package structure of a CIS chip according to any one of claims 1 to 6, characterized in that: It includes the following steps: S1. Make a cofferdam layer on the glass. The cofferdam cavity of the cofferdam layer corresponds to the position of the photosensitive device of the CIS chip. Bond the CIS chip and the cofferdam layer on the glass to form a closed cavity. S2, thinning the upper silicon layer of the CIS chip; S3, making a groove in the silicon layer above the photosensitive area of ​​the CIS chip; S4, placing the functional chip in the groove with the PAD of the functional chip exposed; S5, performing straight hole etching on the silicon layer corresponding to the CIS chip PAD position and the cutting street position to form the cutting street straight hole and the connecting straight hole; S6 forms RDL on the upper surface of the silicon layer and the connecting straight holes, and leads the PAD of the CIS chip from the straight holes to the upper surface of the silicon layer through the RDL, so that the PAD of the functional chip is interconnected with the relevant functional pins of the CIS chip through the RDL, and the RDL reserves the pad position on the upper surface of the silicon layer; S7. A solder resist layer is provided on the upper surface of the silicon layer of the CIS chip to expose the solder pad position; S8. Solder balls are placed at the pad position, and then the straight holes are cut along the cutting paths to obtain the fan-out packaging structure of a single CIS chip.

8. The method for manufacturing a fan-out package structure of a CIS chip according to claim 7, wherein: In step S1, the dam layer is obtained by coating, planing, and developing, and the CIS chip is bonded to the dam layer by bonding adhesive.

9. The method for manufacturing a fan-out packaging structure of a CIS chip according to claim 7, wherein: A DAF film is pasted in the groove of the silicon layer. The material of the DAF film is epoxy resin or polyimide. Then the functional chip is placed in the inner cavity of the DAF film, and the PAD of the functional chip is ensured to be exposed.

10. The method for manufacturing a fan-out packaging structure of a CIS chip according to claim 7, wherein: In step S7, a layer of positive photoresist is applied on the upper surface of the silicon layer of the CIS chip by spin coating or spray coating as a solder resist layer, and then exposed and developed to expose the pad position.

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