A method and system for implementing chip testing

Abstract

The application discloses a kind of method and system for realizing chip testing, it is related to chip testing technical field, including, chip testing daughterboard is assembled, multiple chips to be tested are loaded in chip loading area, switch matrix, decoder and activation control unit are configured, and chip mapping matrix is generated;Select single chip to carry out high temperature operating life test, real-time monitoring chip power consumption stability, calculate chip power consumption deviation;Execute logic function test, timing test and multi-channel voltage output test, evaluate output consistency, generate chip function test data;Based on chip power consumption deviation and chip function test data, using entropy-based risk assessment method, the failure probability of the chip to be tested is calculated, the failure probability distribution is analyzed by constructing failure mechanism decision model, and the power consumption stability test and function test of the chip to be tested are optimized.The application generates chip mapping matrix by three-dimensional matrix operation, reduces the time and complexity of test configuration.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip testing, in particular to a method and system for realizing chip testing. BACKGROUND

[0002] In recent years, chip testing platforms have gradually evolved towards high-density, multi-channel, and high-frequency signal transmission to meet the testing needs of complex chips (such as BGA packaging and SoC chips) in high-performance computing, artificial intelligence, and 5G communication fields. Conventional testing methods usually use automatic test equipment (ATE) combined with special test fixtures to verify the logic function, timing performance, and power stability of chips through fixed pin mapping and single-channel gating. In addition, some advanced testing systems introduce switch matrices and decoders to support multi-chip parallel testing, thereby improving testing efficiency. These technologies show high reliability in standardized testing processes.

[0003] However, existing chip testing technologies still have significant deficiencies when dealing with multi-chip parallel testing. First, traditional testing systems usually rely on fixed pin mapping and channel configuration, making it difficult to flexibly adapt to different chip pin layouts and functional unit requirements, resulting in complex testing configuration and poor universality. Second, in extreme conditions such as high temperature and high voltage, the existing system has limited monitoring capability for chip power stability and multi-channel output consistency, which may affect testing accuracy due to signal routing impedance mismatch or channel gating errors. These deficiencies not only reduce testing efficiency but also may lead to missed detection of potential failed chips, thereby affecting chip reliability verification. Therefore, there is an urgent need for a method that can flexibly configure testing channels and improve multi-chip parallel testing accuracy to meet the diversified needs of complex chip testing. SUMMARY

[0004] In view of the above existing problems, the present application is proposed.

[0005] Therefore, the present application provides a method for realizing chip testing to solve the problems of low testing efficiency and insufficient accuracy caused by fixed pin mapping and insufficient flexibility of channel configuration in multi-chip parallel testing.

[0006] To solve the above technical problems, the present application provides the following technical solutions:

[0007] In a first aspect, the present application provides a method for realizing chip testing, which includes assembling a chip testing sub-board, the chip testing sub-board including a chip loading area, a testing connection area, a signal routing area, a channel selection area, and an activation control area, loading multiple chips to be tested in the chip loading area, configuring a switch matrix, a decoder, and an activation control unit, and generating a chip mapping matrix.

[0008] Inserting the chip test sub-board into the main board array of the high-temperature test platform, selecting a single chip for high-temperature operation life test, monitoring the stability of the chip power consumption in real time, and calculating the chip power consumption deviation;

[0009] By aligning and applying pressure through the automatic compression jig, logical function test, timing test and multi-channel voltage output test are performed, output consistency is evaluated, and chip function test data is generated;

[0010] Based on the chip power consumption deviation and the chip function test data, the entropy-based risk assessment method is used to calculate the failure probability of the chip under test, the failure probability distribution is analyzed by constructing a failure mechanism decision model, and the power consumption stability test and function test of the chip under test are optimized.

[0011] As a preferred scheme of the method for implementing chip testing, the chip mapping matrix is generated, and the specific steps are as follows,

[0012] According to the pin index of each chip under test, the state of the switch matrix is set, and the mapping relationship between the pin index of each chip under test and the signal routing area wire is generated;

[0013] The strobe signal of the decoder is set, the channel selection area of the chip test sub-board is connected with the decoder, and the mapping relationship between the channel index and the decoder output signal is generated;

[0014] According to the programmable logic device of the activation control area, the activation instruction is preset, the signal transmission path matching the activation instruction is matched with the chip under test, and the mapping relationship between the activation instruction of each chip under test and the shared signal line is generated;

[0015] According to the mapping relationship between the pin index of each chip under test and the signal routing area wire, the mapping relationship between the channel index and the decoder output signal, and the mapping relationship between the activation instruction of each chip under test and the shared signal line, the chip mapping matrix is generated through three-dimensional matrix operation.

[0016] As a preferred scheme of the method for implementing chip testing, the mapping relationship between the pin index of each chip under test and the signal routing area wire is that the pin of the chip under test is connected with or disconnected from the wire of the signal routing area.

[0017] The mapping relationship between the channel index and the decoder output signal indicates whether the channel is enabled, and if enabled, whether it is effective.

[0018] The mapping relationship between the activation instruction of each chip under test and the shared signal line indicates whether the chip under test receives the activation instruction and is activated.

[0019] As a preferred scheme of the method for implementing chip testing, the chip power consumption deviation is calculated, and the specific steps are as follows,

[0020] The programmable logic device of the activation control area selects each chip to be tested one by one according to the activation instruction, starts the high-temperature test cavity, and executes the high-temperature operation life test.

[0021] The absolute deviation of the total power consumption and the average power consumption of the chip to be tested is calculated by integral calculation to obtain the chip power consumption deviation.

[0022] As a preferred scheme of the method for implementing chip testing, the steps of generating chip function test data are specifically as follows,

[0023] The signal port of the performance test mainboard transmits the test vector, records the output response of each channel, uses a logic analyzer to capture the output signal, compares the output signal with the expected output signal, and calculates the logic function coverage rate of each chip to be tested.

[0024] All channels are selected by the decoder, a high-frequency clock signal is input, the clock frequency and signal delay of the chip are measured, the absolute deviation of the measured actual clock frequency and the target clock frequency is calculated, and the timing error is obtained.

[0025] The output voltage of each channel is measured using an analog-to-digital converter, the absolute average deviation of the multi-channel output voltage of the chip to be tested and the target voltage is calculated, and the output voltage deviation is obtained.

[0026] The logic function coverage rate, the timing error and the output voltage deviation are output as chip function test data.

[0027] As a preferred scheme of the method for implementing chip testing, the steps of generating chip function test data are specifically as follows,

[0028] The chip power consumption deviation and the chip function test data are normalized, and the state vector of the chip to be tested is constructed with the chip to be tested as the index.

[0029] The state vector of the chip to be tested is discretized into a state interval for each chip to be tested.

[0030] The histogram method is used to calculate the probability of the state vector of the chip to be tested in each state interval by counting the distribution frequency of the state vector of each chip to be tested in the state interval.

[0031] The probabilities of the state vectors of the chips to be tested in each state interval are aggregated to calculate the state entropy of the chip to be tested.

[0032] The degree of deviation of the chip to be tested from the expected performance is measured by weighted normalization of the chip power consumption deviation and the chip function test data to obtain the failure score of the chip to be tested.

[0033] The state entropy of the chip under test is normalized based on the number of state intervals.

[0034] According to the failure score and the normalized state entropy of the chip under test, an exponential weighting function is used to calculate the failure probability of the chip under test.

[0035] As a preferred scheme of the method for implementing chip testing, the chip testing subboard adopts a multi-layer printed circuit board coated with a high-temperature resistant coating, the pin array of the chip loading area supports multiple chip packaging types, and the activation control area is dynamically configured with preset activation instructions through a programmable logic device.

[0036] In a second aspect, the present application provides a system for implementing chip testing, comprising,

[0037] The mapping matrix module is configured to assemble a chip testing subboard, which includes a chip loading area, a test connection area, a signal routing area, a channel selection area, and an activation control area, load multiple chips under test in the chip loading area, configure a switch matrix, a decoder, and an activation control unit, and generate a chip mapping matrix.

[0038] The power consumption deviation module is configured to insert the chip testing subboard into a mainboard array of a high-temperature test platform, select a single chip for high-temperature operation life test, monitor the power consumption stability of the chip in real time, and calculate the power consumption deviation of the chip.

[0039] The functional test module is configured to perform logic function test, timing test, and multi-channel voltage output test by aligning and applying pressure through an automated compression fixture, evaluate output consistency, and generate chip functional test data.

[0040] The failure product evaluation module is configured to calculate the failure probability of the chip under test based on the chip power consumption deviation and the chip functional test data using an entropy-based risk assessment method, analyze the failure probability distribution by constructing a failure mechanism decision model, and optimize the power consumption stability test and functional test of the chip under test.

[0041] In a third aspect, the present application provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, any step of the method for implementing chip testing according to the first aspect of the present application is implemented.

[0042] In a fourth aspect, the present application provides a computer readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, any step of the method for implementing chip testing according to the first aspect of the present application is implemented.

[0043] The beneficial effects of this invention are as follows: This invention dynamically generates the pin index, channel selection weight, and activation signal mapping relationship of each chip under test through three-dimensional matrix operations, realizing flexible configuration of test channels, adapting to the pin layout and functional requirements of different chips, reducing the time and complexity of test configuration, and based on the activation control unit of programmable logic devices (such as FPGAs), it sends preset activation instructions through shared control signal lines, supports parallel testing of multiple chips, and improves test efficiency. Attached Figure Description

[0044] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Fig. 1 A flowchart illustrating the method for implementing chip testing.

[0046] Fig. 2 Flowchart for generating the chip mapping matrix.

[0047] Fig. 3 A flowchart for generating chip functional test data.

[0048] Fig. 4 This is a flowchart of the entropy-based risk assessment method. Detailed Implementation

[0049] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0050] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0051] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0052] Reference Figs. 1-4 This is one embodiment of the present invention, which provides a method for implementing chip testing, including the following steps:

[0053] S1. Assemble the chip test sub-board. The chip test sub-board includes a chip loading area, a test connection area, a signal routing area, a channel selection area, and an activation control area. Multiple chips under test are loaded into the chip loading area. A switch matrix, a decoder, and an activation control unit are configured to generate a chip mapping matrix. The specific steps are as follows:

[0054] The chip test daughterboard uses a multilayer high-frequency printed circuit board (PCB), such as a 10-layer structure, with a typical size of 150mm × 150mm and a thickness of approximately 2.0mm, to support high-frequency signal transmission, with a frequency range of up to 20GHz. The chip test daughterboard includes the following functional areas: a chip loading area, located in the center, with a size of 30mm × 30mm, featuring a general-purpose pin array, such as a 16×16 grid, with a pin pitch of approximately 0.3mm; and a test connection area, surrounding the chip loading area, for example, 15mm wide, with provisions for a high-density spring pin array. The mounting locations are as follows: for example, the spacing is approximately 0.6mm, with a total of 512 spring pins; the signal routing area is configured with impedance matching traces, with an impedance of, for example, 50Ω, and the trace length not exceeding 70mm; the channel selection area reserves installation space for decoders and switches, supporting multi-channel output selection, for example, 16 channels; the activation control area reserves installation space for programmable logic devices, supporting multi-chip parallel testing, for example, 16 chips, which send preset activation commands through shared control signal lines, chip select signal lines, and address signal lines, and the surface is coated with a high-temperature resistant coating, such as a polyimide coating.

[0055] Electrical connectivity tests are performed on multilayer high-frequency printed circuit boards. A flying probe tester is used to verify the connectivity and insulation between each pin to ensure that there are no short circuits or open circuits.

[0056] Using an automated placement machine, such as the Yamaha YSM20, electronic components for switch matrices, decoders, and activation control areas are mounted on a multilayer high-frequency printed circuit board for chip testing. For example, switch matrix chips, such as ADG1408 with 8 channels, are soldered in the signal routing area. The soldering temperature is controlled between 255°C and 270°C, the soldering time does not exceed 5 seconds, and the soldering strength is not less than 15MPa. Decoder chips, such as SN74HC138, and NMOS switches, such as BSS138, are soldered in the channel selection area. Programmable logic devices, such as FPGAs, are soldered in the activation control area. X-ray inspection equipment is used to check the soldering quality to ensure that there are no cold solder joints or short circuits, resulting in an electronic component assembly.

[0057] In the test connection area of ​​the electronic component assembly, reflow soldering technology is used to fix the spring pin array. In the general pin array position of the chip loading area, conductive adhesive is used to fix the pins to ensure stable electrical connection between the pins and the printed circuit board. A high-precision microscope is used to check the mounting flatness of the spring pin array and the bonding quality of the general pin array. An automatic pick-and-place machine is used to accurately place multiple chips under test on the general pin array, such as 16 BGA packaged chips. Each chip under test has 144 pins and contains 16 kinetic energy units. Micro-soldering technology is used to fix the chips under test. A multimeter is used to test the electrical connectivity between each chip under test and the general pin array to ensure that all pins are correctly connected, thus generating a chip test sub-board.

[0058] Using programming software such as LabVIEW, set the state of the switch matrix according to the pin index of each chip under test. For example, connect the pins to the traces in the signal routing area to obtain the mapping relationship between the pin index of each chip under test, such as 1 to 144, and the traces in the signal routing area. Set the state value to 0 or 1, where 0 indicates disconnection and 1 indicates connection. Use a digital oscilloscope to verify the signal integrity of the pin connection.

[0059] Depending on the number of functional units in the chip under test, LabVIEW's digital I / O is used to connect to the channel selection area of ​​the chip test daughterboard. Communication with the decoder is achieved via USB or PCIe interface. The decoder on the chip test daughterboard is configured by setting the decoder's strobe signals, supporting multi-channel output strobe (e.g., 16 channels). A mapping relationship between channel indices and decoder output signals is generated. The strobe signal value is set to 0 or 1, where 0 indicates the channel is not selected and 1 indicates the channel is selected. The channel strobe weight indicates the strobe validity status, with a value of 0 or 1, where 0 indicates invalid strobe and 1 indicates valid strobe. A logic analyzer is used to verify the decoder's strobe function.

[0060] Using the IP Integrator tool in Vivado (a programming software), the programmable logic device in the activation control area is configured, and the activation instruction is preset. The activation instruction includes format bits and status bits. Through Vivado's I / O Planning function, the pin-shared control signal lines, chip select signal lines, and address signal lines of the programmable logic device are allocated for transmission to ensure that the signal transmission path matches the chip under test. The mapping relationship between the activation instruction and the shared signal lines of each chip under test is generated, and the activation signal value is set to 0 or 1, where 0 indicates that the chip under test is not activated, and 1 indicates that the chip under test is activated.

[0061] The MATLAB script loads the mapping relationships between pin indices and signal routing area traces, channel indices and decoder output signals for each chip under test, and activation instructions and shared signal lines for each chip under test. A chip mapping matrix is ​​then generated through three-dimensional matrix operations, as shown in the following formula:

[0062] ;

[0063] in, This is a chip mapping matrix, representing the total number of pins of all chips under test on the chip test sub-board that are correctly connected to the active chip through valid channels. Its value range is [value range missing]. This reflects the integrity of the chip test daughterboard connection configuration, for example, when When the signal is complete, it indicates that all 144 pins of the 16 chips under test are correctly connected. This represents the total number of pins on the chip under test. This refers to the pin index variable of the chip under test. For the number of channels, For the channel's index variable, The number of chips to be tested. This is the index variable for the chip under test. Indicates the first chip test daughterboard The first chip under test Is the pin connected to the first pin through the signal routing area? Each channel has a value of 0 or 1, where 0 indicates a disconnected connection and 1 indicates a successful connection. For example... This indicates that pin 1 of chip 1 under test is connected to channel 1. Indicates the first The gating weights of each channel, For the first The strobe signal value for each channel, For the first The activation signal value of the chip under test.

[0064] S2. Insert the chip test daughterboard into the motherboard array of the high-temperature test platform, select a single chip for high-temperature operation life test, monitor the chip power consumption stability in real time, and calculate the chip power consumption deviation.

[0065] The chip mapping matrix is ​​analyzed to extract the pin index, channel index, and activation signal mapping relationship of each chip under test, ensuring that all pins of each chip under test are effectively connected to the channel;

[0066] An automatic insertion device is used. The robotic arm aligns the spring pin array of the chip test daughter board with the spring pin interface of the motherboard array of the high-temperature test platform, applies contact pressure, such as 2N, and inserts the chip test daughter board into the motherboard array of the high-temperature test platform. A multimeter is used to test the electrical continuity between the motherboard array and the chip test daughter board to confirm that all spring pins are correctly connected.

[0067] The preset activation command is transmitted to the chip under test (DUT) via shared control signals, chip select signals, and address signal lines. Using the control software of the high-temperature test platform, such as the ESPEC control interface, the high-temperature operational lifespan test conditions are set, including the temperature, humidity, power supply, and test duration of the high-temperature test chamber. Temperature and humidity sensors and voltmeters are used to verify the stability of the test conditions, ensuring that the temperature, humidity, and voltage are within preset ranges. For example, the temperature is set to 150°C with an error of ±0.5°C, and the humidity is set to 50% with an error of ±5%, to meet the specific temperature and humidity requirements of the high-temperature operational lifespan test, ensuring the stability of the entire test environment and minimizing the impact of objective factors on the high-temperature operational lifespan test. The power supply is provided through a Keysight E36300, applying 1.3 times the nominal voltage to each DUT with a voltage error of ±0.01 volts, and the test duration is 256 hours.

[0068] The programmable logic devices in the activation control area are activated, and each chip under test is selected one by one according to the activation instruction. The high-temperature test chamber is started, and a high-temperature operation life test is performed. Based on real-time monitoring of the voltage and current of the chip under test, the real-time power consumption of the chip under test is calculated. The absolute deviation between the total power consumption and the average power consumption of the chip under test is calculated by integration. The power consumption consistency of multiple chips under test under high temperature and high voltage conditions is evaluated, and the chip power consumption deviation is obtained. The calculation formula is as follows:

[0069] ;

[0070] ;

[0071] in, Indicates time The deviation between the total power consumption and the average power consumption of multiple chips under test reflects the power consumption stability of the chips under test under high temperature and high voltage conditions. This is the time point for power consumption testing. and These are the upper and lower limits of the sampling time window for voltage and current, typically represented by the value. Second, For all chips under test at time Total power consumption For the first The chip under test in time power consumption, To apply in the The voltage of the chip under test For the first The chip under test in time The current.

[0072] S3. Align and apply pressure using an automated pressing fixture to perform logic function tests, timing tests, and multi-channel voltage output tests, evaluate output consistency, and generate chip function test data.

[0073] The chip mapping matrix is ​​analyzed to extract the pin index, channel index, and activation signal mapping relationship of each chip under test, ensuring that all pins of each chip under test are effectively connected to the channel;

[0074] An automated pressing fixture is used to place the chip test sub-board onto the performance test motherboard. Specifically, the high-precision camera of the automated pressing fixture identifies the alignment marks on the chip test sub-board, such as the optical marks located in the test connection area. The pressing assembly applies pressure to the chip test sub-board via a servo motor. The uniformity of the applied pressure is verified by a pressure sensor to ensure that the 512 spring pin array of the chip test sub-board establishes a stable electrical connection with the signal terminal of the performance test motherboard. The electrical connectivity between the performance test motherboard and the chip test sub-board is tested with a multimeter to confirm that all 512 spring pins are correctly connected.

[0075] Use motherboard performance testing software, such as Keysight PathWave Test, to perform logic function tests. The specific steps are as follows:

[0076] A single chip under test (DUT) is selected, and 16 channels are selected through a decoder. Test vectors are input to verify the logic operation function of the DUT. The test vectors are predefined binary input sequences covering the 16 processing units of the DUT (each unit corresponds to one channel). The test vectors are transmitted through the signal ports of the performance test motherboard, and the output response of each channel is recorded. A logic analyzer, such as the Keysight U4154A, is used to capture the output signal and compare it with the expected output signal to calculate the logic function coverage of each DUT. The expected output signal is based on the specifications of the DUT. The test software on the performance test motherboard creates test vectors according to the specifications of the DUT and calculates the expected output corresponding to each test vector based on the truth table of the specifications of the DUT.

[0077] The same chip under test is used for both gating and logic function testing. All channels are gated through a decoder, a high-frequency clock signal, such as 100MHz, is input, the chip's clock frequency and signal delay are measured, and the absolute deviation between the measured actual clock frequency and the target clock frequency is calculated to obtain the timing error.

[0078] For both gating and logic function testing of the same chip under test (DUT), all channels are gated using a decoder. A target output voltage is set, such as 1.2 volts. A standard input signal, such as 1 volt, is applied. An analog-to-digital converter (e.g., Texas Instruments ADS127L01, sampling rate 1 MS / s) is used to measure the output voltage of each channel. The absolute average deviation between the multi-channel output voltage of the DUT and the target voltage is calculated to evaluate the multi-channel output accuracy. The output voltage deviation is calculated as follows:

[0079] ;

[0080] in, In time The average deviation between the multi-chip multi-channel output voltage and the target voltage. For the first The chip under test in the first Each channel in time Voltage measurement value at that time For the first The chip under test in the first The target voltage for each channel;

[0081] The logic function coverage, timing error, and output voltage deviation are output as chip functional test data.

[0082] S4. Based on chip power consumption deviation and chip functional test data, the entropy-based risk assessment method is used to calculate the failure probability of the chip under test. By constructing a failure mechanism decision model, the failure probability distribution is analyzed, and the power consumption stability test and functional test of the chip under test are optimized.

[0083] The chip power consumption deviation and chip function test data are normalized, and the state vector of the chip under test is constructed using the chip under test as an index.

[0084] For each chip under test, the state vector of the chip under test is discretized into state intervals, such as 10 equal-width intervals. The histogram method is used to calculate the probability of the state vector of the chip under test in each state interval by statistically analyzing the distribution frequency of the state vector of each chip under test in the state interval.

[0085] The state vector of the chip under test is aggregated to determine the probability in each state interval, and the state entropy of the chip under test is calculated as follows:

[0086] ;

[0087] in, For the first The state entropy of the chip under test The number of state intervals. This is the index variable for the state interval. For the first The state vector of the chip under test is in the th... The probability of each state interval;

[0088] By weighted normalizing the chip power consumption deviation and chip function test data, the degree to which the chip under test deviates from the expected performance is measured, and the failure score of the chip under test is obtained.

[0089] Based on the number of state intervals, the state entropy of the chip under test is normalized;

[0090] Based on the failure score and normalized state entropy of the chip under test, the failure probability of the chip under test is calculated using an exponential weighting function, as shown in the following formula:

[0091] ;

[0092] in, For the first The failure probability of each chip under test. Indicates the first The normalized state entropy of the chip under test, The base of the natural logarithm, This is a failure amplification factor, adjusting the impact of the failure score on the failure probability; a recommended value is 1. For the first Failure score of each chip under test;

[0093] Based on the failure probability of all chips under test, a failure probability histogram is plotted to statistically analyze the distribution of failure probabilities of all chips under test. The horizontal axis represents the failure probability of the chips under test, and the vertical axis represents the number of chips under test. A failure probability threshold is set based on the distribution of failure probabilities.

[0094] When the failure probability of the chip under test is greater than the failure probability threshold, it is marked as a potentially failed chip; otherwise, it is considered a non-failed chip.

[0095] Based on the standard distribution of chip power consumption deviation and chip function test data of non-failed chips, thresholds are set for chip power consumption deviation, logic function coverage, timing error, and output voltage deviation. For example, the power consumption deviation threshold is 1.5W, the logic function coverage threshold is 96%, the timing error threshold is 0.5MMz, and the output voltage deviation threshold is 0.04V. The chip power consumption deviation and chip function test data of potentially failed chips are summarized. For each potentially failed chip, the failure mechanism is defined. Specifically, when the power consumption deviation is greater than the power consumption deviation threshold, the main mechanism is oxide layer cracking; when the logic function coverage is greater than the logic function coverage threshold, the main mechanism is logic cell manufacturing defects; when the timing error is greater than the timing error threshold, the main mechanism is clock path delay; and when the output voltage deviation is greater than the output voltage deviation threshold, the main mechanism is ion contamination.

[0096] A training set is created based on the state vector, binary failure labels (potential failure and non-failure), and failure mechanism labels of the chip under test. The training set is in matrix form, with rows representing the chip under test and columns representing the state vector, binary failure labels, and failure mechanisms.

[0097] Based on classification and regression tree algorithms, a failure mechanism decision model for potential failure chips is constructed. The maximum depth and minimum number of leaf node samples of the failure mechanism classification model are initialized. By calculating the Gini index, the contributions of chip power consumption deviation, logic function coverage, timing error and output voltage deviation to failure mechanism classification are evaluated and used as segmentation criteria to obtain the failure mechanism distribution of potential failure chips.

[0098] The training set is input into the failure mechanism decision model, and the leave-one-out method is used to perform cross-validation training on the failure mechanism decision model. Taking 16 chips under test as an example, the training set of 16 chips under test is divided into a training set of 15 chips and a validation set of 1 chip. 16 iterations are performed. The state vector and failure mechanism label of the training set are extracted as input. The Gini index of the root node of the failure mechanism decision model is calculated. The state and split point with the largest information gain are selected. The training set is divided into two subsets according to the split point. The Gini index is recursively calculated for each subset. The best feature and split point of the next layer are selected. The splitting process is repeated until the stopping condition is met (reaching the maximum depth of 4, the number of subset samples ≤ 2 or the Gini index is 0). The validation set is input into the state vector test subtree of a single chip to obtain the predicted failure mechanism label. The predicted failure mechanism label is compared with the real failure mechanism label and the prediction accuracy is recorded. Different validation chips are selected in each iteration to generate 16 subtrees. The failure mechanism decision model is trained by majority voting. The above failure mechanism decision model training is the existing technology and will not be described in detail.

[0099] Based on the distribution of failure mechanisms of potentially failing chips, the power consumption stability test and functional test of the chip under test are optimized, as detailed below:

[0100] To address manufacturing defects in logic units, indicating that there are manufacturing defects in the internal logic units of the chip under test (DUT) due to photolithography errors or uneven doping, we increase the coverage of the test vectors, generate more binary sequences, focus on verifying the boundary conditions of the logic units, adjust the switch matrix configuration of the chip test board, optimize the routing of the signal routing area, and in subsequent tests, prioritize additional functional verification for DUTs with logic function coverage below the logic function coverage threshold, use a logic analyzer to capture detailed output responses, and identify the location of defects.

[0101] Clock path delay indicates that there is a delay in the internal clock path of the chip under test, which is caused by uneven wiring or capacitance effect. It can be addressed by reducing the input clock frequency, adjusting the signal routing area of ​​the chip test board, shortening the clock signal trace length, and reducing the test temperature during high-temperature operation life test to reduce the impact of thermal stress on the clock path.

[0102] Regarding ion contamination, it indicates that the large deviation in the chip channel output voltage may be due to ion contamination (such as sodium ions) during the manufacturing process affecting electrical performance. To address this, we can increase the pressure between the chip test daughterboard and the performance test motherboard, and reduce the test humidity during high-temperature operation lifespan testing to reduce the risk of ion migration.

[0103] The oxide layer cracking indicates that the leakage current of the chip increases under high temperature and high voltage. Since the oxide layer cracking is caused by this, the voltage of the high temperature operation life test can be reduced to reduce electrical stress and extend the high temperature operation life test duration. The thickness of the high temperature resistant coating can also be increased to ensure contact reliability.

[0104] This embodiment also provides a system for chip testing, including: a mapping matrix module for assembling a chip test sub-board, the chip test sub-board including a chip loading area, a test connection area, a signal routing area, a channel selection area, and an activation control area, loading multiple chips under test in the chip loading area, configuring a switch matrix, a decoder, and an activation control unit, and generating a chip mapping matrix; a power consumption deviation module for inserting the chip test sub-board into the motherboard array of a high-temperature test platform, selecting a single chip for high-temperature operation lifespan testing, monitoring chip power consumption stability in real time, and calculating chip power consumption deviation; a functional test module for aligning and applying pressure using an automated pressing fixture, performing logic function tests, timing tests, and multi-channel voltage output tests, evaluating output consistency, and generating chip functional test data; and a failure evaluation module for calculating the failure probability of the chip under test based on chip power consumption deviation and chip functional test data using an entropy-based risk assessment method, analyzing the failure probability distribution by constructing a failure mechanism decision model, and optimizing the power consumption stability test and functional test of the chip under test.

[0105] This embodiment also provides a computer device suitable for implementing a chip testing method, including: a memory and a processor; the memory is used to store computer-executable instructions, and the processor is used to execute the computer-executable instructions to implement the chip testing method proposed in the above embodiment.

[0106] The computer device can be a terminal, comprising a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device's casing, or an external keyboard, touchpad, or mouse.

[0107] This embodiment also provides a storage medium storing a computer program, which, when executed by a processor, implements the chip testing method proposed in the above embodiments. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0108] In summary, this invention dynamically generates the pin index, channel selection weight, and activation signal mapping relationship for each chip under test through three-dimensional matrix operations using a chip mapping matrix. This enables flexible configuration of test channels, adapting to the pin layout and functional requirements of different chips, reducing test configuration time and complexity. Based on the activation control unit of a programmable logic device (such as an FPGA), preset activation instructions are sent through shared control signal lines, supporting parallel testing of multiple chips and improving test efficiency.

[0109] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for chip testing, characterized in that: include, Assemble a chip test sub-board by loading multiple chips under test into the chip loading area, configuring a switch matrix, decoder, and activation control unit, and generating a chip mapping matrix; the chip test sub-board includes a chip loading area, a test connection area, a signal routing area, a channel selection area, and an activation control area; Insert the chip test daughterboard into the motherboard array of the high-temperature test platform, select a single chip for high-temperature operation life test, monitor the chip power consumption stability in real time, and calculate the chip power consumption deviation. By aligning and applying pressure using an automated pressing fixture, logic function tests, timing tests, and multi-channel voltage output tests are performed to evaluate output consistency and generate chip function test data. Based on chip power consumption deviation and chip functional test data, the failure probability of the chip under test is calculated using the entropy-based risk assessment method. The specific steps are as follows. The chip power consumption deviation and chip function test data are normalized, and the state vector of the chip under test is constructed using the chip under test as an index. For each chip under test, the state vector of the chip under test is discretized into a state interval; The histogram method is used to calculate the probability of the state vector of each chip under test in each state interval by statistically analyzing the distribution frequency of the state vector in the state interval. Aggregate the probabilities of the state vector of the chip under test in each state interval, and calculate the state entropy of the chip under test; By weighted normalizing the chip power consumption deviation and chip function test data, the degree to which the chip under test deviates from the expected performance is measured, and the failure score of the chip under test is obtained. Based on the number of state intervals, the state entropy of the chip under test is normalized; Based on the failure score and normalized state entropy of the chip under test, the failure probability of the chip under test is calculated using an exponential weighting function. By constructing a failure mechanism decision model to analyze the failure probability distribution, the power consumption stability test and functional test of the chip under test are optimized.

2. The method for implementing chip testing as described in claim 1, characterized in that: The specific steps for generating the chip mapping matrix are as follows: Based on the pin index of each chip under test, the state of the switch matrix is ​​set to generate the mapping relationship between the pin index of each chip under test and the signal routing area traces. Set the decoder's strobe signal, connect the channel selection area of ​​the chip test subboard to the decoder, and generate a mapping relationship between the channel index and the decoder's output signal; Based on the programmable logic device in the activation control area, preset activation instructions are generated, the signal transmission path of the activation instructions is matched with the chip under test, and the mapping relationship between the activation instructions and the shared signal lines of each chip under test is generated. Based on the mapping relationship between the pin index of each chip under test and the signal routing area traces, the mapping relationship between the channel index and the decoder output signal, and the mapping relationship between the activation command of each chip under test and the shared signal line, a chip mapping matrix is ​​generated through three-dimensional matrix operations.

3. The method for chip testing as described in claim 2, characterized in that: The mapping relationship between the pin index of each chip under test and the traces in the signal routing area refers to the connection and disconnection of the pins of the chip under test and the traces in the signal routing area. The mapping relationship between the channel index and the decoder output signal refers to whether the channel is selected, and if so, whether the selection is valid. The mapping relationship between the activation command of each chip under test and the shared signal line indicates whether the chip under test has received the activation command and been activated.

4. The method for implementing chip testing as described in claim 1, characterized in that: The specific steps for calculating the chip power consumption deviation are as follows: The programmable logic device in the activation control area selects each chip under test one by one according to the activation instruction, starts the high-temperature test chamber, and performs high-temperature operation life test. The chip power consumption deviation is obtained by calculating the absolute deviation between the total power consumption and the average power consumption of the chip under test through integration.

5. The method for implementing chip testing as described in claim 1, characterized in that: The specific steps for generating chip functional test data are as follows: Test vectors are transmitted through the signal ports of the performance test motherboard, the output response of each channel is recorded, and the output signal is captured using a logic analyzer. The output signal is then compared with the expected output signal to calculate the logic function coverage of each chip under test. By using a decoder to select all channels, inputting a high-frequency clock signal, measuring the chip's clock frequency and signal delay, and calculating the absolute deviation between the measured actual clock frequency and the target clock frequency, the timing error is obtained. The output voltage of each channel is measured using an analog-to-digital converter, and the absolute average deviation between the multi-channel output voltage of the chip under test and the target voltage is calculated to obtain the output voltage deviation. The logic function coverage, timing error, and output voltage deviation are output as chip functional test data.

6. The method for implementing chip testing as described in claim 1, characterized in that: The chip test sub-board uses a multilayer printed circuit board with a high-temperature resistant coating on the surface. The pin array of the chip loading area supports multiple chip package types. The activation control area is dynamically configured with preset activation instructions through programmable logic devices.

7. A system for implementing chip testing, based on the method for implementing chip testing according to any one of claims 1 to 6, characterized in that: include, The mapping matrix module is used to assemble a chip test sub-board. The chip test sub-board includes a chip loading area, a test connection area, a signal routing area, a channel selection area, and an activation control area. Multiple chips under test are loaded in the chip loading area, and a switch matrix, decoder, and activation control unit are configured to generate a chip mapping matrix. The power consumption deviation module is used to insert the chip test daughterboard into the motherboard array of the high temperature test platform, select a single chip for high temperature operation life test, monitor the chip power consumption stability in real time, and calculate the chip power consumption deviation. The functional test module is used to perform logic function tests, timing tests, and multi-channel voltage output tests by aligning and applying pressure through an automated pressing fixture, evaluating output consistency, and generating chip functional test data. The failure evaluation module is used to calculate the failure probability of the chip under test based on chip power consumption deviation and chip functional test data, using the entropy-based risk assessment method. By constructing a failure mechanism decision model, it analyzes the failure probability distribution and optimizes the power consumption stability test and functional test of the chip under test.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, it implements the steps of the chip testing method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the steps of the chip testing method according to any one of claims 1 to 6.

Images