A low-power hot-start method for multi-core systems and the multi-core system

Abstract

This invention belongs to the field of low-power technology and discloses a low-power hot-start method for a multi-core system and a multi-core system. The method includes: when a target functional module needs to enter a low-power state, controlling the first random access memory area corresponding to the target functional module to enter a low-power data retention state, controlling the second random access memory area corresponding to the target functional module to be powered off, and controlling the target processing core implementing the target functional module to enter a sleep state; upon receiving a startup command, running a secondary bootloader in the first random access memory area, which calls a communication interface maintenance program to establish a communication connection with the host; downloading the service firmware of the target functional module to the second random access memory area through the secondary bootloader; and running the service firmware in the second random access memory area. This allows the functional module to enter a low-power standby state when idle and achieve rapid hot-start upon receiving a wake-up command, thus balancing low power consumption and high response speed.

Description

Technical Field

[0001] This invention belongs to the field of low-power technology, and specifically relates to a low-power hot-start method for multi-core systems and the multi-core system itself. Background Technology

[0002] With the rapid development of mobile communications, the Internet of Things (IoT), and portable electronic devices, extremely high demands are placed on the battery life of these devices. Therefore, effectively reducing power consumption has become one of the core research topics in this field. Embedded systems, especially functional chips used as peripherals (such as wireless connectivity chips (WCNs), modems, etc.), are used to implement functional modules and are typically not continuously operating within the device, but are only activated when the host requires their services. Managing power consumption during idle periods without service demand is crucial for achieving overall low power consumption for the device.

[0003] In existing technologies, the common low-power management method for the aforementioned functional modules is to completely cut off their power supply when there is no service demand. This method reduces the static power consumption of the functional module to zero, making it the most thorough way to achieve the lowest power consumption. However, its significant drawback is that when the host needs to reactivate the functional module, a complete cold start process must be executed. This process is time-consuming, significantly increasing system response latency and failing to meet the needs of applications with high real-time requirements. Summary of the Invention

[0004] The purpose of this invention is to provide a low-power control method for multi-core systems, enabling functional modules to enter a low-power standby state when idle and to achieve rapid hot start upon receiving a wake-up command, thereby balancing low power consumption and high response speed.

[0005] In a first aspect, embodiments of the present invention provide a low-power hot-start method for a multi-core system, wherein the multi-core system is connected to a host computer, the multi-core system includes multiple processing cores, each processing core being configured to implement a functional module, and the method includes:

[0006] When any target functional module among the plurality of functional modules needs to enter a low-power state, the first random storage area corresponding to the target functional module is controlled to enter a low-power data retention state, the second random storage area corresponding to the target functional module is controlled to be powered off, and the target processing core implementing the target functional module is controlled to enter a sleep state; wherein, the first random storage area is used to store the secondary boot program and the communication interface maintenance program, and the capacity of the first random storage area is smaller than the capacity of the second random storage area.

[0007] Upon receiving a startup command, the secondary bootloader in the first random access memory area is run, and the secondary bootloader calls the communication interface maintenance program to establish a communication connection with the host.

[0008] The secondary bootloader downloads the service firmware of the target functional module to the second random storage area.

[0009] Run the service firmware in the second random storage area to restore the operation of the target functional module.

[0010] Optionally, the first random access memory region and the second random access memory region are logical regions partitioned within the same physical RAM of the target processing core; the second random access memory region is used to store the main business firmware and data of the target functional module.

[0011] Furthermore, for any functional module, the capacity of the first random storage area corresponding to the functional module is independently configured according to the communication interface type and / or wake-up latency requirements of the functional module.

[0012] Optionally, controlling the first random access memory area corresponding to the target functional module to enter a low-power data retention state includes:

[0013] The power management circuit controls the first random access memory region to enter an ultra-low power data retention state. In the ultra-low power data retention state, the power supply voltage of the first random access memory region is reduced to a data retention voltage that can maintain data without loss; and the first random access memory region cannot respond to normal read and write access operations.

[0014] Optionally, the startup command is:

[0015] A wake-up command sent by the host through the communication interface;

[0016] Alternatively, a wake-up signal triggered by an external interrupt signal, including interrupt signals triggered by changes in the level of a general-purpose input / output pin, timeout of a real-time timer, or sensor data reaching a threshold.

[0017] Optionally, the method further includes:

[0018] Before the step of downloading the service firmware of the target functional module to the second random storage area through the secondary bootloader, the service firmware of the target functional module is security verified through the secondary bootloader to obtain the verification result;

[0019] If the verification result is that the business firmware security verification is passed, the step of downloading the business firmware of the target functional module to the second random storage area through the secondary boot program is executed.

[0020] Optionally, the target functional module is a wireless communication module, which includes a Wi-Fi module and a Bluetooth module.

[0021] Secondly, embodiments of the present invention provide a multi-core system connected to a host, comprising:

[0022] Multiple processing cores, each configured to implement a functional module;

[0023] The power management circuit is coupled to the plurality of processing cores;

[0024] The power management circuit is configured as follows:

[0025] When any target functional module among the plurality of functional modules needs to enter a low-power state, the first random storage area corresponding to the target functional module is controlled to enter a low-power data retention state, the second random storage area corresponding to the target functional module is controlled to be powered off, and the target processing core implementing the target functional module is controlled to enter a sleep state; wherein, the first random storage area is used to store the secondary boot program and the communication interface maintenance program, and the capacity of the first random storage area is smaller than the capacity of the second random storage area.

[0026] Upon receiving a startup command, the secondary bootloader in the first random access memory area is run, and the secondary bootloader calls the communication interface maintenance program to establish a communication connection with the host.

[0027] The secondary bootloader downloads the service firmware of the target functional module to the second random storage area.

[0028] Run the service firmware in the second random storage area to restore the operation of the target functional module.

[0029] Optionally, the first random access memory region and the second random access memory region are logical regions partitioned within the same physical RAM of the target processing core; the second random access memory region is used to store the main business firmware and data of the target functional module.

[0030] Furthermore, for any functional module, the capacity of the first random storage area corresponding to the functional module is independently configured according to the communication interface type and / or wake-up latency requirements of the functional module.

[0031] Optionally, controlling the first random access memory area corresponding to the target functional module to enter a low-power data retention state includes:

[0032] The power management circuit controls the first random access memory region to enter an ultra-low power data retention state. In the ultra-low power data retention state, the power supply voltage of the first random access memory region is reduced to a data retention voltage that can maintain data without loss; and the first random access memory region cannot respond to normal read and write access operations.

[0033] Optionally, the startup command is:

[0034] A wake-up command sent by the host through the communication interface;

[0035] Alternatively, a wake-up signal triggered by an external interrupt signal, including interrupt signals triggered by changes in the level of a general-purpose input / output pin, timeout of a real-time timer, or sensor data reaching a threshold.

[0036] Optionally, the method further includes:

[0037] Before the step of downloading the service firmware of the target functional module to the second random storage area through the secondary bootloader, the service firmware of the target functional module is security verified through the secondary bootloader to obtain the verification result;

[0038] If the verification result is that the business firmware security verification is passed, the step of downloading the business firmware of the target functional module to the second random storage area through the secondary boot program is executed.

[0039] Optionally, the target functional module is a wireless communication module, which includes a Wi-Fi module and a Bluetooth module.

[0040] Thirdly, embodiments of the present invention provide a computer-readable storage medium that, when instructions in the computer-readable storage medium are executed by a multi-core system, enables the multi-core system to perform the method described in the first aspect.

[0041] Fourthly, embodiments of the present invention provide a computer program product, including a computer program that, when executed by a multi-core system, implements the method described in the first aspect.

[0042] The technical solution provided by this invention, through innovative RAM partitioning design and refined power control, achieves partial maintenance and partial power-off of the system state. The ultimate technical effect is that standby power consumption approaches the ultra-low level of a "complete power-off" solution, while startup speed approaches the instantaneous response capability of a "completely power-on" solution, thus solving the technical dilemma of the incompatibility between low power consumption and fast startup in traditional solutions. Furthermore, by completely powering off the second random access memory area, which occupies most of the memory, and controlling the processing core to enter hibernation, the static leakage current and dynamic power consumption of these two major power sources are fundamentally eliminated. Simultaneously, maintaining only a very small area of ​​the first random access memory area at a nanoampere level data retention state minimizes the overall standby power consumption of the system. Since the first random access memory area is always powered, the secondary boot program and communication interface maintenance program stored within it are immediately available. After system wake-up, there is no need to execute time-consuming ROM code initialization, communication interface enumeration, and basic driver loading processes; execution can jump directly, thus greatly shortening the recovery time from receiving instructions to full readiness.

[0043] Moreover, the rapid response capability brought by fast warm-up greatly reduces the perceived delay in function activation. At the same time, the frequent switching between active and sleep states without significant power consumption provides greater flexibility in system design and contributes to overall energy efficiency improvement.

[0044] Furthermore, compared to the approach of using two independent physical RAMs, this invention preferably achieves partition management through logical partitioning, eliminating the need for additional physical memory resources, saving chip area, and reducing manufacturing costs. Moreover, by verifying the downloaded business firmware through a secondary bootloader, the integrity and reliability of the firmware are ensured, avoiding multi-core system boot failures or security risks due to firmware errors or tampering, thus guaranteeing the reliability and security of the multi-core system. Attached Figure Description

[0045] Figure 1 A flowchart of a low-power hot-start method for a multi-core system provided in an embodiment of the present invention;

[0046] Figure 2 A block diagram of a system architecture provided for an embodiment of the present invention;

[0047] Figure 3 This is a schematic diagram of the overall technical solution of an embodiment of the present invention;

[0048] Figure 4 This is a schematic diagram of the structure of a multi-core system according to an embodiment of the present invention. Detailed Implementation

[0049] The present invention will be described in detail below through embodiments.

[0050] With the rapid development of mobile communications, the Internet of Things (IoT), and portable electronic devices, extremely high demands are placed on the battery life of these devices. Therefore, effectively reducing power consumption has become one of the core research topics in this field. Embedded systems, especially functional chips used as peripherals (such as wireless connectivity chips (WCNs), modems, etc.), are used to implement functional modules and are typically not continuously operating within the device, but are only activated when the host requires their services. Managing power consumption during idle periods without service demand is crucial for achieving overall low power consumption for the device.

[0051] In existing technologies, the common low-power management method for the aforementioned functional modules is to completely cut off their power supply when there is no service demand. This method reduces the static power consumption of the functional module to zero, making it the most thorough way to achieve the lowest power consumption. However, its significant drawback is that when the host needs to reactivate the functional module, a complete cold start process must be executed. This process is time-consuming, significantly increasing system response latency and failing to meet the needs of applications with high real-time requirements.

[0052] To address the aforementioned technical problems in the prior art, embodiments of the present invention provide a low-power hot-start method, apparatus, and multi-core system for a multi-core system.

[0053] The key to this invention is that, for some functional modules, when there is no business activity, they can complete the rapid multi-core system startup without completely shutting down, but while maintaining very low power consumption.

[0054] To ensure clarity in the description of the solutions, the technical terms involved in the embodiments of the present invention will be explained before introducing them.

[0055] 1. A multi-core system refers to a system that contains multiple CPU cores. For example, the WCN wireless connectivity chip system contains multiple Cortex M33 cores.

[0056] 2. USB communication, short for Universal Serial Bus, is a serial bus standard and a technical specification for input / output interfaces.

[0057] 3. RAM (Random Access Memory) is a type of memory used to store temporary data, allowing random access and writing of data. Data in RAM is lost when power is turned off.

[0058] 4. RAM retention refers to the ability of certain RAM regions to retain data without initialization after a software reset. This feature is extremely useful in embedded systems, especially when critical data or status information needs to be saved.

[0059] 5. Firmware is the program that runs on a chip or other device.

[0060] After introducing the above technical terms, the following will provide a detailed description of a low-power hot-start method for a multi-core system and the multi-core system provided by the embodiments of the present invention.

[0061] This invention provides a low-power hot-start method for a multi-core system. The multi-core system is connected to a host and includes multiple processing cores (also known as CPU cores). Each processing core is configured to implement a functional module, wherein the functional module can be a wireless communication module, which mainly includes a Wi-Fi module and a Bluetooth module.

[0062] like Figure 1 As shown, the method may include the following steps:

[0063] S110, when any target functional module among multiple functional modules needs to enter a low-power state, the first random storage area corresponding to the target functional module is controlled to enter a low-power data retention state, the second random storage area corresponding to the target functional module is powered off, and the target processing core that implements the target functional module is controlled to enter a sleep state.

[0064] The first random access storage area is used to store the secondary boot program and the communication interface maintenance program, and the capacity of the first random access storage area is smaller than the capacity of the second random access storage area.

[0065] In one implementation of this invention, the first random access memory (RAM) region and the second random access memory (RAM) region can be two logical regions partitioned by a memory controller within the same physical RAM of the target processing core. The first RAM region and the second random access memory region can be two independent physical RAMs. The capacity of the first RAM region is much smaller than that of the second RAM region. The capacity of the first RAM region can be pre-configured based on the communication interface type and wake-up latency requirements of the target functional module, only needing to store the most basic boot and communication programs, thereby minimizing the area of ​​the constantly powered area and reducing overall power consumption. This invention does not specifically limit the capacity of the first RAM region; it can be determined according to actual conditions.

[0066] For example, for communication interface types, the capacity of the first random access memory required by a functional module that processes gigabit Ethernet is typically greater than the capacity of the first random access memory required by a functional module that processes low-speed serial ports.

[0067] For wake-up latency requirements, functional modules with extremely high real-time requirements (such as voice wake-up) usually need a slightly larger first random access memory area to save more context states in order to achieve instant recovery; while functional modules that are not sensitive to latency can use a very small first random access memory area to save area and power consumption.

[0068] The above example is to illustrate that the capacity of the first random access memory area can be determined according to the actual situation for different functional modules, but for the same functional module, the capacity of the first random access memory area is much smaller than the capacity of the second random access memory area.

[0069] Specifically, when any target functional module (such as a Wi-Fi module or Bluetooth module) in a multi-core system completes its current business processing, it needs to enter a low-power state to save power. At this time, the power management circuit of the multi-core system can receive a sleep command sent by the host and perform corresponding control on the first random access memory area, the second random access memory area, and the target processing core that implements the target functional module. The control operations of the first random access memory area, the second random access memory area, and the target processing core will be described in detail below.

[0070] First, the power management circuit controls the first random access memory region to enter an ultra-low power data retention state. In the ultra-low power data retention state, the power supply voltage of the first random access memory region is reduced to a data retention voltage that can maintain data without loss; and the first random access memory region cannot respond to normal read and write access operations.

[0071] Specifically, the process of controlling the first random access memory region to enter a low-power data retention state can be as follows: the voltage regulator inside the power management circuit reduces the voltage supplied to the first random access memory region to a data retention voltage that can only maintain its internal data from loss, while simultaneously cutting off its clock signal. At this time, the first random access memory region cannot respond to any external read / write access operations, but its internally stored secondary boot program and communication interface maintenance program, and other critical data, are completely preserved, thus laying the foundation for subsequent rapid warm-up.

[0072] Secondly, the specific process of powering down the second random access memory area corresponding to the target functional module can be as follows: the power management circuit completely cuts off the power supply to the second random access memory area corresponding to the target functional module. This eliminates all static and dynamic power consumption in the second random access memory area, which is a key step in achieving ultra-low standby power consumption. Furthermore, since the second random access memory area is mainly used to store the main business firmware and runtime data of the target functional module, this data does not need to be retained after entering the low-power state. Therefore, powering down the second random access memory area will not affect the functional integrity of the multi-core system. When the power supply is cut off, all data in the second random access memory area is lost.

[0073] Third, the process of controlling the target processing core of the target functional module to enter a sleep state can be as follows: the power management circuit cuts off the clock signal input to the target processing core through clock gating technology, and can also reduce its supply voltage through power gating technology. This can significantly reduce the dynamic and static power consumption of the target processing core, putting it in an inactive state that can be quickly woken up.

[0074] It should be noted that the control operations on the first random access memory area, the second random access memory area, and the target processing core are not strictly ordered. They can be executed in parallel by the power management circuit or in any order. The purpose is to enable the target functional module as a whole to enter a standby state with extremely low power consumption but rapid recovery.

[0075] S120: Upon receiving a boot command, the secondary boot program in the first random access memory area is run. The secondary boot program then calls the communication interface maintenance program to establish a communication connection with the host.

[0076] Specifically, when a multi-core system needs to recover from a low-power state, a warm-start process for the target functional module is triggered upon receiving a startup command. The startup command can be a specific wake-up command actively sent by the host through a communication interface (such as USB), or a wake-up signal triggered by an external interrupt signal (such as a GPIO level change, sensor triggering, or timer timeout). This embodiment of the invention does not specifically limit the source of the startup command.

[0077] Once the power management circuitry of a multi-core system detects the startup command, it performs the following operations:

[0078] First, power supply and startup environment are restored. Specifically, the power management circuit restores the normal operating voltage to the first random access memory area, causing it to exit the low-power data retention state. Simultaneously, it releases the sleep control of the target processing core, provides it with a clock signal, and wakes it from sleep mode to prepare for instruction execution.

[0079] Secondly, the process jumps to the secondary bootloader. After the target processing core wakes up, its program counter is directly redirected by hardware or firmware logic to a specific address in the first random access memory area, and the secondary bootloader stored in the first random access memory area begins execution. It is evident that this process completely skips the primary boot code stored in ROM that must be executed when a multi-core system powers on, thus saving a significant amount of initialization time.

[0080] Secondly, the secondary bootloader, acting as the overall coordinator of the warm boot process, executes the following key tasks in sequence:

[0081] The first key task is to perform minimal hardware initialization. Specifically, the secondary bootloader first executes a piece of lightweight initialization code to configure the most basic working environment of the target processing core (e.g., initializing the stack pointer and disabling interrupts), a process that takes very little time.

[0082] The second key task is to invoke and run the communication interface maintenance program. Specifically, the secondary bootloader locates, invokes, and jumps to the communication interface maintenance program, which is also stored in the first random access memory area. This communication interface maintenance program is dedicated code optimized for low-power wake-up scenarios. It is configured to: initialize the interface controller (such as a USB device controller) necessary for communication with the host, and execute the necessary protocol processes required to re-establish a complete communication link with the host. For example, if the communication interface is USB, it performs a fast USB device enumeration process to restore the high-speed data transfer channel with the host.

[0083] Once the communication interface maintenance program has successfully completed its operation, a stable and reliable communication connection is established between the multi-core system and the host, preparing for the subsequent download of service firmware.

[0084] At this point, the most time-consuming communication link reconstruction phase of the warm boot process has been completed. Since the secondary bootloader and communication interface maintenance program are both resident in the first random access memory area and their states are maintained, the system does not need to reload them from slow non-volatile memory (such as Flash) or perform a complete hardware initialization, thus achieving a very fast recovery from a low-power state to a communication-ready state.

[0085] S130 downloads the service firmware of the target functional module to the second random access storage area through the secondary boot program.

[0086] Specifically, after the secondary bootloader successfully calls the communication interface maintenance program and establishes a stable communication connection with the host, the multi-core system then enters the business firmware loading stage. The core of this step is to efficiently and reliably load the complete business function firmware into the power-off secondary random access memory area through the restored high-speed communication channel and resume its execution.

[0087] The specific process may include the following steps:

[0088] The first step is to initiate a firmware transfer request. Specifically, the secondary bootloader sends a request message to the host through the established communication interface. This request message requests the latest service firmware image of the target functional module. The request message may include the identifier of the target functional module, the version number of the required firmware, and other information to ensure that the host sends the correct firmware package.

[0089] The second step is to receive and verify the firmware data. Specifically, after receiving the aforementioned request message, the host retrieves the corresponding business firmware data from its own storage system and transmits the firmware data stream at high speed to the multi-core system via a communication interface (such as USB bulk transfer or PCIe memory write operation). The secondary bootloader can allocate a temporary buffer in the first random access memory area to receive these data packets and can perform the following operations:

[0090] As one implementation of the present invention, before the step of downloading the service firmware of the target functional module to the second random storage area through the secondary boot program, the service firmware of the target functional module is security verified through the secondary boot program to obtain the verification result.

[0091] If the verification result is that the business firmware security verification is passed, the step of downloading the business firmware of the target functional module to the second random storage area through the secondary bootloader is executed.

[0092] Specifically, the Cyclic Redundancy Check (CRC) code of the received data or its digital signature can be calculated to ensure that the firmware has not been erroneous or tampered with during transmission, thereby achieving secure verification of the business firmware.

[0093] As another implementation of this invention, the order of the service firmware can also be reassembled. Specifically, if data transmission uses a packet-splitting mechanism, the secondary bootloader is responsible for sorting and reassembling the data packets to reconstruct a complete firmware image.

[0094] The third step involves writing the firmware data obtained in the second step into the second random access memory area. Specifically, after the firmware data is verified to be correct, the secondary bootloader controls the writing of the reconstructed complete service firmware image to a predetermined address in the second random access memory area, which has now been powered on. During this period, the power management circuitry has already restored normal power to the second random access memory area in advance, either in response to the instructions of the secondary bootloader or according to a preset timing sequence. The process of writing the firmware data obtained in the second step into the second random access memory area can be done block by block or by direct DMA transfer to achieve maximum efficiency.

[0095] S140, run the service firmware in the second random access memory area to restore the operation of the target functional module.

[0096] Specifically, after the entire business firmware is successfully downloaded and written to the second random access memory area, the secondary bootloader executes the final jump instruction, redirecting the program execution flow from itself (located in the first random access memory area) to the entry address of the business firmware in the second random access memory area. At this point, the target processing core begins executing the main business code of the target functional module, and the module's functionality is fully restored, enabling it to respond normally to the host's business commands.

[0097] The low-power hot-start method provided in this invention has significant differences and advantages over the cold-start process of the prior art in that: this invention does not require re-downloading the secondary boot program and communication interface maintenance program that are already resident in the first storage area, but only needs to download the volatile service firmware, which greatly reduces the amount of data transmission and shortens the recovery time.

[0098] The technical solution provided by this invention, through innovative RAM partitioning design and refined power control, achieves partial maintenance and partial power-off of the system state. The ultimate technical effect is that standby power consumption approaches the ultra-low level of a "complete power-off" solution, while startup speed approaches the instantaneous response capability of a "completely power-on" solution, thus solving the technical dilemma of the incompatibility between low power consumption and fast startup in traditional solutions. Furthermore, by completely powering off the second random access memory area, which occupies most of the memory, and controlling the processing core to enter hibernation, the static leakage current and dynamic power consumption of these two major power sources are fundamentally eliminated. Simultaneously, maintaining only a very small area of ​​the first random access memory area at a nanoampere level data retention state minimizes the overall standby power consumption of the system. Since the first random access memory area is always powered, the secondary boot program and communication interface maintenance program stored within it are immediately available. After system wake-up, there is no need to execute time-consuming ROM code initialization, communication interface enumeration, and basic driver loading processes; execution can jump directly, thus greatly shortening the recovery time from receiving instructions to full readiness.

[0099] Moreover, the rapid response capability brought by fast warm-up greatly reduces the perceived delay in function activation. At the same time, the frequent switching between active and sleep states without significant power consumption provides greater flexibility in system design and contributes to overall energy efficiency improvement.

[0100] Furthermore, compared to the approach of using two independent physical RAMs, this invention preferably achieves partition management through logical partitioning, eliminating the need for additional physical memory resources, saving chip area, and reducing manufacturing costs. Moreover, by verifying the downloaded business firmware through a secondary bootloader, the integrity and reliability of the firmware are ensured, avoiding multi-core system boot failures or security risks due to firmware errors or tampering, thus guaranteeing the reliability and security of the multi-core system.

[0101] After a detailed description of the low-power warm-start method for multi-core systems provided in the embodiments of the present invention, the system architecture of the embodiments of the present invention will be described below with reference to specific examples. For example... Figure 2 The diagram shown is a block diagram of the entire multi-core system. This multi-core system can include multiple CPU cores, such as... Figure 2 Core 1, Core 2, ..., Core n, each core is configured to implement a functional module (corresponding to...) Figure 2 The core consists of Service 1, Service 2, ..., Service n, each with corresponding ROM (Read-Only Memory) and RAM resources. Alternatively, some cores may lack ROM resources, but each part of the cores has RAM resources. The capacity of the RAM resources corresponding to each core can be determined based on the service requirements.

[0102] In existing technologies, each core corresponds to one RAM resource. This invention divides the RAM resource into two parts, referred to as RAM0 (the second random access memory area described in the above embodiments) and RAM1 (the first random access memory area described in the above embodiments). RAM1 has a smaller capacity, only needing to maintain interface communication (where the communication interface controller refers to a digital logic unit responsible for protocol processing and data scheduling, belonging to a chip-level component; and the communication interface PHY is a physical layer chip responsible for signal conversion and electrical connection, belonging to a board-level component; the two work together but are at different levels), and handle minor system overhead such as secondary boot, for example, USB enumeration and related event processing, and implementing business boot functions. RAM0, with a larger capacity, is used to implement the requirements of the business itself. In this embodiment, RAM0 and RAM1 can be controlled independently; that is, in a low-power state, RAM1 can be controlled to maintain low-power data, and RAM0 can be controlled to power off. The specific control process has been described in detail in the above embodiments and will not be repeated here.

[0103] The overall technical solution of the embodiments of the present invention will be further described in detail below with reference to examples.

[0104] like Figure 3As shown in the diagram, this embodiment divides the storage space into six parts. Region ① contains the ROM code for service 1, and regions ② and ③ correspond to... Figure 2 In the illustrated embodiment, the RAM1 region is used, while the remaining regions are RAM0 regions. The specific size of the RAM1 region can be flexibly configured according to actual application needs. Its main function is to maintain the system communication interface and implement the secondary boot function. It is worth noting that the capacity of RAM1 is much smaller than the total RAM required to run the complete business functions. Figure 3 Business 1, Business 2, and Business 3 in the context of Figure 2 The meanings are the same, and they can refer to functional modules.

[0105] The workflow of a multi-core system is as follows:

[0106] A. The processing core of Service 1 first executes its ROM code to complete initialization. This ROM code contains the basic system boot functions, enabling the multi-core system to be correctly recognized after establishing communication with the host and to receive firmware downloads through the communication interface. It should be noted that in the entire multi-core system, only one copy of the ROM code needs to exist; it does not need to be configured separately for each processing core.

[0107] B. The main function of the ROM code is to download the firmware to the RAM1 area. After the download is complete, the system runs the code within RAM1, which ensures that the system can maintain normal communication with external devices. RAM1 mentioned here can be the RAM1 area corresponding to any processing core in the system.

[0108] C. When at least one service in the system is running, if any of the services enters an idle state and needs to switch to a low-power state, the RAM1 area corresponding to that service will enter a data retention state, its corresponding processing core will suspend execution, the RAM0 area will be powered off, and the whole system will enter a low-power standby mode, waiting for the next wake-up to quickly resume operation.

[0109] D. If all services in the system enter a stopped state, all processing cores switch to their corresponding RAM1 for operation. Subsequently, all RAM0 areas are powered off, each processing core enters a hibernation state, and all RAM1 areas enter a data retention state. At this time, the system maintains operation with minimal RAM1 resource consumption, waiting for a service wake-up signal to trigger a fast warm start. The specific warm start process has been described in detail in the previous embodiments and will not be repeated here.

[0110] This invention also provides a multi-core system 40, connected to a host 41, such as... Figure 4 As shown, it includes:

[0111] Multiple processing cores 401, namely processing core 1, processing core 2, ..., processing core n, each processing core is configured to implement a functional module;

[0112] Power management circuit 402 is coupled to the plurality of processing cores;

[0113] The power management circuit is configured as follows:

[0114] When any target functional module among the plurality of functional modules needs to enter a low-power state, the first random storage area corresponding to the target functional module is controlled to enter a low-power data retention state, the second random storage area corresponding to the target functional module is controlled to be powered off, and the target processing core implementing the target functional module is controlled to enter a sleep state; wherein, the first random storage area is used to store the secondary boot program and the communication interface maintenance program, and the capacity of the first random storage area is smaller than the capacity of the second random storage area.

[0115] Upon receiving a startup command, the secondary bootloader in the first random access memory area is run, and the secondary bootloader calls the communication interface maintenance program to establish a communication connection with the host.

[0116] The secondary bootloader downloads the service firmware of the target functional module to the second random storage area.

[0117] Run the service firmware in the second random storage area to restore the operation of the target functional module.

[0118] Optionally, the first random access memory region and the second random access memory region are logical regions partitioned within the same physical RAM of the target processing core; the second random access memory region is used to store the main business firmware and data of the target functional module.

[0119] Furthermore, for any functional module, the capacity of the first random storage area corresponding to the functional module is independently configured according to the communication interface type and / or wake-up latency requirements of the functional module.

[0120] Optionally, controlling the first random access memory area corresponding to the target functional module to enter a low-power data retention state includes:

[0121] The power management circuit controls the first random access memory region to enter an ultra-low power data retention state. In the ultra-low power data retention state, the power supply voltage of the first random access memory region is reduced to a data retention voltage that can maintain data without loss; and the first random access memory region cannot respond to normal read and write access operations.

[0122] Optionally, the startup command is:

[0123] A wake-up command sent by the host through the communication interface;

[0124] Alternatively, a wake-up signal triggered by an external interrupt signal, including interrupt signals triggered by changes in the level of a general-purpose input / output pin, timeout of a real-time timer, or sensor data reaching a threshold.

[0125] Optionally, the method further includes:

[0126] Before the step of downloading the service firmware of the target functional module to the second random storage area through the secondary bootloader, the service firmware of the target functional module is security verified through the secondary bootloader to obtain the verification result;

[0127] If the verification result is that the business firmware security verification is passed, the step of downloading the business firmware of the target functional module to the second random storage area through the secondary boot program is executed.

[0128] Optionally, the target functional module is a wireless communication module, which includes a Wi-Fi module and a Bluetooth module.

[0129] This invention also provides a computer-readable storage medium that, when the instructions in the computer-readable storage medium are executed by a multi-core system, enables the multi-core system to perform the method described in the first aspect.

[0130] This invention also provides a computer program product, including a computer program that, when executed by a multi-core system, implements the method described in the first aspect.

[0131] The technical solution provided by this invention, through innovative RAM partitioning design and refined power control, achieves partial maintenance and partial power-off of the system state. The ultimate technical effect is that standby power consumption approaches the ultra-low level of a "complete power-off" solution, while startup speed approaches the instantaneous response capability of a "completely power-on" solution, thus solving the technical dilemma of the incompatibility between low power consumption and fast startup in traditional solutions. Furthermore, by completely powering off the second random access memory area, which occupies most of the memory, and controlling the processing core to enter hibernation, the static leakage current and dynamic power consumption of these two major power sources are fundamentally eliminated. Simultaneously, maintaining only a very small area of ​​the first random access memory area at a nanoampere level data retention state minimizes the overall standby power consumption of the system. Since the first random access memory area is always powered, the secondary boot program and communication interface maintenance program stored within it are immediately available. After system wake-up, there is no need to execute time-consuming ROM code initialization, communication interface enumeration, and basic driver loading processes; execution can jump directly, thus greatly shortening the recovery time from receiving instructions to full readiness.

[0132] Moreover, the rapid response capability brought by fast warm-up greatly reduces the perceived delay in function activation. At the same time, the frequent switching between active and sleep states without significant power consumption provides greater flexibility in system design and contributes to overall energy efficiency improvement.

[0133] Furthermore, compared to the approach of using two independent physical RAMs, this invention preferably achieves partition management through logical partitioning, eliminating the need for additional physical memory resources, saving chip area, and reducing manufacturing costs. Moreover, by verifying the downloaded business firmware through a secondary bootloader, the integrity and reliability of the firmware are ensured, avoiding multi-core system boot failures or security risks due to firmware errors or tampering, thus guaranteeing the reliability and security of the multi-core system.

[0134] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention without departing from the principles and spirit of the present invention.

Claims

1. A low-power hot-start method for a multi-core system, characterized in that, The multi-core system is connected to a host computer, and the multi-core system includes multiple processing cores, each of which is configured to implement a functional module. The method includes: When any target functional module among multiple functional modules needs to enter a low-power state, the first random storage area corresponding to the target functional module is controlled to enter a low-power data retention state, the second random storage area corresponding to the target functional module is controlled to be powered off, and the target processing core that implements the target functional module is controlled to enter a sleep state; wherein, the first random storage area is used to store the secondary boot program and the communication interface maintenance program, and the capacity of the first random storage area is smaller than the capacity of the second random storage area. Upon receiving a startup command, the secondary bootloader in the first random access memory area is run, and the secondary bootloader calls the communication interface maintenance program to establish a communication connection with the host. The secondary bootloader downloads the service firmware of the target functional module to the second random storage area. Run the service firmware in the second random storage area to restore the operation of the target functional module.

2. The method according to claim 1, characterized in that, The first random access memory region and the second random access memory region are logical regions partitioned within the same physical RAM of the target processing core; the second random access memory region is used to store the main business firmware and data of the target functional module; Furthermore, for any functional module, the capacity of the first random storage area corresponding to the functional module is independently configured according to the communication interface type and / or wake-up latency requirements of the functional module.

3. The method according to claim 1, characterized in that, The step of controlling the first random access memory area corresponding to the target functional module to enter a low-power data retention state includes: The power management circuit controls the first random access memory region to enter an ultra-low power data retention state. In the ultra-low power data retention state, the power supply voltage of the first random access memory region is reduced to a data retention voltage that can maintain data without loss; and the first random access memory region cannot respond to normal read and write access operations.

4. The method according to claim 1, characterized in that, The startup command is: A wake-up command sent by the host through the communication interface; Alternatively, a wake-up signal triggered by an external interrupt signal, including interrupt signals triggered by changes in the level of a general-purpose input / output pin, timeout of a real-time timer, or sensor data reaching a threshold.

5. The method according to any one of claims 1 to 4, characterized in that, The method further includes: Before the step of downloading the service firmware of the target functional module to the second random storage area through the secondary bootloader, the service firmware of the target functional module is security verified through the secondary bootloader to obtain the verification result; If the verification result is that the business firmware security verification is passed, the step of downloading the business firmware of the target functional module to the second random storage area through the secondary boot program is executed.

6. The method according to any one of claims 1 to 4, characterized in that, The target functional module is a wireless communication module, which includes a Wi-Fi module and a Bluetooth module.

7. A multi-core system connected to a host computer, characterized in that, include: Multiple processing cores, each configured to implement a functional module; The power management circuit is coupled to the plurality of processing cores; The power management circuit is configured as follows: When any target functional module among multiple functional modules needs to enter a low-power state, the first random storage area corresponding to the target functional module is controlled to enter a low-power data retention state, the second random storage area corresponding to the target functional module is controlled to be powered off, and the target processing core that implements the target functional module is controlled to enter a sleep state; wherein, the first random storage area is used to store the secondary boot program and the communication interface maintenance program, and the capacity of the first random storage area is smaller than the capacity of the second random storage area. Upon receiving a startup command, the secondary bootloader in the first random access memory area is run, and the secondary bootloader calls the communication interface maintenance program to establish a communication connection with the host. The secondary bootloader downloads the service firmware of the target functional module to the second random storage area. Run the service firmware in the second random storage area to restore the operation of the target functional module.

8. The system according to claim 7, characterized in that, The first random access memory region and the second random access memory region are logical regions partitioned within the same physical RAM of the target processing core; the second random access memory region is used to store the main business firmware and data of the target functional module; Furthermore, for any functional module, the capacity of the first random storage area corresponding to the functional module is independently configured according to the communication interface type and / or wake-up latency requirements of the functional module.

9. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by a multi-core system, the multi-core system is enabled to perform the method as described in any one of claims 1-6.

10. A computer program product, characterized in that, Includes a computer program that, when executed by a multi-core system, implements the method of any one of claims 1-6.

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