A method and apparatus for USB multiplexing with multiple CPUs

Abstract

This invention relates to the field of data processing technology, specifically to a USB multiplexing method and apparatus for multiple CPUs, comprising: an interrupt module, including a first interrupt unit connected to a master CPU and a second interrupt unit connected to a slave CPU; a USB module for outputting interrupt information based on an endpoint device; a master CPU for responding to received interrupt information from an endpoint device, determining the event type of the interrupt information; determining, based on the event type of the interrupt information, whether to communicate through the second interrupt unit; and controlling the first interrupt unit to enter an enabled state; and a slave CPU for controlling the second interrupt unit to enter an enabled state; and when the second interrupt unit receives interrupt information sent by the first interrupt unit, determining, based on the event type of the interrupt information, whether to return information to the master CPU through the first interrupt unit. This apparatus enables communication between multiple CPUs.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and more specifically to a multi-CPU USB multiplexing method and apparatus in the field of data processing technology. Background Technology

[0002] In the field of System-on-Chips (SoCs), power consumption is one of the most important parameters. To reduce SoC power consumption, typically one Universal Serial Bus (USB) supports only one Central Processing Unit (CPU). The USB is directly connected to this CPU and notifies the CPU via an internal interrupt (INT interrupt). Therefore, if multiple CPUs exist, multiple USB ports are needed to meet communication requirements, resulting in higher costs.

[0003] Based on this, a solution was designed in the relevant technology that can support multiple CPUs through a single USB port. The USB provides multiple interrupts that are connected to each CPU. Although this can meet the need to communicate with multiple CPUs via USB, this solution cannot respond normally when the USB host sends standard protocol commands such as reset. Only a complete chip reset can solve this problem. After the chip is reset, it takes a long time to resume normal operation. In addition, many business scenarios do not allow reset. In some business scenarios, after the chip is reset, it cannot be restored to the working state before the reset, which cannot meet the business requirements. Summary of the Invention

[0004] The purpose of this invention is to provide a USB multiplexing method and apparatus for multiple CPUs, and the specific technical solution adopted is as follows:

[0005] In a first aspect, embodiments of the present invention provide a USB multiplexing method for multiple CPUs, the method comprising:

[0006] The USB module is used as an endpoint device to output interrupt information;

[0007] In response to the received interrupt information, the main CPU determines the event type of the interrupt information;

[0008] Based on the event type of the interrupt information, determine whether to communicate through the second interrupt unit connected to the CPU; and control the first interrupt unit connected to the main CPU to enter the enabled state so as to communicate with the slave CPU based on the first interrupt unit; wherein, the first interrupt unit and the second interrupt unit can communicate with each other;

[0009] The CPU controls the second interrupt unit to enter an enabled state, so as to communicate with the main CPU based on the second interrupt unit;

[0010] When the second interrupt unit receives the interrupt information sent by the first interrupt unit, it determines whether to return information to the main CPU through the first interrupt unit based on the event type of the interrupt information.

[0011] In some possible implementations, the main CPU is further configured to determine, based on the event type and preset type of the interrupt information, whether it is necessary to receive the processing completion information returned from the CPU; if the event type satisfies the preset type, upon receiving the processing completion information, determine whether it is necessary to operate on other endpoint devices used by the main CPU.

[0012] In some possible implementations, the main CPU is further configured to determine, based on the event type, whether to return information to the host side of the USB if the event type does not meet the preset type.

[0013] In some possible implementations, the main CPU is also used to determine a preset interrupt with the USB module; control the preset interrupt to enter an enabled state; and receive interrupt information based on the preset interrupt being in the enabled state.

[0014] In some possible implementations, the preset interrupt is a common interrupt for the master CPU and the slave CPU, respectively connected to the master CPU and the slave CPU, and is used to notify the master CPU and the slave CPU of the interrupt information of the endpoint device.

[0015] In some possible implementations, the CPU is further configured to disable a preset interrupt from the USB module to mask the interrupt information; and to receive the interrupt information sent by the first interrupt unit based on the second interrupt unit being in an enabled state.

[0016] In some possible implementations, the slave CPU is further configured to determine, based on the event type of the interrupt information, whether it is necessary to operate on the endpoint device corresponding to the slave CPU; if it is necessary to operate on the endpoint device corresponding to the slave CPU, when the operation is detected to be completed, it is configured, based on the event type, to determine whether to notify the master CPU through the first interrupt unit.

[0017] In some possible implementations, the interrupt module is further configured to connect the first interrupt unit corresponding to the master CPU and the second interrupt unit corresponding to the slave CPU via a common path; and to synchronize information between the master CPU and the slave CPU through the first interrupt unit and the second interrupt unit.

[0018] In some possible implementations, the main CPU is also configured to determine that the interrupt information has been received when it receives a standard protocol command sent by the USB host.

[0019] Secondly, embodiments of the present invention provide a multi-CPU USB multiplexing device, the device comprising:

[0020] The interrupt module includes: a first interrupt unit connected to the main CPU and a second interrupt unit connected to the slave CPU, wherein the first interrupt unit and the second interrupt unit are capable of communication.

[0021] The USB module is used to output interrupt information based on the endpoint device;

[0022] The main CPU is configured to respond to the received interrupt information from the endpoint device, determine the event type of the interrupt information, determine whether to communicate through the second interrupt unit based on the event type of the interrupt information, and control the first interrupt unit to enter an enabled state so as to communicate with the slave CPU based on the first interrupt unit.

[0023] The slave CPU is used to control the second interrupt unit to enter the enabled state so as to communicate with the master CPU based on the second interrupt unit; when the second interrupt unit receives the interrupt information sent by the first interrupt unit, it determines whether to return information to the master CPU through the first interrupt unit based on the event type of the interrupt information.

[0024] Thirdly, a computer program product is provided, comprising: computer program code, which, when run on a computer, causes the computer to perform the method described in the first aspect.

[0025] Fourthly, a computer-readable storage medium is provided that stores computer program code, which, when executed on a computer, causes the computer to perform the method described in the first aspect.

[0026] This invention offers the following advantages: In a multi-CPU USB multiplexing device, the interrupt module is designed with a first interrupt unit matched to the master CPU and a second interrupt unit matched to the slave CPU, enabling communication between the first and second interrupt units. After the USB module outputs interrupt information based on the endpoint device, the master CPU, in response to the received interrupt information, determines the event type of the interrupt information; based on the event type, it determines whether to communicate through the second interrupt unit; and controls the first interrupt unit to enter an enabled state to communicate with the slave CPU. Thus, the master CPU receives information sent by the slave CPU through the first interrupt unit in the interrupt module and sends interrupt information to the slave CPU through the second interrupt unit connected to the slave CPU. The slave CPU controls the second interrupt unit to enter an enabled state to communicate with the master CPU; when the second interrupt unit receives the interrupt information sent by the first interrupt unit, it determines whether to return information to the master CPU through the first interrupt unit based on the event type of the interrupt information. Thus, in a multi-CPU USB multiplexing device, by designing an interrupt module, each CPU is provided with a separate interrupt unit, so that the current CPU can be notified of the status of other endpoint devices besides its corresponding endpoint device through these interrupt units. Moreover, the CPUs can interrupt each other through the interrupt units, thereby achieving the purpose of communication between multiple CPUs. Attached Figure Description

[0027] To more clearly illustrate the technical solutions and advantages in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram of the composition structure of a multi-CPU USB multiplexing device provided in related technologies;

[0029] Figure 2 This is a schematic diagram of the composition structure of a multi-CPU USB multiplexing device provided in an embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of another component structure of a multi-CPU USB multiplexing device provided in an embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram illustrating the implementation process of a multi-CPU USB multiplexing method provided in an embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0033] To further illustrate the technical means and effects adopted by the present invention to achieve its intended purpose, the following, in conjunction with the accompanying drawings and preferred embodiments, details the specific implementation, structure, features, and effects of a multi-CPU USB multiplexing method proposed according to the present invention. In the following description, different "one embodiment" or "another embodiment" do not necessarily refer to the same embodiment. Furthermore, specific features, structures, or characteristics in one or more embodiments may be combined from any suitable form.

[0034] In the description of the embodiments of the present invention, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present invention, "multiple" means two or more.

[0035] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0037] In related technologies, communication between USB and CPU is as follows: Figure 1 As shown, a single USB port typically supports only one CPU. The USB port is directly connected to this CPU and notifies the CPU via an INT interrupt. Although this approach is simple, if there are multiple CPUs, multiple USB ports are needed to meet the communication requirements, which increases the cost.

[0038] Based on this, embodiments of the present invention provide a multi-CPU USB multiplexing device. The specific solution of the multi-CPU USB multiplexing device provided by the present invention will be described in detail below with reference to the accompanying drawings. Please refer to... Figure 2 This diagram illustrates the structural composition of a multi-CPU USB multiplexing device according to an embodiment of the present invention. The device 200 includes:

[0039] Interrupt module 201 includes: a first interrupt unit connected to the main CPU and a second interrupt unit connected to the slave CPU, wherein the first interrupt unit 205 and the second interrupt unit 206 are capable of communication.

[0040] Here, the interrupt module can be implemented through multiple interrupt units that can communicate with each other, with each interrupt unit independently corresponding to a CPU. The first and second interrupt units can be internal interrupts (i.e., INT interrupts).

[0041] In some possible implementations, the interrupt module is also used to connect the first interrupt unit corresponding to the master CPU and the second interrupt unit corresponding to the slave CPU via a common path; and to synchronize information between the master CPU and the slave CPU through the first interrupt unit and the second interrupt unit. Figure 3 As shown, the interrupt module includes: CPU_INT(0), CPU_INT(1), ..., CPU_INT(n). CPU_INT(0) sends status information of other CPUs to CPU(0), and CPU_INT(n) sends status information of other CPUs to CPU(n). Each CPU has a separate CPU_INT(n) sent to its corresponding CPU(n) to notify the current CPU(n) of the status of any EP endpoints used besides EP0. Furthermore, CPUs can interrupt each other through CPU_INT(n).

[0042] USB module 202 is used to output interrupt information based on endpoint devices.

[0043] Here, the USB has 16 endpoints (EPs) from EP0 to EP15. When the USB is first connected, enumeration is performed through EP0. During enumeration, a CPU needs to process the data to be sent. Only after successful enumeration can the other EP endpoints function normally. During USB operation, actions such as suspend / disconnect are performed. These actions are notified to the CPU through EP0, and the CPU needs to perform deinitialization processing on these actions. During this time, the various EP endpoints cannot send or receive data normally.

[0044] After suspending / disconnecting, USB can be restored to use through actions such as resetting / resume or plugging / unplugging the USB interface. These actions are also notified to the CPU through EP0, and the CPU needs to initialize the channels it uses.

[0045] USB may reset at any time. This action is notified to the CPU via EP0. The CPU needs to perform deinitialization on each channel and then re-enumerate. During this process, the channels are unusable. All the processing of the above EP0 information may involve processing logic for each channel, and the order in which they are completed may be required.

[0046] In the USB module, interrupt information is generated and output via EP0.

[0047] The main CPU 203 is configured to respond to the received interrupt information from the endpoint device, determine the event type of the interrupt information, determine whether to communicate through the second interrupt unit based on the event type of the interrupt information, and control the first interrupt unit to enter an enabled state so as to communicate with the slave CPU based on the first interrupt unit.

[0048] Here, the main CPU can be Figure 3 CPU (0) in the middle, from the CPU can be Figure 3 The CPUs (1) to (n) in the interrupt module are as follows: When the main CPU receives a standard protocol command sent by the USB host, it determines that the interrupt information has been received; in this way, for standard protocol commands such as reset, it receives the interrupt information output by EP0, and through the interrupt unit corresponding to each CPU in the interrupt module, it synchronizes the information status of EP0 among the CPUs.

[0049] The main CPU is also used to determine a preset interrupt with the USB module; control the preset interrupt to enter an enabled state; and receive the interrupt information based on the preset interrupt in the enabled state.

[0050] Here, a preset interrupt is used as a common interrupt for both the master CPU and the slave CPU, connecting the master CPU and the slave CPU respectively, and is used to notify the master CPU and the slave CPU of the interrupt information of the endpoint device. For example... Figure 3 As shown, the preset interrupt can be Figure 3 The INT interrupt between USB and CPU (0) is provided to all CPUs. This common INT interrupt (i.e., the default interrupt) of USB is provided to all CPUs, and this interrupt is used to notify EP0 of its status.

[0051] The main CPU is also used to determine, based on the event type and preset type of the interrupt information, whether it is necessary to receive the processing completion information returned from the CPU; if the event type meets the preset type, when the processing completion information is received, it is determined whether it is necessary to operate on other endpoint devices used by the main CPU.

[0052] Here, if the interrupt information's event type belongs to a preset type, then it is determined that a processing completion message returned from the CPU needs to be received. For example, if the interrupt information's event type requires handshake communication, then the main CPU determines that it needs to wait for the processing completion message returned from the CPU. Only after receiving the processing completion message from the CPU will it proceed to the next processing step; that is, after receiving the processing completion message from the CPU, it will continue to determine whether it is necessary to operate on other endpoint devices used by the main CPU, such as disabling / enabling data communication and data backup of other endpoint devices.

[0053] The main CPU is also configured to determine, based on the event type, whether to return information to the host side of the USB if the event type does not meet the preset type.

[0054] Here, if the event type does not meet the preset type, that is, there is no need to wait for the processing completion information returned from the CPU, after receiving the interrupt information, the event type of the interrupt information is determined to determine whether to return information to the USB host and whether to operate on other endpoint devices used by the main CPU.

[0055] For example, if the event type of the interrupt information indicates that the processing of the interrupt information is related to other endpoint devices, then it is determined that operations need to be performed on other endpoint devices used by the main CPU; for example, disabling / enabling data communication and data backup of other endpoint devices.

[0056] In some possible implementations, such as Figure 3 As shown, the software implementation flow of the main CPU (i.e., CPU(0)) is as follows:

[0057] The first step is to enable the INT interrupt so that interrupt information from USB EP0 can be received;

[0058] The second step is to enable the CPU_INT(0) interrupt so that interrupt information from other CPUs can be received.

[0059] The third step, upon receiving an INT interrupt (i.e., interrupt information), determines whether the following two actions, the fourth and fifth steps, are necessary based on the received EP0 event type:

[0060] The fourth step is to determine whether to notify the CPU (1) via CPU_INT(1) and, based on the EP0 event type, whether to wait for the CPU (1) to return the information that the processing is complete. If it is necessary to wait, the fifth step can only be executed after the completion information is received.

[0061] The fifth step is to determine whether to operate on other EP endpoints used by CPU0. If so, operate on the other EP endpoints. This operation includes whether to disable / enable data communication and data backup of other EP endpoints.

[0062] Step 6: After processing steps 4 and 5, determine whether it is necessary to return information to the USB host based on the received EP0 event type.

[0063] CPU204 is used to control the second interrupt unit to enter the enabled state so as to communicate with the main CPU based on the second interrupt unit; when the second interrupt unit receives the interrupt information sent by the first interrupt unit, it determines whether to return information to the main CPU through the first interrupt unit based on the event type of the interrupt information.

[0064] Here, the master CPU synchronizes the interrupt information output by EP0 to the slave CPU via the second interrupt unit, thereby synchronizing the states between the master and slave CPUs. The slave CPU is used to disable preset interrupts with the USB module to mask the interrupt information; it receives the interrupt information sent by the first interrupt unit based on the second interrupt unit being in an enabled state.

[0065] like Figure 3 As shown, INT interrupts are disabled from the CPU (e.g., CPU(1) to CPU(n)) to mask interrupt information output by USB EP0. Simultaneously, interrupts from the corresponding interrupt units of the CPU are enabled, such as... Figure 3 As shown, taking CPU (1) as an example, CPU_INT (1) is enabled so that interrupt information sent by CPU (0) can be received.

[0066] In some possible implementations, the CPU is further configured to determine, based on the event type of the interrupt information, whether an operation needs to be performed on the endpoint device corresponding to the CPU; if an operation needs to be performed on the endpoint device corresponding to the CPU, when the operation is detected to be completed, it is determined, based on the event type, whether to notify the main CPU through the first interrupt unit.

[0067] Here, after receiving the interrupt information through the second interrupt unit, the CPU determines whether to perform an operation on the endpoint device corresponding to the CPU by identifying the event type of the interrupt information. This operation includes whether to disable / enable data communication and data backup for other EP endpoints. After completing the operation, based on the event type, it determines whether to notify the main CPU of the operation completion message through the first interrupt unit.

[0068] In some possible implementations, with Figure 3The CPU (1) in this example is used to illustrate the process. The software processing flow of CPU (1) is as follows:

[0069] The first step is to disable the INT (i.e., default interrupt) interrupt so that interrupt information from USB EP0 (i.e., endpoint device) can be masked.

[0070] The second step is to enable CPU_INT(1) (i.e., the second interrupt unit) so that interrupt information from CPU(0) (i.e., the main CPU) can be received.

[0071] The third step is to determine whether to operate on the EP endpoint it uses based on the event type of the interrupt information sent by the CPU (0) upon receiving the CPU_INT(1) interrupt. This operation includes whether to disable / enable data communication and data backup of other EP endpoints.

[0072] The fourth step is to determine whether it is necessary to notify the CPU (0) via CPU_INT(0) after processing the third step, based on the type of event received.

[0073] This invention provides a method for USB multiplexing across multiple CPUs, such as... Figure 4 As shown, it can be done through Figure 4 The steps shown are to be implemented as follows:

[0074] 401 uses a USB module based on the endpoint device to output interrupt information;

[0075] 402. In response to the received interrupt information, the main CPU determines the event type of the interrupt information;

[0076] 403. Based on the event type of the interrupt information, determine whether to communicate through the second interrupt unit connected to the CPU; and control the first interrupt unit connected to the main CPU to enter the enabled state so as to communicate with the slave CPU based on the first interrupt unit;

[0077] The first interrupt unit and the second interrupt unit are able to communicate with each other.

[0078] 404, the CPU controls the second interrupt unit to enter the enabled state, so as to communicate with the main CPU based on the second interrupt unit;

[0079] 405. When the second interrupt unit receives the interrupt information sent by the first interrupt unit, it determines whether to return information to the main CPU through the first interrupt unit based on the event type of the interrupt information.

[0080] Through steps 401 to 405 above, after the USB module outputs interrupt information based on the endpoint device, the master CPU responds to the received interrupt information and determines the event type of the interrupt information; based on the event type of the interrupt information, it determines whether to communicate through the second interrupt unit; the master CPU receives information sent by the slave CPU through the first interrupt unit in the interrupt module, and sends interrupt information to the slave CPU through the second interrupt unit connected to the slave CPU. The slave CPU controls the second interrupt unit to enter the enabled state to communicate with the master CPU based on the second interrupt unit; when the second interrupt unit receives the interrupt information sent by the first interrupt unit, it determines whether to return information to the master CPU through the first interrupt unit based on the event type of the interrupt information. Thus, in a multi-CPU USB multiplexing device, by designing an interrupt module, a separate interrupt unit is provided for each of the other CPUs, so that the status of other endpoint devices besides the corresponding endpoint device can be notified to the current CPU through these interrupt units. Moreover, the CPUs can interrupt each other through the interrupt units to achieve the purpose of communication between multiple CPUs. Even in a reset scenario, data communication between the master CPU and the slave CPU can still be achieved relatively simply and accurately, thereby meeting business requirements.

[0081] Optionally, the transmission medium can be a wired link (e.g., but not limited to, coaxial cable, optical fiber, and Digital Subscriber Line (DSL)) or a wireless link (e.g., but not limited to, Wireless Fidelity (WIFI), Bluetooth, and mobile device networks). It should be noted that the system provided in the above embodiments is only an example illustrating the division of the functional modules described above. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the computer device can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the method embodiments provided in the above embodiments belong to the same concept, and their specific implementation processes are detailed in the method embodiments, and will not be repeated here.

[0082] Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. For example, as shown... Figure 5 As shown, the computer device 500 includes: a memory 501, a processor 502, and a computer program 503 stored in the memory 501 and running on the processor 502, wherein when the processor 502 executes the computer program 503, the computer device can execute any of the aforementioned multi-CPU USB multiplexing methods.

[0083] Furthermore, this embodiment of the invention also protects a system that may include a memory and a processor. The memory stores executable program code, and the processor is used to call and execute the executable program code to perform a multi-CPU USB multiplexing method provided by this embodiment of the invention. This embodiment can divide the system into functional modules based on the above method example. For example, each module can correspond to a specific function, or two or more functions can be integrated into one processing module. The integrated module can be implemented in hardware. It should be noted that the module division in this embodiment is illustrative and only represents a logical functional division; other division methods may exist in actual implementation. It should also be noted that all relevant content of each step involved in the above method embodiment can be referenced to the functional description of the corresponding functional module, and will not be repeated here.

[0084] It should be understood that the system provided in this embodiment is used to execute the aforementioned multi-CPU USB multiplexing method, and therefore can achieve the same effect as the aforementioned implementation method. When using integrated units, the system may include a processing module and a storage module. When the system is applied to a device, the processing module can be used to control and manage the device's operations. The storage module can be used to support the device in executing mutual program code, etc. The processing module may be a processor or a controller, which can implement or execute various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this invention. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of Digital Signal Processing (DSP) and a microprocessor, etc., and the storage module may be a memory.

[0085] Furthermore, the system provided in the embodiments of the present invention may specifically be a chip, component, or module. The chip may include a connected processor and a memory; wherein, the memory is used to store instructions, and when the processor calls and executes the instructions, the chip can execute the multi-CPU USB multiplexing method provided in the above embodiments. This embodiment also provides a computer-readable storage medium storing computer program code. When the computer program code is run on a computer, it causes the computer to execute the above-described related method steps to implement the multi-CPU USB multiplexing method provided in the above embodiments.

[0086] This embodiment also provides a computer program product. When the computer program product is run on a computer, it causes the computer to perform the aforementioned related steps to implement the multi-CPU USB multiplexing method provided in the above embodiment. The system, computer-readable storage medium, computer program product, or chip provided in this embodiment are all used to execute the corresponding methods provided above. Therefore, the beneficial effects they achieve can be referred to in the beneficial effects of the corresponding methods provided above, and will not be repeated here. Through the description of the above embodiments, those skilled in the art can understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the system can be divided into different functional modules to complete all or part of the functions described above. In the embodiments provided by this invention, it should be understood that the disclosed system and method can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the division of modules or units is only a logical functional division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, system or unit, and can be electrical, mechanical or other forms.

[0087] It should be noted that the order of the above embodiments of the present invention is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. The processes depicted in the accompanying drawings do not necessarily require a specific or sequential order to achieve the desired results. In some embodiments, multiple task processing and parallel processing are possible or may be advantageous. The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. The above content is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be covered within the protection scope of the present invention.

Claims

1. A multi-CPU USB multiplexing device, characterized in that, The multi-CPU USB multiplexing device includes: The interrupt module includes: a first interrupt unit connected to the main CPU and a second interrupt unit connected to the slave CPU, wherein the first interrupt unit and the second interrupt unit are capable of communication. The USB module is used to output interrupt information based on the endpoint device; The main CPU is configured to respond to received interrupt information from the endpoint device, determine the event type of the interrupt information; determine whether to communicate through the second interrupt unit based on the event type of the interrupt information; and control the first interrupt unit to enter an enabled state to communicate with the slave CPU based on the first interrupt unit; it is also configured to determine whether to receive processing completion information returned by the slave CPU based on the event type of the interrupt information and a preset type; if the event type meets the preset type, determine whether to operate on other endpoint devices used by the main CPU when the processing completion information is received; and if the event type does not meet the preset type, determine whether to return information to the USB host based on the event type. The slave CPU is used to control the second interrupt unit to enter the enabled state so as to communicate with the master CPU based on the second interrupt unit; when the second interrupt unit receives the interrupt information sent by the first interrupt unit, it determines whether to return information to the master CPU through the first interrupt unit based on the event type of the interrupt information.

2. The multi-CPU USB multiplexing device according to claim 1, characterized in that, The main CPU is also used to determine a preset interrupt with the USB module; control the preset interrupt to enter an enabled state; and receive interrupt information based on the preset interrupt in the enabled state.

3. The multi-CPU USB multiplexing device according to claim 2, characterized in that, The preset interrupt serves as a common interrupt for both the master CPU and the slave CPU, connecting to both the master CPU and the slave CPU respectively, and is used to notify the master CPU and the slave CPU of the interrupt information of the endpoint device.

4. The multi-CPU USB multiplexing device according to claim 1, characterized in that, The CPU is also configured to disable a preset interrupt from the USB module to mask the interrupt information; and to receive the interrupt information sent by the first interrupt unit based on the second interrupt unit being in an enabled state.

5. A multi-CPU USB multiplexing device according to claim 4, characterized in that, The slave CPU is further configured to determine, based on the event type of the interrupt information, whether it is necessary to operate on the endpoint device corresponding to the slave CPU; if it is necessary to operate on the endpoint device corresponding to the slave CPU, when the operation is detected to be completed, it is configured to determine, based on the event type, whether to notify the master CPU through the first interrupt unit.

6. A multi-CPU USB multiplexing device according to claim 1, characterized in that, The interrupt module is also used to connect the first interrupt unit corresponding to the master CPU and the second interrupt unit corresponding to the slave CPU based on a common path; and to synchronize information between the master CPU and the slave CPU through the first interrupt unit and the second interrupt unit.

7. A multi-CPU USB multiplexing device according to claim 1, characterized in that, The main CPU is also used to determine that the interrupt information has been received when it receives a standard protocol command sent by the USB host.

8. A USB multiplexing method for multiple CPUs, characterized in that, A USB multiplexing device for multiple CPUs according to any one of claims 1 to 7, wherein the USB multiplexing method for multiple CPUs comprises: The USB module is used as an endpoint device to output interrupt information; In response to the received interrupt information, the main CPU determines the event type of the interrupt information; Based on the event type of the interrupt information, determine whether to communicate through the second interrupt unit connected to the CPU; and control the first interrupt unit connected to the main CPU to enter the enabled state so as to communicate with the slave CPU based on the first interrupt unit; wherein, the first interrupt unit and the second interrupt unit can communicate with each other; The CPU controls the second interrupt unit to enter an enabled state, so as to communicate with the main CPU based on the second interrupt unit; When the second interrupt unit receives the interrupt information sent by the first interrupt unit, it determines whether to return information to the main CPU through the first interrupt unit based on the event type of the interrupt information.

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