Data transfer method and apparatus based on an accelerator card

Abstract

The application relates to the technical field of computer hardware acceleration and data processing, and discloses a data transmission method and device based on an acceleration card, which comprises the following steps: collecting original data streams of external equipment, performing real-time feature analysis on the original data streams through a mode recognition engine to obtain space-time correlation features, and performing binary coding on the space-time correlation features to obtain feature mark data; according to the instantaneous bandwidth of an M.2 interface and the load state of an AI chip, utilizing a dynamic compression engine to compress the feature mark data into optimized compressed data; inputting the optimized compressed data into a heterogeneous computing distributor to distribute path selection instructions for the optimized compressed data according to the feature mark types of the optimized compressed data through the heterogeneous computing distributor; and according to the path selection instructions, completing data transmission of the optimized compressed data through the heterogeneous computing distributor to obtain data transmission results. The application can make the final data transmission results meet the space-time consistency requirements of high-precision AI reasoning.

Description

Technical Field

[0001] This invention relates to a data transmission method and apparatus based on an accelerator card, belonging to the field of computer hardware acceleration and data processing technology. Background Technology

[0002] Accelerator card-based data transmission methods are a core technology for improving the performance of heterogeneous computing systems. As a hardware hub connecting external devices and AI chips, the M.2 accelerator card provides high-throughput data transmission capabilities through channels. In scenarios such as AI inference and real-time video analysis, the massive amounts of raw data generated by external devices (such as sensors and cameras) need to be pre-processed by the accelerator card before being efficiently transmitted to the AI ​​chip. However, traditional transmission solutions face three challenges: dynamic bandwidth fluctuations leading to data accumulation, unbalanced AI chip computing load causing processing delays, and performance loss caused by mismatch between data characteristics and computing resources. Therefore, there is an urgent need for an adaptive transmission method that can dynamically coordinate interface bandwidth, chip load, and data characteristics to achieve low-latency, high-precision end-to-end data processing.

[0003] Existing solutions use a fixed compression algorithm, which cannot respond to instantaneous bandwidth fluctuations of the M.2 interface. When the bandwidth drops sharply, the fixed compression ratio causes data packet transmission delays, directly causing misalignment of the time window for spatiotemporal feature analysis and reducing feature extraction accuracy. Due to the lack of a real-time feature analysis engine, invalid information in the original data stream is transmitted indiscriminately. This not only occupies limited bandwidth but also causes the AI ​​chip to fall into ineffective computation, weakening the accuracy of effective feature recognition. If the heterogeneous computing allocator does not dynamically sense the AI ​​chip load, high-priority tasks may be assigned to overloaded computing units. This defect, combined with the previous two, causes feature data to miss processing time, spatiotemporal correlation to break, and the final output results to deviate from the real scene.

[0004] In summary, the core contradiction of existing technologies lies in the lack of a coordinated scheduling mechanism for the three resources of bandwidth, data, and computing. Static compression, featureless filtering, and rigid path allocation form a cascading failure chain, which can all be attributed to insufficient system-level accuracy, inaccurate bandwidth adaptation reducing feature timeliness, redundant data transmission diluting feature density, and improper load allocation distorting feature calculation logic. The combined effect of these three factors makes it difficult for the final data transmission results to meet the spatiotemporal consistency requirements of high-precision AI inference. Summary of the Invention

[0005] This invention provides a data transmission method and apparatus based on an accelerator card, the main purpose of which is to ensure that the final data transmission result meets the spatiotemporal consistency requirements of high-precision AI inference.

[0006] To achieve the above objectives, the present invention provides a data transmission method based on an accelerator card, comprising:

[0007] A data transmission system is constructed, wherein the data transmission system includes external devices, an M.2 accelerator card, an M.2 interface, and an AI chip, and the M.2 accelerator card includes a pattern recognition engine, a dynamic compression engine, and a heterogeneous computing allocator;

[0008] The raw data stream from the external device is collected, and the pattern recognition engine performs real-time feature analysis on the raw data stream to obtain spatiotemporal related features. The spatiotemporal related features are then binary encoded into feature tag data.

[0009] Based on the instantaneous bandwidth of the M.2 interface and the load status of the AI ​​chip, the feature tag data is compressed into optimized compressed data using the dynamic compression engine;

[0010] The optimized compressed data is input into the heterogeneous computing allocator so that, according to the feature tag type of the optimized compressed data, the heterogeneous computing allocator can allocate path selection instructions to the optimized compressed data.

[0011] According to the path selection instruction, the optimized compressed data is transmitted through the heterogeneous computing allocator to obtain the data transmission result.

[0012] Optionally, the construction of the data transmission system includes:

[0013] Prepare external devices and the M.2 accelerator card;

[0014] A pattern recognition engine is deployed in the front-end area of ​​the M.2 accelerator card;

[0015] A dynamic compression engine is deployed in the central region of the M.2 accelerator card;

[0016] A heterogeneous computing allocator is deployed in the back-end control area of ​​the M.2 accelerator card;

[0017] An AI chip is integrated on the M.2 accelerator card;

[0018] Construct an M.2 interface connecting the external device and the M.2 accelerator card;

[0019] The data transmission system is determined by the external device, the M.2 accelerator card, the M.2 interface, the AI ​​chip, the pattern recognition engine, the dynamic compression engine, and the heterogeneous computing distributor.

[0020] Optionally, the acquisition of the raw data stream from the external device includes:

[0021] The raw data stream from the external device is transmitted to the M.2 accelerator card via the M.2 interface;

[0022] The raw data stream is received in the M.2 accelerator card through the M.2 interface to complete the process of acquiring the raw data stream from the external device.

[0023] Optionally, the step of performing real-time feature analysis on the original data stream using the pattern recognition engine to obtain spatiotemporal related features includes:

[0024] The pattern recognition engine employs bidirectional LSTM to capture the inter-frame motion features of the raw data stream;

[0025] The pattern recognition engine employs convolutional kernels to extract the spatial distribution pattern of the original data stream.

[0026] In the pattern recognition engine, the inter-frame motion features and the spatial distribution pattern are weighted and fused through an attention mechanism to obtain spatiotemporal related features.

[0027] Optionally, the step of binary encoding the spatiotemporal related features into feature-labeled data includes:

[0028] Extract timestamps, feature types, and spatial indexes from the spatiotemporal related features;

[0029] Encode the timestamp into a 64-bit timer value;

[0030] Encode the feature type into a type identifier;

[0031] Encode the spatial index into a coordinate hash value;

[0032] By concatenating the 64-bit timer value, the type identifier, and the coordinate hash value, a binary code is obtained;

[0033] The checksum of the binary code is generated using the CRC-8 checksum algorithm;

[0034] By concatenating the binary code with the check code, feature marker data is obtained.

[0035] Optionally, the step of compressing the feature tag data into optimized compressed data using the dynamic compression engine based on the instantaneous bandwidth of the M.2 interface and the load state of the AI ​​chip includes:

[0036] When the instantaneous bandwidth is less than the preset bandwidth, the dynamic compression engine calls the tensor folding compression algorithm on the M.2 accelerator card's onboard accelerator card.

[0037] While retaining the key motion vectors of the coordinate hash values ​​in the feature marker data, the tensor folding compression algorithm is executed through the adjustable pipeline silicon wafer on the accelerator card to reduce the dimensionality of the coordinate hash values ​​in the feature marker data, thereby obtaining the dimensionality-reduced hash values.

[0038] Based on the dimensionality reduction hash value, the process of compressing the feature-labeled data into optimized compressed data is completed;

[0039] When the load condition is greater than the preset load, the dynamic compression engine calls the sparse matrix compression algorithm on the accelerator card.

[0040] The hardware counter of the entropy coding coprocessor on the accelerator card is used to count the feature type frequency of non-zero value elements in the feature tag data;

[0041] A priority queue of non-zero value elements is generated using the frequency of the aforementioned feature type.

[0042] Based on the priority queue and the Huffman tree generation rules pre-stored in the silicon ROM on the accelerator card, the fixed-length optimized encoding table of the non-zero value elements is generated using the Huffman coding in the sparse matrix compression algorithm.

[0043] Detect zero-value elements in the feature-labeled data;

[0044] The sparse coding matrix of the zero-value elements is generated using run-length encoding in the sparse matrix compression algorithm.

[0045] The entropy coding coprocessor converts the fixed-length optimized coding table and the sparse coding matrix into optimized compressed data.

[0046] Optionally, the step of converting the fixed-length optimized coding table and the sparse coding matrix into optimized compressed data through the entropy coding coprocessor includes:

[0047] Extract the non-zero and zero-value elements from the feature-labeled data;

[0048] After the entropy coding coprocessor receives the fixed-length optimized coding table and the sparse coding matrix, it uses the fixed-length optimized coding table to encode and map the non-zero value elements to obtain non-zero value codes.

[0049] The zero-value elements are encoded and mapped using the sparse coding matrix to obtain the zero-value code;

[0050] The non-zero value code and the zero value code are encapsulated using the entropy coding coprocessor to obtain optimized compressed data.

[0051] Optionally, the step of allocating a transmission path for the optimized compressed data through the heterogeneous computing allocator according to the feature tag type of the optimized compressed data includes:

[0052] The feature tag type, the instantaneous bandwidth of the M.2 interface, and the load status of the AI ​​chip are input into the decision tree model of the heterogeneous computing allocator, so that the path selection instruction for the optimized compressed data is output through the decision tree model;

[0053] The path selection instruction includes the target device identifier, transmission path identifier, data packet identifier, and task priority.

[0054] Optionally, the step of completing the data transmission of the optimized compressed data through the heterogeneous computing allocator according to the path selection instruction, and obtaining the data transmission result, includes:

[0055] The path selection instruction is parsed by the control logic unit in the heterogeneous computing allocator to obtain parsed instruction information.

[0056] The control logic unit is used to activate the bus transmission logic corresponding to the parsed instruction information.

[0057] According to the bus transmission logic, the optimized compressed data is converted to a new format to obtain converted data.

[0058] Based on the target device, data packet identifier, and task priority in the parsing instruction information, the format-converted data is transmitted through the bus transmission logic to obtain the data transmission result.

[0059] To address the aforementioned problems, the present invention also provides a data transmission device based on an accelerator card, the device comprising:

[0060] The system construction module is used to build a data transmission system, wherein the data transmission system includes external devices, an M.2 accelerator card, an M.2 interface, and an AI chip, and the M.2 accelerator card includes a pattern recognition engine, a dynamic compression engine, and a heterogeneous computing allocator;

[0061] The feature encoding module is used to collect the raw data stream of the external device, perform real-time feature analysis on the raw data stream through the pattern recognition engine to obtain spatiotemporal related features, and encode the spatiotemporal related features into feature tag data in binary.

[0062] The data compression module is used to compress the feature tag data into optimized compressed data using the dynamic compression engine based on the instantaneous bandwidth of the M.2 interface and the load status of the AI ​​chip;

[0063] The path selection module is used to input the optimized compressed data into the heterogeneous computing allocator, so as to allocate path selection instructions to the optimized compressed data through the heterogeneous computing allocator according to the feature tag type of the optimized compressed data;

[0064] The data transmission module is used to complete the data transmission of the optimized compressed data through the heterogeneous computing allocator according to the path selection instruction, and obtain the data transmission result.

[0065] Compared to the problems described in the background art, the embodiments of the present invention efficiently acquire raw data streams from external devices through the M.2 interface, providing a foundation for subsequent processing and serving as the starting point of the entire data transmission system. This ensures timely data acquisition and avoids processing delays caused by untimely data acquisition. Furthermore, the embodiments of the present invention address the problem of "lack of a real-time feature analysis engine" in the background art through feature analysis. This allows for the real-time extraction of effective features from the raw data stream, filtering out invalid information, reducing the amount of data transmitted and processed subsequently, improving data usefulness and processing efficiency, preventing AI chips from getting bogged down in invalid calculations, and enhancing the accuracy of effective feature recognition. Furthermore, the embodiments of the present invention generate structured feature-labeled data by binary encoding spatiotemporally related features, facilitating subsequent transmission and processing, improving data manageability and identifiability, and providing a convenient data format for subsequent compression and transmission operations. The embodiments of the present invention overcome the limitations of "traditional transmission methods" in the background art by utilizing the dynamic compression engine to compress the feature-labeled data into optimized compressed data. This invention overcomes the shortcomings of using a fixed compression algorithm by adaptively selecting the compression algorithm based on the instantaneous bandwidth of the M.2 interface and the load status of the AI ​​chip. This improves bandwidth utilization, avoids data accumulation and transmission delays caused by bandwidth fluctuations, and ensures the efficiency and adaptability of data transmission, guaranteeing the accuracy of spatiotemporal feature analysis. This embodiment of the invention addresses the problem of "heterogeneous computing allocator not dynamically sensing the AI ​​chip load" in the background technology. By dynamically allocating path selection instructions based on feature tag types through the heterogeneous computing allocator, it achieves reasonable allocation of computing resources, preventing high-priority tasks from being assigned to overloaded computing units, improving the overall system efficiency and the timeliness of data processing. This embodiment of the invention completes data transmission by executing path selection instructions, achieving efficient and accurate data transmission, improving the reliability and accuracy of data transmission, ensuring that data arrives at the target device in a timely and accurate manner, meeting the spatiotemporal consistency requirements of high-precision AI inference, improving the performance and effectiveness of the entire data transmission system, and avoiding problems such as missed processing time for feature data and the breakage of spatiotemporal correlation. Therefore, the data transmission method and device based on the accelerator card provided by this embodiment of the invention can ensure that the final data transmission result meets the spatiotemporal consistency requirements of high-precision AI inference. Attached Figure Description

[0066] Figure 1 This is a flowchart illustrating a data transmission method based on an accelerator card according to an embodiment of the present invention.

[0067] Figure 2 This is a schematic diagram illustrating the sparse coding matrix of the data transmission device based on the accelerator card, provided in an embodiment of the present invention.

[0068] Figure 3 This is a schematic diagram illustrating the process of optimizing and compressing data in a data transmission device based on an accelerator card, according to an embodiment of the present invention.

[0069] Figure 4 This is a schematic diagram of a module for implementing the data transmission device based on an accelerator card, according to an embodiment of the present invention.

[0070] The objectives, features, and advantages of this invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0071] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0072] This application provides a data transmission method based on an accelerator card. The execution entity of the data transmission method based on the accelerator card includes, but is not limited to, at least one of the following electronic devices that can be configured to execute the method provided in this application: a server, a terminal, etc. In other words, the data transmission method based on the accelerator card can be executed by software or hardware installed on a terminal device or a server device. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0073] Example 1:

[0074] Reference Figure 1 The diagram shown is a flowchart illustrating a data transmission method based on an accelerator card according to an embodiment of the present invention. In this embodiment, the data transmission method based on an accelerator card includes:

[0075] S1. Construct a data transmission system, wherein the data transmission system includes external devices, an M.2 accelerator card, an M.2 interface, and an AI chip, and the M.2 accelerator card includes a pattern recognition engine, a dynamic compression engine, and a heterogeneous computing allocator.

[0076] In one embodiment of the present invention, constructing a data transmission system includes: preparing an external device and an M.2 accelerator card; deploying a pattern recognition engine in the front-end region of the M.2 accelerator card; deploying a dynamic compression engine in the middle region of the M.2 accelerator card; deploying a heterogeneous computing distributor in the back-end control region of the M.2 accelerator card; integrating an AI chip on the M.2 accelerator card; constructing an M.2 interface connecting the external device and the M.2 accelerator card; and determining the data transmission system through the external device, the M.2 accelerator card, the M.2 interface, the AI ​​chip, the pattern recognition engine, the dynamic compression engine, and the heterogeneous computing distributor.

[0077] The external device refers to a data generation device connected to the M.2 accelerator card via an M.2 interface, used to acquire raw data streams. Typical devices include high frame rate cameras in the industrial field, CT / MRI image acquisition devices in the medical field, and LiDAR point cloud generators in the field of autonomous driving. High frame rate cameras, such as 4K@120fps visual sensors, are connected to the accelerator card via an M.2 interface to acquire image data in industrial production. CT / MRI image acquisition devices transmit medical image data to the accelerator card via an M.2 interface, and LiDAR point cloud generators send point cloud data to the accelerator card via an M.2 interface.

[0078] Furthermore, the pattern recognition engine is deployed in the programmable logic unit of the M.2 accelerator card's front-end area, and its functionality is implemented based on the CLB (Configurable Logic Block) array of an FPGA (Field-Programmable Logic Array). The FPGA provides high flexibility and programmability, allowing users to customize hardware logic according to specific application requirements. In addition, the pattern recognition engine contains 3×3 The system employs 7×7 adjustable convolutional kernels, which are matrices used for feature extraction. The size of these kernels can be adjusted according to specific application requirements to capture different features in the data. The pattern recognition engine is directly connected to the M.2 interface PHY layer via a 40Gbps on-chip network (NoC), ensuring high-speed and low-latency data transmission. The PHY layer is responsible for the transmission and reception of physical signals. The pattern recognition engine receives the raw data stream from external devices and performs real-time feature analysis. It is responsible for real-time feature analysis of the raw data stream, extracting spatiotemporal correlation features, and generating feature-labeled data. Specific functions include using bidirectional LSTM to capture inter-frame motion features, using convolutional kernels to extract spatial distribution patterns, and weighted fusion of these features through an attention mechanism. The bidirectional LSTM capture of inter-frame motion features is implemented based on RNN units deployed in the pattern recognition engine, specifically through a programmable logic array in the FPGA. By leveraging its flexible hardware resources to construct RNN units for processing sequential data, the parallel computing capabilities and customizability of FPGAs enable RNN units to efficiently capture inter-frame motion features. The extraction of spatial distribution patterns using convolutional kernels is based on convolutional kernels deployed in the pattern recognition engine. The convolutional kernel is a hardware module inside the FPGA, composed of configurable logic blocks (CLBs). By programming and configuring the size (e.g., 3×3 to 7×7) and parameters of the convolutional kernel, spatial distribution patterns in the data can be flexibly extracted. The weighted fusion of these features through an attention mechanism is based on the attention weight calculation unit deployed in the pattern recognition engine. This unit is also constructed from the FPGA's CLB array and is specifically used to perform weight calculations in the attention mechanism. It receives output features from bidirectional LSTM units and convolutional kernels, calculates the weight of each feature, and then performs weighted fusion to generate more discriminative spatiotemporal correlated features.

[0079] Furthermore, the dynamic compression engine refers to the compression processing module deployed in the central area of ​​the M.2 accelerator card. It adopts a dual-pipeline architecture: the lossless compression channel is a static pipeline based on entropy coding, while the lossy compression channel is a dynamically adjustable pipeline. The lossless compression channel is a 5-stage fixed pipeline implemented by an onboard entropy coding ASIC. The static pipeline of entropy coding mainly consists of a dedicated entropy coding coprocessor, which includes a control unit, an encoding lookup table, and a data cache. The control unit manages the encoding process, the encoding lookup table stores predefined encoding rules, and the data cache temporarily stores data to be encoded. The lossy compression channel is an adjustable pipeline built on the FPGA dynamic logic region. It is directly connected to a bandwidth monitoring circuit via a PHY layer probe. The bandwidth monitoring circuit is an analog-digital mixed-signal circuit integrated into the M.2 interface PHY layer, which monitors the bandwidth usage and physical layer bit error rate of the M.2 interface in real time, providing accurate bandwidth measurement data with a measurement error of less than 3%. The system's dynamic bandwidth awareness and adaptive compression functions provide crucial real-time feedback. The dynamic compression engine can adaptively select compression algorithm combinations, such as tensor folding compression and sparse matrix compression, based on the instantaneous bandwidth measurement of the M.2 interface and the load status of the AI ​​chip. This compresses the feature-labeled data into optimized compressed data. The adjustable pipeline controller dynamically adjusts the pipeline stages and configuration based on the instantaneous bandwidth measurement of the M.2 interface to optimize compression performance. In addition, the dynamic compression engine also includes a tensor folding accelerator and a sparse matrix encoder. The tensor folding accelerator is responsible for performing tensor dimension folding operations and is implemented by dedicated hardware circuitry. It can reduce the dimensionality of high-dimensional data while retaining key feature information. The sparse matrix encoder is used to implement the sparse matrix compression algorithm and includes a hardware-implemented Huffman encoder and a run-length encoder. The Huffman encoder constructs a Huffman tree based on the feature type distribution and generates an encoding table. The run-length encoder efficiently encodes zero-value elements.

[0080] Furthermore, the heterogeneous computing allocator is located in the back-end control area of ​​the M.2 accelerator card. Its firmware carrier is a RISC-V MCU integrated in the accelerator card's main control chip. It is bidirectionally connected via an AXI-Stream bus, with the upstream connection to the dynamic compression engine output and the downstream connection to the AI ​​chip's MAC array and the host PCIe interface. It incorporates a lightweight decision tree model and control logic unit, and also includes a task scheduling unit and a task distribution bus interface. Based on information such as feature label type, it allocates transmission paths for optimized compressed data. The decision tree model is deployed on the RISC-V MCU. On the MCU, leveraging the MCU's processing power and storage resources, a lightweight decision tree algorithm is run on the MCU. The model can quickly make resource scheduling decisions based on the input feature vector (such as feature label type, NPU load, PCIe bandwidth, etc.). The control logic unit is implemented by a dedicated control circuit, including an instruction parser and a command generator. The instruction parser is responsible for parsing the path selection instructions output by the decision tree model and extracting key information such as target device identifier and transmission path identifier. The command generator generates specific control commands based on the parsed instructions. The task scheduling unit is implemented based on a priority queue and a timing controller. The priority queue is used to manage tasks of different priorities, and the timing controller ensures that high-priority tasks can be processed in a timely manner. The task distribution bus interface consists of an AXI-Stream protocol multiplexer and a data format converter. The multiplexer is responsible for switching between different transmission paths, and the data format converter ensures that data can be converted between different bus protocols.

[0081] Furthermore, the M.2 interface refers to an enhanced interface module based on the M.2 physical specification. It not only includes a standard M.2 physical interface for connecting external devices and the M.2 accelerator card, but also integrates dedicated interface circuits, such as bandwidth monitoring circuits and status feedback channels. The M.2 interface provides physical connectivity and supports high-speed protocols such as PCIe 4.0×4, ensuring high-speed data transmission between external devices (such as high frame rate cameras, CT / MRI devices, LiDAR, etc.) and the M.2 accelerator card. The interface module includes a PHY layer circuit responsible for signal conversion and transmission, ensuring efficient data flow between external devices and the accelerator card. The interface module integrates a bandwidth monitoring circuit, which can measure the transmission rate and bit error rate in real time, and constructs a status feedback channel through reserved pins to achieve real-time feedback of data transmission status.

[0082] Furthermore, the AI ​​chip is integrated on an M.2 accelerator card and includes four independently startable and stopable MAC arrays, each containing 2048 INT8 computing units. Its local cache is 4MB SRAM, divided into feature cache and weight cache. The cache allocation strategy is dynamically adjusted by the decision tree of the heterogeneous computing allocator. The MAC array is directly connected to the HBM2 cache of the accelerator card through a through-silicon via (TSV) to ensure high-speed data transmission and processing. The feature cache and weight cache are allocated in 4MB SRAM, and the cache allocation strategy is dynamically adjusted by the decision tree of the heterogeneous computing allocator according to computing needs to improve cache utilization and data access efficiency.

[0083] Furthermore, the M.2 accelerator card refers to a dedicated hardware accelerator card that conforms to the M.2 2280 specification and connects to external devices via a PCIe 4.0 x4 interface. It integrates components such as a pattern recognition engine, a dynamic compression engine, a heterogeneous computing allocator, and an AI chip to achieve data preprocessing, compression, and transmission.

[0084] S2. Collect the raw data stream from the external device, perform real-time feature analysis on the raw data stream through the pattern recognition engine to obtain spatiotemporal related features, and encode the spatiotemporal related features into feature tag data using binary encoding.

[0085] This invention embodiment efficiently acquires raw data streams from external devices via the M.2 interface, providing a foundation for subsequent processing. It serves as the starting point for the entire data transmission system, ensuring timely data acquisition and avoiding processing delays caused by untimely data acquisition.

[0086] In one embodiment of the present invention, the process of acquiring the raw data stream of the external device includes: transmitting the raw data stream of the external device to an M.2 accelerator card via an M.2 interface; and receiving the raw data stream in the M.2 accelerator card via the M.2 interface to complete the process of acquiring the raw data stream of the external device.

[0087] It should be noted that the acquisition of raw data streams from external devices mainly relies on the M.2 interface in the M.2 accelerator card. External devices are connected to the accelerator card through the M.2 interface, and the accelerator card uses the M.2 interface to receive the raw data streams.

[0088] Furthermore, this embodiment of the invention solves the problem of "lack of real-time feature analysis engine" in the background technology through feature analysis. It can extract effective features from the original data stream in real time, filter out invalid information, reduce the amount of data transmitted and processed in the future, improve the usefulness of the data and processing efficiency, avoid AI chips from getting stuck in invalid calculations, and improve the recognition accuracy of effective features.

[0089] In one embodiment of the present invention, the step of performing real-time feature analysis on the original data stream through the pattern recognition engine to obtain spatiotemporal related features includes: using bidirectional LSTM to capture inter-frame motion features of the original data stream in the pattern recognition engine; using convolutional kernels to extract the spatial distribution pattern of the original data stream in the pattern recognition engine; and using an attention mechanism to weightedly fuse the inter-frame motion features and the spatial distribution pattern in the pattern recognition engine to obtain spatiotemporal related features.

[0090] The bidirectional LSTM (Long Short-Term Memory) is a special type of recurrent neural network (RNN) structure that can simultaneously utilize forward and backward information of sequence data for feature learning. It effectively captures long-term dependencies in the sequence by introducing gating mechanisms (input gate, forget gate, and output gate). A bidirectional LSTM consists of two LSTM layers: a forward layer that processes data sequentially and a backward layer that processes data in reverse order. The outputs of the two layers are then fused, allowing for the simultaneous use of contextual information. In video analysis, for a video segment containing multiple consecutive frames, a bidirectional LSTM can simultaneously consider the influence of previous frames on the current frame and the potential correlation between subsequent frames. For example, in a surveillance video analyzing the trajectory of a target object, a bidirectional LSTM can integrate the object's starting position, direction of motion, and velocity in previous frames, as well as the object's potential correlation in subsequent frames. The movement trend is analyzed to more accurately predict the position and state of an object in the current frame. Furthermore, the spatial distribution pattern refers to the arrangement and combination rules of pixel values ​​or features in space within a single image or video frame. It describes the spatial information such as the shape, structure, and texture of objects in the image, reflecting the layout and interrelationships of objects in space. For example, in an image of a product in industrial production, the spatial distribution pattern may be represented by the outline shape of the product, surface texture, and the relative positions of various components. Furthermore, the attention mechanism is a neural network mechanism that simulates human visual attention. It allows the model to automatically focus on the part most relevant to the current task when processing input data, while ignoring relatively unimportant parts. The attention mechanism calculates the importance weights of the input features and performs weighted fusion of features, thereby enabling the model to utilize key information more effectively.

[0091] Furthermore, this embodiment of the invention generates structured feature-labeled data by binary encoding spatiotemporal related features, which facilitates subsequent transmission and processing, improves data manageability and identifiability, and provides a convenient data format for subsequent compression and transmission operations.

[0092] In one embodiment of the present invention, the step of binary encoding the spatiotemporal related features into feature marker data includes: extracting a timestamp, feature type, and spatial index from the spatiotemporal related features; encoding the timestamp into a 64-bit timer value; encoding the feature type into a type identifier; encoding the spatial index into a coordinate hash value; concatenating the 64-bit timer value, the type identifier, and the coordinate hash value to obtain a binary code; generating a checksum of the binary code using a CRC-8 checksum algorithm; and concatenating the binary code and the checksum to obtain the feature marker data.

[0093] The timestamp refers to the time stamp corresponding to the generation of the original data or feature data. It is usually a numerical value representing time and is used to identify the position of the data on the time axis, reflecting the time of data generation or collection, and helping to establish the order and time interval relationship of the data in the time dimension. The feature type refers to the identifier for classifying the extracted spatiotemporal related features, which is used to distinguish different types of features so that subsequent data processing and analysis can take corresponding operations according to the characteristics of different features. It reflects the semantic or functional category of features and is a label used to classify and identify features. For example, in industrial vision inspection scenarios, the feature types extracted from image data can include various types such as "edge features", "texture features", and "shape features". "Edge features" represent the outline of an object or the boundary information between different regions. "Texture features" describe the texture pattern of the object's surface. "Shape features" are used to represent the overall shape of the object. The spatial index refers to the encoding or numerical value used to identify the spatial location of a feature. It provides a means to quickly locate and reference the spatial distribution of features, and can help establish a mapping relationship between features and spatial locations. It is convenient to organize, query and process features in the spatial dimension. For example, in a two-dimensional image, the spatial index can be pixel coordinates. The data structure of the feature label data is [HEADER (16bit)][timestamp (64bit)][feature type (4bit)][spatial index (16bit)][CRC (8bit)]).

[0094] Optionally, the process of encoding the timestamp into a 64-bit timer value is to encode the timestamp into a 64-bit high-precision timer value (precision 1μs) using binary structured encoding. Further, the process of encoding the feature type into a type identifier refers to encoding the feature type into a 4-bit type identifier (0x01-0x0F corresponding to different features). Further, the process of encoding the spatial index into a coordinate hash value refers to encoding the spatial index into a 16-bit coordinate hash value (5 bits each for X / Y / Z axes, reserving 1 bit). Further, the process of generating the check code of the binary encoding using the CRC-8 check algorithm refers to generating an 8-bit check code using the CRC-8 check algorithm.

[0095] S3. Based on the instantaneous bandwidth of the M.2 interface and the load status of the AI ​​chip, the feature tag data is compressed into optimized compressed data using the dynamic compression engine.

[0096] This invention overcomes the shortcomings of the traditional transmission scheme that uses a fixed compression algorithm by using the dynamic compression engine to compress the feature tag data into optimized compressed data. It can adaptively select the compression algorithm according to the instantaneous bandwidth of the M.2 interface and the load state of the AI ​​chip, thereby improving bandwidth utilization, avoiding data accumulation and transmission delay caused by bandwidth fluctuations, and ensuring the efficiency and adaptability of data transmission, thus guaranteeing the accuracy of spatiotemporal feature analysis.

[0097] In one embodiment of the present invention, the step of compressing the feature marker data into optimized compressed data using the dynamic compression engine based on the instantaneous bandwidth of the M.2 interface and the load state of the AI ​​chip includes: when the instantaneous bandwidth is less than a preset bandwidth, using the dynamic compression engine to call the tensor folding compression algorithm on the accelerator card of the M.2 accelerator card; while retaining the key motion vectors of the coordinate hash values ​​in the feature marker data, executing the tensor folding compression algorithm through the adjustable pipeline silicon on the accelerator card to perform dimensionality reduction processing on the coordinate hash values ​​in the feature marker data to obtain dimensionality-reduced hash values; based on the dimensionality-reduced hash values, completing the process of compressing the feature marker data into optimized compressed data; when the load state is greater than a preset load, using the dynamic compression engine to call the tensor folding compression algorithm on the M.2 accelerator card of ... The dynamic compression engine invokes the sparse matrix compression algorithm on the accelerator card; it uses the hardware counter of the entropy coding coprocessor on the accelerator card to count the feature type frequency of non-zero value elements in the feature tag data; it uses the feature type frequency to generate a priority queue of non-zero value elements; based on the priority queue and the Huffman tree generation rules pre-stored in the silicon ROM on the accelerator card, it uses Huffman coding in the sparse matrix compression algorithm to generate a fixed-length optimized encoding table for the non-zero value elements; it detects zero value elements in the feature tag data; it uses run-length encoding in the sparse matrix compression algorithm to generate a sparse encoding matrix for the zero value elements; and it uses the entropy coding coprocessor to convert the fixed-length optimized encoding table and the sparse encoding matrix into optimized compressed data.

[0098] See Figure 3 The diagram shown is a flowchart illustrating the optimized compressed data implementation process of the data transmission device based on the accelerator card according to an embodiment of the present invention.

[0099] The preset bandwidth refers to a bandwidth threshold pre-set by the system based on application scenarios and performance requirements. It is used to determine whether the current network or interface transmission capacity meets the basic requirements for data transmission. For example, in a live video streaming scenario, to ensure smooth transmission of 720p resolution and 30fps video, the preset bandwidth might be set to 5Mbps. If the actual available bandwidth is higher than this value, higher quality video can be transmitted normally. If it is lower than this value, the system may trigger bandwidth optimization strategies, such as reducing the video resolution or frame rate. Furthermore, the onboard acceleration card refers to the hardware components and circuits integrated on the M.2 acceleration card to implement functions such as data processing, compression, and transmission acceleration. For example, the dynamic compression engine on the M.2 acceleration card. Adjustable pipeline silicon wafers and silicon ROMs for storing Huffman tree generation rules are all components on the accelerator card. The tensor folding compression algorithm is an algorithm for compressing high-dimensional data (such as images and videos). It reduces data redundancy by performing tensor decomposition and dimensional folding, achieving efficient data representation and compression. For example, when processing 4K resolution video data, the tensor folding compression algorithm can fold the spatial and temporal dimensions in video frames, reducing the data volume and thus reducing transmission bandwidth requirements without significantly reducing video quality. The key motion vectors refer to vector information in a video sequence that accurately describes the motion state and trajectory of objects. These vectors typically contain information about the object's motion. Key features include the direction, speed, and position changes of the movement. For example, in a football match, when tracking the trajectory of a football, key motion vectors can describe the direction of movement (e.g., from left to right, forward, etc.), speed (e.g., the number of pixels moved per second), and position changes (e.g., from the center of the screen to the upper right corner) of the football over several consecutive frames. The preset load is a load threshold pre-set by the system based on the performance of the AI ​​chip and the application scenario. It is used to determine whether the current computing task of the AI ​​chip is too heavy, thereby deciding whether to adjust the task allocation or activate the load balancing strategy. For example, in an image recognition task, if the computing resources of the AI ​​chip are occupied by more than 80%, the preset load may be set to 80%. When the actual load exceeds this value, the system... This may trigger strategies such as task queuing or allocation to other computing units to ensure timely task processing. The hardware counter is a dedicated counting unit integrated into a chip or hardware circuit, used to quickly count the frequency of specific events or data occurrences. For example, in an entropy coding coprocessor, the hardware counter can be used to count the frequency of different feature types (such as high dynamic range data, low latency sensitive data, etc.) in feature-labeled data, providing a basis for subsequent Huffman coding. The non-zero value element refers to an element in a dataset or matrix whose value is not zero. In sparse matrices, non-zero value elements often contain key information, and the distribution and value of non-zero value elements are important for data compression and processing. For example, in a matrix representing an image...Most pixel values ​​may be zero (e.g., a black background), while non-zero values ​​represent objects in the image (e.g., white text or patterns). These non-zero values ​​contain key information about the image and need to be effectively encoded and stored. The feature type frequency refers to the number or proportion of different feature types appearing in the feature-labeled data. It reflects the distribution of various features in the data and provides important statistical information for subsequent data processing and compression. For example, in a video analysis scenario, if the feature types include "people," "vehicles," and "buildings," and statistical analysis shows that the "people" feature appears 50 times, the "vehicles" feature appears 30 times, and the "buildings" feature appears 20 times in a certain video clip, then... Their feature type frequencies are 50%, 30%, and 20%, respectively. The priority queue is a data structure used to store and manage tasks or data items with different priorities. In data processing and task scheduling, the priority queue ensures that high-priority tasks or data items are processed before low-priority items. For example, in AI inference tasks, if there is a task queue containing tasks such as "real-time object detection," "image classification," and "video summarization," with high, medium, and low priorities respectively, the priority queue will process the "real-time object detection" task first, then the "image classification" task, and finally the "video summarization" task. The silicon ROM (Read-Only) Memory (ROM) is a read-only memory integrated into a chip, used to store fixed data or program code pre-written during chip manufacturing. In M.2 accelerator cards, silicon ROM can be used to store key algorithm parameters such as Huffman tree generation rules. For example, in the sparse matrix compression algorithm module of an M.2 accelerator card, the silicon ROM stores Huffman tree generation rules, including the algorithm steps and data structure definitions of Huffman coding. These rules are called by the hardware circuit during compression to generate a Huffman coding table. The Huffman tree generation rules are a set of algorithms and logic used to construct a Huffman tree based on the frequency distribution of data. A Huffman tree is a binary tree structure used to implement Huffman coding, which can assign different length codes to data elements of different frequencies, thereby achieving data... Lossless compression of data, for example, when constructing a Huffman tree based on the frequency distribution of feature types, firstly, the frequency of each feature type is counted. Then, following the principle of a greedy algorithm, the two feature types with the lowest frequencies are merged into a new node, and this process is repeated until a complete binary tree is constructed. Finally, leaf nodes represent the original feature types, and non-leaf nodes represent the merged frequencies. The paths between nodes determine the length of the Huffman code and the specific code value. The fixed-length optimized coding table is a table that maps data elements to fixed-length codes. In data compression, by using a fixed-length optimized coding table, the original data can be converted into a shorter coded representation, thereby reducing the amount of data and improving transmission and storage efficiency. For example, in the compression of feature-labeled data, assuming there are four feature types...The symbols "A", "B", "C", and "D" have frequencies of 40%, 30%, 20%, and 10%, respectively. A fixed-length optimized encoding table constructed based on Huffman tree generation rules might map "A" to "00", "B" to "01", "C" to "10", and "D" to "11". Through this fixed-length encoding table, each feature type is represented by a two-bit code. Zero-value elements refer to elements in a dataset or matrix that have a value of zero. In sparse matrices, zero-value elements typically constitute a large proportion. Efficiently encoding these elements can significantly reduce data storage and transmission overhead. For example, in a matrix representing an image, most pixel values ​​may be zero (e.g., a black background). These zero-value elements can be compressed using methods such as run-length encoding to reduce data volume and improve storage and transmission efficiency. The sparse encoding matrix refers to a matrix generated after compressing the zero-value elements in the original data using a specific encoding method (such as run-length encoding). It retains the non-zero-value elements and their position information of the original data, while replacing consecutive zero-value elements with their starting position and length, thereby achieving efficient data representation.

[0100] See Figure 2 The diagram shown is a schematic representation of a sparse coding matrix for implementing the accelerator card-based data transmission device according to an embodiment of the present invention. Figure 2 In this example, assuming the original data is a one-dimensional array containing a large number of zero-value elements, the original data is 0,0,0,5,0,8,0,0,0,0,3,0. Run-length encoding is used to encode consecutive zero-value elements to generate a sparse encoding matrix. The first three consecutive zero-value elements can be represented by the starting position 0 and the length 3. The subsequent zero-value elements are also encoded in the same way to generate the final sparse encoding matrix.

[0101] Optionally, the process of compressing the feature-labeled data into optimized compressed data based on the dimensionality-reduced hash value refers to using the dimensionality-reduced hash value as the optimized compressed data.

[0102] In another embodiment of the present invention, the step of converting the fixed-length optimized coding table and the sparse coding matrix into optimized compressed data through the entropy coding coprocessor includes: obtaining non-zero value elements and zero value elements in the feature label data; after the entropy coding coprocessor receives the fixed-length optimized coding table and the sparse coding matrix, using the fixed-length optimized coding table to encode the non-zero value elements to obtain non-zero value codes; using the sparse coding matrix to encode the zero value elements to obtain zero value codes; and using the entropy coding coprocessor to encapsulate the non-zero value codes and the zero value codes to obtain optimized compressed data.

[0103] Optionally, the process of encapsulating the non-zero value code and the zero value code using the entropy coding coprocessor to obtain optimized compressed data refers to...

[0104] S4. Input the optimized compressed data into the heterogeneous computing allocator, so that the heterogeneous computing allocator can allocate path selection instructions to the optimized compressed data according to the feature tag type of the optimized compressed data.

[0105] This invention addresses the problem in the prior art where "the heterogeneous computing allocator fails to dynamically sense the AI ​​chip load." By dynamically allocating path selection instructions based on feature tag types through the heterogeneous computing allocator, it achieves a reasonable allocation of computing resources, avoids high-priority tasks being assigned to overloaded computing units, and improves the overall system efficiency and the timeliness of data processing.

[0106] In one embodiment of the present invention, allocating a transmission path for the optimized compressed data through the heterogeneous computing allocator according to the feature tag type of the optimized compressed data includes: inputting the feature tag type, the instantaneous bandwidth of the M.2 interface, and the load status of the AI ​​chip into the decision tree model of the heterogeneous computing allocator, so as to output a path selection instruction for the optimized compressed data through the decision tree model; wherein, the path selection instruction includes a target device identifier, a transmission path identifier, a data packet identifier, and a task priority.

[0107] The feature tag type refers to the type identifier portion of the feature tag data; the instantaneous bandwidth refers to the maximum data transfer rate that the M.2 interface can provide at a specific moment, reflecting the actual transmission capacity of the interface at that moment; the load status refers to the computational workload of the AI ​​chip at a certain moment, usually represented by the chip's resource utilization or the number of tasks being processed; the target device identifier is a tag or address used to uniquely identify the data transfer destination, ensuring that data can be accurately sent to the specified device or component. For example, in the system, the NPU unit of the AI ​​chip has a unique target device identifier "NPU_01", and the host CPU has an identifier "CPU_01". During transmission, these identifiers are used to determine the data receiver. The transmission path identifier is used to distinguish different data transmission paths, helping the system identify and select the appropriate data transmission route. For example, when data is transmitted through the AXI bus inside the M.2 accelerator card, the corresponding transmission path identifier is "AXI_Bus_Path", while when it is sent to the host memory through the TLP message reassembly module of the M.2 interface, the transmission path identifier is "TLP_PCIE_Path". The packet identifier is a unique identifier used to distinguish different packets, helping the receiving end to identify and reassemble packets, ensuring the integrity and order of data transmission. For example, the binary code of a packet is "10101010 01010101", and its corresponding packet identifier can be "DP_001", used to uniquely identify the packet during transmission. Task priority refers to the priority level assigned to a task based on its importance and urgency, determining the scheduling order of tasks in the system. For example, in a real-time target tracking task, if the target may pose a security threat, the task will be given a high priority, such as "Priority_Level_High", to ensure that the system prioritizes the task and responds promptly.

[0108] S5. According to the path selection instruction, the data transmission of the optimized compressed data is completed through the heterogeneous computing allocator to obtain the data transmission result.

[0109] This invention completes data transmission by executing path selection instructions, achieving efficient and accurate data transmission, improving the reliability and accuracy of data transmission, ensuring that data can reach the target device in a timely and accurate manner, meeting the spatiotemporal consistency requirements of high-precision AI inference, improving the performance and effectiveness of the entire data transmission system, and avoiding the problems of feature data missing processing time and spatiotemporal correlation breakage.

[0110] In one embodiment of the present invention, the step of transmitting the optimized compressed data through the heterogeneous computing allocator according to the path selection instruction to obtain the data transmission result includes: parsing the path selection instruction through the control logic unit in the heterogeneous computing allocator to obtain parsing instruction information; activating the bus transmission logic corresponding to the parsing instruction information using the control logic unit; converting the optimized compressed data according to the bus transmission logic to obtain format-converted data; and transmitting the format-converted data through the bus transmission logic based on the target device, data packet identifier, and task priority in the parsing instruction information to obtain the data transmission result.

[0111] The bus transmission logic refers to a series of rules and mechanisms that control how data is transmitted on the bus in a data transmission system. It defines the data transmission format, timing, control signals, etc., to ensure that data can be transmitted efficiently and accurately between different devices or components according to predetermined rules. The bus transmission logic usually includes data packing and unpacking rules, transmission priority management, error detection and correction mechanisms, etc., to ensure the reliability of data transmission.

[0112] For example, the path selection instruction is parsed by the control logic unit in the heterogeneous computing allocator. For instance, the control logic unit parses the path selection instruction and extracts key information, including the target device identifier (e.g., "NPU_Unit_1"), the transmission path identifier (e.g., "AXI_Bus_Path"), the data packet identifier (e.g., "Data_Packet_ID_1234"), and the task priority (e.g., "Priority_Level_High"). Further, the control logic unit activates the bus transmission logic corresponding to the parsed instruction information. For example, based on the parsed instruction information, the control logic unit determines the specific path for data transmission. If the target device is the NPU unit of an AI chip, and the transmission path is the AXI bus inside the accelerator card, it will activate the corresponding AXI bus. The line transmission logic encapsulates the optimized compressed data according to the specified packet identifier and sends the data to the NPU unit of the AI ​​chip based on task priority information. Simultaneously, it updates the internal task scheduling table, recording the transmission status and priority of the packet to ensure that high-priority tasks are processed first. Regarding format conversion, if the optimized compressed data has already been encapsulated into a format suitable for AXI bus transmission by the entropy coding coprocessor, re-encapsulation is usually unnecessary. However, if the packet identifier in the path selection instruction is inconsistent with the encapsulated data format, simple format adjustments may be required to ensure that the packet identifier can be correctly identified and used. The host PCIe bus typically has its own specific data transmission format and protocol. If the encapsulation format of the optimized compressed data is inconsistent with the transmission requirements of the host PCIe bus, format conversion is required before transmission.

[0113] Compared to the problems described in the background art, the embodiments of the present invention efficiently acquire raw data streams from external devices through the M.2 interface, providing a foundation for subsequent processing and serving as the starting point of the entire data transmission system. This ensures timely data acquisition and avoids processing delays caused by untimely data acquisition. Furthermore, the embodiments of the present invention address the problem of "lack of a real-time feature analysis engine" in the background art through feature analysis. This allows for the real-time extraction of effective features from the raw data stream, filtering out invalid information, reducing the amount of data transmitted and processed subsequently, improving data usefulness and processing efficiency, preventing AI chips from getting bogged down in invalid calculations, and enhancing the accuracy of effective feature recognition. Furthermore, the embodiments of the present invention generate structured feature-labeled data by binary encoding spatiotemporally related features, facilitating subsequent transmission and processing, improving data manageability and identifiability, and providing a convenient data format for subsequent compression and transmission operations. The embodiments of the present invention overcome the limitations of "traditional transmission methods" in the background art by utilizing the dynamic compression engine to compress the feature-labeled data into optimized compressed data. This invention overcomes the shortcomings of using a fixed compression algorithm by adaptively selecting the compression algorithm based on the instantaneous bandwidth of the M.2 interface and the load status of the AI ​​chip. This improves bandwidth utilization, avoids data accumulation and transmission delays caused by bandwidth fluctuations, and ensures the efficiency and adaptability of data transmission, guaranteeing the accuracy of spatiotemporal feature analysis. This embodiment of the invention addresses the problem of "heterogeneous computing allocator not dynamically sensing the AI ​​chip load" in the background technology. By dynamically allocating path selection instructions based on feature tag types through the heterogeneous computing allocator, it achieves reasonable allocation of computing resources, preventing high-priority tasks from being assigned to overloaded computing units, improving the overall system efficiency and the timeliness of data processing. This embodiment of the invention completes data transmission by executing path selection instructions, achieving efficient and accurate data transmission, improving the reliability and accuracy of data transmission, ensuring that data arrives at the target device in a timely and accurate manner, meeting the spatiotemporal consistency requirements of high-precision AI inference, improving the performance and effectiveness of the entire data transmission system, and avoiding problems such as missed processing time for feature data and the breakage of spatiotemporal correlation. Therefore, the data transmission method and device based on the accelerator card provided by this embodiment of the invention can ensure that the final data transmission result meets the spatiotemporal consistency requirements of high-precision AI inference.

[0114] Example 2:

[0115] like Figure 4 The diagram shown is a functional block diagram of a data transmission device based on an accelerator card according to the present invention.

[0116] The data transmission device 400 based on an accelerator card described in this invention can be installed in an electronic device. Depending on the functions implemented, the data transmission device based on the accelerator card may include a system construction module 401, a feature encoding module 402, a data compression module 403, a path selection module 404, and a data transmission module 405. The module described in this invention can also be called a unit, which refers to a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, and are stored in the memory of the electronic device.

[0117] In this embodiment of the invention, the functions of each module / unit are as follows:

[0118] The system construction module 401 is used to construct a data transmission system, wherein the data transmission system includes external devices, an M.2 accelerator card, an M.2 interface, and an AI chip, and the M.2 accelerator card includes a pattern recognition engine, a dynamic compression engine, and a heterogeneous computing allocator.

[0119] The feature encoding module 402 is used to collect the raw data stream of the external device, perform real-time feature analysis on the raw data stream through the pattern recognition engine to obtain spatiotemporal related features, and encode the spatiotemporal related features into feature tag data in binary.

[0120] The data compression module 403 is used to compress the feature tag data into optimized compressed data using the dynamic compression engine based on the instantaneous bandwidth of the M.2 interface and the load status of the AI ​​chip.

[0121] The path selection module 404 is used to input the optimized compressed data into the heterogeneous computing allocator, so as to allocate path selection instructions to the optimized compressed data through the heterogeneous computing allocator according to the feature tag type of the optimized compressed data;

[0122] The data transmission module 405 is used to complete the data transmission of the optimized compressed data through the heterogeneous computing allocator according to the path selection instruction, and obtain the data transmission result.

[0123] In detail, the modules in the data transmission device 400 based on the accelerator card described in this embodiment of the invention employ the same methods as described above during use. Figure 1 The data transmission method based on the accelerator card described herein uses the same technical means and can produce the same technical effect, so it will not be repeated here.

[0124] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0125] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A method for data transfer based on an acceleration card, characterized in that, The method comprises: constructing a data transmission system, wherein the data transmission system comprises an external device, an M.2 acceleration card, an M.2 interface, an AI chip, the M.2 acceleration card comprises a pattern recognition engine, a dynamic compression engine, and a heterogeneous computing distributor; collecting a raw data stream of the external device, performing real-time feature analysis on the raw data stream through the pattern recognition engine to obtain space-time correlation features, and performing binary coding on the space-time correlation features to obtain feature label data; according to the instantaneous bandwidth of the M.2 interface and the load state of the AI chip, using the dynamic compression engine to compress the feature label data into optimized compressed data, specifically comprising: when the instantaneous bandwidth is less than a preset bandwidth, using the dynamic compression engine to call a tensor folding compression algorithm in the acceleration card on-board of the M.2 acceleration card; while retaining the key motion vectors of the coordinate hash values in the feature label data, performing dimension reduction processing on the coordinate hash values in the feature label data through the adjustable pipeline silicon chip in the acceleration card on-board to obtain reduced hash values; based on the reduced hash values, completing the process of compressing the feature label data into optimized compressed data; when the load state is greater than a preset load, using the dynamic compression engine to call a sparse matrix compression algorithm in the acceleration card on-board; counting the feature type frequency of non-zero value elements in the feature label data through the hardware counter of the entropy encoding coprocessor in the acceleration card on-board; generating a priority queue of the non-zero value elements using the feature type frequency; generating a fixed-length optimized encoding table of the non-zero value elements using the Huffman encoding in the sparse matrix compression algorithm according to the priority queue and the pre-stored Huffman tree generation rule in the silicon ROM in the acceleration card on-board; detecting zero value elements in the feature label data; generating a sparse encoding matrix of the zero value elements using the run-length encoding in the sparse matrix compression algorithm; converting the fixed-length optimized encoding table and the sparse encoding matrix into optimized compressed data through the entropy encoding coprocessor, specifically comprising: obtaining non-zero value elements and zero value elements in the feature label data; after the entropy encoding coprocessor receives the fixed-length optimized encoding table and the sparse encoding matrix, encoding mapping the non-zero value elements using the fixed-length optimized encoding table to obtain non-zero value encoding; encoding mapping the zero value elements using the sparse encoding matrix to obtain zero value encoding; using the entropy encoding coprocessor to package the non-zero value encoding and the zero value encoding to obtain optimized compressed data; inputting the optimized compressed data into the heterogeneous computing distributor to assign path selection instructions to the optimized compressed data through the heterogeneous computing distributor according to the feature label type of the optimized compressed data; according to the path selection instructions, completing the data transmission of the optimized compressed data through the heterogeneous computing distributor to obtain a data transmission result.

2. The method of claim 1, wherein the data transfer is performed by a host computer and the acceleration card. The construction of the data transmission system comprises: preparing an external device and an M.2 acceleration card; deploying a mode recognition engine in a front-end area of the M.2 acceleration card; deploying a dynamic compression engine in a middle area of the M.2 acceleration card; deploying a heterogeneous computing allocator in a back-end control area of the M.2 acceleration card; integrating an AI chip on the M.2 acceleration card; constructing an M.2 interface connecting the external device and the M.2 acceleration card; determining a data transmission system through the external device, the M.2 acceleration card, the M.2 interface, the AI chip, the mode recognition engine, the dynamic compression engine, and the heterogeneous computing allocator.

3. The method of claim 1, wherein the data transfer is performed by a host computer and the acceleration card. the process of collecting the original data stream of the external device includes: transmitting the original data stream of the external device to the M.2 acceleration card through the M.2 interface; receiving the original data stream through the M.2 interface in the M.2 acceleration card to complete the process of collecting the original data stream of the external device.

4. The method of claim 1, wherein the data transfer is performed by a host computer and the acceleration card. the process of performing real-time feature analysis on the original data stream through the mode recognition engine to obtain space-time correlation features includes: capturing inter-frame motion features of the original data stream through a bidirectional LSTM in the mode recognition engine; extracting spatial distribution patterns of the original data stream through a convolution kernel in the mode recognition engine; weighting and fusing the inter-frame motion features and the spatial distribution patterns through an attention mechanism in the mode recognition engine to obtain space-time correlation features.

5. The method of claim 1, wherein the data transfer is performed by a host computer and the acceleration card. the process of binary encoding the space-time correlation features into feature tag data includes: extracting a timestamp, a feature type, and a spatial index from the space-time correlation features; encoding the timestamp into a 64-bit timer value; encoding the feature type into a type identifier; encoding the spatial index into a coordinate hash value; splicing the 64-bit timer value, the type identifier, and the coordinate hash value to obtain a binary code; generating a check code for the binary code using a CRC-8 check algorithm; splicing the binary code and the check code to obtain feature tag data.

6. The accelerator card-based data transfer method of claim 1, wherein, the process of assigning path selection instructions to the optimized compressed data through the heterogeneous computing allocator according to the feature tag type of the optimized compressed data includes: inputting the feature tag type, an instantaneous bandwidth of the M.2 interface, and a load state of the AI chip into a decision tree model of the heterogeneous computing allocator to output path selection instructions for the optimized compressed data through the decision tree model; wherein the path selection instructions include a target device identifier, a transmission path identifier, a data packet identifier, and a task priority.

7. The accelerator card-based data transfer method of claim 1, wherein, the process of completing data transmission of the optimized compressed data through the heterogeneous computing allocator according to the path selection instructions to obtain a data transmission result includes: performing instruction analysis on the path selection instructions through a control logic unit in the heterogeneous computing allocator to obtain analysis instruction information; activating bus transmission logic corresponding to the analysis instruction information using the control logic unit; performing format conversion on the optimized compressed data according to the bus transmission logic to obtain format conversion data; Based on the target device, the data packet identifier and the task priority in the parsed instruction information, the format conversion data is transmitted by the bus transmission logic to obtain a data transmission result.

8. An accelerator card based data transfer apparatus, comprising: The device comprises: A system construction module is configured to construct a data transmission system, wherein the data transmission system comprises an external device, an M.2 acceleration card, an M.2 interface, and an AI chip, the M.2 acceleration card comprises a pattern recognition engine, a dynamic compression engine, and a heterogeneous computing distributor; A feature encoding module is configured to collect original data streams of the external device, perform real-time feature analysis on the original data streams by the pattern recognition engine to obtain space-time correlation features, and encode the space-time correlation features into feature marker data in binary form; A data compression module is configured to compress the feature marker data into optimized compressed data by using the dynamic compression engine according to the instantaneous bandwidth of the M.2 interface and the load state of the AI chip, and specifically comprises: When the instantaneous bandwidth is less than a preset bandwidth, the dynamic compression engine is used to call a tensor folding compression algorithm in the M.2 acceleration card on board; While keeping the key motion vectors of the coordinate hash values in the feature marker data, the tensor folding compression algorithm is executed by an adjustable pipeline silicon chip on board the M.2 acceleration card to perform dimension reduction processing on the coordinate hash values in the feature marker data to obtain reduced hash values; Based on the reduced hash values, the process of compressing the feature marker data into optimized compressed data is completed; When the load state is greater than a preset load, the dynamic compression engine is used to call a sparse matrix compression algorithm on board the M.2 acceleration card; The feature type frequency of non-zero value elements in the feature marker data is counted by a hardware counter of an entropy encoding coprocessor on board the M.2 acceleration card; The feature type frequency is used to generate a priority queue of the non-zero value elements; According to the priority queue and a pre-stored Huffman tree generation rule in a silicon ROM on board the M.2 acceleration card, a fixed-length optimized encoding table of the non-zero value elements is generated by using Huffman encoding in the sparse matrix compression algorithm; Zero value elements in the feature marker data are detected; A sparse encoding matrix of the zero value elements is generated by using run-length encoding in the sparse matrix compression algorithm; The fixed-length optimized encoding table and the sparse encoding matrix are converted into optimized compressed data by the entropy encoding coprocessor, and specifically comprises: Non-zero value elements and zero value elements in the feature marker data are obtained; After the entropy encoding coprocessor receives the fixed-length optimized encoding table and the sparse encoding matrix, the non-zero value elements are encoded and mapped by using the fixed-length optimized encoding table to obtain non-zero value encoding; The zero value elements are encoded and mapped by using the sparse encoding matrix to obtain zero value encoding; The non-zero value encoding and the zero value encoding are packaged by the entropy encoding coprocessor to obtain optimized compressed data. The path selection module is configured to input the optimized compressed data into the heterogeneous computing allocator, so as to allocate path selection instructions for the optimized compressed data through the heterogeneous computing allocator according to a feature label type of the optimized compressed data. The data transmission module is configured to complete data transmission of the optimized compressed data through the heterogeneous computing allocator according to the path selection instructions, and obtain a data transmission result.

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