FIR (Finite Impulse Response) filtering method and filter based on probability and fixed-point hybrid calculation

Abstract

The invention discloses an FIR (Finite Impulse Response) filtering method and filter based on probability and fixed-point hybrid calculation, relates to the technical field of communication and the field of digital signal processing, and solves the problems of high hardware complexity and long critical path. According to the technical scheme, the method is characterized in that a high-order part in a digital signal and a filter coefficient are subjected to fixed-point multiply-accumulate operation to obtain a high-order calculation result; preprocessing the filter coefficient to generate a random symbol of a selection end in a multiplexer; converting a low-order part in the digital signal into a parallel probability bit stream; according to a random symbol of a selection end, controlling and selecting a parallel probability bit stream to carry out probability multiply-accumulate operation to obtain a bipolar probability bit; carrying out backward conversion on the bipolar probability bit to obtain a low-order calculation result; adding the high-order calculation result and the low-order fixed-point result, and outputting an FIR filtering result; the effects of optimizing resource consumption, realizing precision-complexity-energy efficiency collaborative optimization and expanding the application range of the FIR filter are achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of digital signal processing, more particularly, it relates to a FIR filtering method and a filter based on probability and fixed-point hybrid calculation. BACKGROUND

[0002] Finite impulse response (FIR) filter as a core component in the field of digital signal processing, plays an irreplaceable role in the field of communication system, image processing, radar signal analysis, etc. With the rapid development of 5G communication, edge computing and Internet of Things technology, higher requirements are put forward for the calculation accuracy, real-time performance and energy efficiency of the filter. The traditional FIR filter relies on high-precision fixed-point multiplication and accumulation operation, and its hardware resource consumption and calculation complexity increase exponentially with the number of bits, especially in low-power embedded scenarios, the key path delay, area overhead and calculation accuracy are difficult to balance. Therefore, how to realize resource optimization and energy efficiency improvement through algorithm and architecture innovation while ensuring calculation accuracy has become the key direction of current research.

[0003] In the prior art, the schemes based on stochastic computing (SC) and approximate processing provide a new idea for reducing complexity. For example, one is to combine stochastic computing with residue number system (RNS), replace the traditional multiplication and addition unit with probability bit stream, which significantly reduces the hardware resources, but the dynamic range limitation of the residue number system and the inherent randomness of the stochastic computing make it difficult to guarantee high-precision, and the modulo operation complexity brought by the residue base conversion offsets part of the benefits in the long bit stream scenario. Another is to use probability calculation and Max-log approximation to convert multiplication and addition into logic gate operations, but the error accumulation is serious in the low-degree variable node and hierarchical iteration scenarios, especially when the filter coefficient dynamic range is large, the normalization error will significantly affect the output accuracy. Another is to propose semi-probabilistic calculation for LDPC decoder, but its design is limited to the sparse check nodes in the decoding scenario, and cannot be directly migrated to the dense multiplication and addition operation of FIR filter.

[0004] Therefore, it can be seen that although stochastic computing and approximate processing reduce complexity, they have inherent defects in high-precision guarantee, dynamic coefficient adaptability and hierarchical calculation error control. Especially in mixed signal processing, high-precision filtering and other scenarios, traditional methods are difficult to balance high-precision calculation and low-precision calculation efficiency, resulting in limited overall system performance. SUMMARY

[0005] In order to address the deficiencies in the prior art, the purpose of the present invention is to provide an FIR filtering method and filter based on a hybrid calculation of probability and fixed-point calculation, and adopt a hybrid FIR filter based on a hybrid of probability calculation and fixed-point calculation. By decomposing the input signal into high-order fixed-point calculation and low-order probability calculation, the high-order fixed-point calculation part ensures the calculation accuracy while the low-order probability calculation part introduces parallel probability calculation, converting the low-order multiplication and accumulation operation into a parallel bit stream probability logic operation, and being able to implement the originally complex multiplication and addition operation using gate-level circuits and logic, thereby solving the irreconcilable contradiction between high-order precision and low-order efficiency in the existing random calculation scheme, effectively solving the problems of high hardware complexity and long critical path, optimizing resource consumption, realizing the coordinated optimization of precision-complexity-energy efficiency, and expanding the application scope of the FIR filter.

[0006] The above technical objectives of the present invention are achieved through the following technical solutions:

[0007] In a first aspect, an FIR filtering method based on hybrid probability and fixed-point calculation is provided, comprising the following steps: performing fixed-point multiplication and accumulation operations on the high-order portion of a digital signal and a filter coefficient to obtain a high-order calculation result;

[0008] Preprocessing the filter coefficients to generate random symbols for the selection end of the multiplexer;

[0009] Convert the low-order part of the digital signal into a parallel probability bit stream;

[0010] According to the random symbol of the selection end control symbol selection end, the parallel probability bit stream is controlled to perform probability multiplication and accumulation operation to obtain a bipolar probability bit;

[0011] Backward conversion is performed on the bipolar probability bits to obtain a low-bit calculation result;

[0012] The high-order calculation result is added to the low-order fixed-point result, and the FIR filtering result is output.

[0013] Furthermore, the random symbol of the selection end is generated by serial processing, including:

[0014] Calculate the absolute value of the filter coefficients one by one, add them up to get the total, and calculate the normalized probability value of each filter coefficient;

[0015] Comparing the probability value with the corresponding bit of the first sequence bit by bit to generate a thermometer code;

[0016] The bits at the same position in the thermometer code are added together to generate a random symbol stream at the selected end.

[0017] Furthermore, the random symbols of the selection end are generated by parallel processing, including:

[0018] Simultaneously calculate the absolute values of all filter coefficients, and obtain the cumulative sum of the absolute values through parallel processing, and calculate the normalized probability values of each filter coefficient;

[0019] Simultaneously compare all the normalized probability values with corresponding bits of the first sequence, and generate a random symbol stream of the selection end through thermometer decoding instead of addition operation.

[0020] Further, if the first sequence is an MCAS sequence, the input end of the multiplexer adopts a low-difference sequence.

[0021] Further, if the first sequence is a low-difference sequence, the input end of the multiplexer adopts an MCAS sequence.

[0022] Further, if the first sequence is a low-difference sequence, then:

[0023] Generate a bit stream consistent with the generated value compared with the low-difference sequence through thermometer encoding;

[0024] Exchange the order of the bit stream through the selected line without overhead to generate the parallel probability bit stream.

[0025] Further, the method further comprises: multiplying the positive and negative signs of the random symbol with the corresponding bit stream in the parallel probability bit stream;

[0026] Normalizing the absolute value of the element corresponding to the selection end;

[0027] Performing probability multiplication and accumulation operation based on the multiplication and normalization results to obtain the bipolar probability bit.

[0028] Further, the method further comprises: if the filter coefficients are a fixed group or multiple groups, storing the filter coefficients in a memory.

[0029] In a second aspect, an FIR filter based on probability and fixed-point hybrid calculation is provided, comprising: a fixed-point FIR module, a preprocessing module, a probability FIR module, and filter merging, the probability FIR module comprising a parallel bit stream generation module, a bit stream calculation module, and a backward conversion module; wherein,

[0030] The fixed-point calculation module is configured to perform fixed-point multiplication and accumulation operation on the high bit part of the digital signal and the filter coefficients to obtain a high bit calculation result.

[0031] The preprocessing module is configured to preprocess the filter coefficients to generate random symbols of the selection end of the multiplexer.

[0032] The parallel bit stream generation module is configured to convert a low bit part in the digital signal into a parallel probability bit stream.

[0033] The bit stream calculation module is configured to control selection of the parallel probability bit stream for probability multiplication accumulation operation according to the random symbol of the selection end, to obtain a bipolar probability bit.

[0034] The backward conversion module is configured to perform backward conversion on the bipolar probability bit to obtain a low bit calculation result.

[0035] The filter merging module adds the high bit calculation result and the low bit fixed point result to output an FIR filter result.

[0036] Further, the parallel bit stream generation module comprises:

[0037] A thermometer encoding unit is configured to generate a bit stream consistent with a value generated by comparison of a low difference sequence by means of thermometer encoding;

[0038] A line selection unit is configured to exchange the order of the bit streams without cost by means of line selection to generate the parallel probability bit stream.

[0039] And / or, a symbol adjustment unit is configured to multiply the positive and negative symbols of the random symbol with corresponding bit streams in the parallel probability bit stream.

[0040] Compared with the prior art, the present application has the following beneficial effects:

[0041] 1. The FIR filter method based on probability and fixed point hybrid calculation provided by the present application decomposes an input signal into high bit fixed point calculation and low bit probability calculation, the high bit fixed point calculation part guarantees calculation precision, the low bit probability calculation part introduces parallel probability calculation, converts low bit multiplication accumulation operation into parallel bit stream probability logic operation, can implement originally complex multiplication and addition operation by means of gate circuit and logic, effectively solves the problems of high hardware complexity and long critical path, optimizes resource consumption, realizes precision-complexity-energy efficiency collaborative optimization, and expands the application range of the FIR filter.

[0042] 2. The present application synchronously generates all probability bit streams by adopting a bit level parallel architecture, optimizes random symbol generation by combining a low difference sequence and an MCAS sequence, improves probability calculation precision, eliminates serial time delay of traditional probability calculation, improves hybrid system clock frequency, and reduces low bit calculation error to 1 / 4 of equivalent fixed point calculation by sequence optimization.

[0043] 3The present application reduces the area overhead of the probability calculation part by introducing thermometer coding to asymmetrically normalize the filter coefficients in the preprocessing module, combining with the XOR symbol processing of the backward conversion module, and simplifying the bipolar operation into unipolar logical operation.

[0044] 4The present application supports dynamic update and multi-group storage of filter coefficients through a serial / parallel switchable preprocessing architecture. BRIEF DESCRIPTION OF DRAWINGS

[0045] The accompanying drawings, which are included to provide a further understanding of the embodiments of the present application and are incorporated in and constitute a part of this application, illustrate embodiments of the present application and, together with the description, serve to explain the principles of the present application. In the drawings:

[0046] Figure 1 is a flowchart in the embodiment 1 of the present application;

[0047] Figure 2 is a preprocessing process diagram of the filter coefficients in the embodiment 1 of the present application;

[0048] Figure 3 is a serial processing process diagram in the filter coefficient preprocessing in the embodiment 1 of the present application;

[0049] Figure 4 is a parallel processing process diagram in the filter coefficient preprocessing in the embodiment 1 of the present application;

[0050] Figure 5 is a principle process diagram of the parallel bit stream generation module based on probability calculation in the embodiment 1 of the present application;

[0051] Figure 6 is a principle process diagram of the multiply-accumulate calculation module based on probability calculation in the embodiment 1 of the present application;

[0052] Figure 7 is a system block diagram of the FIR filter in the embodiment 2 of the present application;

[0053] Figure 8 is a system block diagram of the probability FIR module in the embodiment 2 of the present application. DETAILED DESCRIPTION

[0054] To make the objects, technical solutions and advantages of the present application clearer, further detailed description will be given to the present application in combination with embodiments and drawings, and the illustrative embodiments of the present application and the description thereof are only used to explain the present application, and do not limit the present application.

[0055] Embodiment 1: FIR filtering method based on probability and fixed-point hybrid calculation, as shown in Figure 1 、 Figure 2 , includes the following steps:

[0056] S1: fixed-point multiplication and accumulation operation is performed on the high bit part in the digital signal and the filter coefficient to obtain a high bit calculation result;

[0057] S2: the filter coefficient is preprocessed to generate a random symbol stream in the selection end of the multiplexer;

[0058] S3: the low bit part in the digital signal is converted into a parallel probability bit stream;

[0059] S4: the random symbol in the selection end is controlled according to the selection end control symbol to control the selection of the parallel probability bit stream to perform a probability multiplication and accumulation operation to obtain a bipolar probability bit;

[0060] S5: the bipolar probability bit is backward converted to obtain a low bit calculation result;

[0061] S6: the high bit calculation result and the low bit fixed-point result are added to output the FIR filtering result.

[0062] In step S1, the high bit part is the highest weight part of a binary number, and the specific bit number is determined according to the precision and can be changed. The higher the required precision, the more bits should be selected for the high bit.

[0063] For example, assuming that the input signal is There are 8 bits in total, and the filter coefficient is , wherein the low bit is calculated by probability, and the multiplication and accumulation calculation can be written as:

[0064] (1);

[0065] wherein, is the input signal; is the i-th input signal; is the high bit part of the i-th input signal; is the low bit part of the i-th input signal; is the filter coefficient; K is the bit number of the low bit part; i is the filter tap; is the coefficient of the i-th tap of the filter coefficient; n is the filter tap number; is the calculation result.

[0066] It can be seen from formula (1) that by dividing the high and low bits of , 1 multiplication and accumulation can be decomposed into 2 multiplication and accumulation operations, the high bit part is calculated by fixed-point, and the low bit part is calculated by probability.

[0067] In step S2, the random symbol in the selection end is generated by serial processing, such as Figure 3As shown, it includes: calculating the absolute value of each filter coefficient and accumulating the sum, and calculating the normalized probability value of each filter coefficient; comparing the probability value with the corresponding bit of the first sequence bit by bit to generate a thermometer code; adding the bits at the same position in the thermometer code to generate the random symbol stream of the selection end. Figure 4 As shown, it includes: calculating the absolute value of all filter coefficients at the same time, and obtaining the accumulated sum of the absolute values through parallel processing, and calculating the normalized probability value of each filter coefficient; comparing all normalized probability values with the corresponding bits of the first sequence at the same time, and generating the random symbol stream of the selection end through thermometer decoding instead of the addition operation.

[0068] In order to improve the multiplication and accumulation calculation accuracy based on probability calculation, the application adopts two special sequences:

[0069] In some embodiments, if the first sequence is an MCAS sequence, the input end in the multiplexer adopts a low-discrepancy sequence.

[0070] That is, in the generation of the random symbol of the selection end, an MCAS (maximal concentrated autocorrelation sequence) sequence is adopted, and a low-discrepancy sequence such as a Sobol sequence is adopted on the input end. The following embodiments explain the principle in this sequence manner.

[0071] In addition, the two groups of special sequences can be used in the opposite way, that is, a low-discrepancy sequence is used on the selection end, and an MCAS sequence is used on the input end, and the principle is completely equivalent.

[0072] Therefore, in some embodiments, if the first sequence is a low-discrepancy sequence, the input end in the multiplexer adopts an MCAS sequence.

[0073] After adopting the special sequence, the performance improvement of 3dB per bit stream in probability calculation can be improved to about 5dB.

[0074] However, even if the special sequence is used, the calculation accuracy of probability calculation is still lower than that of fixed-point calculation, so in order to ensure the calculation accuracy, the application combines probability calculation with fixed-point calculation, and calculates the high bits using traditional fixed-point calculation technology, and calculates the low bits using probability calculation technology.

[0075] In step S3, the low bit part is the part of the lowest weight of the binary number, and the specific number of bits is the difference between the total number of bits and the number of bits of the high bit part.

[0076] In some embodiments, if the first sequence is a low-difference sequence, then: a thermometer encoding is used to generate a bit stream consistent with the value produced by comparing the low-difference sequence; and a multiplexer is used to exchange the order of the bit stream without overhead, generating a parallel probability bit stream, as shown in Figure 5 .

[0077] To facilitate understanding, the embodiments first illustrate the principle of a multiplexer (MUX) implementing the multiply-accumulate operation of a probability bit:

[0078] For example, in a probability calculation, a value is represented as the probability of a bit being 1 in a random bit stream without weight, and the multiply-accumulate calculation can be completed by a multiplexer (MUX). Taking a 2-input MUX as an example, the selection end inputs a binary random symbol , the expectation is , the input end inputs two unipolar random bit streams and , the expectations are and , and all are independent of , where the value range of , and is , then the probability of the output satisfies:

[0079] (2);

[0080] wherein is a binary random symbol; is a random bit stream; is a random bit stream; is an expectation; is an expectation; is an expectation; denotes that the random variable Z is 1; denotes that the random variable X is 1; denotes that the random variable S is 1; denotes that the random variable S is 1; denotes that the random variable Y is 1; is the probability of the random event "the random variable Z is 1"; is the probability of the random event "the random variable X is 1"; is the probability of the random event "the random variable S is 1"; is the probability of the random event "the random variable Y is 1"; is the probability of the random event "the random variable S is 0".

[0081] By formula (2), the multiply-accumulate calculation is completed. Similarly, it can be extended to a multi-input MUX, assuming that:

[0082] (3);

[0083] Then:

[0084] (4);

[0085] wherein, is the probability bit of the i-th input probability ; is the input signal; is the probability of the i-th number appearing in the selection end; n is the number of input ports of the MUX except the selection end; and i is the i-th input.

[0086] The above formula realizes the multiply-accumulate function, that is, realizes the function of the FIR filter in the probability domain.

[0087] In some embodiments, the method further includes: multiplying the positive and negative signs of the random symbol with the corresponding bit stream in the parallel probability bit stream; normalizing the absolute value of the element corresponding to the selection end; and performing a probability multiply-accumulate operation based on the multiplied and normalized results to obtain the bipolar probability bit.

[0088] Specifically in the FIR filter, there are positive and negative in the FIR filter. Since the selection end of the multiplexer MUX can only be positive, and the sum must be 1, if it is necessary to realize any signed multiplication, it is necessary to multiply the sign to the bit stream corresponding to the input end in advance, and it is necessary to normalize the absolute value of the element corresponding to the selection end. As shown in Figure 6 Based on the above, the general multiply-accumulate operation formula based on probability calculation is:

[0089] (5);

[0090] wherein, is the normalized result of the absolute value of the coefficient of the selection end; is the sign of ; denotes the i-th input signal; is the signal multiplied by the sign of the corresponding position coefficient, is the output of the FIR filter after probability calculation scaling; is the output of the actual FIR.

[0091] Considering that there are positive and negative in FIR filter, the conclusion in formula (4) needs to be extended to Bipolar representation. Considering that the range of unipolarity is [0, 1] and the interval is 1, the range of Bipolar representation is In order to extend the unipolar range to Bipolar [-1, 1], the interval needs to be first increased to 2, that is, multiplied by 2, to become [0, 2], and then translated, that is, by subtracting 1 to obtain the interval [-1, 1], therefore, the value of Bipolar range representation is related to the probability of bit being 1 in the probability bit stream

[0092] (6);

[0093] wherein, is the value; is the probability of bit being 1 in the probability bit stream.

[0094] Substituting into formula (4) has:

[0095] (7);

[0096] wherein, is the input signal; is the probability of the selected end appearing i.

[0097] That is, the multiplexer MUX can also complete the multiply-accumulate operation of signed numbers.

[0098] In step S5, the backward conversion is to sum the Bipolar probability bits to obtain the probability p of appearing 1, and then calculate x according to formula (6) in reverse.

[0099] Suppose that a multiply-accumulate operation of order is calculated, the bit stream length is , the bit stream representation is , wherein , the random symbol stream of the selected end is , based on the general multiply-accumulate calculation formula in formula (6), then the calculation formula of the multiply-accumulate output is:

[0100] (8);

[0101] wherein, is the i-th bit of the bit stream ; and indicates the i-th random symbol of the random symbol stream of the selected end.

[0102] ​Considering the definition of the complement, the low part is always non-negative, i.e. formula (5) in is always greater than or equal to 0, which makes half of the resulting bit stream fixed to 1. To minimize the overhead, formula (8) can be further simplified. Let be the characteristic function that

[0103] (9).

[0104] Substituting into formula (5) gives

[0105] (10) ;

[0106] Therefore, if the bit stream representation of is then

[0107] (11).

[0108] Compared with the simplified version, the calculation accuracy is improved by about 7dB at the same bit stream length.

[0109] In some embodiments, the method further comprises: if the filter coefficients are fixed in one or more groups, storing the filter coefficients in a memory.

[0110] Embodiment 2: provides a FIR filter based on probability and fixed-point hybrid calculation, as shown in Figure 7 , comprising a fixed-point FIR module, a preprocessing module, a probability FIR module and a filter merging module, as shown in Figure 8 , the probability FIR module comprises a parallel bit stream generation module, a bit stream calculation module and a backward conversion module; wherein the fixed-point calculation module is used to perform fixed-point multiplication and accumulation operation on the high part of the digital signal and the filter coefficients to obtain a high calculation result; the preprocessing module is used to preprocess the filter coefficients to generate a random symbol of the selection end of the multiplexer; the parallel bit stream generation module is used to convert the low part of the digital signal into a parallel probability bit stream; the bit stream calculation module is used to control the selection of the parallel probability bit stream to perform probability multiplication and accumulation operation according to the random symbol of the selection end to obtain a bipolar probability bit; the backward conversion module is used to perform backward conversion on the bipolar probability bit to obtain a low calculation result; the filter merging module adds the high calculation result and the low fixed-point result to output the FIR filtering result.

[0111] In some embodiments, the parallel bit stream generation module includes: a thermometer encoding unit, which is used to generate a bit stream with a numerical value consistent with that generated by comparing the low-discrepancy sequence through thermometer encoding; a line selection unit, which is used to exchange the order of the bit stream without overhead through line selection to generate a parallel probability bit stream; and a sign adjustment unit, which is used to multiply the positive and negative signs of the random symbol with the corresponding bit stream in the parallel probability bit stream.

[0112] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0113] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0114] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0115] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0116] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An FIR filtering method based on probability and fixed-point hybrid calculation, characterized in that: The following steps are involved: Perform fixed-point multiplication and accumulation operations on the high-order part of the digital signal and the filter coefficient to obtain the high-order calculation result; Preprocessing the filter coefficients to generate random symbols for the selection end of the multiplexer; Convert the low-order part of the digital signal into a parallel probability bit stream; According to the random symbol of the selection end, the parallel probability bit stream is controlled to be selected to perform probability multiplication and accumulation operation to obtain a bipolar probability bit; Backward conversion is performed on the bipolar probability bits to obtain a low-bit calculation result; The high-order calculation result is added to the low-order fixed-point result, and the FIR filtering result is output.

2. The FIR filtering method based on probability and fixed-point hybrid calculation according to claim 1, characterized in that: The random symbol of the selection end is generated by serial processing, including: Calculating the absolute values ​​of the filter coefficients one by one, accumulating them to obtain a total, and calculating the normalized probability value of each filter coefficient; Comparing the probability value with the corresponding bit of the first sequence bit by bit to generate a thermometer code; The bits at the same position in the thermometer code are added together to generate a random symbol stream at the selected end.

3. The FIR filtering method based on probability and fixed-point hybrid calculation according to claim 1, characterized in that: The random symbols of the selection end are generated by parallel processing, including: Simultaneously calculating the absolute values ​​of all the filter coefficients, obtaining a cumulative sum of the absolute values ​​through parallel processing, and calculating a normalized probability value for each of the filter coefficients; All normalized probability values ​​are compared with corresponding bits of the first sequence at the same time, and the addition operation is replaced by thermometer decoding to generate a random symbol stream at the selection end.

4. The FIR filtering method based on probability and fixed-point hybrid calculation according to claim 2 or 3, characterized in that: If the first sequence is an MCAS sequence, the input end of the multiplexer adopts a low-variance sequence.

5. The FIR filtering method based on probability and fixed-point hybrid calculation according to claim 2 or 3, characterized in that: If the first sequence is a low-variance sequence, the input end of the multiplexer adopts the MCAS sequence.

6. The FIR filtering method based on probability and fixed-point hybrid calculation according to claim 3, characterized in that: If the first sequence is a low-divergence sequence, then: generating a bit stream consistent with the value generated by comparison with the low-discrepancy sequence through thermometer coding; The order of the bit streams is exchanged without overhead by selecting lines to generate the parallel probability bit streams.

7. The FIR filtering method based on probability and fixed-point hybrid calculation according to claim 1, characterized in that: The method further includes: multiplying the positive and negative signs of the random symbols by the corresponding bit streams in the parallel probability bit streams; Normalize the absolute value of the element corresponding to the selected end; A probability multiplication and accumulation operation is performed based on the multiplication and normalization results to obtain the bipolar probability bit.

8. The FIR filtering method based on probability and fixed-point hybrid calculation according to claim 1, characterized in that: The method further includes: If the filter coefficients are fixed in one or more groups, the filter coefficients are stored in a memory.

9. An FIR filter based on a hybrid calculation of probability and fixed point, characterized in that: include: Fixed-point FIR module, pre-processing module, probability FIR module and filtering merging module, the probability FIR module includes a parallel bit stream generation module, a bit stream calculation module, and a backward conversion module; wherein, The fixed-point calculation module is used to perform fixed-point multiplication and accumulation operations on the high-order part of the digital signal and the filter coefficient to obtain a high-order calculation result; The pre-processing module is used to pre-process the filter coefficients to generate random symbols for the selection end of the multiplexer; The parallel bit stream generation module is used to convert the low-order part of the digital signal into a parallel probability bit stream; The bit stream calculation module is used to control the selection of the parallel probability bit stream to perform probability multiplication and accumulation operations according to the random symbol of the selection end to obtain bipolar probability bits; The backward conversion module is used to perform backward conversion on the bipolar probability bits to obtain a low-bit calculation result; The filtering and merging module adds the high-order calculation result and the low-order fixed-point result, and outputs an FIR filtering result.

10. The FIR filter based on probability and fixed-point hybrid calculation according to claim 9, characterized in that: The parallel bit stream generation module includes: a thermometer encoding unit for generating, by thermometer encoding, a bit stream having a value consistent with that generated by comparison with the low-discrepancy sequence; A line selection unit, configured to exchange the order of the bit streams without overhead by line selection to generate the parallel probability bit streams; And / or, a sign adjustment unit, configured to multiply the positive and negative signs of the random sign with the corresponding bit stream in the parallel probability bit stream.

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