Packing method and system for improving cross-DIE transmission efficiency and storage medium

Abstract

The invention relates to a packing method and system for improving cross-DIE transmission efficiency and a storage medium, and the method comprises the steps: selecting an assembly line through an arbiter according to a preset assembly line arbitration level; fIFO queue depths of items contained in a request transmission channel, a response transmission channel and a data transmission channel are read, the number of available items is recorded through a first counter, and the number of sent items is recorded through a second counter; according to the values of the first counter and the second counter, determining an optimal format for entry packaging; reading entries from different FIFO queues according to the optimal format and writing the entries into slots corresponding to the frame segments; and transmitting the packed frame segments to a packing transmitter, and further transmitting the packed frame segments to a physical layer of the assembly line so as to complete packing transmission. According to the method, assembly line two-way fairness, multi-channel queuing fairness, channel flow control and tradeoff between the packing utilization rate and delay are achieved from packing logic, and the high-frequency time sequence requirement of the DIE assembly line is met.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of data transmission, and particularly relates to a packet assembly method and system for improving cross-DIE transmission efficiency and a storage medium. BACKGROUND

[0002] CXL (Compute Express Link) is an open standard high-speed interconnection protocol, which provides cache-consistent low-latency high-bandwidth communication between a host processor and an additional device (such as a memory expansion card, an accelerator, etc.) by inheriting the physical layer of PCIe (Peripheral Component Interconnect Express). Among them, the CXL.cache protocol stack provides cache consistency load and storage semantics between the host and the device, which is used to access the remote cache or device memory.

[0003] In the CXL.cache operation, the transaction layer needs to generate a variety of variable-size data packets (such as cache line requests, data-containing responses, etc.), and divide or aggregate them into fixed-length frame segments (Flit) in the Link Layer for transmission. In CXL 1.x and CXL 2.0 versions, each frame segment is 528 bits (66 bytes) long, including several 16-byte slots and 2-byte CRC checks. Generally, each 528-bit frame segment can accommodate up to 4 16B slots, and if waiting for exactly 4 to be sent frame segments or data to send a complete frame segment, the bandwidth utilization can be maximized, but this will increase the delay; if a partially filled frame segment is sent immediately, the bandwidth will be wasted and the effective throughput will be reduced. In addition, the frame segment packet assembly of CXL.cache also needs to balance the traffic of the three channels of request (REQ), response (RESP) and data (DATA) in one link direction, and realize the transmission fairness in the host-to-device and device-to-host two directions.

[0004] Related technologies have a variety of packet assembly schemes, but these methods often rely on static priority enumeration or simple timeout degradation strategies, and do not quantify the difference in the number of messages sent of different message types as a unified dynamic ranking measure. In general, the existing packet assembly implementation scheme does not completely realize the two-way fairness and multi-channel balance in one system, and there are still many details that need to be improved. SUMMARY

[0005] The application provides a packet assembly method and system for improving cross-DIE transmission efficiency and a storage medium, which aims to solve the technical problem that the existing packet assembly scheme is difficult to realize the pipeline two-way fair transmission and multi-data channel traffic balance.

[0006] To solve the above technical problems, in a first aspect, the application provides a packet assembly method for improving cross-DIE transmission efficiency, comprising the following steps: S101. Selecting a pipeline that needs to be packet assembled and transmitted by an arbitrator according to a preset pipeline arbitration level to start packet assembly, wherein the preset pipeline arbitration level is used to determine the priority of different pipelines and the packet assembly manner, and the pipeline includes a first direction pipeline from a host to a device and a second direction pipeline from the device to the host; S102. Reading the FIFO queue depth of the entries contained in the request, response and data three transmission channels respectively, wherein the number of available entries of each FIFO queue is recorded by a first counter, and the number of entries sent by each transmission channel is recorded by a second counter; S103. Determining the optimal format for packet assembling the entries of different transmission channels according to the values of the first counter and the second counter corresponding to each of the request, response and data three transmission channels; S104. Reading the entries from the FIFO queue corresponding to each of the different transmission channels according to the optimal format and writing the entries into the slot corresponding to the frame segment, and determining whether the packet assembly of the frame segment is completed according to the preset pipeline arbitration level; S105. Transmitting the frame segment that has completed packet assembly to a packet assembly transmitter, and further sending the completed frame segment to the physical layer of the pipeline through the packet assembly transmitter to complete packet assembly transmission.

[0007] Further, the preset pipeline arbitration level in step S101 is specifically: Prioritizing the packet assembly transmission of the first direction pipeline; or, Prioritizing the packet assembly transmission of the second direction pipeline; or, Selecting the first direction pipeline or the second direction pipeline according to the transmission demand to perform packet assembly transmission in a round-robin manner; or, Idle.

[0008] Further, step S103 includes the following sub-steps: S1031. Determining a plurality of preset formats for packet assembling the entries contained in the request, response and data three transmission channels in different quantities; S1032. Based on the values of the first counter corresponding to each of the request, response and data three transmission channels, distinguishing the first type of preset format that completely meets the entry number requirement and the second type of preset format that partially meets the entry number requirement from the preset format; S1033、based on the values of the second counters corresponding to the three transmission channels of request, response and data, calculate the first weight value after the first packet is packaged according to the preset format, select the preset format corresponding to the maximum value of the first weight value as the optimal format, define the first weight value as M1, which satisfies the following relationship: M1 = (C_lowest - C_mid) + (C_lowest - C_highest); C_lowest is the minimum value of the second counter corresponding to the three transmission channels of request, response and data after the first packet is packaged according to the preset format, C_mid is the value of the second counter corresponding to the three transmission channels of request, response and data after the first packet is packaged according to the preset format, C_highest is the maximum value of the second counter corresponding to the three transmission channels of request, response and data after the first packet is packaged according to the preset format; Wherein, if the first type of preset format is not empty, the optimal format is selected from the first type of preset format; otherwise, the optimal format is selected from the second type of preset format.

[0009] Further, if the first weight value M1 corresponding to multiple preset formats is maximum, based on the values of the second counters corresponding to the three transmission channels of request, response and data, calculate the second weight value after the first packet is packaged according to the preset format, select the preset format corresponding to the maximum value of the second weight value as the optimal format, define the second weight value as M2, which satisfies the following relationship: M2 = C_mid - C_highest.

[0010] Further, if the current preset pipeline arbitration level is not idle, step S104 includes the following substeps: S1041, for the pipeline currently preferentially performing packet transmission, judge whether the first type of preset format is not empty, if yes, execute step S1042; if no, execute step S1043: S1042, update the packet counter, make its value plus 1, read the entries from the FIFO queue corresponding to the different transmission channels according to the optimal format, write the read entries into the empty slot positions of the frame segment in turn, and at the same time make the value of the preset timeout loop control threshold minus 1; if the four slot positions of the frame segment are all completed, execute step S1046, otherwise return to step S1041; S1043, judge whether the second type of preset format is not empty, if yes, execute step S1044; if no, execute step S1045; S1044, updating the group packet counter, reading out entries from the FIFO queue corresponding to different transmission channels according to the optimal format, writing the read out entries into the empty slot positions corresponding to the frame segment in sequence, and decreasing the preset timeout cycle control threshold value by 1 at the same time; if all the four slot positions of the frame segment complete entry writing, step S1046 is executed, otherwise step S1045 is executed; S1045, judging whether the value of the group packet counter is less than the preset timeout cycle control threshold value, if yes, returning to step S1041; if no, step S1046 is executed; S1046, if the slot position of the frame segment that currently completes entry writing is the first one, modifying the preset pipeline arbitration level to select the first direction pipeline or the second direction pipeline to perform group packet transmission in a polling manner according to transmission requirements; if the slot position of the frame segment that currently completes entry writing is the second one or the third one, skipping the slot position of the frame segment that currently needs to perform group packet, and completing group packet of the frame segment; if the slot position of the frame segment that currently completes entry writing is the fourth one, completing group packet of the frame segment.

[0011] Further, the group packet method for improving cross-DIE transmission efficiency further comprises the steps of: S106, issuing an arbitration signal for modifying the preset pipeline arbitration level through the arbitrator.

[0012] Further, for the pipeline that currently does not perform group packet transmission, the group packet method for improving cross-DIE transmission efficiency further comprises the steps of: S201, judging whether the first preset format is empty, if yes, step S202 is executed; if no, step S203 is executed; S202, updating the group packet counter, reading out entries from the FIFO queue corresponding to different transmission channels according to the optimal format, writing the read out entries into the empty slot positions corresponding to the frame segment in sequence, and updating the group packet counter at the same time; unless all the four slot positions of the frame segment complete entry writing, returning to step S201; S203, if the slot position of the frame segment that currently completes entry writing is the fourth one, completing group packet of the frame segment; if no, returning to step S201.

[0013] In a second aspect, the application further provides a group packet system for improving cross-DIE transmission efficiency, comprising: An arbitration module is configured to select a pipeline for packetization by an arbitrator according to a preset pipeline arbitration level to start packetization, the preset pipeline arbitration level is used to determine the priority of different pipelines and the packetization manner, and the pipeline includes a first direction pipeline from a host to a device and a second direction pipeline from the device to the host; A reading module is configured to read the FIFO queue depth of entries contained in each of a request, a response and data three transmission channels respectively, wherein the number of available entries of each FIFO queue is recorded by a first counter, and the number of entries sent of each transmission channel is recorded by a second counter; A format module is configured to determine the optimal format for packetizing entries of different transmission channels according to the values of the first counter and the second counter corresponding to each of the three transmission channels; A packetization module is configured to read entries from the FIFO queue corresponding to each of the transmission channels and write the entries into the slot corresponding to a frame segment according to the optimal format, and determine whether the packetization of the frame segment is completed according to the preset pipeline arbitration level; A transmission module is configured to transmit the frame segment completed packetization to a packetization transmitter, and further transmit the completed frame segment to the physical layer of the pipeline through the packetization transmitter to complete packetization transmission.

[0014] In a third aspect, the present application further provides a computer device, comprising a memory, a processor, and a packetization program for improving cross-DIE transmission efficiency stored in the memory and executable on the processor, wherein the processor implements the steps of the packetization method for improving cross-DIE transmission efficiency as described in any one of the above embodiments when executing the packetization program for improving cross-DIE transmission efficiency.

[0015] In a fourth aspect, the present application further provides a storage medium, wherein the storage medium stores a packetization program for improving cross-DIE transmission efficiency, and the processor implements the steps of the packetization method for improving cross-DIE transmission efficiency as described in any one of the above embodiments when executing the packetization program for improving cross-DIE transmission efficiency.

[0016] The present application has the advantages that the packetization method for improving cross-DIE transmission efficiency based on the CXL.cache protocol stack realizes pipeline bidirectional fairness, multi-channel queuing fairness, channel flow control, and the trade-off between packetization utilization rate and delay from the perspective of packetization logic, and meets the high-frequency timing requirements of the DIE pipeline. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1is a step flow diagram of a packet assembly method for improving cross-DIE transmission efficiency provided by an embodiment of the present application. Figure 2 is a complete packet assembly logic diagram of a priority pipeline provided by an embodiment of the present application. Figure 3 is a partial packet assembly logic diagram of a priority pipeline provided by an embodiment of the present application. Figure 4 is an empty packet assembly logic diagram of a priority pipeline provided by an embodiment of the present application. Figure 5 is a complete packet assembly logic diagram of a non-priority pipeline provided by an embodiment of the present application. Figure 6 is a structure diagram of a packet assembly system for improving cross-DIE transmission efficiency provided by an embodiment of the present application. Figure 7 is a structure diagram of a computer device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0018] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0019] Please refer to Figure 1 , Figure 1 is a step flow diagram of a packet assembly method for improving cross-DIE transmission efficiency provided by an embodiment of the present application. The packet assembly method for improving cross-DIE transmission efficiency comprises the following steps: S101, selecting a pipeline that needs to be packet assembled and transmitted by an arbitrator according to a preset pipeline arbitration level to start packet assembly, wherein the preset pipeline arbitration level is used to determine the priority of different pipelines and the way of packet assembly, and the pipeline includes a first direction pipeline from a host to a device and a second direction pipeline from the device to the host.

[0020] As described in the background, the CXL.cache protocol stack provides cache consistency load and storage semantics between the host and the device at both ends of the DIE (silicon-based core) for accessing the remote cache or device memory. The CXL protocol is full duplex, and its pipeline includes the Host to Device (H2D) direction, which can send cache requests at the same time, and the Device to Host (D2H) direction, which can simultaneously transmit cache responses and data.

[0021] The preset pipeline arbitration level in step S101 comprises: Prioritize the first-direction pipeline packet transmission (H2D); or, Prioritize the second direction pipeline packet transmission (D2H); or, Selecting the first direction pipeline or the second direction pipeline to perform packet transmission in a round-robin manner according to transmission requirements (BOTH); or Idle (NONE).

[0022] It can be understood that the preset pipeline arbitration level involved in the embodiment of the present invention, "giving priority to the packet transmission of the first-direction pipeline", means that when the pipelines in both directions have packet transmission requirements, the packet transmission of one of them is given priority. If the priority party does not have a packet transmission requirement at this time, the link data of the pipeline is in an available state, and the packet transmission of the non-priority party can be carried out. The simple idle state means that there is no specific arbitration level. When any pipeline has a packet transmission requirement, the right to use the link is obtained by preemption. In the embodiment of the present invention, the arbitrator adjusts the preset pipeline arbitration level once every packet transmission cycle, but the preset pipeline arbitration level is only a macro strategy, and the specific packet transmission and transmission scheme needs to be implemented according to the subsequent methods of the embodiment of the present invention.

[0023] S102. Read the FIFO queue depths of the entries contained in each of the three transmission channels for request, response, and data that need to be packaged, respectively. For each of the FIFO queues, the number of available entries is recorded using a first counter, and for each of the transmission channels, the number of entries that have been sent is recorded using a second counter.

[0024] This embodiment of the present invention defines three key transmission channels within the CXL.cache protocol stack: request (Req), response (Rsp), and data (Data). Without a fair queuing strategy for these channels, a continuous flow of data will fill up the packetization frame segments, significantly delaying the delivery of responses and disrupting cache coherence timing. Conversely, prioritizing only responses or requests will waste significant bandwidth. Therefore, it is necessary to determine which transmission channel is lagging behind at the current stage and prioritize its servicing (packetization) to achieve dynamic traffic balancing among the three channels.

[0025] This embodiment of the present invention designs a credit mechanism based on FIFO (first-in-first-out) queues. Specifically, independent, credit-based FIFO queues are maintained for the request, response, and data transmission channels. These are defined as the Req FIFO, Rsp FIFO, and Data-Header FIFO, respectively. In practice, each Req FIFO entry stores a 79-bit cached request, each Rsp FIFO entry stores a 20-bit cached response, and each Data-Header FIFO entry stores 17-bit data.

[0026] Each of the FIFO queues records the number of available entries through a first counter. In an embodiment of the present invention, the first counters of the FIFO queues corresponding to the three transmission channels of request, response and data are respectively ReqCnt, RspCnt and DataCnt, and the second counters corresponding to the three transmission channels of request, response and data are respectively ReqPrio, RspPrio and DataPrio.

[0027] In particular, the credit-based FIFO queue in the embodiment of the present invention has a credit return mechanism. After the host or device at one end of the DIE processes the request of the corresponding transmission channel, it will add credit points to the FIFO queue of the corresponding transmission channel of the host or device at the other end through packet grouping to increase the number of available entries in the FIFO queue.

[0028] S103: Determine an optimal format for grouping entries of different transmission channels according to the values ​​of the first counter and the second counter corresponding to the three transmission channels of request, response, and data.

[0029] Step S103 includes the following sub-steps: S1031. Determine a plurality of preset formats for packaging different numbers of items contained in three transmission channels: request, response, and data.

[0030] Specifically, the CXL.cache packet size is fixed (528 bits, consisting of four 16-byte slots). In this embodiment of the present invention, six preset formats are designed based on the sizes of entries contained in the three transmission channels: request, response, and data. These formats package a specific number of request, response, and data entries, respectively.

[0031] Table 1 Preset format example table

[0032] For example, the default format for H0 is to group 1 entry from the data with 2 entries from the response.

[0033] S1032、based on the value of the first counter corresponding to each of the request, response and data transmission channels, distinguishing from the preset format a first type of preset format that completely meets the entry number requirement and a second type of preset format that partially meets the entry number requirement.

[0034] As shown in Table 1 above, each preset format has a certain number of entries for the request, response and data transmission channels, for example, the preset format of H2 requires 4 entries from data and 1 entry from response, if the data transmission channel has only 3 entries at this time, then the preset format of H2 at this time is not met.

[0035] S1033、based on the value of the second counter corresponding to each of the request, response and data transmission channels, calculating a first weight value after packeting according to the preset format, selecting the preset format corresponding to the maximum value of the first weight value as the optimal format, defining the first weight value as M1, which satisfies the following relationship: M1 = (C_lowest - C_mid) + (C_lowest - C_highest); C_lowest is the minimum value of the second counter corresponding to each of the request, response and data transmission channels after packeting according to the preset format, C_mid is a value in the middle of the second counter corresponding to each of the request, response and data transmission channels after packeting according to the preset format, and C_highest is the maximum value of the second counter corresponding to each of the request, response and data transmission channels after packeting according to the preset format. Among them, if the first type of preset format is not empty, the optimal format is selected from the first type of preset format; otherwise, the optimal format is selected from the second type of preset format.

[0036] If the first weight value M1 corresponding to multiple preset formats is the maximum value, based on the value of the second counter corresponding to each of the request, response and data transmission channels, a second weight value after packeting according to the preset format is calculated, and the preset format corresponding to the maximum value of the second weight value is selected as the optimal format, and the second weight value is defined as M2, which satisfies the following relationship: M2 = C_mid - C_highest.

[0037] Based on the ranking strategy described in the above embodiment, this embodiment of the present invention ensures that the format selected for each packet grouping consistently minimizes the largest gap between different channels, thereby narrowing the gap during the next packet grouping. During implementation, after comparing the total number of packets sent from the three different channels, the impact of different packet grouping formats on the ranking of the three current channel totals is calculated, resulting in thirteen different channel total ranking orders, as shown in Table 2.

[0038] Table 2 Example table of preset format priority ranking

[0039] As in the third case of Table 2, the second counter value of the response channel is equal to the second counter value of the request channel and is greater than the second counter value of the data channel. In this case, according to the optimal format selection method of the embodiment of the present invention, the preset format of G3 will be selected as the optimal format.

[0040] S104 , reading entries from the FIFO queues corresponding to the different transmission channels according to the optimal format and writing them into slots corresponding to frame segments, and determining whether the frame segments are packaged according to the preset pipeline arbitration level.

[0041] Since the embodiment of the present invention designs two pipelines in different directions and needs to ensure the flow balance between the two pipelines, the packet assembly process on the pipeline will have different timeout and degradation logic according to the preset pipeline arbitration level.

[0042] Specifically, if the current preset pipeline arbitration level is non-idle, step S104 includes the following sub-steps: S1041: For the pipeline currently prioritizing packet grouping and transmission, determine whether the first type of preset format is not empty. If so, execute step S1042; if not, execute step S1043: S1042: Update the packet group counter, increment its value by 1, read entries from the FIFO queues corresponding to the different transmission channels according to the optimal format, write the read entries into the empty slots corresponding to the frame segments in sequence, and simultaneously decrement the value of the preset timeout cycle control threshold by 1; if entries have been written into all four slots of the frame segments, execute step S1046; otherwise, return to step S1041; S1043: Determine whether the second type of preset format is not empty. If so, execute step S1044; if not, execute step S1045; S1044, update the group packet counter, make its value plus 1, read out entries from the FIFO queue corresponding to the different transmission channel according to the optimal format, write the read out entries into the empty slot positions corresponding to the frame segment in turn, and make the value of the preset timeout cycle control threshold minus 1 at the same time; if the four slot positions of the frame segment are all completed for entry writing, execute step S1046, otherwise execute step S1045; S1045, judge whether the value of the group packet counter is less than the preset timeout cycle control threshold, if yes, return to step S1041; if no, execute step S1046; S1046, if the slot position of the frame segment which is currently completed for entry writing is the first one, modify the preset pipeline arbitration level to select the first direction pipeline or the second direction pipeline according to the transmission requirement to perform group packet transmission in a polling manner; if the slot position of the frame segment which is currently completed for entry writing is the second one or the third one, skip the slot position of the frame segment which currently needs to perform group packet, and complete the group packet of the frame segment; if the slot position of the frame segment which is currently completed for entry writing is the fourth one, complete the group packet of the frame segment.

[0043] In the embodiment of the application, the case of group packet transmission by the first direction pipeline is described, at this time, the preset pipeline arbitration level is to preferentially perform group packet transmission (D2H) by the first direction pipeline, or to select the first direction pipeline or the second direction pipeline according to the transmission requirement to perform group packet transmission (BOTH) in a polling manner, and polling is performed by the first direction pipeline. Since the arbitration level is not idle at this time, the first direction pipeline needs to complete the group packet as soon as possible, and therefore it is not required to perform group packet in a complete format. It can be understood that group packet in a complete format refers to that data is written into the four slot positions of the frame segment. In step S1041, it is judged whether writing of slot position data in the first type of preset format can be performed before group packet, and the purpose is to preferentially perform group packet in a complete format, so that as much data as possible can be written into the slot position, and correspondingly, step S1042 writes slot position data in the first type of preset format, so as to realize data writing in a full slot position.

[0044] Figure 2 The case of group packet in the preset format of G2 as the optimal format is specifically shown in the figure, C1 stage represents the selection process of the preset format, wherein Available=1 represents that the first type of preset format is taken as the optimal format, and NonEmpty=1 represents that the second type of preset format is taken as the optimal format, and C2 stage represents the transmission process of group packet. Further, as Figure 3As shown, in step S1043, whether the slot data can be written in the second type of preset format is determined before packaging. This is because there is no available complete format packaging solution in step S1041 (or during the loop process). Compared with the first type of preset format, the items required by the second type of preset format are not fully satisfied. However, when the first pipeline is prioritized, the purpose is to make the data that can be written to the slot as much as possible and to complete the packaging quickly. Figure 2 The difference between the illustrated process and the example is that step S1044 writes the slot data in accordance with the second type of preset format. Although the slot has data written therein, the data is not complete.

[0045] like Figure 4 As shown, in step S1045, determining whether the value of the packet assembly counter is less than a preset timeout loop control threshold is used to determine whether the current packet assembly process has timed out. This design is intended because step S104 performs packet assembly and transmission on a specific pipeline. Even so, the method designed in this embodiment of the present invention does not want to continue waiting for the current pipeline to complete packet assembly when there is no data to be assembled. Therefore, if the preset timeout loop control threshold has been exceeded at this time, if no data entries have been written to certain slots, as described in step S1046, the preset pipeline arbitration level can be modified in a certain manner to poll another pipeline, or the slots without written entries can be directly cleared to complete packet assembly, thereby terminating the packet assembly process of the current pipeline early. Of course, as described in the steps of the above embodiment, if entries are written to all four slots of the frame segment, complete frame segment assembly can be performed without triggering the timeout loop control, achieving the highest packet assembly bandwidth utilization.

[0046] Preferably, in the embodiment of the present invention, in order to reduce the waiting time of the pipeline as much as possible, after determining in step S1045 that the value of the packet group counter exceeds the preset timeout cycle control threshold, the value of the preset timeout cycle control threshold can be reduced (e.g., Figure 3 , halve the preset timeout loop control threshold value).

[0047] On the other hand, as described in the above embodiment, when the preset pipeline arbitration level is not idle, only one of the pipelines is packetized and transmitted. The pipeline currently not performing packetization and transmission can first perform packetization without timeout restrictions and quickly transmit its completed frame segments after obtaining packetization and transmission permission. Specifically, for the pipeline currently not performing packetization and transmission, the packetization method for improving cross-DIE transmission efficiency further includes the following steps: S201, determine whether the first type of preset format is not empty, if so, execute step S202; if not, execute step S203; S202: Update the packet group counter to increase its value by 1, read entries from the FIFO queues corresponding to the different transmission channels according to the optimal format, write the read entries into the empty slots corresponding to the frame segments in sequence, and update the packet group counter to increase its value by 1. Unless entries are written into all four slots of the frame segments, return to step S201. S203: If the slot of the frame segment to which the entry is currently written is the fourth, then the packing of the frame segment is completed; if not, return to step S201.

[0048] Please refer to Figure 5 The embodiment of the present invention is still described in terms of the first-direction pipeline packaging process, which is different from Figures 2 to 4 , the current pipeline arbitration level is second-direction pipeline priority (H2D) or idle and preempted by the second pipeline. Unlike step S104, when the pipeline that does not prioritize packet transmission performs packet assembly, it is not subject to timeout constraints. To maximize packet assembly bandwidth utilization, it no longer writes entries based on the second type of preset format, but only writes relevant entries based on the first type of preset format. This allows it to assemble frame fragments containing complete entry data in all four slots within an unlimited timeframe. It is important to note that this packet assembly process still incorporates a packet assembly counter. This is intended to ensure that if the pipeline can obtain an arbitration level for priority packet transmission or obtain an arbitration level through polling, it can quickly execute the packet assembly mechanism of step S104 using the existing packet assembly counter.

[0049] S105: Transmit the packetized frame segments to a packet assembling transmitter, and further transmit the completed frame segments to a physical layer of the pipeline through the packet assembling transmitter to complete the packet assembling transmission.

[0050] It can be understood that the packet assembly method described in the embodiment of the present invention is consistent with the DIE design and the CXL.cache protocol stack. The arbitrator, packet assembly transmitter, and units for reading and updating the FIFO queue can all be set in the DIE, and the corresponding method logic can be executed through the packet assembly method described in the embodiment of the present invention.

[0051] The packet assembly method for improving cross-DIE transmission efficiency further comprises the steps of: S106: Sending, through the arbitrator, an arbitration signal for modifying the preset pipeline arbitration level.

[0052] In the embodiment of the present application, the arbitration signal is mainly used to modify the preset pipeline arbitration level, such as changing the pipeline for group packet transmission to another one, or modifying to a polling state, which can be set according to actual needs. Wherein, the arbitration signal is sent by the arbitrator, which means that the host and device on both sides of the DIE can receive the arbitration signal, such as shown in Figures 2 to 5 The arbitration signal is also used for the host and device to update the values of the first counter and the second counter corresponding to the three transmission channels of request, response and data respectively, so as to realize the update of the credit mechanism of the FIFO queue.

[0053] It can be understood that the preset format and the priority ranking as shown in Table 1 and Table 2 are a usable numerical rule adopted in the implementation process of the embodiment of the present application, based on which the matching degree of the embodiment of the present application with the existing CXL.cache protocol stack on a specific data size can be clearly embodied, and the efficiency of CXL.cache group packet is maximized based on the method of the embodiment of the present application, but this does not limit the scope of protection of the present application.

[0054] The present application achieves the beneficial effect of providing a group packet method for improving the cross-DIE transmission efficiency based on the CXL.cache protocol stack, which realizes the bidirectional fairness of the pipeline, the fairness of the multi-channel queuing, the channel flow control, and the trade-off between the utilization rate and the delay of the group packet from the group packet logic, and meets the high frequency timing requirements of the DIE pipeline.

[0055] The embodiment of the present application also provides a group packet system 300 for improving the cross-DIE transmission efficiency, please refer to Figure 6 , Figure 6 is a structure diagram of the group packet system for improving the cross-DIE transmission efficiency provided by the embodiment of the present application, which comprises: An arbitration module 301 is used to select the pipeline that needs to be group packet transmission by the arbitrator according to the preset pipeline arbitration level to start group packet, the preset pipeline arbitration level is used to determine the priority of different pipelines and the way of group packet, the pipeline includes the first direction pipeline from the host to the device and the second direction pipeline from the device to the host; A reading module 302 is used to read the FIFO queue depth of the entries contained in the request, response and data three transmission channels respectively, wherein, the number of available entries of each FIFO queue is recorded by the first counter, and the number of entries sent by each transmission channel is recorded by the second counter; A format module 303 is used to determine the optimal format for grouping the entries of different transmission channels according to the values of the first counter and the second counter corresponding to the three transmission channels of request, response and data respectively. The packet assembling module 304 is configured to read entries from the FIFO queues corresponding to different transmission channels according to the optimal format and write the entries into corresponding slot positions of a frame segment, and determine whether packet assembling of the frame segment is completed according to the preset pipeline arbitration level. The transmission module 305 is configured to transmit the frame segment after packet assembling to a packet assembler, and further transmit the completed frame segment to a physical layer of the pipeline through the packet assembler to complete packet transmission.

[0056] The packet assembling system 300 for improving cross-DIE transmission efficiency can implement the steps in the packet assembling method for improving cross-DIE transmission efficiency in the above embodiments, and achieve the same technical effects. For details, refer to the description in the above embodiments, which will not be repeated here.

[0057] The embodiment of the present application further provides a computer device, please refer to Figure 7 , Figure 7 is a structural schematic diagram of the computer device provided by the embodiment of the present application, the computer device 400 comprises a memory 402, a processor 401 and a packet assembling program for improving cross-DIE transmission efficiency stored in the memory 402 and capable of running on the processor 401.

[0058] The processor 401 invokes the packet assembling program for improving cross-DIE transmission efficiency stored in the memory 402, and executes the steps in the packet assembling method for improving cross-DIE transmission efficiency provided by the embodiment of the present application, please combine Figure 1 , specifically comprising the following steps: S101, selecting a pipeline that needs to be packet assembled and transmitted by an arbitrator according to a preset pipeline arbitration level to start packet assembling, the preset pipeline arbitration level is used to determine the priority of different pipelines and the packet assembling manner, the pipeline includes a first direction pipeline from a host to a device, and a second direction pipeline from a device to a host.

[0059] The preset pipeline arbitration level in step S101 is specifically: prioritizing packet assembling transmission of the first direction pipeline; or, prioritizing packet assembling transmission of the second direction pipeline; or, selecting the first direction pipeline or the second direction pipeline according to transmission requirements to perform packet assembling transmission in a polling manner; or, idle.

[0060] S102, read the FIFO queue depth of the items contained in the request, response and data three transmission channels respectively, wherein the number of available items of each FIFO queue is recorded by a first counter, and the number of items sent by each transmission channel is recorded by a second counter.

[0061] S103, determine the optimal format for grouping the items of different transmission channels according to the values of the first counter and the second counter corresponding to each of the request, response and data three transmission channels.

[0062] Step S103 includes the following sub-steps: S1031, determine a plurality of preset formats for grouping the items contained in the request, response and data three transmission channels with different quantities; S1032, based on the value of the first counter corresponding to each of the request, response and data three transmission channels, distinguish from the preset formats a first type of preset format that completely meets the item number requirement and a second type of preset format that partially meets the item number requirement; S1033, based on the value of the second counter corresponding to each of the request, response and data three transmission channels, calculate the first weight value after grouping according to the preset format, select the preset format corresponding to the maximum value of the first weight value as the optimal format, and define the first weight value as M1, which satisfies the following relationship: M1 = (C_lowest - C_mid) + (C_lowest - C_highest); C_lowest is the minimum value of the second counter corresponding to each of the request, response and data three transmission channels after grouping according to the preset format, C_mid is the intermediate size value of the second counter corresponding to each of the request, response and data three transmission channels after grouping according to the preset format, and C_highest is the maximum value of the second counter corresponding to each of the request, response and data three transmission channels after grouping according to the preset format; Wherein, if the first type of preset format is not empty, the optimal format is selected from the first type of preset format; otherwise, the optimal format is selected from the second type of preset format.

[0063] If the first weight values ​​M1 corresponding to multiple preset formats are all the largest, then based on the values ​​of the second counters corresponding to the three transmission channels of request, response, and data, the second weight value after packetization according to the preset format is calculated, and the preset format corresponding to the largest second weight value is selected as the optimal format definition. The second weight value is M2, which satisfies the following relationship: M2 = C_mid - C_highest.

[0064] S104 , reading entries from the FIFO queues corresponding to the different transmission channels according to the optimal format and writing them into slots corresponding to frame segments, and determining whether the frame segments are packaged according to the preset pipeline arbitration level.

[0065] If the current preset pipeline arbitration level is non-idle, step S104 includes the following sub-steps: S1041: For the pipeline currently prioritizing packet grouping and transmission, determine whether the first type of preset format is not empty. If so, execute step S1042; if not, execute step S1043: S1042: Update the packet group counter, increment its value by 1, read entries from the FIFO queues corresponding to the different transmission channels according to the optimal format, write the read entries into the empty slots corresponding to the frame segments in sequence, and simultaneously decrement the value of the preset timeout cycle control threshold by 1; if entries have been written into all four slots of the frame segments, execute step S1046; otherwise, return to step S1041; S1043: Determine whether the second type of preset format is not empty. If so, execute step S1044; if not, execute step S1045; S1044: Update the packet group counter, increment its value by 1, read entries from the FIFO queues corresponding to the different transmission channels according to the optimal format, write the read entries into the empty slots corresponding to the frame segments in sequence, and simultaneously decrement the value of the preset timeout cycle control threshold by 1; if entries have been written into all four slots of the frame segments, execute step S1046; otherwise, execute step S1045; S1045: Determine whether the value of the packet group counter is less than a preset timeout cycle control threshold. If so, return to step S1041; if not, execute step S1046; S1046: If the slot of the frame segment to which the entry is currently written is the first slot, modify the preset pipeline arbitration level to select the first direction pipeline or the second direction pipeline to perform packet transmission in a round-robin manner according to transmission requirements; If the slot of the frame segment to which the current entry is written is the second or the third, the slot of the frame segment to which the current entry is written is skipped, and the packetization of the frame segment is completed. If the slot of the frame segment to which the current entry is written is the fourth, the packetization of the frame segment is completed.

[0066] For the pipeline that does not currently perform packetization transmission, the packetization method for improving the cross-DIE transmission efficiency further includes the steps of: S201, determining whether the first preset format is empty, if yes, performing step S202, and if no, performing step S203; S202, updating the packetization counter, reading out entries from the FIFO queue corresponding to the different transmission channels according to the optimal format, and writing the read out entries into the empty slots of the frame segment in sequence, and updating the packetization counter, unless all the four slots of the frame segment are completed entry writing, returning to step S201; S203, if the slot of the frame segment to which the current entry is written is the fourth, the packetization of the frame segment is completed, and if no, returning to step S201.

[0067] S105, transmitting the frame segment completed packetization to a packetization transmitter, and further transmitting the completed frame segment to the physical layer of the pipeline through the packetization transmitter to complete packetization transmission.

[0068] The packetization method for improving the cross-DIE transmission efficiency further includes the steps of: S106, issuing an arbitration signal for modifying the preset pipeline arbitration level through the arbitrator.

[0069] The computer device 400 provided by the embodiment of the present application can realize the steps in the packetization method for improving the cross-DIE transmission efficiency in the above-mentioned embodiment, and can realize the same technical effects, and the description in the above-mentioned embodiment is referred to herein.

[0070] The embodiment of the present application further provides a storage medium, and the storage medium stores a packetization program for improving the cross-DIE transmission efficiency, the packetization program for improving the cross-DIE transmission efficiency realizes each process and step in the packetization method for improving the cross-DIE transmission efficiency provided by the embodiment of the present application when executed by a processor, and can realize the same technical effects, and the description is not repeated herein to avoid repetition.

[0071] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by a packet assembling program for improving the cross-DIE transmission efficiency to instruct the relevant hardware (which can be a mobile phone, a computer, a server, an air conditioner, a network device, or the like) to complete, and the program can be stored in a computer readable storage medium. When the program is executed, the processes of the above-mentioned embodiment methods can be included. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM), a random access memory (RAM), or the like.

[0072] It should be noted that in this document, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusions, so that processes, methods, articles, or devices that include a series of elements not only include those elements, but also include other elements not explicitly listed, or include elements inherent to such processes, methods, articles, or devices. Without more limitations, the element defined by the statement "comprising a" does not exclude the presence of other identical elements in the process, method, article, or device that includes the element.

[0073] The embodiments of the present application are described above in conjunction with the drawings, and the disclosed are only the preferred embodiments of the present application, but the present application is not limited to the above-mentioned specific embodiments, and the above-mentioned specific embodiments are only illustrative, not restrictive. Those skilled in the art can make many equivalent changes in form without departing from the purpose of the present application and the scope protected by the claims, and all such changes are within the protection of the present application.

Claims

1. A packet grouping method for improving cross-DIE transmission efficiency, characterized in that: The following steps are involved: S101: An arbiter selects a pipeline for packet assembly and transmission according to a preset pipeline arbitration level to start packet assembly. The preset pipeline arbitration level is used to determine the priority of different pipelines and a packet assembly method. The pipelines include a first-direction pipeline from a host to a device and a second-direction pipeline from a device to a host. S102, respectively reading the FIFO queue depths of entries contained in the three transmission channels for request, response, and data that need to be packaged, wherein the number of available entries in each FIFO queue is recorded using a first counter, and the number of entries sent by each transmission channel is recorded using a second counter; S103: Determine an optimal format for grouping entries of different transmission channels according to the values ​​of the first counter and the second counter corresponding to the request, response, and data transmission channels, respectively; S104: Read entries from the FIFO queues corresponding to the different transmission channels according to the optimal format and write them into slots corresponding to frame segments, and determine whether the frame segments are packaged according to the preset pipeline arbitration level; S105: Transmit the packetized frame segments to a packet assembling transmitter, and further transmit the completed frame segments to a physical layer of the pipeline through the packet assembling transmitter to complete the packet assembling transmission.

2. The packet assembly method for improving cross-DIE transmission efficiency according to claim 1, characterized in that: The preset pipeline arbitration level in step S101 is specifically: Prioritize the packet transmission of the first direction pipeline; or, Prioritize the second direction pipeline packet transmission; or, Selecting the first direction pipeline or the second direction pipeline to perform packet transmission in a round-robin manner according to transmission requirements; or idle.

3. The packet assembly method for improving cross-DIE transmission efficiency according to claim 2, characterized in that: Step S103 includes the following sub-steps: S1031. Determine multiple preset formats for packaging different numbers of items contained in the three transmission channels of request, response, and data; S1032: Based on the values ​​of the first counters corresponding to the request, response, and data transmission channels, distinguish between a first type of preset format that fully meets the entry number requirement and a second type of preset format that partially meets the entry number requirement from the preset formats; S1033. Calculate a first weight value after packetization according to the preset format based on the values ​​of the second counters corresponding to the request, response, and data transmission channels, select the preset format corresponding to the maximum first weight value as the optimal format, and define the first weight value as M1, which satisfies the following relationship: M1 = (C_lowest - C_mid) + (C_lowest - C_highest); C_lowest is the minimum value of the second counter corresponding to each of the request, response, and data transmission channels after packet assembly is completed according to the preset format; C_mid is the middle value of the second counter corresponding to each of the request, response, and data transmission channels after packet assembly is completed according to the preset format; C_highest is the maximum value of the second counter corresponding to each of the request, response, and data transmission channels after packet assembly is completed according to the preset format; If the first type of preset formats is not empty, the optimal format is selected from the first type of preset formats; otherwise, the optimal format is selected from the second type of preset formats.

4. The packet assembly method for improving cross-DIE transmission efficiency according to claim 3, characterized in that: If the first weight values ​​M1 corresponding to multiple preset formats are all the largest, then based on the values ​​of the second counters corresponding to the three transmission channels of request, response, and data, the second weight value after packetization according to the preset format is calculated, and the preset format corresponding to the largest second weight value is selected as the optimal format. The second weight value is defined as M2, which satisfies the following relationship: M2 = C_mid - C_highest.

5. The packet assembly method for improving cross-DIE transmission efficiency according to claim 4, characterized in that: If the current preset pipeline arbitration level is non-idle, step S104 includes the following sub-steps: S1041: For the pipeline currently prioritizing packet grouping and transmission, determine whether the first type of preset format is not empty. If so, execute step S1042; if not, execute step S1043: S1042: Update the packet group counter, increment its value by 1, read entries from the FIFO queues corresponding to the different transmission channels according to the optimal format, write the read entries into the empty slots corresponding to the frame segments in sequence, and simultaneously decrement the value of the preset timeout cycle control threshold by 1; if entries have been written into all four slots of the frame segments, execute step S1046; otherwise, return to step S1041; S1043: Determine whether the second type of preset format is not empty. If so, execute step S1044; if not, execute step S1045; S1044: Update the packet group counter, increment its value by 1, read entries from the FIFO queues corresponding to the different transmission channels according to the optimal format, write the read entries into the empty slots corresponding to the frame segments in sequence, and simultaneously decrement the value of the preset timeout cycle control threshold by 1; if entries have been written into all four slots of the frame segments, execute step S1046; otherwise, execute step S1045; S1045: Determine whether the value of the packet group counter is less than a preset timeout cycle control threshold. If so, return to step S1041; if not, execute step S1046; S1046: If the slot of the frame segment to which the entry is currently written is the first slot, modify the preset pipeline arbitration level to select the first direction pipeline or the second direction pipeline to perform packet transmission in a round-robin manner according to transmission requirements; If the slot of the frame segment whose entry is currently written is the second or third, skip the slot of the frame segment that needs to be packaged and complete the package of the frame segment; If the slot of the frame segment to which the entry is currently written is the 4th, the packaging of the frame segment is completed.

6. The packet assembly method for improving cross-DIE transmission efficiency according to claim 1, characterized in that: The packet assembly method for improving cross-DIE transmission efficiency further comprises the steps of: S106: Sending, through the arbitrator, an arbitration signal for modifying the preset pipeline arbitration level.

7. The packet assembly method for improving cross-DIE transmission efficiency according to claim 5, characterized in that: For the pipeline that is not currently performing packet grouping and transmission, the packet grouping method for improving cross-DIE transmission efficiency further includes the following steps: S201, determine whether the first type of preset format is not empty, if so, execute step S202; if not, execute step S203; S202: Update the packet group counter to increase its value by 1, read entries from the FIFO queues corresponding to the different transmission channels according to the optimal format, write the read entries into the empty slots corresponding to the frame segments in sequence, and update the packet group counter to increase its value by 1. Unless entries are written into all four slots of the frame segments, return to step S201. S203: If the slot of the frame segment to which the entry is currently written is the fourth, then the packaging of the frame segment is completed; if not, return to step S201.

8. A package assembly system for improving cross-DIE transmission efficiency, characterized in that: include: an arbitration module, configured to select, through an arbiter, a pipeline requiring packet assembly and transmission according to a preset pipeline arbitration level to initiate packet assembly, wherein the preset pipeline arbitration level is used to determine the priority of different pipelines and a method for performing packet assembly, wherein the pipelines include a first-direction pipeline from the host to the device and a second-direction pipeline from the device to the host; a reading module, configured to read the FIFO queue depths of entries contained in each of the three transmission channels for request, response, and data that need to be packaged, respectively, wherein for each of the FIFO queues, a first counter is used to record the number of available entries, and for each of the transmission channels, a second counter is used to record the number of entries sent; a format module, configured to determine an optimal format for grouping entries of different transmission channels according to the values ​​of the first counter and the second counter corresponding to the request, response, and data transmission channels respectively; a packet assembly module, configured to read entries from the FIFO queues corresponding to the different transmission channels according to the optimal format and write the entries into slots corresponding to frame segments, and determine whether packet assembly of the frame segments is completed according to the preset pipeline arbitration level; The transmission module is configured to transmit the frame segments that have completed packetization to a packetization transmitter, and further transmit the completed frame segments to the physical layer of the pipeline through the packetization transmitter to complete packetization transmission.

9. A computer device, characterized in that: include: A memory, a processor, and a package assembly program for improving cross-DIE transmission efficiency stored in the memory and executable on the processor, wherein when the processor executes the package assembly program for improving cross-DIE transmission efficiency, the steps in the package assembly method for improving cross-DIE transmission efficiency as described in any one of claims 1 to 7 are implemented.

10. A storage medium, characterized in that: The storage medium stores a package assembly program for improving cross-DIE transmission efficiency. When the package assembly program for improving cross-DIE transmission efficiency is executed by the processor, the steps of the package assembly method for improving cross-DIE transmission efficiency as described in any one of claims 1 to 7 are implemented.

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