Method of manufacturing deposition mask, method of manufacturing display device, and electronic device

Abstract

A method of manufacturing a deposition mask, a method of manufacturing a display device using the deposition mask, and an electronic device are provided. A method of manufacturing a deposition mask includes depositing a first inorganic layer such that the first inorganic layer surrounds a surface of a substrate; depositing a second inorganic layer on the first inorganic layer; forming a photoresist pattern on a portion of the second inorganic layer disposed on the front surface of the substrate; forming a plurality of first openings penetrating through the second inorganic layer and penetrating into the first inorganic layer according to a predetermined thickness by etching a portion of the second inorganic layer and a portion of the first inorganic layer using the photoresist pattern as a mask; removing the photoresist pattern; depositing a protective layer on the second inorganic layer including a plurality of first openings; and exposing the mask film formed by the second inorganic layer.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a method of manufacturing a deposition mask, a method of manufacturing a display device using the deposition mask, and an electronic device. BACKGROUND

[0002] A wearable device in the form of glasses or a helmet that forms a focal point at a short distance from a user's eyes has been developed. For example, such a wearable device can be a head-mounted display (HMD) or augmented reality (AR) glasses. Such a wearable device can provide a user with an AR picture or a virtual reality (VR) picture.

[0003] A wearable device such as an HMD or AR glasses can be implemented to have a display specification of about 3000 pixels per inch (PPI) or more, so that a user can use the wearable device for a relatively long time without dizziness. To this end, a silicon on organic light emitting diode (OLEDoS) technology, which can provide a small high-resolution organic light emitting display device, has been proposed. OLEDoS is a technology for placing an organic light emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is disposed.

[0004] In some cases, in order to manufacture a high-resolution display panel of about 3000 pixels per inch (PPI) or more, a high-resolution deposition mask can be required. As a deposition mask for manufacturing an OLEDoS display panel, a mask in which an inorganic film is deposited on a silicon substrate and the deposited inorganic film is patterned to form a mask film is being studied. However, due to the relatively low thickness of the mask film formed of the inorganic film, the mask has a high risk of breakage. SUMMARY

[0005] Aspects of the disclosure provide a deposition mask capable of reducing damage to the mask by increasing the rigidity of the mask, a method of manufacturing the same, a method of manufacturing a display device using the deposition mask, and an electronic device.

[0006] According to an aspect of the disclosure, a method of manufacturing a deposition mask is disclosed, the method including: depositing a first inorganic layer such that the first inorganic layer surrounds a surface of a substrate; depositing a second inorganic layer on the first inorganic layer; forming a photoresist pattern on a portion of the second inorganic layer disposed on a front surface of the substrate; forming a plurality of first openings penetrating the second inorganic layer and penetrating the first inorganic layer according to a predetermined thickness by etching a portion of the second inorganic layer and a portion of the first inorganic layer using the photoresist pattern as a mask; removing the photoresist pattern; depositing a protective layer on the second inorganic layer including the plurality of first openings; and exposing a mask film formed of the second inorganic layer including the plurality of first openings by etching the protective layer, the second inorganic layer, the first inorganic layer, and the substrate in a direction perpendicular to the substrate starting from a back surface of the substrate.

[0007] In an embodiment, exposing the mask film includes forming a first unit opening exposing a surface of the first inorganic layer disposed on the back surface of the substrate by sequentially etching the protective layer and the second inorganic layer disposed on the back surface of the substrate.

[0008] In an embodiment, exposing the mask film further includes forming a second unit opening exposing the back surface of the substrate by etching the first inorganic layer disposed on the back surface of the substrate.

[0009] In an embodiment, exposing the mask film further includes forming a third unit opening exposing the first inorganic layer disposed on the front surface of the substrate by etching the substrate in the second unit opening.

[0010] In an embodiment, exposing the mask film further includes forming a unit opening exposing the mask film by etching the first inorganic layer disposed on the front surface of the substrate.

[0011] In an embodiment, depositing the protective layer includes covering portions of the first inorganic layer exposed through the plurality of first openings and compensating for a thickness variation of the portions of the first inorganic layer.

[0012] In an embodiment, a material of the first inorganic layer and a material of the protective layer are the same.

[0013] In an embodiment, each of the first inorganic layer and the protective layer includes silicon oxide (SiO x ).

[0014] In an embodiment, the second inorganic layer includes silicon nitride (SiN x ).

[0015] In an embodiment, the substrate includes silicon (Si).

[0016] In an embodiment, depositing the protective layer includes depositing silicon nitride (SiN x ) using a low pressure CVD (LPCVD) process.

[0017] In an embodiment, the deposition of the protective layer includes forming a single layer or multiple layers using an atomic layer deposition (ALD) method with at least one inorganic material selected from AlO x , SiO2, and SiN x .

[0018] According to an aspect of the disclosure, a method of manufacturing a display device is disclosed, the method including manufacturing a mask, disposing a deposition substrate on a surface of the manufactured mask, disposing a deposition source to face a surface of the deposition substrate facing the mask, and evaporating a deposition material included in the deposition source and allowing the evaporated deposition material to pass through the mask and be deposited on the deposition substrate, wherein the manufacturing of the mask includes depositing a first inorganic layer to surround a surface of a substrate, depositing a second inorganic layer on the first inorganic layer, forming a photoresist pattern on a portion of the second inorganic layer disposed on a front surface of the substrate, forming a plurality of first openings penetrating the second inorganic layer and penetrating the first inorganic layer according to a predetermined thickness by etching a portion of the second inorganic layer and a portion of the first inorganic layer using the photoresist pattern as a mask, removing the photoresist pattern, depositing a protective layer on the second inorganic layer including the plurality of first openings, and exposing a mask film formed of the second inorganic layer including the plurality of first openings by etching the protective layer, the second inorganic layer, the first inorganic layer, and the substrate in a direction perpendicular to the substrate starting from a rear surface of the substrate.

[0019] In an embodiment, the exposing of the mask film includes forming a first unit opening exposing a surface of the first inorganic layer disposed on the rear surface of the substrate by sequentially etching the protective layer and the second inorganic layer disposed on the rear surface of the substrate.

[0020] In an embodiment, the exposing of the mask film further includes forming a second unit opening exposing the rear surface of the substrate by etching the first inorganic layer disposed on the rear surface of the substrate.

[0021] In an embodiment, the exposing of the mask film further includes forming a third unit opening exposing the first inorganic layer disposed on the front surface of the substrate by etching the substrate in the second unit opening.

[0022] In an embodiment, the exposing of the mask film further includes forming a unit opening exposing the mask film by etching the first inorganic layer disposed on the front surface of the substrate.

[0023] In an embodiment, the deposition of the protective layer includes covering portions of the first inorganic layer exposed through the plurality of first openings and compensating for a thickness variation of the portions of the first inorganic layer.

[0024] In an embodiment, a material of the first inorganic layer and a material of the protective layer are the same.

[0025] In an embodiment, each of the first inorganic layer and the protective layer includes silicon oxide (SiO x ).

[0026] According to an aspect of the disclosure, an electronic device can include a display device configured to provide an image, a processor configured to provide an image data signal to the display device, a memory configured to store data information for operation, and a power module configured to generate power, wherein the display device is manufactured by manufacturing a mask, disposing a deposition base on a surface of the manufactured mask, disposing a deposition source to face another surface of the deposition base, and evaporating a deposition material included in the deposition source, wherein the evaporated deposition material passes through the mask and is deposited on the deposition base, wherein the manufacturing of the mask includes depositing a first inorganic layer so that the first inorganic layer surrounds a surface of the base, depositing a second inorganic layer on the first inorganic layer, forming a photoresist pattern on a portion of the second inorganic layer disposed on a front surface of the base, forming a plurality of first openings penetrating the second inorganic layer and penetrating the first inorganic layer according to a predetermined thickness by etching a portion of the second inorganic layer and a portion of the first inorganic layer using the photoresist pattern as a mask, removing the photoresist pattern, depositing a protective layer on the second inorganic layer including the plurality of first openings, and exposing a mask film formed of the second inorganic layer including the plurality of first openings by etching the protective layer, the second inorganic layer, the first inorganic layer, and the base in a direction perpendicular to the base starting from a rear surface of the base.

[0027] According to the method of manufacturing a deposition mask and the method of manufacturing a display device using the same, the rigidity of the mask can be increased to reduce damage to the mask and increase a mask manufacturing yield. BRIEF DESCRIPTION OF DRAWINGS

[0028] The above and other aspects and features of the disclosure will become more apparent by describing in detail embodiments thereof with reference to the attached drawings, in which:

[0029] Figure 1 is an exploded perspective view illustrating a display device according to an embodiment;

[0030] Figure 2 is a block diagram illustrating a display device according to an embodiment;

[0031] Figure 3 is an equivalent circuit diagram of a first sub-pixel according to an embodiment;

[0032] Figure 4 is a layout diagram illustrating an example of a display panel according to an embodiment;

[0033] Figure 5 and Figure 6 is a layout diagram illustrating an embodiment of a display area of Figure 4 ;

[0034] Figure 7 is a cross-sectional view showing an example of a display panel taken along a line II-II' of Figure 5

[0035] Figure 8 is a perspective view showing a head-mounted display according to an embodiment;

[0036] Figure 9 is an exploded perspective view showing an example of a head-mounted display of Figure 8

[0037] Figure 10 is a perspective view showing another example of a head-mounted display according to an embodiment;

[0038] Figure 11 is a perspective view of a mask according to an embodiment;

[0039] Figure 12 is a schematic plan view of a mask according to an embodiment;

[0040] Figures 13-23 is a cross-sectional view showing a process step of a method of manufacturing a mask according to an embodiment;

[0041] Figure 24 is a view schematically showing a deposition apparatus according to an embodiment;

[0042] Figure 25 is a block diagram of an electronic device according to one embodiment of the present disclosure; and

[0043] Figure 26 is a schematic diagram of an electronic device according to various embodiments of the present disclosure. DETAILED DESCRIPTION

[0044] Embodiments supported by the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments of the present disclosure are shown. Aspects supported by the present disclosure may, however, be implemented in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these example embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the example aspects of the present disclosure to those skilled in the art.

[0045] It will also be understood that when a layer or substrate is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present. Throughout the specification, like reference numerals refer to like components.

[0046] ​​It will be understood that, although the terms "first" and "second" etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element discussed below could be termed a second element without departing from the teachings of aspects supported by the present disclosure. Similarly, a second element could also be termed a first element.

[0047] Considering the measurements in question and the errors associated with the measurement of a particular quantity, the term "about" or "approximately" as used herein includes the stated value and includes a suitable range of deviation from the particular value as determined by one of ordinary skill in the art. For example, the term "about" or "approximately" can mean within one or more standard deviations, or within ± 30%, ± 20%, ± 10%, or ± 5% of the stated value.

[0048] The term "substantially" as used herein means approximately or virtually. The term "substantially equal" means approximately or virtually equal. The term "substantially the same" means approximately or virtually the same. The term "substantially perpendicular" means approximately or virtually perpendicular. The term "substantially parallel" means approximately or virtually parallel.

[0049] Each of the features of various embodiments of the present disclosure can be combined partially or wholly or with each other, and technically various interlocks and drives are possible. Each embodiment can be implemented independently of each other, or can be implemented together.

[0050] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0051] Figure 1 is an exploded perspective view illustrating a display device according to an embodiment. Figure 2 is a block diagram illustrating a display device according to an embodiment.

[0052] Referring to Figure 1 and Figure 2 The display device 10 according to an embodiment is a device that displays a moving image or a still image. The display device 10 according to an embodiment can be applied to a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer, a mobile communication terminal, an electronic organizer, an electronic book, a portable multimedia player (PMP), a navigation system, or an ultra mobile PC (UMPC), etc. For example, the display device 10 according to an embodiment can be applied as a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IoT) terminal. Alternatively, the display device 10 according to an embodiment can be applied to a smart watch, a watch phone, and a head-mounted display (HMD) for implementing virtual reality and augmented reality, etc.

[0053] The display device 10 according to an embodiment includes a display panel 100, a heat dissipation layer 200, a circuit board 300, a timing control circuit (a timing controller) 400, and a power supply circuit (a power supply unit) 500.

[0054] The display panel 100 can have a planar shape similar to a quadrangular shape. For example, the display panel 100 can have a planar shape similar to a quadrangular shape having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 100, a corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect can be a right angle or a rounded corner having a predetermined curvature. The planar shape of the display panel 100 is not limited to the quadrangular shape, and can be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 can conform to the planar shape of the display panel 100, but embodiments of the disclosure are not limited thereto.

[0055] As shown in FIG. 1A, the display panel 100 includes a display area DAA in which an image is displayed and a non-display area NDA in which an image is not displayed. Figure 2

[0056] The display area DAA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0057] The plurality of pixels PX can be arranged in a matrix form in the first direction DR1 and the second direction DR2. The plurality of scan lines SL and the plurality of emission control lines EL can extend in the first direction DR1 while being disposed in the second direction DR2. The plurality of data lines DL can extend in the second direction DR2 while being disposed in the first direction DR1.

[0058] The plurality of scan lines SL includes a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines GBL. The plurality of emission control lines EL includes a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0059] The plurality of pixels PX includes a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 can include a plurality of pixel transistors as shown in FIG. 1B, and the plurality of pixel transistors can be formed by a semiconductor process and disposed in a semiconductor substrate SSUB (see FIG. 2). Figure 3 Figure 7 For example, the plurality of data transistors of the data driver 700 can be formed of a complementary metal-oxide semiconductor (CMOS).

[0060] ​​Each of the plurality of sub-pixels SP1, SP2, and SP3 can be connected to a respective one of a plurality of write scan lines GWL, a respective one of a plurality of control scan lines GCL, a respective one of a plurality of bias scan lines GBL, a respective one of a plurality of first emission control lines EL1, a respective one of a plurality of second emission control lines EL2, and a respective one of a plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 can receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL, and emit light from the light emitting element according to the data voltage.

[0061] The non-display area NDA includes a scan driver 610, an emission driver 620, and a data driver 700.

[0062] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors can be formed in a semiconductor substrate SSUB (see FIG. 1) by a semiconductor process. For example, the plurality of scan transistors and the plurality of light emitting transistors can be formed by CMOS. Although the scan driver 610 is shown to be disposed at the left side of the display area DAA and the emission driver 620 is shown to be disposed at the right side of the display area DAA in Figure 7 , embodiments of the present specification are not limited thereto. For example, the scan driver 610 and the emission driver 620 together can be disposed at the left side or the right side of the display area DAA. Figure 2

[0063] The scan driver 610 can include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 can receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 can generate write scan signals according to the scan timing control signal SCS of the timing control circuit 400, and sequentially output them to the write scan lines GWL. The control scan signal output unit 612 can generate control scan signals in response to the scan timing control signal SCS, and sequentially output them to the control scan lines GCL. The bias scan signal output unit 613 can generate bias scan signals according to the scan timing control signal SCS, and sequentially output them to the bias scan lines GBL.

[0064] ​The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 can receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 can generate first emission control signals in accordance with the emission timing control signal ECS, and sequentially output them to the first emission control line EL1. The second emission control driver 622 can generate second emission control signals in accordance with the emission timing control signal ECS, and sequentially output them to the second emission control line EL2.

[0065] The data driver 700 can include a plurality of data transistors, and the plurality of data transistors can be formed by a semiconductor process in a semiconductor substrate SSUB (see Figure 7 ). For example, the plurality of data transistors can be formed by CMOS.

[0066] The data driver 700 can receive digital video data DATA and a data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage in accordance with the data timing control signal DCS, and outputs the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 610, and the analog data voltage can be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0067] The heat dissipation layer 200 can overlap the display panel 100 in a third direction DR3 that is a thickness direction of the display panel 100. The heat dissipation layer 200 can be disposed on a surface of the display panel 100, for example, on a rear surface of the display panel 100. The heat dissipation layer 200 functions to dissipate heat generated from the display panel 100. The heat dissipation layer 200 can include graphite or a metal layer having high thermal conductivity, such as silver (Ag), copper (Cu), or aluminum (Al), for example.

[0068] The circuit board 300 can be electrically connected to the plurality of first pads PD1 (see Figure 4 ) of the first pad portion PDA1 (see Figure 4 ) of the display panel 100 by using a conductive adhesive member, such as an anisotropic conductive film, for example. The circuit board 300 can be a flexible printed circuit board or a flexible film having a flexible material. Although the circuit board 300 is electrically connected to the plurality of first pads PD1 (see Figure 1The circuit board 300 is shown to be unfolded, but can be folded. In this case, one end of the circuit board 300 can be disposed on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. The one end of the circuit board 300 can be an opposite end of a plurality of first pads PD1 (see Figure 4 ) of a first pad portion PDA1 (see Figure 4 ) of the circuit board 300 connected to the display panel 100 by using a conductive adhesive member.

[0069] The timing control circuit 400 can receive digital video data DATA and a timing signal inputted from the outside. The timing control circuit 400 can generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 100 in response to the timing signal. The timing control circuit 400 can output the scan timing control signal SCS to the scan driver 610, and output the emission timing control signal ECS to the emission driver 620. The timing control circuit 400 can output the digital video data DATA and the data timing control signal DCS to the data driver 700.

[0070] The power supply circuit 500 can generate a plurality of panel driving voltages according to a power voltage from the outside. For example, the power supply circuit 500 can generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT, and supply them to the display panel 100. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT will be described later in connection with Figure 3 .

[0071] Each of the timing control circuit 400 and the power supply circuit 500 can be formed as an integrated circuit (IC), and attached to one surface of the circuit board 300. In this case, the scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the timing control circuit 400 can be supplied to the display panel 100 through the circuit board 300. Further, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 can be supplied to the display panel 100 through the circuit board 300.

[0072] Alternatively, each of the timing control circuit 400 and the power supply circuit 500 can be disposed in the non-display area NDA of the display panel 100, similarly to the scan driver 610, the emission driver 620, and the data driver 700. In this case, the timing control circuit 400 can include a plurality of timing transistors, and each of the power supply circuits 500 can include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors can be formed in a semiconductor substrate SSUB (see Figure 7The plurality of timing transistors and the plurality of power transistors can be formed in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, the plurality of timing transistors and the plurality of power transistors can be formed of CMOS. Each of the timing control circuit 400 and the power supply circuit 500 can be provided between the data driver 700 and the first pad portion PDA1 (see FIG. 1A). Figure 4

[0073] Figure 3 is an equivalent circuit diagram of a first sub-pixel according to an embodiment.

[0074] Referring to Figure 3 , the first sub-pixel SP1 can be connected to a write scan line GWL, a control scan line GCL, a bias scan line GBL, a first emission control line EL1, a second emission control line EL2, and a data line DL. In addition, the first sub-pixel SP1 can be connected to a first drive voltage line VSL to which a first drive voltage VSS (see FIG. 1A) corresponding to a low potential voltage is applied, a second drive voltage line VDL to which a second drive voltage VDD (see FIG. 1A) corresponding to a high potential voltage is applied, and a third drive voltage line VIL to which a third drive voltage VINT (see FIG. 1A) corresponding to an initialization voltage is applied. That is, the first drive voltage line VSL can be a low potential voltage line, the second drive voltage line VDL can be a high potential voltage line, and the third drive voltage line VIL can be an initialization voltage line. In this case, the first drive voltage VSS can be lower than the third drive voltage VINT. The second drive voltage VDD can be higher than the third drive voltage VINT. Figure 2 Figure 2 Figure 2

[0075] The first sub-pixel SP1 includes a plurality of transistors T1 to T6, a light emitting element LE, a first capacitor CP1, and a second capacitor CP2.

[0076] ​​​​The light emitting element LE emits light in response to a drive current (Ids) flowing through a channel of the first transistor T1. The amount of light emitted by the light emitting element LE can be proportional to the drive current (Ids). The light emitting element LE can be disposed between the fourth transistor T4 and the first drive voltage line VSL. A first electrode of the light emitting element LE can be connected to a drain electrode of the fourth transistor T4, and a second electrode of the light emitting element LE can be connected to the first drive voltage line VSL. The first electrode of the light emitting element LE can be an anode electrode, and the second electrode of the light emitting element LE can be a cathode electrode. The light emitting element LE can be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer disposed between the first electrode and the second electrode, but embodiments of the present disclosure are not limited thereto. For example, the light emitting element LE can be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode, in which case the light emitting element LE can be a micro light emitting diode.

[0077] The first transistor T1 can be a drive transistor that controls a source-drain current Ids (herein, referred to as a "drive current (Ids)") flowing between a source electrode and a drain electrode of the first transistor T1 according to a voltage applied to a gate electrode of the first transistor T1. The first transistor T1 includes the gate electrode connected to the first node N1, the source electrode connected to the drain electrode of the sixth transistor T6, and the drain electrode connected to the second node N2.

[0078] The second transistor T2 can be disposed between one electrode of the first capacitor CP1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect the one electrode of the first capacitor CP1 to the data line DL. Accordingly, a data voltage of the data line DL can be applied to the one electrode of the first capacitor CP1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to the one electrode of the first capacitor CP1.

[0079] The third transistor T3 can be disposed between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. To this end, the first transistor T1 can operate like a diode since the gate electrode and the drain electrode of the first transistor T1 are connected. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0080] The fourth transistor T4 can be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Accordingly, the driving current (Ids) of the first transistor T1 can be supplied to the light emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0081] The fifth transistor T5 can be disposed between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line GBL to connect the third node N3 to the third driving voltage line VIL. Accordingly, the third driving voltage VINT of the third driving voltage line VIL can be applied to the first electrode of the light emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0082] The sixth transistor T6 can be disposed between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Accordingly, the second driving voltage VDD of the second driving voltage line VDL can be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0083] The first capacitor CP1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor CP1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0084] The second capacitor CP2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor CP2 includes one electrode connected to the gate electrode of the first transistor T1 and the other electrode connected to the second driving voltage line VDL.

[0085] The first node N1 is a node between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor CP1, and the one electrode of the second capacitor CP2. The second node N2 is a node between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a node between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE.

[0086] Each of the first transistor T1 to the sixth transistor T6 can be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1 to the sixth transistor T6 can be a P-type MOSFET, but embodiments of the present disclosure are not limited thereto. Each of the first transistor T1 to the sixth transistor T6 can be an N-type MOSFET. Alternatively, some of the first transistor T1 to the sixth transistor T6 can be P-type MOSFETs, and each of the remaining transistors can be an N-type MOSFET.

[0087] Although the first sub-pixel SP1 is shown to include six transistors T1 to T6 and two capacitors C1 and C2 in Figure 3 , it should be noted that the equivalent circuit diagram of the first sub-pixel SP1 is not limited to the equivalent circuit diagram shown in Figure 3 . For example, the number of transistors and the number of capacitors of the first sub-pixel SP1 are not limited to those shown in Figure 3 .

[0088] In addition, the equivalent circuit diagram of the second sub-pixel SP2 (see Figure 2 ) and the equivalent circuit diagram of the third sub-pixel SP3 (see Figure 2 ) can be substantially the same as the equivalent circuit diagram of the first sub-pixel SP1 described in connection with Figure 3 . Therefore, the description of the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 are omitted in the present specification.

[0089] Figure 4 is a layout diagram showing an example of a display panel according to an embodiment.

[0090] Referring to Figure 4 , the display area DAA of the display panel 100 according to an embodiment includes a plurality of pixels PX arranged in a matrix form. The non-display area NDA of the display panel 100 according to an embodiment includes a scan driver 610, a emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a first pad portion PDA1, and a second pad portion PDA2.

[0091] The scan driver 610 can be disposed at a first side of the display area DAA, and the emission driver 620 can be disposed at a second side of the display area DAA. For example, the scan driver 610 can be disposed at one side of the display area DAA in the first direction DR1, and the emission driver 620 can be disposed at the other side of the display area DAA in the first direction DR1. That is, the scan driver 610 can be disposed at a left side of the display area DAA, and the emission driver 620 can be disposed at a right side of the display area DAA. However, embodiments of the present specification are not limited thereto, and the scan driver 610 and the emission driver 620 together can be disposed at the first side or the second side of the display area DAA.

[0092] The first pad portion PDA1 can include a plurality of first pads PD1 connected to pads or bumps of the circuit board 300 (see Figure 1 ) by a conductive adhesive member. The first pad portion PDA1 can be disposed at a third side of the display area DAA. For example, the first pad portion PDA1 can be disposed at one side of the display area DAA in the second direction DR2.

[0093] The first pad portion PDA1 can be disposed outside the data driver 700 in the second direction DR2. That is, the first pad portion PDA1 can be disposed closer to an edge of the display panel 100 than the data driver 700.

[0094] The second pad portion PDA2 can include a plurality of second pads PD2 corresponding to check pads for checking whether the display panel 100 normally operates. The plurality of second pads PD2 can be connected to a jig or a probe during a checking process, or can be connected to a circuit board for checking. The circuit board for checking can be a printed circuit board formed of a rigid material or a flexible printed circuit board formed of a flexible material.

[0095] The first distribution circuit 710 distributes data voltages applied through the first pad portion PDA1 to the plurality of data lines DL (see Figure 2 ). For example, the first distribution circuit 710 can distribute data voltages applied through one first pad PD1 of the first pad portion PDA1 to P (P is a positive integer of 2 or more) data lines DL, and as a result, the number of the plurality of first pads PD1 can be reduced. The first distribution circuit 710 can be disposed at the third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 can be disposed at one side of the display area DAA in the second direction DR2. That is, the first distribution circuit 710 can be disposed at a lower side of the display area DAA.

[0096] The second distribution circuit 720 distributes a signal applied through the second pad portion PDA2 to the scan driver 610 and the emission driver 620. The second pad portion PDA2 and the second distribution circuit 720 can be configured to check the operation of each of the plurality of pixels PX in the display area DAA. The second distribution circuit 720 can be disposed at a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 can be disposed at another side of the display area DAA in the second direction DR2. That is, the second distribution circuit 720 can be disposed at an upper side of the display area DAA.

[0097] Figure 5 and Figure 6 is a layout diagram illustrating an embodiment of a display area of Figure 4 .

[0098] Referring to Figure 5 and Figure 6 , each of the plurality of pixels PX includes a first emission area EA1 that is an emission area of a first sub-pixel SP1, a second emission area EA2 that is an emission area of a second sub-pixel SP2, and a third emission area EA3 that is an emission area of a third sub-pixel SP3.

[0099] Each of the first emission area EA1, the second emission area EA2, and the third emission area EA3 can have a polygonal shape, a circular shape, an elliptical shape, or an irregular shape in a plan view.

[0100] A maximum length of the third emission area EA3 in the first direction DR1 can be less than a maximum length of the first emission area EA1 in the first direction DR1 and a maximum length of the second emission area EA2 in the first direction DR1. The maximum length of the first emission area EA1 in the first direction DR1 and the maximum length of the second emission area EA2 in the first direction DR1 can be substantially the same.

[0101] A maximum length of the third emission area EA3 in the second direction DR2 can be longer than a maximum length of the first emission area EA1 in the second direction DR2 and a maximum length of the second emission area EA2 in the second direction DR2. The maximum length of the first emission area EA1 in the second direction DR2 can be longer than the maximum length of the second emission area EA2 in the second direction DR2.

[0102] As Figure 5 and Figure 6As shown in FIG, the first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a hexagonal shape formed by six straight lines in a plan view, but the embodiments of the present disclosure are not limited thereto. The first emission area EA1, the second emission area EA2, and the third emission area EA3 may have a polygonal shape other than a hexagonal shape, a circular shape, an elliptical shape, or an irregular shape in a plan view.

[0103] like Figure 5 As shown in , in each of the plurality of pixels PX, the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the second direction DR2. In addition, the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the first direction DR1. In some aspects, the second emission area EA2 and the third emission area EA3 may be adjacent to each other in the first direction DR1. The area of ​​the first emission area EA1, the area of ​​the second emission area EA2, and the area of ​​the third emission area EA3 may be different.

[0104] Alternatively, as Figure 6 As shown in , the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the first direction DR1, but the second emission area EA2 and the third emission area EA3 may be adjacent to each other in the first oblique direction DD1, and the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the second oblique direction DD2. The first oblique direction DD1 may be a direction between the first direction DR1 and the second direction DR2 and may refer to a direction inclined 45 degrees relative to the first direction DR1 and the second direction DR2, and the second oblique direction DD2 may be a direction perpendicular to the first oblique direction DD1.

[0105] The first emission area EA1 may emit light of a first color, the second emission area EA2 may emit light of a second color, and the third emission area EA3 may emit light of a third color. Here, the first color light may be light of a blue wavelength band, the second color light may be light of a green wavelength band, and the third color light may be light of a red wavelength band. For example, the blue wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 370 nm to approximately 460 nm, the green wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 480 nm to approximately 560 nm, and the red wavelength band may be a wavelength band of light having a main peak wavelength in the range of approximately 600 nm to approximately 750 nm.

[0106] In reference Figure 5 and Figure 6In the described example, each of the plurality of pixels PX includes three emission areas EA1, EA2, and EA3, but embodiments of the present disclosure are not limited thereto. That is, each of the plurality of pixels PX can include four emission areas.

[0107] In some aspects, the layout of the emission areas of the plurality of pixels PX is not limited to the example layout shown in Figure 6 and Figure 7 For example, the emission areas of the plurality of pixels PX can be arranged in a strip structure in which the emission areas are arranged in a first direction DR1, a structure in which the emission areas are arranged in a diamond shape, or a hexagonal structure in which the emission areas have a hexagonal shape in a plan view are arranged side by side as shown in Figure 5

[0108] Figure 7 is a cross-sectional view showing an example of the display panel taken along a line I1-I1' of Figure 3

[0109] Referring to Figure 3 , the display panel 100 includes a semiconductor backplane SBP, a light-emitting element backplane EBP, a display element layer EML, a sealing layer TFE, an organic layer APL, a cover layer CVL, and a polarizing plate POL.

[0110] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating layers SINS1 to SINS3 covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively. The plurality of pixel transistors PTR can be the first transistor T1 to the sixth transistor T6 described with reference to Figure 3

[0111] The semiconductor substrate SSUB can be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The semiconductor substrate SSUB can be a substrate doped with a first type of impurity. A plurality of well regions WA can be provided on a top surface of the semiconductor substrate SSUB. The plurality of well regions WA can be regions doped with a second type of impurity. The second type of impurity can be different from the aforementioned first type of impurity. In an example in which the first type of impurity is a P-type impurity, the second type of impurity can be an N-type impurity. Alternatively, when the first type of impurity is an N-type impurity, the second type of impurity can be a P-type impurity.

[0112] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH provided between the source region SA and the drain region DA.

[0113] ​​​A lower insulating layer BINS can be provided between the gate electrode GE and the well region WA. A side insulating layer SINS can be provided on a side surface of the gate electrode GE. The side insulating layer SINS can be provided on the lower insulating layer BINS.

[0114] Each of the source region SA and the drain region DA can be a region doped with a second type impurity. The gate electrode GE of the pixel transistor PTR can overlap the well region WA in a third direction DR3. The channel region CH can overlap the gate electrode GE in the third direction DR3. The source region SA can be provided on one side of the gate electrode GE, and the drain region DA can be provided on the other side of the gate electrode GE.

[0115] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 provided between the channel region CH and the source region SA, and a second low-concentration impurity region LDD2 provided between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 can be a region having a lower impurity concentration than that of the source region SA due to the lower insulating layer BINS. The second low-concentration impurity region LDD2 can be a region having a lower impurity concentration than that of the drain region DA due to the lower insulating layer BINS. Due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2, a distance between the source region SA and the drain region DA can increase. Therefore, a length of the channel region CH of each of the plurality of pixel transistors PTR can increase, so that breakdown and hot carrier phenomena that can be caused by a short channel can be prevented.

[0116] A first semiconductor insulating layer SINS1 can be provided on the semiconductor substrate SSUB. The first semiconductor insulating layer SINS1 can be formed of a silicon carbon nitride (SiCN) or silicon oxide (SiO x ) based inorganic layer, but embodiments of the present disclosure are not limited thereto.

[0117] A second semiconductor insulating layer SINS2 can be provided on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 can be formed of a silicon oxide (SiO x ) based inorganic layer, but embodiments of the present disclosure are not limited thereto.

[0118] A plurality of contact terminals CTE can be disposed on the second semiconductor insulating layer SINS2. Each of the plurality of contact terminals CTE can be connected to any one of the gate electrode GE, the source region SA, and the drain region DA of each of the pixel transistors PTR through a hole penetrating the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The plurality of contact terminals CTE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0119] A third semiconductor insulating layer SINS3 can be disposed on a side surface of each of the plurality of contact terminals CTE. A top surface of each of the plurality of contact terminals CTE can be exposed without being covered by the third semiconductor insulating layer SINS3. The third semiconductor insulating layer SINS3 can be formed of a silicon oxide (SiO x ) based inorganic layer, but embodiments of the present disclosure are not limited thereto.

[0120] The semiconductor substrate SSUB can be replaced with a glass substrate or a polymer (such as a polyimide, for example) resin substrate. In this case, thin film transistors (e.g., the pixel transistors PTR) can be disposed on the glass substrate or the polymer resin substrate. The glass substrate can be a rigid substrate that is not bendable, and the polymer resin substrate can be a flexible substrate that can be bendable or curved.

[0121] The light emitting element backplane EBP includes a plurality of conductive layers ML1-ML8, a plurality of vias VA1-VA9, and a plurality of insulating layers INS1-INS9. In some aspects, the light emitting element backplane EBP includes a plurality of insulating layers INS1-INS8 disposed between the first conductive layer ML1 and the eighth conductive layer ML8.

[0122] The first conductive layer ML1 to the eighth conductive layer ML8 are used to connect the plurality of contact terminals CTE exposed from the semiconductor backplane SBP to realize the circuit of the first sub-pixel SP1 shown in FIG. 1B. For example, in conjunction with FIG. 1B, the first transistor T1 to the sixth transistor T6 are formed in the semiconductor backplane SBP, and the connection of the first transistor T1 to the sixth transistor T6 with the first capacitor CP1 and the second capacitor CP2 is realized through the first conductive layer ML1 to the eighth conductive layer ML8. In some aspects, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode AND of the light emitting element LE is also realized through the first conductive layer ML1 to the eighth conductive layer ML8. Figure 7 Figure 7

[0123] ​​A first insulating layer INS1 can be disposed on the semiconductor backplane SBP. Each of a plurality of first vias VA1 can penetrate the first insulating layer INS1 to connect to a contact terminal CTE exposed from the semiconductor backplane SBP. Each of a plurality of first conductive layers ML1 can be disposed on the first insulating layer INS1 and can be connected to the first via VA1.

[0124] A second insulating layer INS2 can be disposed on the first insulating layer INS1 and the first conductive layer ML1. Each of a plurality of second vias VA2 can penetrate the second insulating layer INS2 and be connected to the exposed first conductive layer ML1. Each of a plurality of second conductive layers ML2 can be disposed on the second insulating layer INS2 and can be connected to the second via VA2.

[0125] A third insulating layer INS3 can be disposed on the second insulating layer INS2 and the second conductive layer ML2. Each of a plurality of third vias VA3 can penetrate the third insulating layer INS3 and be connected to the exposed second conductive layer ML2. Each of a plurality of third conductive layers ML3 can be disposed on the third insulating layer INS3 and can be connected to the third via VA3.

[0126] A fourth insulating layer INS4 can be disposed on the third insulating layer INS3 and the third conductive layer ML3. Each of a plurality of fourth vias VA4 can penetrate the fourth insulating layer INS4 and be connected to the exposed third conductive layer ML3. Each of a plurality of fourth conductive layers ML4 can be disposed on the fourth insulating layer INS4 and can be connected to the fourth via VA4.

[0127] A fifth insulating layer INS5 can be disposed on the fourth insulating layer INS4 and the fourth conductive layer ML4. Each of a plurality of fifth vias VA5 can penetrate the fifth insulating layer INS5 and be connected to the exposed fourth conductive layer ML4. Each of a plurality of fifth conductive layers ML5 can be disposed on the fifth insulating layer INS5 and can be connected to the fifth via VA5.

[0128] A sixth insulating layer INS6 can be disposed on the fifth insulating layer INS5 and the fifth conductive layer ML5. Each of a plurality of sixth vias VA6 can penetrate the sixth insulating layer INS6 and be connected to the exposed fifth conductive layer ML5. Each of a plurality of sixth conductive layers ML6 can be disposed on the sixth insulating layer INS6 and can be connected to the sixth via VA6.

[0129] A seventh insulating layer INS7 can be disposed on the sixth insulating layer INS6 and the sixth conductive layer ML6. Each of a plurality of seventh vias VA7 can penetrate the seventh insulating layer INS7 and be connected to the exposed sixth conductive layer ML6. Each of a plurality of seventh conductive layers ML7 can be disposed on the seventh insulating layer INS7 and can be connected to the seventh via VA7.

[0130] An eighth insulating layer INS8 can be disposed on the seventh insulating layer INS7 and the seventh conductive layer ML7. Each of a plurality of eighth vias VA8 can penetrate the eighth insulating layer INS8 and be connected to the exposed seventh conductive layer ML7. Each of a plurality of eighth conductive layers ML8 can be disposed on the eighth insulating layer INS8 and can be connected to the eighth via VA8.

[0131] The first conductive layer ML1 to the eighth conductive layer ML8 and the first via VA1 to the eighth via VA8 can be formed of substantially the same material. The first conductive layer ML1 to the eighth conductive layer ML8 and the first via VA1 to the eighth via VA8 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The first insulating layer INS1 to the eighth insulating layer INS8 can be formed of substantially the same material. The first insulating layer INS1 to the eighth insulating layer INS8 can be formed of a silicon oxide (SiO x ) based inorganic layer, but embodiments of the present disclosure are not limited thereto.

[0132] The thicknesses of the first conductive layer ML1, the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thicknesses of the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, and the sixth via VA6, respectively. The thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be greater than the thickness of the first conductive layer ML1. The thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6 can be substantially the same. For example, the thickness of the first conductive layer ML1 can be approximately 10 nm to 100 nm, and the thickness of each of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be approximately 100 nm to 200 nm. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be approximately 100 nm to 200 nm. The thicknesses of the second conductive layer ML2, the third conductive layer ML3, the fourth conductive layer ML4, the fifth conductive layer ML5, and the sixth conductive layer ML6 can be approximately 100 nm to 200 nm.

[0133] The thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be greater than the thickness of the first conductive layer ML1, the thickness of the second conductive layer ML2, the thickness of the third conductive layer ML3, the thickness of the fourth conductive layer ML4, the thickness of the fifth conductive layer ML5, and the thickness of the sixth conductive layer ML6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8, respectively. The thickness of each of the seventh via VA7 and the eighth via VA8 can be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh conductive layer ML7 and the thickness of the eighth conductive layer ML8 can be substantially the same. For example, the thickness of each of the seventh conductive layer ML7 and the eighth conductive layer ML8 can be approximately 100 nm to 200 nm, and the thickness of each of the seventh via VA7 and the eighth via VA8 can be approximately 100 nm to 200 nm. The thickness of each of the seventh via VA7 and the eighth via VA8 can be approximately 100 nm to 200 nm.

[0134] A ninth insulating layer INS9 can be disposed on the eighth insulating layer INS8 and the eighth conductive layer ML8. The ninth insulating layer INS9 can be formed of a silicon oxide (SiO x )-based inorganic layer, but embodiments of the present disclosure are not limited thereto.

[0135] Each of a plurality of ninth vias VA9 can penetrate the ninth insulating layer INS9 and be connected to the exposed eighth conductive layer ML8. The ninth via VA9 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The thickness of the ninth via VA9 can be approximately 100 nm to 200 nm.

[0136] A display element layer EML can be disposed on the light emitting element back plate EBP. The display element layer EML can include a light emitting element LE including a first electrode AND, a light emitting stack IL, and a second electrode CAT, a reflective electrode layer RL, a tenth insulating layer INS10 and an eleventh insulating layer INS11, a tenth via VA10, and a pixel definition layer PDL.

[0137] The reflective electrode layer RL can be disposed on the ninth insulating layer INS9. The reflective electrode layer RL can include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, as shown in FIG. 1B, the reflective electrode layer RL can include a first reflective electrode RL1, a second reflective electrode RL2, a third reflective electrode RL3, and a fourth reflective electrode RL4. Figure 8 The reflective electrode layer RL can be disposed on the ninth insulating layer INS9. The reflective electrode layer RL can include at least one reflective electrode RL1, RL2, RL3, and RL4. For example, as shown in FIG. 1B, the reflective electrode layer RL can include a first reflective electrode RL1, a second reflective electrode RL2, a third reflective electrode RL3, and a fourth reflective electrode RL4.

[0138] Each of the plurality of first reflective electrodes RL1 can be disposed on the ninth insulating layer INS9 and can be connected to the ninth via hole VA9. The first reflective electrode RL1 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. Alternatively, the first reflective electrode RL1 can include titanium nitride (TiN).

[0139] Each of the plurality of second reflective electrodes RL2 can be disposed on the first reflective electrode RL1. The second reflective electrode RL2 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the second reflective electrode RL2 can include aluminum (Al).

[0140] Each of the plurality of third reflective electrodes RL3 can be disposed on the second reflective electrode RL2. The third reflective electrode RL3 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. Alternatively, the third reflective electrode RL3 can include titanium nitride (TiN).

[0141] The plurality of fourth reflective electrodes RL4 can be disposed on the plurality of third reflective electrodes RL3, respectively. The fourth reflective electrode RL4 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the fourth reflective electrode RL4 can include titanium (Ti).

[0142] Since the second reflective electrode RL2 is an electrode that substantially reflects light from the light emitting element LE, a thickness of the second reflective electrode RL2 can be greater than a thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 can be approximately 100 nm to 300 nm, and the thickness of the second reflective electrode RL2 can be approximately 500 nm to 1000 nm.

[0143] The tenth insulating layer INS10 can be disposed on the ninth insulating layer INS9. The tenth insulating layer INS10 can be disposed between reflective electrode layers RL adjacent to each other in a horizontal direction. The tenth insulating layer INS10 can be formed of silicon oxide (SiO​x The tenth insulating layer INS10 and the eleventh insulating layer INS11 can be optical auxiliary layers through which light emitted from the light emitting element LE and reflected by the reflective electrode layer RL passes.

[0144] The eleventh insulating layer INS11 can be provided on the tenth insulating layer INS10 and the reflective electrode layer RL. The eleventh insulating layer INS11 can be formed of an inorganic layer of a silicon oxide (SiO x The tenth insulating layer INS10 and the eleventh insulating layer INS11 can be optical auxiliary layers through which light emitted from the light emitting element LE and reflected by the reflective electrode layer RL passes.

[0145] To adjust the resonance distance of light emitted from the light emitting element LE in at least one of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the tenth insulating layer INS10 or the eleventh insulating layer INS11 can not be provided under the first electrode AND. For example, the first electrode AND of the first sub-pixel SP1 can be directly provided on the reflective electrode layer RL. The eleventh insulating layer INS11 can be provided under the first electrode AND of the second sub-pixel SP2. The tenth insulating layer INS10 and the eleventh insulating layer INS11 can be provided under the first electrode AND of the third sub-pixel SP3. However, as shown in FIG. 1B, in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the eleventh insulating layer INS11 can be provided under the first electrode AND. Figure 9

[0146] In summary, in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the distance between the first electrode AND and the reflective electrode layer RL can be different. That is, to adjust the distance from the reflective electrode layer RL to the first electrode AND according to the main wavelength of light emitted from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, the presence or absence of the tenth insulating layer INS10 and the eleventh insulating layer INS11 can be set in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, the distance between the first electrode AND and the reflective electrode layer RL in the third sub-pixel SP3 can be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 and the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1, and the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 can be greater than the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1. However, embodiments of the present disclosure are not limited thereto.

[0147] ​In some aspects, although the tenth insulating layer INS10 and the eleventh insulating layer INS11 are shown in the embodiments of the present specification, a twelfth insulating layer (not shown) disposed under the first electrode AND of the first sub-pixel SP1 can be added. In this case, the eleventh insulating layer INS11 and the twelfth insulating layer (not shown) can be disposed under the first electrode AND of the second sub-pixel SP2, and the tenth insulating layer INS10, the eleventh insulating layer INS11, and the twelfth insulating layer (not shown) can be disposed under the first electrode AND of the third sub-pixel SP3.

[0148] Each of the plurality of tenth vias VA10 can penetrate the eleventh insulating layer INS11 in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, and can be connected to the exposed reflective electrode layer RL. The tenth via VA10 can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The thickness of the tenth via VA10 in the second sub-pixel SP2 can be less than the thickness of the tenth via VA10 in the third sub-pixel SP3.

[0149] The first electrode AND of each of the plurality of light emitting elements LE can be disposed on the eleventh insulating layer INS11 and connected to the tenth via VA10. The first electrode AND of each of the plurality of light emitting elements LE can be connected to the drain region DA or the source region SA of the pixel transistor PTR through the tenth via VA10, the first to fourth reflective electrodes RL1 to RL4, the first to ninth vias VA1 to VA9, the first to eighth conductive layers ML1 to ML8, and the contact terminal CTE. The first electrode AND of each of the plurality of light emitting elements LE can be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. Alternatively, the first electrode AND of each of the plurality of light emitting elements LE can be titanium nitride (TiN).

[0150] The pixel definition layer PDL can be disposed on a portion of the first electrode AND of each of the plurality of light emitting elements LE. The pixel definition layer PDL can cover the edges of the first electrode AND of each of the plurality of light emitting elements LE. The pixel definition layer PDL can be used to separate the first, second, and third emission areas EA1, EA2, and EA3.

[0151] The first emission area EA1 can be defined as an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission area EA2 can be defined as an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission area EA3 can be defined as an area in which the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0152] The pixel definition layer PDL can include a first pixel definition layer PDL1, a second pixel definition layer PDL2, and a third pixel definition layer PDL3. The first pixel definition layer PDL1 can be disposed on an edge of the first electrode AND of each of the plurality of light emitting elements LE, the second pixel definition layer PDL2 can be disposed on the first pixel definition layer PDL1, and the third pixel definition layer PDL3 can be disposed on the second pixel definition layer PDL2. The first pixel definition layer PDL1, the second pixel definition layer PDL2, and the third pixel definition layer PDL3 can be formed of an inorganic layer of a silicon oxide (SiO x ) base, but embodiments of the disclosure are not limited thereto. The first pixel definition layer PDL1, the second pixel definition layer PDL2, and the third pixel definition layer PDL3 can each have a thickness of about .

[0153] When the first pixel definition layer PDL1, the second pixel definition layer PDL2, and the third pixel definition layer PDL3 are formed as one pixel definition layer, the height of the one pixel definition layer increases, so that the first encapsulation inorganic layer TFE1 can be cut off due to step coverage. The step coverage refers to a ratio of a degree of coating a thin film on an inclined portion to a degree of coating the thin film on a flat portion. In some cases, the lower the step coverage, the more likely the thin film is to be cut off at the inclined portion.

[0154] Accordingly, to prevent the first encapsulation inorganic layer TFE1 from being cut off due to step coverage, the first pixel definition layer PDL1, the second pixel definition layer PDL2, and the third pixel definition layer PDL3 can have a cross-sectional structure having a stepped portion. For example, the width of the first pixel definition layer PDL1 can be greater than the width of the second pixel definition layer PDL2 and the width of the third pixel definition layer PDL3, and the width of the second pixel definition layer PDL2 can be greater than the width of the third pixel definition layer PDL3. The width of the first pixel definition layer PDL1 refers to a horizontal length of the first pixel definition layer PDL1 defined in the first direction DR1 and the second direction DR2.

[0155] The light emitting stack IL can include a plurality of intermediate layers. The light emitting stack IL can include a first stack layer IL1, a second stack layer IL2, and a third stack layer IL3 that emit different colors of light. The first stack layer IL1, the second stack layer IL2, and the third stack layer IL3 are discontinuously connected and disconnected between adjacent sub-pixels SP1, SP2, and SP3.

[0156] The first stack layer IL1 can have a structure in which a first hole transport layer, a first organic light emitting layer that emits light of a first color, and a first electron transport layer are sequentially stacked. The first stack layer IL1 can be disposed on the first electrode AND and the pixel defining layer PDL in the first emission area EA1 of the first sub-pixel SP1.

[0157] The second stack layer IL2 can have a structure in which a second hole transport layer, a second organic light emitting layer that emits light of a second color, and a second electron transport layer are sequentially stacked. The second stack layer IL2 can be disposed on the first electrode AND and the pixel defining layer PDL in the second emission area EA2 of the second sub-pixel SP2.

[0158] The third stack layer IL3 can have a structure in which a third hole transport layer, a third organic light emitting layer that emits light of a third color, and a third electron transport layer are sequentially stacked. The third stack layer IL3 can be disposed on the first electrode AND and the pixel defining layer PDL in the third emission area EA3 of the third sub-pixel SP3.

[0159] The second electrode CAT can be disposed on the light emitting stack IL and the pixel defining layer PDL. The second electrode CAT can be formed of a transparent conductive material (TCO) (such as ITO or IZO, for example) that can transmit light or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag, for example). In an example in which the second electrode CAT is formed of a semi-transmissive conductive material, light emitting efficiency can be improved in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 due to a microcavity effect.

[0160] The encapsulation layer TFE can be disposed on the display element layer EML. The encapsulation layer TFE can include at least one inorganic layer TFE1 and TFE2 to prevent oxygen or moisture from penetrating into the display element layer EML. For example, the encapsulation layer TFE can include a first encapsulation inorganic layer TFE1 and a second encapsulation inorganic layer TFE2.

[0161] The first encapsulation inorganic layer TFE1 can be disposed on the second electrode CAT. The first encapsulation inorganic layer TFE1 can be formed to have a thickness of 100 nm to 300 nm. The first encapsulation inorganic layer TFE1 can be formed of at least one selected from silicon nitride (SiN x ), silicon oxynitride (SiON), and silicon oxide (SiO xThe first encapsulation inorganic layer TFE1 can be formed by a chemical vapor deposition (CVD) process.

[0162] The second encapsulation inorganic layer TFE2 can be disposed on the first encapsulation inorganic layer TFE1. The second encapsulation inorganic layer TFE2 can be formed of titanium oxide (TiO x ) or aluminum oxide (AlO x ), but embodiments of the present specification are not limited thereto. The second encapsulation inorganic layer TFE2 can be formed by an atomic layer deposition (ALD) process. The thickness of the second encapsulation inorganic layer TFE2 can be less than the thickness of the first encapsulation inorganic layer TFE1.

[0163] The organic layer APL can be a layer for increasing the interfacial adhesion between the encapsulation layer TFE and the cover layer CVL. The organic layer APL can be an organic layer such as, for example, an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0164] The cover layer CVL can be disposed on the organic layer APL. The cover layer CVL can be a glass substrate or a polymer resin substrate.

[0165] The polarizing plate POL can be disposed on a surface of the cover layer CVL. The polarizing plate POL can be a structure for preventing a reduction in visibility caused by reflection of external light. The polarizing plate POL can include a linear polarizing plate and a phase retardation film. For example, the phase retardation film can be a λ / 4 plate (quarter wave plate), but embodiments of the present disclosure are not limited thereto.

[0166] Figure 8 is a perspective view illustrating a head-mounted display according to an embodiment. Figure 8 is an exploded perspective view illustrating an example of the head-mounted display of Figure 9 .

[0167] Referring to Figure 1 and Figure 2 , the head-mounted display 1000 according to an embodiment includes a first display device 10_1, a second display device 10_2, a display device housing 1100, a housing cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted band 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, and a control circuit board 1600.

[0168] The first display device 10_1 provides an image to the left eye of a user, and the second display device 10_2 provides an image to the right eye of the user. Since each of the first display device 10_1 and the second display device 10_2 is associated with the first optical member 1510 and the second optical member 1520, respectively, the first display device 10_1 and the second display device 10_2 can provide an image to the left eye and the right eye of the user, respectively. Figure 2 and Figure 8The described display apparatus 10 is substantially the same, and thus the description of the first display apparatus 10_1 and the second display apparatus 10_2 will be omitted.

[0169] The first optical member 1510 can be disposed between the first display apparatus 10_1 and the first eyepiece 1210. The second optical member 1520 can be disposed between the second display apparatus 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 can include at least one convex lens.

[0170] The intermediate frame 1400 can be disposed between the first display apparatus 10_1 and the control circuit board 1600 and between the second display apparatus 10_2 and the control circuit board 1600. The intermediate frame 1400 serves to support and fix the first display apparatus 10_1, the second display apparatus 10_2, and the control circuit board 1600.

[0171] The control circuit board 1600 can be disposed between the intermediate frame 1400 and the display apparatus housing 1100. The control circuit board 1600 can be connected to the first display apparatus 10_1 and the second display apparatus 10_2 through connectors. The control circuit board 1600 can convert an image source input from the outside into digital video data DATA (see Figure 9 ), and transmit the digital video data DATA to the first display apparatus 10_1 and the second display apparatus 10_2 through the connectors.

[0172] The control circuit board 1600 can transmit digital video data DATA corresponding to a left-eye image optimized for the left eye of the user to the first display apparatus 10_1, and can transmit digital video data DATA corresponding to a right-eye image optimized for the right eye of the user to the second display apparatus 10_2. Alternatively, the control circuit board 1600 can transmit the same digital video data DATA to the first display apparatus 10_1 and the second display apparatus 10_2.

[0173] The display apparatus housing 1100 serves to accommodate the first display apparatus 10_1, the second display apparatus 10_2, the intermediate frame 1400, the first optical member 1510, the second optical member 1520, and the control circuit board 1600. The housing cover 1200 is disposed such that the housing cover 1200 can cover the open surface of the display apparatus housing 1100. The housing cover 1200 can include the first eyepiece 1210 disposed at the left eye of the user and the second eyepiece 1220 disposed at the right eye of the user. Figure 10 and Figure 10 It is illustrated that the first eyepiece 1210 and the second eyepiece 1220 are separately disposed, but embodiments of the disclosure are not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 can be merged into one.

[0174] The first eyepiece 1210 can be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 can be aligned with the second display device 10_2 and the second optical member 1520. Accordingly, the user can view the image of the first display device 10_1 magnified as a virtual image by the first optical member 1510 through the first eyepiece 1210, and can view the image of the second display device 10_2 magnified as a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0175] The head-mounted band 1300 serves to fix the display device housing 1100 to the head of the user so that the first eyepiece 1210 and the second eyepiece 1220 of the housing cover 1200 are respectively maintained to be disposed at the left eye and the right eye of the user. In an example in which the display device housing 1100 is implemented in a light-weight and compact manner, as shown in FIG. 1B, the head-mounted display 1000 can be provided with a spectacle frame instead of the head-mounted band 1300. Figure 10

[0176] In some aspects, the head-mounted display 1000 can further include a battery for power supply, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port can be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module can be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0177] Figure 10 is a perspective view showing another example of a head-mounted display according to an embodiment.

[0178] Referring to Figure 11 , the head-mounted display 1000_1 according to an embodiment can be a spectacle-type display device in which the display device housing 1200_1 is implemented in a light-weight and compact manner. The head-mounted display 1000_1 according to an embodiment can include a display device 10_3, a left-eye lens 1010, a right-eye lens 1020, a support frame 1030, temple pieces 1040 and 1050, an optical member 1060, an optical path changing member 1070, and a display device housing 1200_1.

[0179] ​The display device housing 1200_1 can accommodate the display device 10_3, the optical member 1060, and the optical path change member 1070. An image displayed in the display device 10_3 can be enlarged by the optical member 1060, and the image can be provided to the right eye of the user through the right-eye lens 1020 after the optical path of the image is changed by the optical path change member 1070. As a result, the user can view an augmented reality image in which a virtual image displayed in the display device 10_3 and a real image seen through the right-eye lens 1020 are combined through the right eye.

[0180] Figure 12 It is shown that the display device housing 1200_1 is disposed at the right end of the support frame 1030, but embodiments of the present disclosure are not limited thereto. For example, the display device housing 1200_1 can be disposed at the left end of the support frame 1030, and in this case, an image of the display device 10_3 can be provided to the left eye of the user. Alternatively, the display device housing 1200_1 can be disposed at both the left end and the right end of the support frame 1030, and in this case, the user can view an image displayed in the display device 10_3 through both the left eye and the right eye.

[0181] Figure 11 is a perspective view of a mask according to an embodiment. Figure 11 is a schematic plan view of a mask according to an embodiment. Figure 12 is a perspective view showing a state in which one unit mask UM is separated from a plurality of unit masks UM. According to Figure 7 and Figure 11 The mask MK according to the embodiment shown in Figure 12 may be used in a process of depositing at least a portion of the light emitting stack IL described above. For example, the light emitting stack IL can be configured to emit different colors of light in the sub-pixels SP1, SP2, and SP3.

[0182] Referring to Figure 7 and Figures 13-23 , the mask MK according to an embodiment can be a shadow mask in which the mask film MM is disposed on a silicon substrate 1700. The mask MK according to an embodiment can be referred to as a "silicon mask". The mask MK can include a unit mask UM and a mask frame MF.

[0183] According to an embodiment, the mask MK can include a silicon substrate 1700, and the mask film MM can be disposed on the silicon substrate 1700. The mask film MM can be disposed in the unit regions 1710 arranged in a matrix form, respectively, and each unit region 1710 can be surrounded by a mask rib region 1721. A portion of the silicon substrate 1700 can be disposed in the mask rib region 1721. The mask rib region 1721 can support the mask film MM.

[0184] The mask film MM can be a portion of the unit mask UM disposed in each of the unit regions 1710.

[0185] The silicon substrate 1700 can include a plurality of unit regions 1710 and a mask frame region 1720 other than the unit regions 1710. The mask frame region 1720 can include a mask rib region 1721 surrounding each of the unit regions 1710 and an outer frame region 1722 disposed at the outermost periphery of the silicon substrate 1700. The mask frame MF can be disposed in the mask frame region 1720. The mask frame MF can include a mask rib surrounding the unit regions 1710.

[0186] The mask rib region 1721 can be a region separating the unit regions 1710. For example, the unit regions 1710 can be arranged in a matrix form, and the mask rib disposed in the mask rib region 1721 can surround the outside of the mask film MM disposed in each of the plurality of unit regions 1710.

[0187] The unit mask UM masking at least a portion of the unit opening COP can be disposed in each of the plurality of unit regions 1710 of the silicon substrate 1700.

[0188] The plurality of unit openings COP can penetrate the mask frame MF along a thickness direction (e.g., the third direction DR3) of the mask MK. The unit openings COP can be formed by partially etching the silicon substrate 1700 from the back.

[0189] Each unit mask UM can include a mask film MM, and the mask film MM can include a mask opening OP.

[0190] The mask opening OP of each mask film MM can be referred to as a "hole" or a "mask hole". The mask opening OP can penetrate the unit mask UM along a thickness direction (e.g., the third direction DR3) of the mask MK.

[0191] One unit mask UM can be used in a deposition process of one display panel 100 (see Figure 23 ). In the disclosure, the term "unit mask UM" can be replaced with the term "mask unit UM".

[0192] Figures 13-23 is a cross-sectional view illustrating a process step of a method of manufacturing a mask (deposition mask) according to an embodiment. For example, Figure 23 may be a cross-sectional view in which a portion of a mask is cut, and Figures 13-23 may be a diagram sequentially showing processes of manufacturing a mask shown in Figure 13 .

[0193] Hereinafter, a method of manufacturing a mask according to an embodiment will be described with reference to Figure 14Methods of manufacturing a mask according to embodiments are described. In the description of the methods and processes herein, the operations can be performed in a different order than illustrated and / or described, or operations can be performed at different times or in different orders. Certain operations can also be omitted from the methods, one or more operations can be repeated, or other operations can be added. Descriptions of “may be provided” and “may be formed” of elements, etc. according to example aspects described herein include methods, processes, and techniques for providing, forming, positioning, and modifying the elements, etc.

[0194] Referring to Figure 15 A substrate 1800 can be prepared. The substrate 1800 can include silicon (Si). The substrate 1800 can be referred to as a film substrate or a body substrate, but embodiments of the disclosure are not limited thereto.

[0195] Referring to Figure 12 The method can include depositing a first inorganic layer 1910 such that the first inorganic layer 1910 surrounds a surface of the substrate 1800. In an example, the first inorganic layer 1910 can include silicon oxide (SiO x ).

[0196] According to one or more embodiments, the first inorganic layer 1910 can include an alternative material or an additional material of silicon oxide (SiO x ). For example, the first inorganic layer 1910 can include at least any one of silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiON), titanium oxide (TiO x ), amorphous silicon (a-Si), and aluminum oxide (AlO x ).

[0197] Referring to Figure 16 The method can include forming an alignment key 2010 on the first inorganic layer 1910. For example, the alignment key 2010 can be patterned such that the alignment key 2010 is aligned with one or more portions of the mask frame region 1720 (see Figures 13-23 ). The alignment key 2010 can include tungsten (W), but embodiments of the disclosure are not limited thereto.

[0198] Referring to Figure 17 The method can include depositing a second inorganic layer 1920 on the first inorganic layer 1910 and the alignment key 2010. The second inorganic layer 1920 can include silicon nitride (SiN x ).

[0199] According to one or more embodiments, the second inorganic layer 1920 can include silicon nitride (SiN x) alternative materials or additional materials. For example, the second inorganic layer 1920 may include silicon (Si), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide (AlO x )

[0200] In reference Figure 17 In the described example embodiment, the first inorganic layer 1910 and the second inorganic layer 1920 are deposited on the substrate 1800, but the embodiments of the present disclosure are not limited thereto. For example, the method may include depositing the inorganic layer as a single layer on the substrate 1800, and in this case, the inorganic layer may include silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide (AlO x In the following description, an embodiment in which the first inorganic layer 1910 and the second inorganic layer 1920 are deposited on the substrate 1800 will be described.

[0201] Reference Figure 17 , the method may include disposing a second inorganic layer 1920 on the front surface of the substrate 1800 ( Figure 11 A photoresist pattern 2110 is formed on a portion of the first inorganic layer 1910 and a portion of the second inorganic layer 1920, and the method may include etching a portion of the first inorganic layer 1910 and a portion of the second inorganic layer 1920 using the photoresist pattern 2110 as a mask. Therefore, by etching the portion of the first inorganic layer 1910 and the portion of the second inorganic layer 1920, the method can form a plurality of first openings OP1 that penetrate the second inorganic layer 1920 and penetrate into the first inorganic layer 1910 according to a predetermined thickness (or depth).

[0202] The method can include forming the plurality of first openings OP1 such that the plurality of first openings OP1 correspond to the cell regions and penetrate the second inorganic layer 1920. In some aspects, the plurality of first openings OP1 can penetrate the second inorganic layer 1920 and can pass into the first inorganic layer 1910 according to a predetermined thickness. As described herein, the process of forming the plurality of first openings OP1 described herein can be a dry etching process, and due to irregularities associated with the etching process, the thickness of the first inorganic layer 1910 can vary in the plurality of first openings OP1. For example, in the plurality of first openings OP1, towards the outer edges of the substrate 1800, the first inorganic layer 1910 can be etched deeper. Thus, after the dry etching process, in the plurality of first openings OP1, the thickness of the first inorganic layer 1910 can be smallest at the outermost edges and can increase towards the center of the substrate 1800.

[0203] In Figure 11 , d1, d2, d3, and d4 represent different depths of etching the first inorganic layer 1910 in the outermost edges of the substrate 1800 during the dry etching process for forming the plurality of first openings OP1. That is, due to the dry etching process for forming the plurality of first openings OP1, the thickness of the first inorganic layer 1910 can decrease towards the outermost edges of the substrate 1800. This variation in the thickness of the first inorganic layer 1910 can result in damage to the mask film MM (see Figure 12 ) formed by the second inorganic layer 1920 in a subsequent process (e.g., a backside etching (BSE) process) for forming the cell openings COP (see Figure 17 and Figure 18 ) that includes etching from the back surface (bottom surface shown in Figure 18 ) of the substrate 1800. Thus, prior to performing the subsequent process (e.g., a backside etching (BSE) process) for forming the cell openings COP, embodiments of the present disclosure include performing a process for compensating for the variation in the thickness of the first inorganic layer 1910. Thus, for example, the method can include performing the step of depositing a protective layer 2210 as shown in Figure 17 .

[0204] Referring to Figure 19 , the method can include removing the photoresist pattern 2110 (see Figure 18 ) and depositing a protective layer 2210 on the second inorganic layer 1920 including the plurality of first openings OP1.

[0205] Since the protective layer 2210 covers the first inorganic layer 1910 exposed through the plurality of first openings OP1, the step of depositing the protective layer 2210 can be a step of compensating for a thickness variation of the first inorganic layer 1910 exposed through the plurality of first openings OP1. For example, the protective layer 2210 can cover the portion of the first inorganic layer 1910 exposed through the first openings OP1 to compensate for a thickness variation of the first inorganic layer 1910 caused by irregularities of the etching process. Since the protective layer 2210 covers the portion of the first inorganic layer 1910 at the outermost edge (or edges) of the substrate 1800, the thickness of which can be reduced due to the dry etching process, damage to the mask film MM due to the low thickness of the first inorganic layer 1910 at the outermost edge (or edges) can be prevented.

[0206] According to one or more embodiments, the material of the first inorganic layer 1910 and the material of the protective layer 2210 can be the same. For example, each of the first inorganic layer 1910 and the protective layer 2210 can include silicon oxide (SiO x ). Thus, for example, the first inorganic layer 1910 and the protective layer 2210 can include the same material.

[0207] According to one or more embodiments, the material of the first inorganic layer 1910 and the material of the protective layer 2210 can be different from each other. For example, each of the first inorganic layer 1910 and the protective layer 2210 can include at least any one of silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si), and aluminum oxide (AlO x ). Thus, for example, the first inorganic layer 1910 can include at least one material different from the material included in the protective layer 2210.

[0208] According to one or more embodiments, the step of depositing the protective layer 2210 can include a step of depositing silicon nitride (SiN x ) using a low pressure CVD (LPCVD) method.

[0209] According to one or more embodiments, the step of depositing the protective layer 2210 can include a step of forming a single layer or a plurality of layers with at least one inorganic material selected from AlO x , SiO2, and SiN x by using an atomic layer deposition (ALD) method.

[0210] Referring to Figures 20-23 , the method can include removing the protective layer 2210 deposited on the front surface of the substrate 1800 (see Figure 18). For example, the method can include polishing the front surface of the substrate 1800 using a chemical mechanical polishing (CMP) process. Thus, at the front surface of the substrate 1800, the polishing can remove the protective layer 2210 and expose the upper surface of the patterned second inorganic layer 1920.

[0211] Referring Figure 20 , the method can include etching the protective layer 2210, the second inorganic layer 1920, the first inorganic layer 1910, and the substrate 1800 from below the substrate 1800 (i.e., from the back surface of the substrate 1800) in a third direction DR3 (in other words, in a vertical direction or a direction perpendicular to the plane of the substrate 1800), thereby exposing a mask film MM formed by the second inorganic layer 1920 including a plurality of first openings OP1 (see Figure 21 ).

[0212] As shown in Figure 20 , the step of exposing the mask film MM includes a step of forming a first unit opening OP11 that exposes a surface of the first inorganic layer 1910 disposed on the back surface of the substrate 1800 by sequentially etching the protective layer 2210 and the second inorganic layer 1920 disposed on the back surface of the substrate 1800. In some aspects, the method can further include forming a first alignment opening OP12 aligned with the alignment key 2010 by sequentially etching the protective layer 2210 and the second inorganic layer 1920 disposed on the back surface of the substrate 1800. However, in some embodiments, the method can omit the process of forming the first alignment opening OP12. The method can include selectively performing the step of forming the first alignment opening OP12 or refraining from performing the step depending on the wavelength of light used to identify the alignment key 2010.

[0213] As shown in Figure 22 , the step of exposing the mask film MM further includes a step of forming a second unit opening OP21 that exposes the back surface of the substrate 1800 by etching the first inorganic layer 1910 disposed on the back surface of the substrate 1800 in the first unit opening OP11 (see Figure 21 ).

[0214] As shown in Figure 23 , the step of exposing the mask film MM further includes a step of forming a second alignment opening OP22 aligned with the alignment key 2010 by etching the first inorganic layer 1910 disposed on the back surface of the substrate 1800 in the second unit opening OP21 (seeFigure 22 ) etching the substrate 1800 to form a third cell opening OP31 exposing the first inorganic layer 1910 disposed on the front surface of the substrate 1800. In some aspects, the method can further include forming a third alignment opening OP32 aligned with the alignment key 2010 by etching the substrate 1800. However, in some embodiments, the method can omit the process of forming the third alignment opening OP32. The method can include selectively performing the step of forming the third alignment opening OP32 or refraining from performing the step depending on the wavelength of light used to identify the alignment key 2010.

[0215] As shown in Figure 24 , the step of exposing the mask film MM further includes a step of forming a cell opening COP exposing the mask film MM by etching the first inorganic layer 1910 disposed on the front surface of the substrate 1800 in the third cell opening OP31 (see Figure 24 ). In some aspects, the method can further include forming a fourth alignment opening OP42 aligned with the alignment key 2010 by etching the first inorganic layer 1910 disposed on the front surface of the substrate 1800. However, in some embodiments, the method can omit the process of forming the fourth alignment opening OP42. The method can include selectively performing the step of forming the fourth alignment opening OP42 or refraining from performing the step depending on the wavelength of light used to identify the alignment key 2010.

[0216] As described herein, in the deposition mask manufactured by the method for manufacturing a mask according to the embodiments, the cross-section of each of the mask rib region 1721 and the outer frame region 1722 includes the substrate 1800 and the first inorganic layer 1910 and the second inorganic layer 1920 on the substrate 1800. In some aspects, the cross-section of the mask film MM includes the second inorganic layer 1920.

[0217] As described herein, in the method of manufacturing a mask according to the embodiments, the method can include performing a deposition process of the protective layer 2210 for compensating for a variation in thickness of the first inorganic layer 1910 before performing a subsequent process (e.g., a backside etching (BSE) process) for forming the cell opening COP. Accordingly, the embodiments of the disclosure support reducing damage to the mask film MM caused by the subsequent process (e.g., a backside etching (BSE) process) for forming the cell opening COP and increasing a mask manufacturing yield.

[0218] Figure 12 is a view schematically showing a deposition apparatus according to the embodiments.

[0219] Referring to Figure 12The deposition apparatus according to the embodiments includes a chamber 2310, a deposition source DS disposed inside the chamber 2310, a mask MK disposed inside the chamber 2310 between the deposition source DS and the first substrate 2320, and a mask support 2340 disposed between the deposition source DS and the mask MK and supporting at least a portion of the mask MK.

[0220] According to one or more embodiments, the mask MK includes a second substrate (see Figure 12 of the silicon substrate 1700), the second substrate including a plurality of unit regions 1710 (see Figure 12 ) and a mask frame region 1720 (see Figure 24 ) other than the unit regions 1710, and the mask MK includes a mask film MM (see Figures 1-10 ).

[0221] Figures 1-10 The first substrate 2320 shown in FIG. 23 can be an example of the display panel 100 described with reference to Figure 24 . Accordingly, the description regarding the first substrate 2320 will be replaced with the description of the display panel 100 with reference to Figure 12 , and the repeated description of the same elements is omitted for the sake of brevity.

[0222] Figures 13-22 The mask MK shown in FIG. 23 can be a second substrate, and the mask MK can include the silicon substrate 1700 described with reference to Figure 12 or the substrate 1800 described with reference to Figures 13-22 . The description regarding the second substrate can be replaced with the description of the silicon substrate 1700 with reference to Figure 24 or the description of the substrate 1800 with reference to Figure 24 .

[0223] The mask support 2340 can function to support and fix the mask MK at the bottom of the mask MK. For example, the mask support 2340 can include an electrostatic chuck. According to one or more embodiments, the mask support 2340 can include a first support region 2341 supporting the mask rib region 1721, and further include a second support region 2342 supporting the outer frame region 1722. However, in some embodiments, the mask support 2340 can be implemented such that the mask support 2340 does not support the mask rib region 1721, and for example, the first support region 2341 can be omitted.

[0224] Figure 1 The deposition apparatus shown in FIG. 23 can include a fixing member 2330 fixing the first substrate 2320. The fixing member 2330 can for example include an electrostatic chuck.

[0225] As described above, the deposition apparatus according to the embodiments can include a chamber 2310, a deposition source DS disposed inside the chamber 2310, a mask MK disposed inside the chamber 2310 between the deposition source DS and the first substrate 2320, and a mask support 2340 disposed between the deposition source DS and the mask MK and supporting at least a portion of the mask MK. Figure 24As illustrated in FIG. 1, a display device 10 (see Figures 13-23 ) manufactured using a deposition apparatus according to one or more embodiments of the disclosure can include aspects of the display device 10 as described below. For example, the display device 10 can include a first substrate 2320 (see Figure 25 ) on which a mask MK is manufactured, a deposition source DS facing a surface (e.g., a rear surface, a bottom surface) of the mask MK, and a deposition material included in the deposition source DS. For example, the deposition material can be evaporated and allowed to pass through the mask MK and be deposited on the first substrate 2320. Figure 25 The display device 10 can include aspects of the display device 10 as described below. For example, the display device 10 can include a first substrate 2320 (see

[0226] A display device according to one embodiment of the disclosure can be applied to various electronic devices. An electronic device according to one embodiment of the disclosure includes the above-described display device, and can further include a module or device having an additional function other than the display device.

[0227] Figure 1 is a block diagram of an electronic device according to one embodiment of the disclosure.

[0228] Referring to Figure 26 , an electronic device 1 according to one embodiment of the disclosure can include a display module 11, a processor 12, a memory 13, and a power module 14.

[0229] The processor 12 can include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0230] The memory 13 can store data information required for the operation of the processor 12 or the display module 11. When the processor 12 executes an application stored in the memory 13, an image data signal and / or an input control signal are transmitted to the display module 11, and the display module 11 can process the received signal and output image information through a display screen.

[0231] The power module 14 can include a power supply module such as a power adapter or a battery, and a power conversion module that converts power supplied by the power supply module to generate power required for the operation of the electronic device 1.

[0232] At least one of the components of the electronic device 1 according to one embodiment of the disclosure can be included in the display device 10 (seeFigure 26 ) in FIG. 1. In addition, some of the various modules functionally included in one module can be included in the display device 10, and other modules can be provided separately from the display device 10. For example, the display device 10 can include the display module 11, and the processor 12, the memory 13, and the power module 14 can be provided in the form of other devices than the display device 10 within the electronic device 1.

[0233] Figure 1 is a schematic view of an electronic device according to various embodiments of the present disclosure.

[0234] Referring to ​ , various electronic devices to which the display device 10 (see ​ ) according to embodiments of the present disclosure is applied can not only include image display electronic devices such as a smartphone 10_1a, a tablet PC (personal computer) 10_1b, a laptop computer 10_1c, a television 10_1d, and a desktop monitor 10_1e, but also can include wearable electronic devices including a display module such as exemplified by smart glasses 10_2a, a head-mounted display 10_2b, and a smart watch 10_2c, and vehicle electronic devices 10_3 including a display module such as a CID (central information display) and an in-vehicle mirror display arranged on an instrument panel and a center instrument panel of a car.

[0235] In summarizing the detailed description, those skilled in the art will appreciate that many changes and modifications can be made to the example embodiments without substantially departing from the principles of the present invention. Accordingly, the disclosed example embodiments of the present invention are used in a generic and descriptive sense, and are not for limiting purposes.

Claims

1. A method for manufacturing a deposition mask, wherein: The method comprises: depositing a first inorganic layer so that the first inorganic layer surrounds a surface of a substrate; depositing a second inorganic layer on the first inorganic layer; forming a photoresist pattern on a portion of the second inorganic layer disposed on the front surface of the substrate; forming a plurality of first openings penetrating the second inorganic layer and the first inorganic layer according to a predetermined thickness by etching a portion of the second inorganic layer and a portion of the first inorganic layer using the photoresist pattern as a mask; removing the photoresist pattern; depositing a protective layer on the second inorganic layer including the plurality of first openings; and The mask film formed of the second inorganic layer including the plurality of first openings is exposed by etching the protective layer, the second inorganic layer, the first inorganic layer, and the substrate in a direction perpendicular to the substrate starting from the rear surface of the substrate.

2. The method according to claim 1, wherein The exposing the mask film includes forming a first cell opening exposing a surface of the first inorganic layer disposed on the rear surface of the substrate by sequentially etching the protective layer and the second inorganic layer disposed on the rear surface of the substrate.

3. The method according to claim 2, wherein: The exposing the mask film further includes forming a second cell opening exposing the rear surface of the substrate by etching the first inorganic layer disposed on the rear surface of the substrate.

4. The method according to claim 3, wherein: The exposing the mask film further includes forming a third cell opening exposing the first inorganic layer disposed on the front surface of the substrate by etching the substrate in the second cell opening.

5. The method according to claim 4, wherein The exposing the mask film further includes forming a cell opening exposing the mask film by etching the first inorganic layer disposed on the front surface of the substrate.

6. The method according to claim 1, wherein The depositing the protection layer includes covering portions of the first inorganic layer exposed by the plurality of first openings and compensating for thickness variations of the portions of the first inorganic layer.

7. The method according to claim 6, wherein: The material of the first inorganic layer is the same as that of the protective layer.

8. The method according to claim 7, wherein: Each of the first inorganic layer and the protective layer includes silicon oxide.

9. The method according to claim 7, wherein: The second inorganic layer includes silicon nitride.

10. The method according to claim 9, wherein: The substrate includes silicon.

11. The method according to claim 1, wherein Depositing the protective layer includes depositing silicon nitride using a low pressure chemical vapor deposition process.

12. The method according to claim 1, wherein Depositing the protective layer includes using an atomic layer deposition method with a selected AlO x , SiO2 and SiN x At least one inorganic material forms a single layer or multiple layers.

13. A method for manufacturing a display device, wherein: The method comprises: manufacturing masks; placing a deposition substrate on the surface of the manufactured mask; disposing a deposition source to face the surface of the deposition substrate facing the mask; and vaporizing a deposition material included in the deposition source, wherein the vaporized deposition material passes through the mask and is deposited on the deposition substrate, Wherein, manufacturing the mask comprises: depositing a first inorganic layer so that the first inorganic layer surrounds a surface of a substrate; depositing a second inorganic layer on the first inorganic layer; forming a photoresist pattern on a portion of the second inorganic layer disposed on the front surface of the substrate; forming a plurality of first openings penetrating the second inorganic layer and the first inorganic layer according to a predetermined thickness by etching a portion of the second inorganic layer and a portion of the first inorganic layer using the photoresist pattern as a mask; removing the photoresist pattern; depositing a protective layer on the second inorganic layer including the plurality of first openings; and The mask film formed of the second inorganic layer including the plurality of first openings is exposed by etching the protective layer, the second inorganic layer, the first inorganic layer, and the substrate in a direction perpendicular to the substrate starting from the rear surface of the substrate.

14. The method according to claim 13, wherein: The exposing the mask film includes forming a first cell opening exposing a surface of the first inorganic layer disposed on the rear surface of the substrate by sequentially etching the protective layer and the second inorganic layer disposed on the rear surface of the substrate.

15. The method according to claim 14, wherein The exposing the mask film further includes forming a second cell opening exposing the rear surface of the substrate by etching the first inorganic layer disposed on the rear surface of the substrate.

16. The method according to claim 15, wherein The exposing the mask film further includes forming a third cell opening exposing the first inorganic layer disposed on the front surface of the substrate by etching the substrate in the second cell opening.

17. The method according to claim 16, wherein The exposing the mask film further includes forming a cell opening exposing the mask film by etching the first inorganic layer disposed on the front surface of the substrate.

18. The method according to claim 13, wherein The depositing the protection layer includes covering portions of the first inorganic layer exposed by the plurality of first openings and compensating for thickness variations of the portions of the first inorganic layer.

19. The method according to claim 18, wherein The material of the first inorganic layer is the same as that of the protective layer.

20. The method according to claim 19, wherein Each of the first inorganic layer and the protective layer includes silicon oxide.

21. An electronic device, wherein: The electronic device comprises: a display device configured to provide an image; a processor configured to provide an image data signal to the display device; a memory configured to store data information for operation; and a power module configured to generate electricity, The display device is manufactured by the following steps: manufacturing masks; placing a deposition substrate on the surface of the manufactured mask; disposing a deposition source to face the other surface of the deposition substrate; and vaporizing a deposition material included in the deposition source, wherein the vaporized deposition material passes through the mask and is deposited on the deposition substrate, Wherein, manufacturing the mask comprises: depositing a first inorganic layer so that the first inorganic layer surrounds a surface of a substrate; depositing a second inorganic layer on the first inorganic layer; forming a photoresist pattern on a portion of the second inorganic layer disposed on the front surface of the substrate; forming a plurality of first openings penetrating the second inorganic layer and the first inorganic layer according to a predetermined thickness by etching a portion of the second inorganic layer and a portion of the first inorganic layer using the photoresist pattern as a mask; removing the photoresist pattern; depositing a protective layer on the second inorganic layer including the plurality of first openings; and The mask film formed of the second inorganic layer including the plurality of first openings is exposed by etching the protective layer, the second inorganic layer, the first inorganic layer, and the substrate in a direction perpendicular to the substrate starting from the rear surface of the substrate.

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