ARM and FPGA firmware online upgrading method and system based on USB interface

Abstract

The invention discloses an ARM (Advanced RISC Machines) and FPGA (Field Programmable Gate Array) firmware online upgrading method and system based on a USB (Universal Serial Bus) interface, and the system comprises an upper computer, the USB interface, a USB chip, an ARM processor, an FPGA, an SRAM (Static Random Access Memory), a FLASH memory, an analog switch and a power supply module, the storage space of the ARM processor is divided into a region A, a region B and a region C, wherein the region A is a BOOT guide region; the area B is an ARM application area; the area C is an ARM backup area; the D area is a state identification area; the E area is an FPGA upgrading area; the F area is an FPGA (Field Programmable Gate Array) backup area; in the upgrading state, the ARM controls the enabling end to be pulled up, the first end is switched to be connected with the third end, and the ARM is connected with the FLASH; the upper computer is communicated with the ARM processor through a USB (Universal Serial Bus) interface to execute synchronous upgrading of ARM and FPGA firmware; and selecting an immediate effective mode or a power failure restart effective mode through the check box interface control. By means of the method, online synchronous upgrading of the ARM firmware and the FPGA firmware can be conveniently achieved, operation is simple, check error version rollback in online upgrading is supported, and the stability of the upgrading process and the upgrading efficiency are effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of firmware upgrade, in particular to an ARM and FPGA firmware online upgrade method and system based on a USB interface. BACKGROUND

[0002] With the increasing complexity of electronic products, cross-platform communication applications are becoming more and more widespread. In order to continuously upgrade the functions and performance, and further optimize the hardware matching, the adaptability of embedded devices is becoming stronger and stronger. However, due to the differences in hardware architecture between cross-platforms, independent upgrade methods bring inconvenience to after-sales maintenance. In particular, for products containing ARM and FPGA, the existing technology generally uses multiple USB ports or switches the system platform to realize online upgrade, which is complex and cumbersome to operate, and has poor stability and reliability during the upgrade process. If there are unexpected situations such as verification errors or power failures, the upgrade will fail, the subsequent program may not be able to load and run, and ultimately the device will malfunction and cannot be used.

[0003] In the Chinese patent document with publication number CN118276908A, a FPGA and ARM software online upgrade method is disclosed. The host computer and FPGA monitoring software communicate through a serial port. The FLASH contains multiple sectors, including: a primary boot program, FPGA monitoring software, ARM monitoring software, FPGA software, and ARM software. The FPGA monitoring software receives the upgrade program and transmits it to the ARM monitoring software. The ARM monitoring software stores the upgrade program in the DDR. After verifying the success of the upgrade program, it writes the upgrade program in the DDR to the corresponding sector of the FLASH memory. After the FPGA software and ARM software code is successfully written to the FLASH, the system is powered off and then powered on again. The console no longer sends the code instruction. The ARM monitoring software first loads the FPGA application program, and then loads the ARM application software after the loading is successful. In the above-mentioned technical solution, although the online upgrade of ARM and FPGA can be realized, the online synchronous upgrade of ARM and FPGA cannot be performed. There is no option to continue the current work after system upgrade. The structure setting cannot support version rollback of ARM and FPGA respectively. The upgrade process is complex and cumbersome. If the upgrade fails, the subsequent program may not be able to load and run, ultimately causing the device to malfunction and cannot be used. The stability and efficiency of the upgrade need to be improved. SUMMARY

[0004] The present application aims to provide an ARM and FPGA firmware online upgrade method and system based on a USB interface, which can conveniently realize online synchronous upgrade of ARM and FPGA firmware, is simple to operate, supports version rollback in online upgrade, and improves the stability and efficiency of the upgrade process.

[0005] To solve the above technical problems, the embodiments of the present invention provide a technical solution as follows: an ARM and FPGA firmware online upgrade system based on a USB interface, comprising: a host computer, a USB interface, a USB chip, an ARM processor, an FPGA, an SRAM memory, a FLASH memory, an analog switch, and a power supply module; the host computer is used to generate and transmit upgrade files; the storage space of the ARM processor is divided into: Area A: a BOOT boot area for performing hardware initialization and jump control; Area B: an ARM application area for running main business and upgrade logic; Area C: an ARM backup area for storing ARM firmware backups; Area D: a status identification area for recording upgrade result status identification; Area E: an FPGA upgrade area for receiving FPGA upgrade file programs and upgrading FPGAs. Firmware; Area F: FPGA backup area, storing stable version FPGA firmware, used for program backup after successful FPGA firmware upgrade; the analog switch includes a first end connected to the FLASH memory, a second end connected to the FPGA, and a third end connected to the ARM processor; in the default state, the enable end is grounded, the first end and the second end are conductive, and the FPGA is directly connected to the FLASH; in the upgrade state, the ARM control enable end is pulled high, switched to the first end and the third end to be conductive, so that the ARM is connected to the FLASH; the host computer communicates with the ARM processor through the USB interface, supports importing synthetic upgrade files, and executes synchronous upgrades of ARM and FPGA firmware; imports independent upgrade files, and performs ARM or FPGA firmware upgrades separately; selects immediate effect or power-off restart effect mode through the check box interface control.

[0006] Furthermore, the USB chip supports USB 2.0 high-speed protocol, enabling high-speed communication with a host computer.

[0007] Furthermore, the USB chip model is USB3300-EZK, the FPGA chip used is EP4CE30F23C8N, the ARM chip used is ST32F407ZET6, the SRAM chip used is IS61WV102416BLL, and the analog switch chip is TMUX4052DYYRQ1.

[0008] To solve the above technical problems, the application further provides an ARM and FPGA firmware online upgrading method based on a USB interface, applied to the system, comprising the following steps: S1: connecting a device with a host computer through a USB interface, initializing the device system, starting the ARM processor from A area, and analyzing a state identifier of D area; if the state identifier is a normal state, jumping to B area for operation; if the state identifier is an abnormal state, copying the C area backup firmware to B area and then jumping; S2: the ARM runs in B area, completes USB enumeration and identifies as a custom VID and PID device; S3: the host computer imports an online upgrading file, transmits data according to a custom protocol, and the ARM executes upgrading according to the file type; if it is UPDATE.bin, it is split into ARM.bin and FPGA.bin, and the synchronous upgrading of the ARM and the FPGA is completed; if it is ARM.bin, the ARM firmware is upgraded to B area; if it is FPGA.bin, the FPGA firmware is upgraded to E area; S4: after the upgrading is completed, executing according to user selection: immediate effect: the FPGA loads new firmware from FLASH, the ARM restarts, copies data from C area to B area, executes a jump program, and jumps to B area after updating an upgrading state identifier; power-off restart effect: maintaining the current system operation until the next restart loads new firmware.

[0009] Further, the storage space of the ARM processor is divided into: A area: BOOT boot area, used for executing hardware initialization and jump control; B area: ARM application area, used for running main business and upgrading logic; C area: ARM backup area, used for storing ARM firmware backup; D area: state identifier area, used for recording upgrading result state identifier; E area: FPGA upgrading area, used for receiving FPGA upgrading file program and upgrading FPGA firmware; F area: FPGA backup area, storing stable version FPGA firmware, used for program backup of successful FPGA firmware upgrading; wherein the addresses of A-D areas are continuously allocated, and the addresses of E-F areas are continuously allocated.

[0010] Further, the upgrading flow of the ARM in step S3 comprises: creating an independent upgrading thread, and running in parallel with a main business thread; when upgrading the FPGA: pulling up an analog switch enable end, switching the ARM connection FLASH; writing E area data into FLASH through SPI; verifying success: backing up to F area; verifying failure: restoring data from F area to FLASH.

[0011] Further, the data transmission in step S3 adopts a custom packet protocol, comprising: a packet sequence number, a fixed length data segment and a CRC check code; the ARM realizes μs level single packet verification through a hardware CRC module, and supports out-of-order data recombination based on the sequence number.

[0012] Further, the DMA double buffer mechanism is adopted: the USB interrupt triggers the package receiving event, and when the DMA carries the previous data, the USB interface receives the subsequent data package in parallel.

[0013] Further, in the step S3, when the ARM firmware is upgraded, the sub-packet data is received and verified, and if the verification is successful, the data is written into the C area, and instruction handshake 2 (the packet data is correct) is given to the upper computer; if the verification fails, instruction handshake 4 (the packet data is incorrect) is given to the upper computer, triggering the upper computer to resend or terminate the process; after all the data is written into the C area, instruction handshake 3 (the ARM upgrade is completed) is given to the upper computer.

[0014] Further, in the step S3, when the FPGA firmware is upgraded, after the upgrade file is written into the E area, the ARM controls the analog switch to switch the connection; the FLASH is erased and the new data is written, and if the verification is successful, the data is backed up to the F area; if the verification fails, the data is restored from the F area to the FLASH, and the rollback result is reported.

[0015] Compared with the prior art, the ARM and FPGA firmware online upgrade method and system based on the USB interface provided by the application divides the storage space of the ARM processor and controls the analog switch, so that the ARM and FPGA firmware can be upgraded online and synchronously by the upper computer under the same USB interface, the upgrade operation process is effectively simplified, the upgrade efficiency is improved, the device can be quickly updated, the user can select the effective mode after the upgrade through the setting of the check box interface control, so that the firmware can be upgraded without affecting the normal work of the current system, the upgrade is flexible, convenient and efficient; in particular, the ARM firmware in the ARM backup area C and the stable version of the FPGA firmware in the FPGA backup area F are fixedly backed up, the version rollback functions of the ARM and the FPGA are supported during the upgrade, and once the upgrade fails, the last stable version can be quickly rolled back, so that the risk of upgrade failure is effectively reduced. BRIEF DESCRIPTION OF DRAWINGS

[0016] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are illustrative, but not restrictive, of the embodiments, wherein elements having the same reference number designates like elements throughout the various figures, and the figures are not necessarily to scale.

[0017] Figure 1 The figure is a block diagram of the ARM and FPGA firmware online upgrade system based on the USB interface in the embodiments of the application. Figure 2 The figure is a schematic diagram of the storage space division structure of the ARM processor in the embodiments of the application. Figure 3This is a flowchart of the steps of the online upgrade method of ARM and FPGA firmware based on the USB interface in an embodiment of the present invention; Figure 4 Schematic diagram of the ARM firmware online upgrade process in an embodiment of the present invention; Figure 5 Schematic diagram of the FPGA firmware online upgrade process in an embodiment of the present invention. DETAILED DESCRIPTION

[0018] To make the objectives, technical solutions, and advantages of the present invention more apparent, various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in various embodiments of the present invention to facilitate a better understanding of the present application. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the claims of this application can be implemented.

[0019] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back, etc.), such directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0020] like Figures 1-2 As shown, one embodiment of the present invention relates to an ARM and FPGA firmware online upgrade system based on a USB interface, including: a USB interface, a USB chip, an ARM processor, an FPGA, an SRAM memory, a FLASH memory, an analog switch, a power supply module, and a host computer for generating and transmitting upgrade files. The host computer includes an upgrade file processing module and an upgrade control module. The upgrade file processing module is used to generate upgrade files, and the upgrade files are transmitted through the upgrade control module. The upgrade control module is connected to the USB interface via a USB cable and communicates with the ARM processor via the USB chip.

[0021] The power supply module is used to power the USB chip, ARM, FPGA, SRAM, analog switches, and FLASH. The ARM processor and FPGA are connected through SRAM, SPI, and nCONFIG. The ARM and FPGA communicate and configure registers via SPI. The ARM and FPGA transmit data through SRAM, which is used for data caching.

[0022] The first end A of the analog switch is connected with the FLASH memory, the second end B is connected with the FPGA, the third end C is connected with the ARM processor, the enable end is grounded in the default state, the first end and the second end are conductive, so that the FPGA is directly connected with the FLASH; in the upgrading state, the ARM controls the enable end to be pulled high, the first end and the third end are conductive, so that the ARM is connected with the FLASH; The host computer end upgrading file processing module is used for generating independent upgrading files, such as the ARM processor upgrading file ARM.bin and the FPGA upgrading file FPGA.bin, and can also generate a synthetic upgrading file UPDATE.bin containing ARM.bin and FPGA.bin, which is used for synchronous upgrading of the ARM and FPGA firmware. The upgrading control module can perform synchronous upgrading of the ARM and FPGA through the synthetic upgrading file, or perform separate upgrading of the ARM processor or the FPGA firmware through independent upgrading files, thereby improving the flexibility and efficiency of system firmware upgrading in the actual operation process; preferably, the host computer is provided with an "immediate effect" check box interface control, if checked, after the firmware upgrading is completed, the system will restart to immediately execute the upgraded firmware; if not checked, the upgraded firmware will be executed after the power-off restart by default.

[0023] The ARM processor is provided with a USB interface and is connected with the host computer in communication through a USB line, and the storage space thereof is divided into six storage areas, including continuous A area, B area, C area, D area, and physically isolated E area and F area; the A area, the B area, the C area and the D area are used for upgrading the ARM, the address range of the area used for upgrading the ARM is 0x08000000-0x08060000, and the E area and the F area are used for upgrading the FPGA, the address range of the area used for upgrading the FPGA is 0x08060001-0x0807FFFF; the A area is a BOOT boot area used for executing hardware initialization and jump control; the B area is an ARM application area used for running main services and upgrading logic, ensuring normal work of the system and realizing system upgrading of the ARM by the USB; the C area is an ARM backup area used for storing an ARM firmware backup, and is used for a backup area of the ARM upgrading program when the upgrading is successful; the D area is a state identifier area recording a storage upgrading result state identifier, recording a partition address variable upgrading, and storing a state identifier; the E area is an FPGA upgrading area used for receiving an FPGA upgrading file program and upgrading the FPGA firmware; and the F area is an FPGA backup area storing a stable version of the FPGA firmware and used for backup of the FPGA upgrading file program.

[0024] Preferably, the USB chip supports the USB2.0 high-speed protocol, and the USB interface realizes USB2.0 high-speed device communication through the USB chip, and the communication speed is 40 times that of a traditional USB full-speed device; In one example, the USB chip model is USB3300-EZK, the FPGA uses a chip EP4CE30F23C8N, the ARM uses a chip ST32F407ZET6, the SRAM uses a chip IS61WV102416BLL, and the analog switch chip is TMUX4052DYYRQ1.

[0025] As shown in FIG. 1, one embodiment of the present application relates to a USB interface-based ARM and FPGA firmware online upgrade method, which is applied to the above system and includes the following steps. Figure 3 Step S1: Connect the device and the host computer through the USB interface, start initialization after system power-on, and start the ARM processor from the A area (BOOT boot area). Analyze the state identifier in the D area (state identifier area). If the state identifier is normal, the address identifier is 0xFFFFFFFF, and jump to the B area (ARM application area) for running. If the state identifier is abnormal, the address identifier is 0xAAAAAAAA, copy the data in the C area (ARM backup area) to the B area (ARM application area) and then jump to the B area. The ARM processor storage space is divided into the A area: BOOT boot area, which performs hardware initialization and jump control; the B area: ARM application area, which runs the main business and upgrade logic; the C area: ARM backup area, which stores the ARM firmware backup; the D area: state identifier area, which records the upgrade result state identifier; the E area: FPGA upgrade area, which is used for receiving the FPGA upgrade file program and upgrading the FPGA firmware; and the F area: FPGA backup area, which stores the stable version of the FPGA firmware and is used for program backup after successful FPGA firmware upgrade. The A area is configured as follows: 1. Initialize the system clock tree and initialize the related external input detection GPIO pin; 2. Support external trigger signal reset of the system. When the system detects an external signal input rising edge signal, the real-time system enters the interrupt service program and performs the reset operation of the system, i.e., copying the C area program to the B area, updating the D area state identifier to 0xFFFFFFFF, and executing the jump flow to enter the B area; 3. Execute the jump program to enter the B area. First, analyze the D area state identifier. If the state identifier is 0xFFFFFFFF, it means that the upgrade is successful, and the normal start can be executed, the jump flow is executed to enter the B area. If the state identifier is 0xAAAAAAAA, it means that the upgrade is abnormal, the C area program data is copied to the B area, the D area state identifier is updated to 0xFFFFFFFF, and the jump flow is executed to enter the B area. The jump flow execution steps are as follows: judge and check the validity of the B area application program, such as whether the stack pointer is within the RAM range; then, jump to the B area reset interrupt vector (0x08000000 + A area offset) through the function pointer.

[0026] ​Preferably, the device adopts an external USB3300 PHY, realizes USB2.0 protocol communication, establishes stable connection with the host computer, and provides 5V power supply for the system through the USB HOST, has strong compatibility and supports larger current load. The USB2.0 theoretical bandwidth reaches 480 Mbps (high-speed mode), which is 40 times higher than the traditional USB1.0 device 12 Mbps (full-speed mode), can significantly shorten the firmware upgrade time; the USB3300 PHY supports differential signal transmission and automatic impedance matching, reduces the influence of electromagnetic interference on the upgrade process; and the device system is optimized in terms of power supply stability, data transmission efficiency and reliability.

[0027] Step S2: the system enters the B area, the USB device and the host computer are connected, the USB2.0 device enumeration process is carried out, and it is identified as a USB custom VID and PID device; The USB2.0 device and the host computer are connected, the USB2.0 device enumeration process is carried out, and it is identified as a USB custom VID (Vender ID supplier identification code) and PID (Product ID product identification code) device. In an example, the specific steps are as follows: the USB host detects the physical connection event of the USB2.0 interface, responds to the bus reset signal of the host computer, initializes the USB device controller (OTG_HS), declares the device identity to the host computer through the preset USB descriptor (Descriptor), declares the custom VID and PID in the device descriptor, ensures that the host computer APP can uniquely identify the device. Receive the configuration request (SET_CONFIGURATION) issued by the host computer, complete the endpoint (Endpoint) configuration, establish a bulk transfer (Bulk Transfer) or interrupt transfer (Interrupt Transfer) channel for subsequent firmware data transmission. Communication channel establishment: configure endpoint 1 (IN / OUT) as bulk transfer mode, and the data packet size is 512 bytes (high-speed mode); the host computer sends function codes through the custom protocol to realize communication with the system and firmware data packet upgrade.

[0028] Step S3: the host computer imports the online upgrade file, starts the USB online upgrade task, transmits the upgrade file data according to the custom firmware upgrade protocol format, and completes the upgrade of the ARM and / or FPGA dual-system; the ARM performs the upgrade task according to the file type, imports the merged upgrade file UPDATE.bin of ARM.bin and FPGA.bin, and completes the synchronous upgrade of ARM and FPGA; when the upgrade file ARM.bin is imported alone, the ARM is upgraded alone; when the upgrade file FPGA.bin is imported alone, the FPGA is upgraded alone; Wherein, the ARM.bin file: write into B area and backup to C area; FPGA.bin file: temporary storage to E area, write into FLASH through analog switch switching FLASH control; The specific steps of the ARM processor performing the upgrade task according to the file type are as follows: Step one: receiving the upgrade file data from the host computer through the USB2.0 interface; Step two: according to the self-defined upgrade protocol, first judge whether it is a FPGA upgrade file, if so, start the FPGA upgrade operation process, receive data processing and save data to E area (FPGA upgrade area); otherwise, judge whether it is an ARM upgrade file, if so, start the ARM upgrade operation process, receive data processing and save data to B area, otherwise return the upgrade error code to the host computer; Step three: the ARM processor controls the enablement of the analog switch through the Select signal, the enablement (en) of the analog switch is pulled down by default, that is, connected to ground through resistance, the first end A and the second end B of the analog switch are turned on, making the FPGA directly connected to the FLASH; the ARM pulls up the enablement (en) through the Select signal, making the first end A and the third end C of the analog switch conductive, making the ARM connected to the FLASH; Step four: the ARM processor writes the data in E area into FLASH through SPI, the data contains CRC check (cyclic redundancy check), and the writing is completed after the check is successful; if the check fails, read the data from F area (FPGA backup area) and write it into FLASH to ensure the normal work of FPGA; Maintain normal communication between ARM and FPGA during the upgrade process, the upgrade thread and the ARM main business thread run in parallel to realize online system upgrade without interruption.

[0029] In one embodiment, an ARM and FPGA firmware online upgrade method based on USB interface is involved, wherein the ARM runs FreeRTOS real-time operating system, and the upgrade task management is realized by creating a dedicated upgrade thread and combining the message queue mechanism, specifically including: Step one: create an independent upgrade thread in FreeRTOS and set it to a blocked state waiting for triggering; Step two: when the USB interface detects the upgrade request of the host computer, trigger the message queue through hardware interrupt, and send a wake-up signal to the upgrade thread; Step three: after the upgrade thread is woken up, it takes control of the USB2.0 interface, starts the DMA transmission channel to receive firmware upgrade file data; Step four: in the data receiving process, the USB hardware interrupt feeds back the transmission state in real time, and the upgrade thread dynamically adjusts the data buffer and performs CRC check.

[0030] In the embodiment, the USB interrupt is only responsible for event notification, and the data transfer is completed by DMA, so as to avoid the influence of interrupt storm on FPGA communication; during the running of the upgrade thread, the task scheduler of FreeRTOS guarantees the continuous running of the main business thread, and ensures that the FPGA control link is not interrupted; the message queue mechanism realizes asynchronous processing of the upgrade instruction, so that even if the upgrade thread crashes, it will not spread to the whole RTOS system.

[0031] In one embodiment of the application, in order to improve the upgrade file transmission efficiency and ensure the stability of the upgrade, the host computer sends the wake-up upgrade thread and the information of the upgrade program including the byte number and the packet number at the same time; the host computer sends the upgrade program packet according to the self-defined upgrade program packet format, returns the detection system receiving processing result, if successful, the next packet data transmission is performed, if failed, the host computer reports an error to remind the user to re-perform the system upgrade or execute the system recovery factory setting operation; the ARM receives the upgrade file, judges whether it is an ARM upgrade file or an FPGA upgrade file according to the self-defined protocol, and performs the corresponding system upgrade operation. The self-defined upgrade program packet format adopts a three-segment protocol structure of packet sequence number + data + CRC check, and realizes efficient and reliable transmission through the following cooperative mechanism: Packet verification mechanism: each data packet contains a unique sequence number to realize out-of-order recombination, the data segment adopts a fixed length of 256 bytes to improve the USB2.0 batch transmission efficiency, the tail CRC check code is linked with the ARM hardware CRC module to realize single packet μs-level check; Interrupt-DMA cooperative architecture: the USB2.0 hardware interrupt only triggers the packet receiving completion event, and the DMA controller is called by the upgrade thread to perform data transfer, when the DMA transfers the front packet data, the USB interface can receive the subsequent data packet in parallel, and the double buffer switches in time.

[0032] Compared with the traditional whole packet verification method, the upgrade file packet transmission method provided by the application realizes 40% improvement in upgrade file transmission efficiency through the packet verification mechanism and the interrupt-DMA cooperative architecture, the 480Mbps bandwidth utilization rate is more than 92%, the hardware acceleration of CRC check and DMA transfer makes the single packet processing delay < 50us, supports breakpoint resume, and can still complete the upgrade in the packet loss environment.

[0033] Step S4: After the upgrade is completed, you can choose to take effect immediately. The firmware in FLASH is loaded into the FPGA via SPI, the ARM system restarts, ARM copies the data from area C to area B, executes the jump program, and updates the upgrade status identifier, jumps to area B, and the system runs the upgraded firmware; you can also choose to power off and restart to take effect. The status of the FPGA remains unchanged, and ARM continues to run the current firmware version in area B and works normally to maintain the current system until the next restart takes effect.

[0034] By setting the "Effective Immediately" check box interface control provided by the host computer, after the ARM and FPGA upgrade is completed normally based on USB, it will not affect the current device system working status. It supports the option of taking effect immediately or after power off and restart.

[0035] like Figure 4 As shown, in one embodiment, a method for online firmware upgrade of ARM and FPGA based on a USB interface is provided. The ARM processor firmware online upgrade process is as follows: the host computer imports the online upgrade file ARM.bin file or a composite upgrade file containing the ARM.bin file; the host computer sends a wake-up online upgrade command via USB, starts the ARM online upgrade task, and sends information related to the online upgrade file package, specifically including the total amount of upgrade data and the number of sub-packets. After receiving the command, the ARM performs a command handshake 1 (online upgrade task startup completed, waiting for data packet reception) and sends it to the host computer; The host computer loads the ARM.bin file for sub-packet transmission. After USB reception is completed, a CRC check is performed to see if the data is correct. If so, the package data is placed in the C area of ​​ARM and instruction handshake 2 (the package data is correct) is performed to the host computer. The host computer then sends the next package data and repeats the above sub-packet reception process until the upgrade file is completely received successfully. The upgrade file data is completely written to the C area and instruction handshake 3 (ARM upgrade completed) is performed to the host computer. Otherwise, instruction handshake 4 (the package data is incorrect) is performed to the host computer. The host computer reports an upgrade error exception prompt and can choose the package retransmission mechanism or re-execute the upgrade process. According to the interface control prompt, select whether to take effect immediately. If yes, the ARM system restarts, enters area A, and reads the upgrade status identifier of area D. If the status identifier is 0xFFFFFFFF, it means success. ARM copies the data from area C to area B, executes the jump program, reads the partition address of area D, updates the upgrade status identifier, jumps to area B, and the system runs normally. The new version upgrade is successful; if it fails, perform instruction handshake 5 (system upgrade exception) to the host computer, update the upgrade status identifier, and directly execute the jump program to area B. The system runs normally with the previous version; if it does not take effect immediately, ARM continues to run the current firmware version of area B and works normally.

[0036] As Figure 4 shown, in one embodiment relates to a kind of based on USB interface ARM and FPGA firmware online upgrade method, wherein, FPGA firmware online upgrade flow is as follows: the online upgrade file FPGA.bin file or the synthesis upgrade file containing FPGA.bin file is imported in host computer end, click the upgrade button of host computer end, can carry out online upgrade; FPGA.bin file is placed in the E area of ARM processor by USB, then ARM processor controls the enablement of analog switch by Select signal, the enablement (en) of analog switch is pulled down on circuit, i.e. it is pulled down by resistance to ground, i.e. the first end A and the second end B of default analog switch are conducted; ARM enables (en) by Select signal pull high, i.e. high level, so that the first end A and the second end C of analog switch are conducted;Then ARM processor erases FLASH by SPI, after erasing, write upgrade file FPGA.bin file into FLASH, and judge whether CRC check is successful, if check is successful, then ARM sends upgrade success prompt A to host computer, and simultaneously, ARM backs up upgrade file FPGA.bin from E area to F area;If check fails, then ARM sends prompt upgrade failure prompt B to host computer, and reverts to the previous version, and simultaneously, ARM erases FLASH, after erasing, write the data of F area into FLASH, and again judge whether CRC check is successful, if check is successful, then ARM sends rollback version success prompt C to host computer;If check fails, then ARM sends rollback version failure prompt D to host computer.

[0037] when host computer end imports the online upgrade synthesis file UPDATE.bin containing upgrade file ARM.bin and FPGA.bin, after clicking the upgrade button of host computer end, ARM.bin and FPGA.bin are respectively stored in C area (ARM backup area) and E area (FPGA upgrade area) by USB transmission, and the synchronous online upgrade ARM and FPGA are displayed in host computer end, the synchronous online upgrade ARM and FPGA task are started by online upgrade instruction, and then synchronous execution ARM processor firmware upgrade flow and FPGA firmware upgrade flow;If synthesis upgrade file UPDATE.bin file only has ARM.bin or FPGA.bin, ARM or FPGA firmware can be upgraded separately.If power failure occurs during upgrade and then leads to upgrade failure, after re-powering, the firmware before upgrade is executed, and system can work normally;It can be selected to upgrade again.

[0038] about the present application, after the normal upgrade of ARM and FPGA firmware, support is selected to take effect immediately or restart to take effect, and operation is as follows: The "immediate effect" check box interface control is arranged on the host computer end; if not checked, after the ARM and FPGA firmware online upgrade is completed, the ARM continues to pull up the Select signal, and the enable (en) is high, the ARM controls the nCONFIG signal connected with the FPGA to be high; at this time, the FPGA and the FLASH are not connected, the nCONFIG signal does not reset the FPGA, the state of the FPGA does not change, the ARM continues to run the current firmware version in the B area, and the device system continues to work normally. The default firmware version of the device after upgrade takes effect after power-off restart, and after power-off restart, the ARM and the FPGA are started at the same time.

[0039] If checked, after the ARM and FPGA firmware online upgrade is completed, the ARM pulls down the enable (en) through the Select signal or the ARM no longer controls the Select signal, so that the enable (en) signal is low, and the system immediately executes the upgraded firmware; specifically: (1) the host computer end sends the "immediate effect" instruction to the ARM; (2) the ARM analyzes the instruction after receiving the instruction, controls the nCONFIG signal connected with the FPGA to be pulled up from low after correct analysis; at this time, the analog switch first end A and the second end B are conductive, and after the nCONFIG signal is pulled up, the firmware in the FLASH is loaded into the FPGA through the SPI; (3) the ARM system restarts, enters the A area, reads the upgrade state identifier of the D area, and according to the identifier 0xFFFFFFFF, the ARM copies data from the C area to the B area, executes the jump process, reads the partition address of the D area, updates the upgrade state identifier, jumps to the B area, and normally runs the upgraded firmware version.

[0040] Compared with the prior art, the ARM and FPGA firmware online upgrade method and system based on the USB interface provided by the application divides the storage space of the ARM processor and controls the analog switch, so that the ARM and FPGA firmware can be online and synchronously upgraded by the host computer under the same USB interface, the upgrade operation process is effectively simplified, the upgrade efficiency is improved, the device can be quickly updated, the user can select the effective mode of the upgraded firmware through the setting of the check box interface control, so that the firmware can be upgraded without affecting the normal work of the current system, the upgrade is flexible, convenient and efficient; in particular, the stable version of the ARM firmware in the ARM backup area C and the stable version of the FPGA firmware in the FPGA backup area F are fixedly backed up, the version rollback functions of the ARM and the FPGA are supported during the upgrade, and once the upgrade fails, the last stable version can be quickly rolled back, so that the risk of upgrade failure is effectively reduced.

[0041] Although the present application has been disclosed in its preferred embodiments with reference to the drawings, it will be apparent to those skilled in the art that modifications and improvements can be made without departing from the spirit and scope of the application, and it is intended to cover in the claims any such modifications and improvements that fall within the scope of the application.

Claims

1. An ARM and FPGA firmware online upgrade system based on USB interface, characterized in that: include: Host computer, USB interface, USB chip, ARM processor, FPGA, SRAM memory, FLASH memory, analog switch and power supply module; The host computer is used to generate and transmit the upgrade file; The storage space of the ARM processor is divided into: Area A: BOOT boot area, which performs hardware initialization and jump control; Area B: ARM application area, which runs the main business and upgrade logic; Area C: ARM backup area, which stores ARM firmware backup; Area D: Status identification area, recording the status of the upgrade result; Area E: FPGA upgrade area, used to receive FPGA upgrade file programs and upgrade FPGA firmware; Area F: FPGA backup area, storing stable version FPGA firmware, used for program backup of successful FPGA firmware upgrade; The analog switch includes a first end connected to the FLASH memory, a second end connected to the FPGA, and a third end connected to the ARM processor; in the default state, the enable end is grounded, the first end and the second end are connected, and the FPGA is directly connected to the FLASH; In the upgrade state, the ARM control enable terminal is pulled high, switching the first terminal and the third terminal to conduct, so that the ARM is connected to the FLASH; The host computer communicates with the ARM processor through the USB interface, supports importing synthetic upgrade files, and performing synchronous upgrades of ARM and FPGA firmware; importing independent upgrade files to upgrade ARM or FPGA firmware separately; and selecting immediate effect or power-off restart effect mode through the check box interface control.

2. The ARM and FPGA firmware online upgrade system based on the USB interface according to claim 1, characterized in that: The USB chip supports USB 2.0 high-speed protocol and realizes high-speed communication with the host computer.

3. The ARM and FPGA firmware online upgrade system based on the USB interface according to claim 1 or 2, characterized in that: The USB chip model is USB3300-EZK, the FPGA chip used is EP4CE30F23C8N, the ARM chip used is ST32F407ZET6, the SRAM chip used is IS61WV102416BLL, and the analog switch chip is TMUX4052DYYRQ1.

4. A method for online upgrading of ARM and FPGA firmware based on a USB interface, applied to the system according to any one of claims 1 to 3, characterized in that: include: Step S1: Connect the device to the host computer via the USB interface, power on and initialize the device system, start the ARM processor from area A, and analyze the status mark of area D: if the status mark is normal, jump to area B for operation; If the status is marked as abnormal, copy the backup firmware in area C to area B and then jump; Step S2: ARM runs in area B, completes USB enumeration and identifies it as a custom VID and PID device; Step S3: The host computer imports the online upgrade file and transmits data according to the custom protocol. ARM performs the upgrade according to the file type. If it is UPDATE.bin, it is split into ARM.bin and FPGA.bin to complete the synchronous upgrade of ARM and FPGA. If it is ARM.bin, the ARM firmware is upgraded to area B; if it is FPGA.bin, the FPGA firmware is upgraded to area E. Step S4: After the upgrade is completed, execute according to the user's selection: Immediate effect: FPGA loads the new firmware from FLASH, ARM restarts, and copies data from area C to area B, executes the jump program, and updates the upgrade status identifier before jumping to area B; Power-off restart effect: maintains the current system operation until the next restart to load the new firmware.

5. The method for online upgrading of ARM and FPGA firmware based on USB interface according to claim 4, characterized in that: The storage space of the ARM processor is divided into: Area A: BOOT boot area, used to perform hardware initialization and jump control; Area B: ARM application area, used to run the main business and upgrade logic; Area C: ARM backup area, used to store ARM firmware backup; Area D: Status identification area, used to record the upgrade result status identification; Area E: FPGA upgrade area, used to receive FPGA upgrade file program and upgrade FPGA firmware; Area F: FPGA backup area, stores stable version FPGA firmware, used for program backup of successful FPGA firmware upgrade; the addresses of the AD area are allocated continuously, and the addresses of the EF area are allocated continuously.

6. The method for online upgrading of ARM and FPGA firmware based on USB interface according to claim 5, characterized in that: The process of ARM performing the upgrade in step S3 includes: creating an independent upgrade thread to run in parallel with the main business thread; When upgrading the FPGA: Pull up the analog switch enable terminal to switch ARM to FLASH; Write the data in area E to FLASH via SPI; Verification successful: backup to area F; Verification failed: Restore data from area F to FLASH.

7. The method for online upgrading of ARM and FPGA firmware based on USB interface according to claim 4, characterized in that: In step S3, the data transmission adopts a custom subpacketization protocol, including: packet sequence number, fixed-length data segment and CRC check code; ARM implements μs-level single-packet verification through the hardware CRC module and supports reorganization of out-of-order data based on sequence number.

8. The method for online upgrading of ARM and FPGA firmware based on USB interface according to claim 7, characterized in that: Adopt DMA double buffer mechanism: USB interrupt triggers packet receiving event, while DMA moves the previous packet of data, the USB interface receives subsequent data packets in parallel.

9. The method for online upgrading of ARM and FPGA firmware based on USB interface according to claim 4, characterized in that: When the ARM firmware is upgraded in step S3, the sub-package data is received and verified. If the verification is successful, it is written into area C, and instruction handshake 2 (the package data is correct) is performed and given to the host computer. If the verification fails, instruction handshake 4 (the package data is wrong) is performed and given to the host computer, triggering the host computer to resend or terminate the process. After all data is written into area C, instruction handshake 3 (ARM upgrade completed) is performed and given to the host computer.

10. The method for online upgrading of ARM and FPGA firmware based on USB interface according to claim 4, characterized in that: When the FPGA firmware is upgraded in step S3, after the upgrade file is written to area E, the ARM controls the analog switch to switch the connection; the FLASH is erased and new data is written. If the verification is successful, it is backed up to area F; if the verification fails, the data is restored from area F to FLASH, and the rollback result is reported.

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