Fpga configuration method, system, and storage medium
By generating and synchronizing the first-stage and second-stage bit streams of the FPGA chip, and using the configuration version of the PCIe module for matching checks, the problem of mismatched bit stream loading in the FPGA chip is solved, ensuring normal chip operation and configuration efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU YIGE TECH CO LTD
- Filing Date
- 2025-07-04
- Publication Date
- 2026-05-29
AI Technical Summary
In existing technologies, FPGA chips are prone to malfunctions when the first-stage bit stream and the second-stage bit stream do not match, which can even lead to chip burnout.
By generating and synchronizing the first-stage bit stream and the second-stage bit stream, and using the configuration version of the PCIe module for matching checks, the consistency of the bit stream of the FPGA chip before loading is ensured, and anomalies caused by mismatches are avoided.
To ensure the normal operation of FPGA chips, improve configuration efficiency, avoid chip malfunctions and damage caused by bit stream mismatch, simplify the configuration process, and reduce storage capacity requirements.
Smart Images
Figure CN120803547B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of computer technology, specifically to FPGA configuration methods, systems, and storage media. Background Technology
[0002] In related technologies, Field Programmable Gate Array (FPGA) chips primarily load FPGA configuration information bitstreams via the Peripheral Component Interconnect Express (PCIe) standard. The PCIe loading process is mainly divided into two stages. In the first stage, the FPGA chip loads the first-stage bitstream from flash memory to enable the PCIe module. Then, the second-stage bitstream is loaded via the PCIe link to configure the FPGA chip's hardware logic circuitry.
[0003] However, as user applications continue to evolve, the bit streams of FPGA configuration information generated will increase, which can easily lead to a mismatch between the first-stage bit stream and the second-stage bit stream loaded by the FPGA chip, resulting in FPGA chip malfunctions. Summary of the Invention
[0004] In view of this, this disclosure provides an FPGA configuration method, system, and storage medium to solve the problem of FPGA chip abnormalities caused by the mismatch between the first-stage bit stream and the second-stage bit stream during FPGA chip loading.
[0005] In a first aspect, this disclosure provides an FPGA configuration method applicable to a host computer, the method comprising:
[0006] Obtain the first configuration information of the FPGA chip and the configuration version corresponding to the first configuration information;
[0007] Based on the first configuration information and the configuration version, a first-stage bit stream and a second-stage bit stream of the PCIe module are generated; wherein, the PCIe module is deployed on the FPGA chip; the first-stage bit stream includes the configuration version; the second-stage bit stream includes the first configuration information and the configuration version;
[0008] The first stage bitstream is synchronized to the FPGA chip; wherein the FPGA chip is configured to start the PCIe module based on the first stage bitstream and write the configuration version in the first stage bitstream to the PCIe module;
[0009] Upon detecting that the PCIe module has started, the configuration version corresponding to the first stage bitstream is read from the PCIe module as the first version information; and the second stage bitstream is loaded, and the configuration version in the second stage bitstream is read as the second version information.
[0010] If the first version information is consistent with the second version information, then the second stage bit stream is written into the PCIe module to configure the hardware logic circuit of the FPGA chip.
[0011] Secondly, this disclosure provides an FPGA configuration method applicable to FPGA chips, wherein a PCIe module is deployed on the FPGA chip; the method includes:
[0012] Obtain the first stage bit stream of the PCIe module; wherein, the first stage bit stream is generated by the host computer based on the first configuration information of the FPGA chip and the configuration version of the first configuration information and synchronized to the FPGA chip; the first stage bit stream includes the configuration version;
[0013] The PCIe module is started based on the first stage bitstream, and the configuration version in the first stage bitstream is written into the PCIe module; wherein, the host computer is configured to, upon detecting that the PCIe module has started, read the configuration version corresponding to the first stage bitstream from the PCIe module as first version information, and load the second stage bitstream, read the configuration version in the second stage bitstream, and use the configuration version of the second stage bitstream as second version information; the second stage bitstream is generated by the host computer based on the first configuration information and the configuration version; the second stage bitstream includes the first configuration information and the configuration version; the host computer is further configured to write the second stage bitstream into the PCIe module if the first version information is consistent with the second version information;
[0014] The second-stage bitstream in the PCIe module is read to configure the hardware logic circuitry of the FPGA chip.
[0015] Thirdly, this disclosure provides an FPGA configuration system, including:
[0016] An FPGA chip on which a PCIe module is deployed, the FPGA chip being configured to perform the FPGA configuration method of the first aspect described above;
[0017] A host computer is connected to the FPGA chip, and the host computer is configured to execute the FPGA configuration method described in the second aspect above.
[0018] Fourthly, this disclosure provides a computer-readable storage medium storing computer instructions for causing a computer to execute the FPGA configuration method described in the first or second aspect above.
[0019] The FPGA configuration method provided in this disclosure involves a host computer first generating a first-stage bitstream and a second-stage bitstream for a PCIe module based on the first configuration information and configuration version of the FPGA chip. Then, the host computer synchronizes the first-stage bitstream to the FPGA chip, enabling the FPGA chip to start the PCIe module using the first-stage bitstream and establish a PCIe link with the host computer. Furthermore, upon detecting the PCIe module startup, the host computer can determine the matching status between the first-stage bitstream loaded by the FPGA chip and the second-stage bitstream to be loaded by checking whether the configuration version corresponding to the first-stage bitstream in the PCIe module is consistent with the configuration version in the second-stage bitstream. Only when the first-stage bitstream loaded by the FPGA chip matches the second-stage bitstream to be loaded is the second-stage bitstream written into the PCIe module to configure the hardware logic circuit of the FPGA chip. This avoids FPGA chip malfunctions due to mismatch between the first-stage and second-stage bitstreams loaded by the FPGA chip, ensuring the normal operation of the FPGA.
[0020] The beneficial effects of the FPGA configuration system and computer-readable storage medium correspond to the beneficial effects of the FPGA configuration method, and will not be elaborated here. Attached Figure Description
[0021] To more clearly illustrate the technical solutions in the specific embodiments of this disclosure or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0022] Figure 1 This is a schematic diagram of the framework of an FPGA configuration system according to an embodiment of the present disclosure;
[0023] Figure 2 This is a flowchart illustrating an FPGA configuration method according to an embodiment of the present disclosure;
[0024] Figure 3 This is a schematic diagram of an FPGA reconfiguration process according to an embodiment of the present disclosure;
[0025] Figure 4 This is a flowchart illustrating another FPGA configuration method according to an embodiment of the present disclosure;
[0026] Figure 5 This is an interactive schematic diagram of an FPGA configuration system according to an embodiment of the present disclosure. Detailed Implementation
[0027] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.
[0028] Field-Programmable Gate Arrays (FPGAs), as a programmable hardware platform, are characterized by their versatility, flexibility, reconfigurability, and parallel computing capabilities, and are widely used in various fields such as medical, computing acceleration, and communication signal processing. FPGAs can be reprogrammed to reconfigure hardware logic circuits, adapting them to different application scenarios and implementing specific digital logic functions.
[0029] With the continuous development of FPGA technology, the capacity and performance of FPGA chips are gradually improving. The bitstream files containing FPGA chip configuration information are also getting larger and larger, which increases the requirements for the capacity of flash memory (Flash) to store the bitstream, thereby increasing the application cost of FPGA.
[0030] Based on this, related technologies utilize the Peripheral Component Interconnect Express (PCIe) standard to load the bitstream of FPGA configuration information, achieving faster loading and reducing the Flash capacity requirements for bitstream loading. The PCIe loading process is mainly divided into two stages. In the first stage, the FPGA chip loads the first-stage bitstream from the flash memory storing it to enable the PCIe module. Then, the second-stage bitstream is loaded via the PCIe link to configure the FPGA chip's hardware logic circuits. Simultaneously, online upgrades or regional reconfigurations are supported. During online upgrades or regional reconfigurations of the FPGA, the second-stage bitstream must match the first-stage bitstream.
[0031] However, as user applications continue to evolve, the number of bitstreams generated for FPGA configuration information is increasing, posing a significant challenge to the management of user bitstream files. If the first-stage bitstream loaded by the FPGA chip does not match the second-stage bitstream, it can lead to malfunctions in the FPGA chip, or even cause it to burn out.
[0032] In view of the above, according to the embodiments of this disclosure, an embodiment of an FPGA configuration method is provided. It should be noted that the steps shown in the flowcharts in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowcharts, in some cases, the steps shown or described may be executed in a different order than that shown here.
[0033] See Figure 1 , Figure 1 This disclosure provides an FPGA configuration system, which includes a host computer and an FPGA board. The FPGA board includes an FPGA chip, a PCIe module (not shown in the figure), and a target storage medium. The FPGA chip is configured with a configuration port, specifically a CFG (Configuration) port. The target storage medium is a non-volatile memory, such as a programmable read-only memory (PROM) or Flash memory. The host computer uses PCIe bitstream loading to generate a first-stage bitstream and a second-stage bitstream based on the first configuration information and configuration version of the FPGA chip. The host computer writes the first-stage bitstream into the target storage medium. When the FPGA chip is powered on, it obtains the first-stage bitstream from the target storage medium through the configuration port to start the PCIe module and establish a PCIe link with the host computer. The FPGA chip then loads the second-stage bitstream from the host computer through the PCIe link to configure the hardware logic circuitry of the FPGA chip.
[0034] This embodiment provides an FPGA configuration method that can be used in the aforementioned host computer. Figure 2 This is a flowchart illustrating an FPGA configuration method according to an embodiment of the present disclosure, as shown below. Figure 2 As shown, the process includes the following steps:
[0035] Step S201: Obtain the first configuration information of the FPGA chip and the configuration version corresponding to the first configuration information.
[0036] Specifically, the host computer is equipped with FPGA development tools, and the host computer uses the development tools to first configure information and its configuration version.
[0037] In practical applications, users describe the logic function of the FPGA chip using a Hardware Description Language (HDL) or schematic input tools in the development tool, taking advantage of the PCIe segmented loading characteristics. Then, using the synthesis tools in the development tool, the design of the FPGA chip's logic function is optimized for the PCIe segmented loading characteristics. The HDL code is converted into a gate netlist to facilitate the subsequent generation of two independent bit streams, where the gate netlist includes basic logic units. Next, using the development tool, the locations of the logic units are determined based on the PCIe segmented loading characteristics, the logic unit placement is implemented, and the logic units are connected and routed to obtain the initial configuration information and configuration version of the FPGA chip.
[0038] Step S202: Based on the first configuration information and configuration version, generate a first-stage bit stream and a second-stage bit stream for the PCIe module; wherein the PCIe module is deployed on the FPGA chip; the first-stage bit stream includes the configuration version; the second-stage bit stream includes the first configuration information and the configuration version.
[0039] Specifically, the development tool, taking advantage of the segmented loading characteristics of PCIe, converts the initial configuration information and configuration version into a bitstream file that can be loaded by the FPGA, resulting in a first-stage bitstream and a second-stage bitstream. The first-stage bitstream has a smaller data volume and typically includes the minimum logic required to initialize the PCIe module and establish the PCIe link.
[0040] It should be noted that the FPGA chip's PCIe module supports mapping bit streams to registers in the PCIe module's extended configuration space. That is, by writing a configuration version to a first preset position in the first-stage bit stream and a second preset position in the second-stage bit stream, this configuration version can be configured into the registers of the PCIe module's extended configuration space. The first and second preset positions can be configured according to actual needs, such as the beginning or end of the bit stream, and are not limited here.
[0041] Step S203: Synchronize the first-stage bit stream to the FPGA chip; wherein the FPGA chip is configured to start the PCIe module based on the first-stage bit stream and write the configuration version in the first-stage bit stream to the PCIe module.
[0042] Specifically, step S203 includes: writing the first-stage bit stream to a target storage medium connected to the FPGA chip; wherein the FPGA chip is configured to read the first-stage bit stream from the target storage medium upon power-up, and to start the PCIe module based on the first-stage bit stream, and to write the configuration version in the first-stage bit stream to the PCIe module.
[0043] Optionally, the target storage medium is PROM; alternatively, it can also be Flash, which is not limited here.
[0044] In practical applications, the host computer uses a Flash programming tool to program the first-stage bitstream to the target storage medium. When the FPGA chip powers on, it loads the first-stage bitstream from the target storage medium, configures the PCIe module, and starts the PCIe module. Simultaneously, the FPGA chip writes the configuration version from the first-stage bitstream into the PCIe module. This configuration version can be written into the PCIe module's extended configuration space.
[0045] Understandably, in this embodiment, the first-stage bitstream is first written to the target storage medium connected to the FPGA chip. When the FPGA chip powers on, it reads the first-stage bitstream from the target storage medium. Therefore, the loss of the first-stage bitstream due to FPGA chip power failure can be avoided, thereby improving the reliability of FPGA chip configuration. Furthermore, since the FPGA chip automatically reads the first-stage bitstream from the target storage medium upon power-up, no manual intervention or external device involvement is required, simplifying the FPGA configuration process. Then, the FPGA chip starts the PCIe module based on the first-stage bitstream, writes the configuration version from the first-stage bitstream into the PCIe module, and thus establishes a PCIe link with the host computer. This allows the FPGA to obtain the second-stage bitstream containing the first configuration information, reducing the demand for Flash memory.
[0046] Step S204: If the PCIe module is detected to be running, read the configuration version corresponding to the first stage bit stream from the PCIe module as the first version information; and load the second stage bit stream and read the configuration version in the second stage bit stream as the second version information.
[0047] Specifically, the host computer deploys driver software. When the driver software detects that the PCIe module is starting up, it reads the configuration version of the first-stage bitstream that was previously written to the PCIe module as the first version information. The driver software then loads the second-stage bitstream generated by the development tools and reads the configuration version from the second-stage bitstream as the second version information.
[0048] In step S205, if the first version information is consistent with the second version information, the second stage bit stream is written into the PCIe module to configure the hardware logic circuit of the FPGA chip.
[0049] Specifically, if the first version information is consistent with the second version information, the driver software writes the second-stage bit stream into the PCIe module so that the FPGA chip configures the hardware logic circuit based on the first configuration information of the second-stage bit stream in the PCIe module.
[0050] The FPGA configuration method provided in this embodiment involves the host computer first generating a first-stage bitstream and a second-stage bitstream for the PCIe module based on the first configuration information and configuration version of the FPGA chip. Then, the host computer synchronizes the first-stage bitstream to the FPGA chip, enabling the FPGA chip to start the PCIe module using the first-stage bitstream and establish a PCIe link with the host computer. Furthermore, upon detecting the PCIe module startup, the host computer can determine the matching status between the first-stage bitstream loaded by the FPGA chip and the second-stage bitstream to be loaded by checking whether the configuration version corresponding to the first-stage bitstream in the PCIe module matches the configuration version in the second-stage bitstream. Only when the first-stage bitstream loaded by the FPGA chip matches the second-stage bitstream to be loaded is the second-stage bitstream written into the PCIe module to configure the hardware logic circuit of the FPGA chip. This avoids FPGA chip malfunctions due to mismatch between the first-stage and second-stage bitstreams, ensuring the normal operation of the FPGA.
[0051] In some optional implementations, step S202 includes: constructing verification information for the configuration version; and generating a first-stage bitstream and a second-stage bitstream based on the first configuration information, the configuration version, and the verification information. The first-stage bitstream includes the configuration version and the verification information; the second-stage bitstream includes the first configuration information, the configuration version, and the verification information.
[0052] Understandably, to promptly detect tampered or erroneous configuration versions during transmission, data verification algorithms are used to construct verification information for the configuration versions, ensuring their validity. These algorithms include parity checks, XOR checks, and Cyclic Redundancy Checks (CRC).
[0053] Furthermore, the FPGA chip is configured to write the configuration version and verification information from the first-stage bit stream into the PCIe module. Step S204 above, reading the configuration version corresponding to the first-stage bit stream from the PCIe module, includes: reading the configuration version and verification information corresponding to the first-stage bit stream from the PCIe module; performing data verification on the read configuration version based on the verification information to obtain a data verification result; and if the data verification result indicates that the verification passed, using the read configuration version as the first version information.
[0054] Understandably, if step S202 above adds data verification to the configuration version using a data verification algorithm during the generation of the first-stage bit stream and the second-stage bit stream, then after the FPGA chip starts the PCIe module based on the first-stage bit stream, it writes the configuration version and verification information from the first-stage bit stream into the PCIe module. The host computer's driver software reads the configuration version and verification information corresponding to the first-stage bit stream from the PCIe module, and performs data verification (such as data integrity verification) on the configuration version corresponding to the first-stage bit stream read from the PCIe module based on the verification information and the data verification algorithm, obtaining the data verification result. If the data verification result indicates that the verification passed, the version information corresponding to the first-stage bit stream read from the PCIe module is used as the first configuration information. If the data verification result indicates that the verification failed, an error message is generated, which indicates that the read configuration version has an error or has been tampered with.
[0055] In some optional implementations, the FPGA configuration method of this disclosure further includes: generating error information if the first version information is inconsistent with the second version information; wherein the error information is used to indicate that the first stage bit stream and the second stage bit stream do not match.
[0056] It is worth noting that if the PCIe module loads an incorrect second-stage bitstream, it will cause users to waste a lot of time analyzing and locating the erroneous bitstream, thus affecting the development and delivery schedule of the FPGA chip, and even causing the FPGA chip to burn out. Therefore, in this embodiment, if the host computer's driver software detects an inconsistency between the first version information and the second version information, it generates an error message to promptly notify the user of the bitstream mismatch.
[0057] The FPGA configuration method provided in this embodiment involves the host computer checking the matching of the first version information and the second version information during the loading of the second-stage bit stream in the PCIe module. If they are inconsistent, an error message is generated. Therefore, the user can be promptly informed of the incorrect bit stream loading, avoiding the user wasting a lot of time analyzing and locating the incorrect bit stream, thereby improving the configuration efficiency of the FPGA chip.
[0058] In some optional implementations, the FPGA configuration method of this disclosure further includes:
[0059] Step a1: In response to the configuration update command for the configuration version, obtain the second configuration information. The method for obtaining the second configuration information is the same as the method for obtaining the first configuration information, and will not be elaborated further here.
[0060] Step a2: Based on the second configuration information and configuration version, generate an updated second-stage bitstream; wherein the updated second-stage bitstream includes the second configuration information and configuration version. The method for generating the updated second-stage bitstream is the same as that for generating the second-stage bitstream in step S202 above, and will not be elaborated further here.
[0061] Step a3: Read the configuration version corresponding to the first-stage bitstream from the PCIe module as the third version information. The method for obtaining the third version information is the same as the method for obtaining the first version information in step S204 above, and will not be elaborated further here.
[0062] Step a4: Load the updated second-stage bitstream and read the configuration version from the updated second-stage bitstream as the fourth version information. The method for obtaining the fourth version information is the same as that for obtaining the second version information in step S204 above, and will not be elaborated further here.
[0063] Step a5: If the third version information is consistent with the fourth version information, then update the second stage bit stream in the PCIe module based on the updated second stage bit stream.
[0064] Understandably, as user applications continue to evolve, the number of bitstreams generated by FPGA chip upgrades increases significantly. If the first-stage bitstream loaded by the PCIe module does not match the second-stage bitstream, it can lead to FPGA chip malfunction or even burnout. Therefore, in this embodiment, during the online upgrade process of the FPGA chip, after the host computer obtains the updated second configuration information, it generates an updated second-stage bitstream based on the second configuration information and configuration version. Before updating the second-stage bitstream in the PCIe module based on the updated second-stage bitstream, the host computer first determines whether the configuration version corresponding to the first-stage bitstream in the PCIe module is consistent with the configuration version of the updated second-stage bitstream. If they are consistent, it indicates that the first-stage bitstream loaded by the FPGA chip matches the updated second-stage bitstream. At this point, the host computer can update the second-stage bitstream in the PCIe module based on the updated second-stage bitstream, thereby ensuring the accuracy of the FPGA configuration update.
[0065] In some optional implementations, the FPGA configuration method of this disclosure further includes:
[0066] Step b1: In response to the reconfiguration command for the first configuration information, obtain the reconfiguration information for the first configuration information.
[0067] Specifically, the configuration related to the target area of the FPGA chip in the first configuration information is reconfigured using development tools, generating a reconfiguration command. In response to the reconfiguration command, reconfiguration information for the first configuration information is obtained. This reconfiguration information includes reconfiguration information for the target area of the FPGA chip.
[0068] Step b2: Based on the reconfiguration information and configuration version, generate a reconfiguration bitstream for the second-stage bitstream; wherein the reconfiguration bitstream includes the configuration version and reconfiguration information. The generation method of the reconfiguration bitstream can refer to the generation method of the second-stage bitstream described above, and will not be elaborated further here.
[0069] Step b3: Read the configuration version corresponding to the first-stage bitstream from the PCIe module as the fifth version information. The method for obtaining the fifth version information is the same as the method for obtaining the first version information in step S204 above, and will not be elaborated further here.
[0070] Step b4: Load the reconfiguration stream and read the configuration version from the reconfiguration stream as the sixth version information. The method for obtaining the sixth version information is the same as that for obtaining the second version information in step S204 above, and will not be elaborated further here.
[0071] Step b5: If the fifth configuration version is consistent with the sixth configuration version, then update the second-stage bit stream in the PCIe module based on the reconfiguration bit stream.
[0072] For example, see Figure 3 The FPGA chip includes a reconfiguration block A (i.e., the target area mentioned above). The development tools of the host computer are used to reconfigure the configuration information corresponding to the reconfiguration block A in the first configuration information to obtain reconfiguration information, so as to obtain a reconfiguration bit stream for the reconfiguration block A, for example, reconfiguration bit streams A1 to A4, so as to update the second stage bit stream in the PCIe module using the reconfiguration bit stream, thereby reconfiguring the logic of the reconfiguration block A in the FPGA chip.
[0073] Understandably, as user applications continue to evolve, the number of bitstreams generated by FPGA region reconfiguration increases significantly. If the first-stage bitstream loaded by the FPGA chip does not match the second-stage bitstream, it can lead to FPGA chip malfunction or even burnout. Therefore, in this embodiment, during the FPGA chip region reconfiguration process, after the host computer obtains the reconfiguration information, it generates a reconfiguration bitstream based on the reconfiguration information and configuration version. Before updating the second-stage bitstream in the PCIe module based on the reconfiguration bitstream, the host computer first determines whether the configuration version corresponding to the first-stage bitstream in the PCIe module is consistent with the configuration version of the reconfiguration bitstream. If they are consistent, it indicates that the first-stage bitstream, second-stage bitstream, and reconfiguration bitstream in the PCIe module match. The host computer then updates the second-stage bitstream in the PCIe module based on the reconfiguration bitstream, thereby ensuring the accuracy of FPGA region reconfiguration.
[0074] This embodiment provides an FPGA configuration method that can be used with the above-mentioned FPGA chip, on which a PCIe module is deployed. Figure 4 This is a flowchart illustrating another FPGA configuration method according to an embodiment of the present disclosure, such as... Figure 4 As shown, the process includes the following steps:
[0075] Step S401: Obtain the first-stage bit stream of the PCIe module; wherein, the first-stage bit stream is generated by the host computer based on the first configuration information and configuration version of the first configuration information of the FPGA chip and synchronized to the FPGA chip; the first-stage bit stream includes the configuration version. For details, please refer to the relevant information in steps S201 to S202 above, which will not be elaborated further here.
[0076] Step S402: Start the PCIe module based on the first-stage bitstream and write the configuration version in the first-stage bitstream into the PCIe module. The host computer is configured to, upon detecting the PCIe module's startup, read the configuration version corresponding to the first-stage bitstream from the PCIe module as the first version information, and load the second-stage bitstream, read the configuration version in the second-stage bitstream, and use the configuration version of the second-stage bitstream as the second version information. The second-stage bitstream is generated by the host computer based on the first configuration information and the configuration version. The second-stage bitstream includes the first configuration information and the configuration version. The host computer is also configured to write the second-stage bitstream into the PCIe module if the first version information and the second version information are consistent. See steps S203 to S205 above for related information; further details are omitted here.
[0077] Step S403: Read the second-stage bit stream from the PCIe module to configure the hardware logic circuit of the FPGA chip.
[0078] The FPGA configuration method provided in this embodiment involves the host computer first generating a first-stage bitstream and a second-stage bitstream for the PCIe module based on the first configuration information and configuration version of the FPGA chip. Then, the host computer synchronizes the first-stage bitstream to the FPGA chip, enabling the FPGA chip to start the PCIe module using the first-stage bitstream and establish a PCIe link with the host computer. Furthermore, upon detecting the PCIe module startup, the host computer can determine the matching status between the first-stage bitstream loaded by the FPGA chip and the second-stage bitstream to be loaded by checking whether the configuration version corresponding to the first-stage bitstream in the PCIe module matches the configuration version in the second-stage bitstream. Only when the first-stage bitstream loaded by the FPGA chip matches the second-stage bitstream to be loaded is the second-stage bitstream written into the PCIe module to configure the hardware logic circuit of the FPGA chip. This avoids FPGA chip malfunctions due to mismatch between the first-stage and second-stage bitstreams, ensuring the normal operation of the FPGA.
[0079] In some alternative implementations, the FPGA chip is connected to the target storage medium. Step S401 includes: reading a first-stage bit stream from the target storage medium upon power-up; wherein the first-stage bit stream in the target storage medium is written by a host computer.
[0080] Optionally, the target storage medium is PROM; alternatively, it can also be Flash, which is not limited here.
[0081] Specifically, the host computer uses a Flash programming tool to program the first-stage bitstream into the target storage medium. When the FPGA chip powers on, it loads the first-stage bitstream through the target storage medium, configures the PCIe module, and starts the PCIe module. Simultaneously, the FPGA chip writes the first-stage bitstream into the PCIe module. The configuration version of the first-stage bitstream can be written into the extended configuration space of the PCIe module.
[0082] As one specific application example, see Figure 5 The overall process of the FPGA configuration method disclosed herein mainly includes: Taking advantage of the segmented loading characteristics of PCIe, the FPGA development tool generates a first-stage bit stream and a second-stage bit stream through synthesis, placement, routing, and bit stream generation. The corresponding preset positions in the first-stage and second-stage bit streams contain configuration versions with first configuration information. The host computer uses a Flash programming tool to program the first-stage bit stream to the target storage medium (such as a PROM). When the FPGA chip is powered on, the first-stage bit stream is loaded through the target storage medium, the PCIe module is configured and started, and the configuration version in the first-stage bit stream is written to the extended configuration space of the PCIe module. See also... Figure 5The PCIe module includes a first configuration space and a second configuration space. The first configuration space is the regular configuration space, used to store the PCIe module's standard configuration from the first-stage bitstream, such as boot information. The second configuration space is the extended configuration space, used to store differentiated configurations such as the configuration version in the first-stage bitstream and the second-stage bitstream. When the host computer's driver software detects the PCIe module booting, it reads the configuration version corresponding to the first-stage bitstream in the PCIe module as the first version information. The driver software loads the second-stage bitstream generated by the development tool and reads the configuration version from the second-stage bitstream as the second version information. The driver software checks whether the first and second version information are consistent. If they are consistent, the second-stage bitstream is loaded into the PCIe module; if they are inconsistent, the user is prompted that the first and second-stage bitstreams do not match.
[0083] This disclosed FPGA configuration method supports the mapping of bitstreams from the FPGA chip's PCIe module to registers in the extended configuration space of the PCIe module. Specifically, by filling the configuration version in preset positions of the first-stage and second-stage bitstreams, this configuration version can be configured into the registers of the PCIe module's extended configuration space. Furthermore, both the first-stage and second-stage bitstreams contain the same configuration version. When the host computer loads the second-stage bitstream, it can perform a match check between the configuration versions of the first-stage and second-stage bitstreams to ensure that the first-stage and second-stage bitstreams loaded by the FPGA chip match. Simultaneously, data verification logic can be added to the configuration version to ensure its integrity. Moreover, during PCIe module bitstream loading, online upgrades, or region reconfiguration, this disclosed FPGA configuration method, through the match check between the configuration versions of the first-stage and second-stage bitstreams, can promptly inform the user of incorrect bitstream loading, improving the efficiency of locating incorrect bitstreams and preventing FPGA chip anomalies due to mismatches between the first-stage and second-stage bitstreams.
[0084] This embodiment also provides an FPGA configuration system, such as Figure 1 As shown, the FPGA configuration system includes an FPGA chip and a host computer. The FPGA chip has a PCIe module deployed on it, and is configured to execute the FPGA configuration method described above for FPGA chips. The host computer is connected to the FPGA chip and is used to execute the FPGA configuration method described above for host computers.
[0085] In some alternative implementations, the FPGA configuration system also includes a target storage medium, wherein the FPGA chip is connected to the target storage medium.
[0086] In some alternative implementations, the target storage medium is a read-only memory or flash memory. In addition, other non-volatile memories may be used, which are not limited here.
[0087] The further functional descriptions of each component of the above FPGA configuration system are the same as those in the corresponding embodiments described above, and will not be repeated here.
[0088] This disclosure also provides a computer-readable storage medium in which the methods described in this disclosure can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium after being downloaded via a network. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the FPGA configuration method suitable for FPGA chips or host computers shown in the above embodiments is implemented.
[0089] A portion of this disclosure can be applied to computer program products, such as computer program instructions, which, when executed by a computer, can invoke or provide methods and / or technical solutions according to this disclosure through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, and installation package files. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions; the computer compiling the instructions and then executing the corresponding compiled program; the computer obtaining and executing the instructions; or the computer obtaining and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.
[0090] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.
Claims
1. An FPGA configuration method, characterized in that, Applicable to a host computer, the method includes: Obtain the first configuration information of the FPGA chip and the configuration version corresponding to the first configuration information; Based on the first configuration information and the configuration version, a first-stage bit stream and a second-stage bit stream of the PCIe module are generated; wherein, the PCIe module is deployed on the FPGA chip; the first-stage bit stream includes the configuration version and the verification information of the configuration version; the second-stage bit stream includes the first configuration information and the configuration version. The first stage bitstream is synchronized to the FPGA chip; wherein the FPGA chip is configured to start the PCIe module based on the first stage bitstream and write the configuration version in the first stage bitstream to the PCIe module; the synchronization of the first stage bitstream to the FPGA chip includes: writing the first stage bitstream to a target storage medium connected to the FPGA chip; wherein the FPGA chip is configured to read the first stage bitstream from the target storage medium upon power-up, start the PCIe module based on the first stage bitstream, and write the configuration version and verification information in the first stage bitstream to the PCIe module; Upon detecting that the PCIe module has started, the configuration version corresponding to the first stage bitstream is read from the PCIe module as first version information; and the second stage bitstream is loaded, and the configuration version in the second stage bitstream is read as second version information; the step of reading the configuration version corresponding to the first stage bitstream from the PCIe module as first version information includes: reading the configuration version and verification information corresponding to the first stage bitstream from the PCIe module; performing data verification on the read configuration version based on the verification information to obtain a data verification result; if the data verification result indicates that the verification is passed, the read configuration version is used as the first version information; If the first version information is consistent with the second version information, then the second stage bit stream is written into the PCIe module to configure the hardware logic circuit of the FPGA chip.
2. The FPGA configuration method according to claim 1, characterized in that, The method further includes: If the first version information is inconsistent with the second version information, an error message is generated; wherein the error message is used to indicate that the first stage bitstream and the second stage bitstream do not match.
3. The FPGA configuration method according to claim 1, characterized in that, The method further includes: In response to a configuration update command for the specified configuration version, obtain the second configuration information; Based on the second configuration information and the configuration version, an updated second-stage bitstream is generated; wherein, the updated second-stage bitstream includes the second configuration information and the configuration version; The configuration version corresponding to the first stage bitstream is read from the PCIe module as the third version information; Load the updated second-stage bitstream, and read the configuration version in the updated second-stage bitstream as the fourth version information; If the third version information is consistent with the fourth version information, then the second stage bitstream in the PCIe module is updated based on the updated second stage bitstream.
4. The FPGA configuration method according to claim 1, characterized in that, The method further includes: In response to a reconfiguration command for the first configuration information, obtain reconfiguration information for the first configuration information; Based on the reconfiguration information and the configuration version, a reconfiguration bitstream is generated for the second stage bitstream; wherein, the reconfiguration bitstream includes the configuration version and the reconfiguration information; Read the configuration version corresponding to the first stage bitstream from the PCIe module as the fifth version information; Load the reconfiguration stream and read the configuration version in the reconfiguration stream as the sixth version information; If the fifth version information is consistent with the sixth version information, then the second-stage bit stream in the PCIe module is updated based on the reconfigured bit stream.
5. An FPGA configuration method, characterized in that, Applicable to FPGA chips, wherein a PCIe module is deployed on the FPGA chip; the method includes: Acquiring the first stage bit stream of the PCIe module includes: reading the first stage bit stream from the target storage medium upon power-up; wherein, the first stage bit stream is generated by the host computer based on the first configuration information of the FPGA chip and the configuration version of the first configuration information and synchronized to the target storage medium connected to the FPGA chip; the first stage bit stream includes the configuration version and the verification information of the configuration version; The PCIe module is started based on the first-stage bitstream, and the configuration version and verification information in the first-stage bitstream are written into the PCIe module. The host computer is configured to, upon detecting the start of the PCIe module, read the configuration version and verification information corresponding to the first-stage bitstream from the PCIe module, perform data verification on the read configuration version based on the verification information, obtain a data verification result, and if the data verification result indicates that the verification passed, use the read configuration version as first version information, load the second-stage bitstream, read the configuration version in the second-stage bitstream, and use the configuration version of the second-stage bitstream as second version information. The second-stage bitstream is generated by the host computer based on the first configuration information and the configuration version. The second-stage bitstream includes the first configuration information and the configuration version. The host computer is further configured to write the second-stage bitstream into the PCIe module if the first version information and the second version information are consistent. The second-stage bitstream in the PCIe module is read to configure the hardware logic circuitry of the FPGA chip.
6. An FPGA configuration system, characterized in that, include: An FPGA chip on which a PCIe module is deployed, the FPGA chip being configured to perform the FPGA configuration method of claim 5; A host computer is connected to the FPGA chip, and the host computer is configured to execute the FPGA configuration method according to any one of claims 1 to 4.
7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to execute the FPGA configuration method of any one of claims 1 to 4, or to execute the FPGA configuration method of claim 5.