Hardware verification method and device, and image forming device and system
By adopting a non-unique verification sequence and a randomized verification strategy in an image forming device, the security risk of verification results being forged during hardware verification of the image forming device is resolved, thereby improving the security and reliability of hardware verification.
Patent Information
- Application Number
- CN202510837154.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-20
- Publication Date
- 2025-10-17
AI Technical Summary
In the prior art, the image forming device has a fixed verification strategy during the hardware verification process, which makes it easy for malicious attackers to forge verification results, resulting in increased security risks.
The hardware verification device receives the verification data packet sent by the target device, verifies it according to a non-unique verification sequence, and determines the verification strategy through customized or randomly generated methods. The target device side and the hardware verification device cooperate with each other to ensure the diversity and randomness of the verification sequence.
It effectively prevents replay attacks, improves the security and reliability of hardware verification, and reduces the risk of malicious exploitation.
Smart Images
Figure CN120803823A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of image forming, in particular to a hardware verification method and device, an image forming device and system BACKGROUND In some cases in actual application, some devices will usually enter a "hardware module to be verified" state by default after first power-on or factory reset, at which time the devices cannot operate normally.
[0002] In related technologies, for example, for an image forming device, when the image forming device enters the "hardware module to be verified" state, an administrator needs to operate a hardware verification device to complete verification of the hardware of the image forming device, and the image forming device will then return to a normal working state. Specifically, the hardware verification device sends a predetermined hardware verification policy to the image forming device, so that the relevant hardware in the image forming device performs self-checking according to the predetermined verification policy, and sends the self-checking result to the hardware verification device. The hardware verification device determines whether the hardware of the image forming device passes the security verification according to the self-checking result, and controls the image forming device to return to the normal working state.
[0003] However, since the verification policy for the device is predetermined, the corresponding hardware qualified verification result can be deduced. When the verification policy sent to the image forming device is captured, a fake verification result can be directly sent to the hardware verification device, thereby cheating the hardware verification device that the hardware verification of the device has been completed, and thus the hardware verification device cannot effectively perform security verification on the hardware of the device, ultimately increasing the security risk of the device. Overall, the hardware verification of the device in the prior art is not perfect.
[0004] It should be noted that the information disclosed in the background section of the present application is only intended to deepen the understanding of the general background of the present application, and should not be regarded as acknowledging or implying in any form that the information constitutes prior art known to those skilled in the art. SUMMARY
[0005] Therefore, the embodiments of the present application provide a hardware verification method and device, an image forming device and system, to solve the problem that the hardware module verification of the device in the prior art is not perfect.
[0006] In a first aspect, the embodiments of the present application provide a hardware verification method applied to a hardware verification device, and the method comprises: receiving a verification data packet of a target hardware module sent by a target device; the target hardware module being a module determined from a plurality of to-be-verified hardware modules of the target device; verifying the verification data packet when it is determined that the target hardware module is a currently specified to-be-verified hardware module according to a verification order; The check sequence is not unique, and is used to determine a currently specified hardware module to be checked when checking a plurality of hardware modules to be checked of the target device.
[0007] In a possible implementation, the method further includes: According to the check sequence, when it is determined that the target hardware module is not the currently specified hardware module to be checked, a check failure response is output.
[0008] In a possible implementation, according to the check sequence, when it is determined that the target hardware module is the currently specified hardware module to be checked, the verification of the check data packet includes: According to the obtained custom instruction, a check sequence for checking the plurality of hardware modules to be checked of the target device is obtained; or According to the plurality of hardware modules to be checked of the target device, a check sequence for checking the plurality of hardware modules to be checked of the target device is randomly generated.
[0009] In a possible implementation, the method further includes: after the target hardware module passes the check, the next hardware module to be checked is taken as the currently specified hardware module to be checked according to the check sequence, and the above steps of receiving the check data packet and checking the check data packet are repeated.
[0010] In a possible implementation, the method further includes: A check strategy of each hardware module to be checked in the plurality of hardware modules to be checked of the target device is determined in a custom or random allocation manner; each hardware module to be checked corresponds to M check strategies, and M is greater than or equal to 1; Hardware check notification information is sent to the target device; the hardware check notification information includes the check strategy corresponding to each module in the plurality of hardware modules to be checked; the check strategy is used to provide the hardware module to be checked to obtain the check data packet.
[0011] In a possible implementation, the target device is an image forming apparatus; the method further includes: Information of the currently specified hardware module to be checked is displayed; The method further includes:
[0012] In a second aspect, an embodiment of the present application provides a hardware check method, applied to a target device, and the method includes: A target hardware module is determined from a plurality of hardware modules to be checked of the target device, and a check data packet of the target hardware module is sent to a hardware check device; The verification data packet is used for the hardware verification device to verify the verification data packet according to the verification sequence when the target hardware module is determined as the currently specified hardware module to be verified.
[0013] In a possible implementation, the target hardware module is determined from the plurality of hardware modules to be verified of the target device, including: displaying a selection interface including information of the plurality of hardware modules to be verified of the target device; the target hardware module is determined through the selection interface in each round; and the number of the target hardware modules is one or more.
[0014] In a possible implementation, the target hardware module is determined through the selection interface in each round, including: the target hardware module is determined through the selection interface in each round according to the selection instruction issued by the user; the selection instruction is an instruction for determining the target hardware module in the selection interface according to the verification sequence; and the verification sequence is a sequence for verifying the plurality of hardware modules to be verified in the target device, which is randomly generated by the hardware verification device or obtained according to a custom instruction.
[0015] In a possible implementation, if the number of the target hardware modules is a plurality, the verification data packet of the target hardware module is sent to the hardware verification device, including: the verification data packet corresponding to the target hardware module is sent to the hardware verification device according to the verification sequence.
[0016] In a possible implementation, after the verification data packet of the target hardware module is sent to the hardware verification device, including: receiving a verification result sent by the hardware verification device; when the verification result indicates that the verification on the current target hardware module is successful, the target hardware module in the next round is determined through the selection interface; and the target hardware module in the next round is a module determined according to the verification sequence. when the verification result indicates that the verification on the current target hardware module fails, the target device is controlled to be locked, so that the target device is in an unusable state.
[0017] In a possible implementation, further including: receiving hardware verification notification information sent by the hardware verification device, so that each module in the plurality of hardware modules to be verified is verified to obtain a verification data packet according to a corresponding verification strategy; wherein each hardware module to be verified corresponds to M verification strategies, M≥1, and the verification strategy of each hardware module to be verified is determined by the hardware verification device in a custom or random allocation manner.
[0018] In a possible implementation, the target device is an image forming apparatus, and the plurality of hardware modules to be verified include any of an engine control module, a scanning control module, a laser scanning module, and a waste toner cartridge module.
[0019] In a third aspect, an embodiment of the present application provides a hardware verification device, comprising: a processor; a memory; and a computer program, wherein the computer program is stored in the memory, and the computer program comprises instructions, which, when executed by the processor, cause the processor to perform the method of any one of the first aspect.
[0020] In a fourth aspect, an embodiment of the present application provides an image forming apparatus, comprising: a processor; a memory; and a computer program, wherein the computer program is stored in the memory, and the computer program comprises instructions, which, when executed by the processor, cause the processor to perform the method of any one of the second aspect.
[0021] In a fifth aspect, an embodiment of the present application provides a hardware verification system, comprising: the hardware verification device of the third aspect; the image forming apparatus of the fourth aspect; wherein the hardware verification device and the image forming apparatus are in communication connection.
[0022] The hardware verification method, device, image forming apparatus and system provided by the present application at least have the following technical effects: In the present application, the hardware verification device receives the verification data packet of the target hardware module sent by the target device, and when the target hardware module is determined as the currently specified hardware module to be verified according to the verification order, the verification data packet is verified. The target hardware module is the module determined from the plurality of hardware modules to be verified of the target device. Moreover, the verification order is not unique, which is used to determine the currently specified hardware module to be verified when verifying the plurality of hardware modules to be verified of the target device. Furthermore, in each embodiment of the present application, the target hardware module can be determined from the hardware modules to be verified of the target device, and the target hardware module can be verified only when it conforms to the currently specified hardware module to be verified of the hardware verification device according to the non-unique verification order. Therefore, the verification order of the plurality of hardware modules to be verified of the target device can be changed, and the target device side needs to cooperate with each other. Thus, it can help to reduce the situation that the data is captured by others for replay attack and other malicious use in the verification process, and the target device is not actually verified. Each embodiment of the present application helps to improve the security and reliability of data verification between the hardware verification device and the target device. BRIEF DESCRIPTION OF DRAWINGS
[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.
[0024] Figure 1 An application scenario schematic diagram provided by an embodiment of the present application.
[0025] Figure 2 A flowchart of a hardware verification method provided by an embodiment of the present application.
[0026] Figure 3 A flowchart of another hardware verification method provided by an embodiment of the present application.
[0027] Figure 4 A structure schematic diagram of a hardware verification device provided by an embodiment of the present application.
[0028] Figure 5 A structure schematic diagram of an image forming device provided by an embodiment of the present application.
[0029] Figure 6 A method flowchart of hardware verification system interaction provided by an embodiment of the present application. DETAILED DESCRIPTION
[0030] For better understanding of the technical solutions of the present application, the embodiments of the present application are described in detail below with reference to the drawings.
[0031] It should be clear that the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.
[0032] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.
[0033] It should be understood that the term "and / or" used herein is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship.
[0034] For ease of understanding, the specific application scenario is first described by way of example as follows.
[0035] Referring to Figure 1 , a schematic diagram of an application scenario is provided for the embodiments of the present application. As Figure 1 shown, the application scenario includes a printer 101 and a computer 102. Wherein, the printer 101 and the computer 102 are interconnected through wired or wireless communication network for information transmission. It should be noted that Figure 1 the printer 101 shown in the figure is only an exemplary description of the target device, and should not be regarded as a limitation of the protection scope of the present application. For example, the target device includes but is not limited to printers, copiers, fax machines, multifunction image making and copying devices, electrostatic printing devices and any other similar devices. Figure 1 The computer 102 shown in the figure is only an exemplary description, and should not be regarded as a limitation of the protection scope of the present application. For example, the hardware verification device includes but is not limited to computers, mobile phones, tablet computers, enterprise internal servers, cloud servers and other electronic devices capable of communicating with the target device.
[0036] In combination with the above application scenario, in actual application, the printer will usually enter the "hardware module to be verified" state by default after the first power-on or factory reset, at which time the printer will not be able to provide normal image forming services.
[0037] In the related art, taking an image forming apparatus as an example, when the image forming apparatus enters a "hardware module to be verified" state, an administrator needs to operate a hardware verification device to complete verification of the hardware of the image forming apparatus, and the image forming apparatus will only then return to a normal working state.
[0038] Specifically, the hardware verification device sends a predetermined hardware verification strategy to the image forming apparatus, so that the relevant hardware in the image forming apparatus performs self-checking according to the predetermined verification strategy, and sends the self-checking result to the hardware verification device. The hardware verification device determines whether the hardware of the image forming apparatus passes the security verification according to the self-checking result, and controls the image forming apparatus to return to a normal working state.
[0039] Of course, in actual application, the hardware verification device will perform security verification on multiple hardware in the image forming apparatus. For example, the predetermined hardware verification strategy is to verify the multiple hardware in the image forming apparatus in turn according to a predetermined order and a predetermined verification strategy.
[0040] However, since the verification strategy for the image forming apparatus is predetermined, only a sufficient number of verification strategies and corresponding verification results need to be collected to deduce the corresponding hardware qualified verification result. Specifically, when the verification strategy issued to the image forming apparatus is captured, a fake verification result can be directly sent to the hardware verification device, thereby cheating the hardware verification device that the verification of the hardware of the image forming apparatus has been completed, thereby making it difficult for the hardware verification device to effectively perform security verification on the hardware of the image forming apparatus, and ultimately increasing the security risk of the image forming apparatus.
[0041] For example, taking multiple hardware modules to be verified in the image forming apparatus as an example. The verification order of the multiple hardware modules is a preset verification order. When performing hardware detection on the image forming apparatus, the hardware verification device will receive the verification result of the image forming apparatus according to the preset verification order. If a malicious attacker captures the image forming apparatus when it is performing hardware detection, it will send a verification qualified result to the hardware verification module according to the preset verification order, in order to cheat the hardware verification device to complete the security verification of the hardware module in the image forming apparatus. Overall, the hardware verification of the device in the prior art is not perfect.
[0042] To solve the above problems, in the embodiment of the present application, the hardware verification device receives the verification data packet of the target hardware module sent by the target device, and verifies the verification data packet when the target hardware module is determined as the currently specified hardware module to be verified according to the verification order. The target hardware module is the module determined from the plurality of hardware modules to be verified of the target device. The verification order is not unique, and is used to determine the currently specified hardware module to be verified when verifying the plurality of hardware modules to be verified of the target device. In the embodiment of the present application, the target hardware module can be determined from the hardware modules to be verified of the target device, and the target hardware module can be verified only when it conforms to the currently specified hardware module to be verified of the hardware verification device according to the non-unique verification order. Therefore, the verification order of the plurality of hardware modules to be verified of the device changes and needs to be coordinated with the target device. Thus, it can help to prevent the situation that the data is captured by others during the verification process and then a replay attack or other malicious use is performed, but the target device is not actually verified securely. The embodiment of the present application helps to improve the security and reliability of data verification between the hardware verification device and the target device. Specifically, the following will be described in detail in combination with the drawings and specific embodiments.
[0043] Referring to Figure 2 A flowchart of a hardware verification method provided by the embodiment of the present application is shown. The method can be applied to Figure 1 the application scenario shown in FIG. 1, as shown in FIG. 2, which mainly includes the following steps. Figure 2
[0044] Step S201: The hardware verification device receives the verification data packet of the target hardware module sent by the target device.
[0045] In the embodiment of the present application, the hardware verification device receives the verification data packet of the target hardware module sent by the target device. The verification data packet is used for the hardware verification device to verify the verification data packet when the target hardware module is determined as the currently specified hardware module to be verified according to the verification order.
[0046] In a possible implementation, the above target device is an image forming device, and the corresponding method flow is that the hardware verification device first displays the information of the currently specified hardware module to be verified, and then the hardware verification device waits to receive the verification data packet of the target hardware module sent by the image forming device when the image forming device enters the verification state.
[0047] In actual application, in order to further ensure the randomness of the corresponding verification strategy of different hardware modules, the hardware verification device can be set to select different verification strategies to perform security authentication on the hardware to be verified.
[0048] Specifically, in a possible implementation, the verification strategy of each to-be-verified hardware module in the plurality of to-be-verified hardware modules of the target device is determined in a self-defined or random allocation manner. Each to-be-verified hardware module corresponds to M verification strategies, and M is greater than or equal to 1.
[0049] It can be understood that each to-be-verified hardware corresponds to a plurality of verification strategies, and the hardware verification apparatus can randomly determine a verification strategy from the plurality of verification strategies corresponding to each to-be-verified hardware as the verification strategy of the to-be-verified hardware.
[0050] In the embodiment of the present application, the verification strategy corresponding to each to-be-verified hardware is not fixed before each verification of the target device, so that a malicious attacker is not easy to deduce the verification result corresponding to the qualified hardware, and to a certain extent, the risk of security verification of the hardware of the image forming apparatus is reduced.
[0051] Step S202: The hardware verification apparatus verifies the verification data packet when determining that the target hardware module is the currently specified to-be-verified hardware module according to the verification sequence.
[0052] In the embodiment of the present application, the hardware verification apparatus verifies the verification data packet when determining that the target hardware module is the currently specified to-be-verified hardware module according to the verification sequence.
[0053] As described above, the verification sequence is not unique, and the verification sequence is used to determine the currently specified to-be-verified hardware module when verifying the plurality of to-be-verified hardware modules of the target device.
[0054] In a possible implementation, when determining that the target hardware module is not the currently specified to-be-verified hardware module according to the verification sequence, a verification failure response is output.
[0055] In actual application, since there are a plurality of to-be-verified hardware modules, it is necessary to verify the verification data packet corresponding to each to-be-verified hardware module in turn. Specifically, in a possible implementation, after the target hardware module is verified to pass, the next to-be-verified hardware module is taken as the currently specified to-be-verified hardware module according to the verification sequence, and the above steps of receiving the verification data packet and verifying the verification data packet are repeated.
[0056] Exemplarily, the target device is an image forming apparatus, and the hardware modules to be verified include an engine control module, a scanning control module, a laser scanning module, and a waste toner cartridge module. The verification sequence includes multiple, and the verification sequence determined by the user this time or randomly generated is to sequentially perform security verification on the laser scanning module, the engine control module, the scanning control module, and the waste toner cartridge module. Specifically, the image forming apparatus first causes the laser scanning module to perform security verification according to the verification sequence; when the security verification of the laser scanning module is completed, the image forming apparatus causes the engine control module to perform security verification; and the like is sequentially performed. After the security verification is completed, the image forming apparatus uploads the verification data packets corresponding to the laser scanning module, the engine control module, the scanning control module, and the waste toner cartridge module to the hardware verification module according to the verification sequence in which the security verification is performed. Alternatively, the laser scanning module in the image forming apparatus performs security verification first according to the verification sequence, and when the security verification of the laser scanning module is completed, the verification data packet is sent to the hardware verification device; then the engine control module in the image forming apparatus performs security verification, and when the security verification of the engine control module is completed, the verification data packet is sent to the hardware verification device, and the like is sequentially performed.
[0057] In a possible implementation, the verification sequence described above is a sequence in which the hardware verification device verifies the multiple hardware modules to be verified in the target device randomly or according to the obtained custom instruction.
[0058] It can be understood that in actual application, when the verification sequence is a fixed verification sequence, the success probability of malicious attackers to speculate malicious interference with hardware security verification is relatively high. Therefore, in a possible implementation, the hardware verification device obtains the verification sequence in which the multiple hardware modules to be verified in the target device are verified according to the obtained custom instruction; or randomly generates the verification sequence in which the multiple hardware modules to be verified in the target device are verified.
[0059] The custom instruction is an instruction for autonomously setting and adjusting the verification sequence of the hardware module to be verified according to verification requirements. For example, the hardware modules to be verified this time are a first hardware module, a second hardware module, a third hardware module, a fourth hardware module, and a fifth hardware module. When the verification requirement is to verify the second hardware module first and the third hardware module last, the custom instruction can be set to adjust the verification sequence of the hardware module to be verified to be the second hardware module, the first hardware module, the fifth hardware module, the fourth hardware module, and the third hardware module in sequence.
[0060] It can be understood that before each time the target device is checked, the checking sequence of the N hardware modules to be checked is randomly generated by the hardware checking device, or the checking sequence of the N hardware modules to be checked is determined by the obtained custom instruction, which to some extent guarantees the randomness of the hardware checking sequence of the target device, reduces the possibility of remote replay attack by malicious attackers, and reduces the risk of security verification of the hardware of the target device.
[0061] In the embodiments of the present application, since the target hardware module in the hardware modules to be checked can be determined on the target device side, and the target hardware module can be checked only when it conforms to the currently specified hardware module to be checked according to the non-unique checking sequence. Therefore, the checking sequence of the plurality of hardware modules to be checked of the device changes and needs to be coordinated with the target device side. Thus, it can help to prevent the situation that the data is captured by others during the checking process and then replay attack and other malicious use are performed, and the target device is actually not subjected to security checking.
[0062] Corresponding to the above method, the present application also provides another hardware checking method. Specifically, it is described in detail below in combination with the drawings and specific embodiments.
[0063] Referring to Figure 3 The flowchart of another hardware checking method provided by the embodiments of the present application is shown. The method can be applied to Figure 1 the application scenario as shown, such as Figure 3 which mainly includes the following steps.
[0064] Step S301: The target device determines a target hardware module from a plurality of hardware modules to be checked of the target device, and sends a checking data packet of the target hardware module to a hardware checking device.
[0065] In the embodiments of the present application, the target device determines a target hardware module from a plurality of hardware modules to be checked, and sends a checking data packet of the target hardware module to a hardware checking device. It can be understood that the checking data packet is used for the hardware checking device to check the checking data packet when the target hardware module is determined to be the currently specified hardware module to be checked according to the checking sequence. The checking sequence is not unique, and is used to determine the currently specified hardware module to be checked when checking the plurality of hardware modules to be checked of the target device.
[0066] Specifically, in a possible implementation, when the target device is an image forming device, the hardware modules to be checked usually include any of the engine control module, the scanning control module, the laser scanning module, and the waste toner box module. Of course, the image forming device also includes other hardware modules to be checked, which are not limited by the present application.
[0067] In actual application, the target hardware module can be determined directly from the relevant selection interface of the target device. Specifically, in a possible implementation, a selection interface including information of a plurality of to-be-verified hardware modules of the target device is displayed; and the target hardware module is determined through the selection interface in each round.
[0068] It should be noted that the number of target hardware modules selected in each round can be one or multiple, which is not limited in the present application.
[0069] For example, the names corresponding to the N to-be-verified hardware modules are output on the display screen of the target device; and then the target hardware module is determined in response to a hardware selection operation triggered by the user.
[0070] Of course, when no hardware selection operation of the user is detected within the preset time, a voice prompt or the hardware security authentication of the target device can be exited at this time.
[0071] In the embodiments of the present application, the information of a plurality of to-be-verified hardware modules can be displayed on the selection interface of the target device, so that the target hardware module can be selected through the selection interface in each round, so as to send the verification data packet of the target hardware module to the hardware verification device. Further, the diversification of the hardware verification sequence can be improved, the limitation can be reduced, and the verification of the currently specified to-be-verified hardware module can be completed in cooperation with the hardware verification device. Further, the target hardware module can be selected flexibly according to the non-unique verification sequence of the hardware verification device, and the verification can be passed only when the two match. Further, the situation that the verification mode of the fixed verification sequence is easily attacked by malicious replay attacks after the data is captured can be prevented. To some extent, the risk of security verification of the hardware of the target device is reduced.
[0072] In order to ensure synchronization with the hardware verification device side, the operator can determine the target hardware module from the plurality of to-be-verified hardware modules according to the verification sequence. Specifically, in a possible implementation, the target hardware module is determined through the selection interface in each round according to the selection instruction issued by the user.
[0073] In a possible implementation, the hardware verification device displays the verification sequence, so that the target hardware module can be determined from the plurality of to-be-verified hardware modules according to the verification sequence.
[0074] In a possible implementation, when the number of target hardware modules is multiple, the verification data packet corresponding to each target hardware module is sent to the hardware verification device according to the verification sequence.
[0075] It can be understood that after the plurality of target hardware modules are selected in the selection interface according to the check order, the target device can send the check data packets in turn according to the check order.
[0076] Further, after each to-be-checked hardware module matches the corresponding check strategy, the target device receives the hardware check notification information sent by the hardware check device, so that each module in the plurality of to-be-checked hardware modules checks to obtain the check data packet according to the corresponding check strategy.
[0077] In the method, each to-be-checked hardware module corresponds to M check strategies, M≥1, and the check strategy of each to-be-checked hardware module is determined by the hardware check device through a self-defined or random allocation manner.
[0078] After the target device sends the check data packet of the target hardware module to the hardware check device, the hardware check device usually needs to feed back the check result to the target device. Specifically, in a possible implementation, the target device receives the check result sent by the hardware check device; when the check result indicates that the current target hardware module is checked successfully, the next round of target hardware module is determined through the selection interface, wherein the next round of target hardware module is the module determined according to the check order; when the check result indicates that the current target hardware module is checked unsuccessfully, the target device is controlled to be locked, so that the target device is in an unusable state.
[0079] It can be understood that when the check fails, the target device controls the lock to ensure the safety of the target device; when the check succeeds, the target device continues to perform the security verification of the next to-be-checked hardware according to the check order. To some extent, the risk of security verification of the hardware of the target device is reduced.
[0080] In the embodiment of the present application, the hardware verification device receives the verification data packet of the target hardware module sent by the target device, and when the target hardware module is determined to be the currently specified hardware module to be verified according to the verification order, the verification data packet is verified. The target hardware module is the module determined from the plurality of hardware modules to be verified of the target device. The verification order is not unique, and is used to determine the currently specified hardware module to be verified when verifying the plurality of hardware modules to be verified of the target device. In the embodiment of the present application, the target hardware module can be determined from the hardware modules to be verified of the target device, and the target hardware module can be verified according to the non-unique verification order, and the target hardware module needs to be consistent with the currently specified hardware module to be verified of the hardware verification device. Therefore, the verification order of the plurality of hardware modules to be verified of the device changes, and needs to be coordinated with the target device. Thus, it can help to reduce the situation that the data is captured by others for replay attack and other malicious use in the verification process, and the target device is not actually verified. The embodiment of the present application helps to improve the security and reliability of data verification between the hardware verification device and the target device.
[0081] In actual application, the verification result can be determined based on different verification strategies according to the above-mentioned steps. Specifically, in a possible implementation, the verification strategy includes an encryption algorithm and a digest algorithm, so that the verification data packet and the verification result can be determined based on the encryption algorithm and the digest algorithm. Of course, those skilled in the art can determine the verification result by other algorithms according to actual needs, and the present application does not make specific limitations thereto.
[0082] In a possible implementation, the above-mentioned verification data packet includes an identifier of the target hardware module and verification data. For determination of the verification result, in a possible implementation, it specifically includes: decrypting the verification data by taking the identifier information of the target hardware module as a key according to a preset encryption algorithm, to obtain a first hash value and plaintext information; if the plaintext information matches the identifier information of the target hardware module, calculating the first hash value according to a preset digest algorithm to obtain a second hash value; and if the first hash value matches the second hash value, the verification of the target hardware module is passed.
[0083] Corresponding to the above-mentioned embodiment, the present application also provides a hardware verification device. Referring to Figure 4A structural schematic diagram of a hardware verification device provided in an embodiment of the present application is shown in FIG. 4. The hardware verification device 400 can include a processor 401, a memory 402, and a communication unit 403. These components communicate through one or more buses. Those skilled in the art can understand that the structure of the hardware verification device shown in the figure does not constitute a limitation on the embodiments of the present application. It can be a bus structure, a star structure, or include more or fewer components, or combine certain components, or have a different arrangement of components.
[0084] The communication unit 403 is configured to establish a communication channel, so that the hardware verification device can communicate with other devices. It receives user data sent by other devices or sends user data to other devices.
[0085] The processor 401 is the control center of the hardware verification device. It connects various parts of the hardware verification device through various interfaces and lines, executes software programs, instructions, and / or modules stored in the memory 402, and calls data stored in the memory, to perform various functions of the hardware verification device and / or process data. The processor can be composed of an integrated circuit (IC), for example, a single packaged IC, or multiple packaged ICs connected together. For example, the processor 401 can only include a central processing unit (CPU). In the embodiments of the present application, the CPU can be a single operation core or include multiple operation cores.
[0086] The memory 402 is configured to store execution instructions of the processor 401. The memory 402 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, a magnetic disk, or an optical disk.
[0087] When the execution instructions in the memory 402 are executed by the processor 401, the hardware verification device 400 can perform Figure 2 some or all of the steps in the embodiments shown in the figure.
[0088] Corresponding to the above-mentioned embodiments, the present application also provides an image forming device. Referring to Figure 5A structural schematic diagram of an image forming apparatus provided by an embodiment of the present application is shown in FIG. 1. The image forming apparatus 500 can include a processor 501, a memory 502, and a communication unit 503. These components communicate via one or more buses. Those skilled in the art can understand that the structure of the image forming apparatus shown in the figure does not constitute a limitation on the embodiments of the present application. It can be a bus structure or a star structure. It can also include more or fewer components than shown in the figure, or combine certain components, or arrange different components.
[0089] The communication unit 503 is configured to establish a communication channel, so that the image forming apparatus can communicate with other devices. It receives user data sent by other devices or sends user data to other devices.
[0090] The processor 501 is the control center of the image forming apparatus. It connects various parts of the image forming apparatus via various interfaces and lines, executes software programs, instructions, and / or modules stored in the memory 502, and calls data stored in the memory, to perform various functions of the image forming apparatus and / or process data. The processor can be composed of integrated circuits (ICs), such as a single packaged IC or multiple packaged ICs connected together. For example, the processor 501 can only include a central processing unit (CPU). In the embodiments of the present application, the CPU can be a single operation core or include multiple operation cores.
[0091] The memory 502 is configured to store execution instructions for the processor 501. The memory 502 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.
[0092] When the execution instructions in the memory 502 are executed by the processor 501, the image forming apparatus 500 can perform Figure 3 some or all of the steps in the embodiments shown.
[0093] In specific implementations, the present application also provides a hardware verification system, which specifically includes the hardware verification device of the above embodiments and the image forming apparatus of the above embodiments. The hardware verification device is communicatively connected to the image forming apparatus.
[0094] Specifically, for ease of understanding, see Figure 6 A hardware verification system interaction method flowchart is provided for the embodiments of the present application. As shown in the figure, the target device includes a control module and a hardware module to be verified. The method mainly includes the following steps.
[0095] Step S601: The hardware verification device obtains the verification order for verifying the plurality of hardware modules to be verified of the target device according to the acquired custom instruction, or randomly generates the verification order for verifying the plurality of hardware modules to be verified of the target device according to the plurality of hardware modules to be verified of the target device.
[0096] Step S602: The hardware verification device determines the verification strategy of each hardware module to be verified in the plurality of hardware modules to be verified of the target device in a custom or random allocation manner.
[0097] Step S603: The hardware verification device sends hardware verification notification information to the target device.
[0098] Step S604: The control module displays a selection interface including the information of the plurality of hardware modules to be verified of the target device.
[0099] Step S605: The control module determines the target hardware module through the selection interface according to the acquired selection instruction corresponding to the verification order issued by the user in each round.
[0100] Step S606: The control module sends the corresponding verification strategy to the target hardware module.
[0101] Step S607: The target hardware module determines the verification data packet according to the verification strategy.
[0102] Specifically, in a possible implementation manner, the verification strategy includes an encryption algorithm and a digest algorithm, and thus the verification data packet can be determined based on the encryption algorithm and the digest algorithm.
[0103] Step S608: The target hardware module sends the verification data packet to the control module.
[0104] Step S609: The control module sends the verification data packet corresponding to the target hardware module to the hardware verification device in the verification order.
[0105] Step S610: The hardware verification device verifies the verification data packet to obtain the verification result when the target hardware module is determined to be the currently specified hardware module to be verified in the verification order.
[0106] In a possible implementation, the check data packet comprises the identifier of the target hardware module and the check data. In a possible implementation, the determining of the check result comprises: decrypting the check data by taking the identifier information of the target hardware module as a key according to a preset encryption algorithm to obtain a first hash value and plaintext information; if the plaintext information matches the identifier information of the target hardware module, calculating the first hash value according to a preset digest algorithm to obtain a second hash value; and if the first hash value matches the second hash value, the check of the target hardware module is passed.
[0107] Step S611: The hardware check device sends the check result to the control module.
[0108] Step S612: When the check result indicates that the check of the current target hardware module fails, the target device is locked to make the target device in an unusable state; and when the check result indicates that the check of the current target hardware module succeeds, the next round of target hardware module is determined through the selection interface.
[0109] In the embodiment of the application, the target hardware module in the hardware modules to be checked can be determined on the target device side, and the target hardware module can be checked only when it matches the hardware module to be checked currently specified by the hardware check device according to the non-unique check order. Therefore, the check order of the hardware modules to be checked of the device can change and needs to be coordinated with the target device side. Thus, it can help to reduce the situation that the data is captured by others for replay attack and other malicious use in the check process, and the target device is actually not checked safely.
[0110] For brevity of description, the specific content can refer to the method embodiment part described above, which is not repeated here.
[0111] In a specific implementation, the application further provides a computer storage medium, wherein the computer storage medium can store a program, and the program can include some or all steps in each embodiment of the simulation scene generation method provided by the application when executed. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM) or a random access memory (RAM), etc.
[0112] In a specific implementation, the application further provides a computer program product, wherein the computer program product contains executable instructions, and when the executable instructions are executed on a computer, the computer executes some or all steps in each embodiment of the simulation scene generation method provided by the application.
[0113] In the embodiments of the present application, "at least one" means one or more, and "multiple" means two or more. The "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent the cases of A alone, A and B together, and B alone. Wherein A and B can be singular or plural. The character " / " generally represents an "or" relationship between the front and rear associated objects. "At least one of the following" and the like means any combination of these items, including any combination of single or multiple items. For example, at least one of a, b and c can represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c can be single or multiple.
[0114] Those of ordinary skill in the art can appreciate that the units and algorithm steps described in the embodiments disclosed herein can be implemented in electronic hardware, computer software and combination of the two. Whether the functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.
[0115] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working process of the above-described system, device and unit can refer to the corresponding process in the foregoing method embodiments, which will not be described here.
[0116] In several embodiments provided in the present application, any function realized in the form of a software function unit and sold or used as an independent product can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the parts that make contributions to the prior art or parts of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various media that can store program codes.
[0117] In the present specification, the same or similar parts among various embodiments can be referred to each other. In particular, for the device embodiments and the terminal embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can refer to the description in the method embodiments.
Claims
1. A hardware verification method, characterized in that: Applied to a hardware verification device, the method includes: receiving a verification data packet of a target hardware module sent by a target device; the target hardware module is a module determined from a plurality of hardware modules to be verified in the target device; When it is determined that the target hardware module is the currently designated hardware module to be verified according to the verification order, verifying the verification data packet; The verification sequence is not unique and is used to determine the currently designated hardware module to be verified when verifying multiple hardware modules to be verified on the target device.
2. The method according to claim 1, characterized in that Also includes: When it is determined according to the verification sequence that the target hardware module is not the currently designated hardware module to be verified, a verification failure response is output.
3. The method according to claim 1, characterized in that When it is determined that the target hardware module is the currently designated hardware module to be verified according to the verification order, the verification data packet is verified, which includes: Obtaining a verification order for verifying multiple hardware modules to be verified on the target device according to the obtained custom instructions; or A verification order for verifying the multiple hardware modules to be verified of the target device is randomly generated according to the multiple hardware modules to be verified of the target device.
4. The method according to any one of claims 1 or 3, characterized in that Also includes: After the target hardware module is verified, the next hardware module to be verified is used as the currently designated hardware module to be verified according to the verification order, and the above steps of receiving the verification data packet and verifying the verification data packet are repeated.
5. The method according to claim 1, wherein Receive the verification data packet of the target hardware module sent by the target device, which also includes: Determining a verification strategy for each of the multiple hardware modules to be verified of the target device by a customized or random allocation method; each hardware module to be verified corresponds to M verification strategies, where M ≥ 1; Sending hardware verification notification information to the target device; the hardware verification notification information includes a verification strategy corresponding to each module in a plurality of hardware modules to be verified; the verification strategy is used to provide the hardware module to be verified to obtain the verification data packet.
6. The method according to claim 1, characterized in that The target device is an image forming apparatus; Receive the verification data packet of the target hardware module sent by the target device, which also includes: Display the information of the currently specified hardware module to be verified; Waiting to receive a verification data packet of the target hardware module sent by the image forming apparatus when entering a verification state.
7. A hardware verification method, characterized in that: Applied to a target device, the method includes: Determine a target hardware module from a plurality of hardware modules to be verified of the target device, and send a verification data packet of the target hardware module to a hardware verification device; Among them, the verification data packet is used by the hardware verification device to verify the verification data packet when determining that the target hardware module is the currently designated hardware module to be verified according to the verification order; the verification order is not unique, and is used to determine the currently designated hardware module to be verified when verifying multiple hardware modules to be verified of the target device.
8. The method according to claim 7, characterized in that Determining a target hardware module from a plurality of hardware modules to be verified of the target device includes: Displaying a selection interface including information of multiple hardware modules to be verified of the target device; The target hardware module is determined through the selection interface in each round; the number of the target hardware modules is one or more.
9. The method according to claim 8, characterized in that Determining the target hardware module through the selection interface in each round includes: According to the selection instructions issued by the user, the target hardware module is determined through the selection interface in each round; the selection instructions are instructions for determining the target hardware module in the selection interface according to the verification order; the verification order is the order of verifying multiple hardware modules to be verified in the target device, which is randomly generated by the hardware verification device or obtained according to the custom instructions obtained.
10. The method according to claim 9, characterized in that If there are multiple target hardware modules, sending the verification data packets of the target hardware modules to the hardware verification device includes: The verification data packets corresponding to the target hardware modules are sent to the hardware verification device respectively according to the verification order.
11. The method according to claim 8, characterized in that Sending the verification data packet of the target hardware module to the hardware verification device, and then comprising: Receiving a verification result sent by the hardware verification device; When the verification result indicates that the verification of the current target hardware module is successful, the target hardware modules for the next round are determined on the selection interface; the target hardware modules for the next round are modules determined according to the verification order; When the verification result indicates that the verification of the current target hardware module fails, the target device is controlled to lock, so that the target device is in an unusable state.
12. The method according to claim 7, characterized in that Also includes: Receive hardware verification notification information sent by the hardware verification device, so that each module in the multiple hardware modules to be verified is verified according to the corresponding verification strategy to obtain a verification data packet; wherein each hardware module to be verified corresponds to M verification strategies, M ≥ 1, and the verification strategy of each hardware module to be verified is determined by the hardware verification device through customization or random allocation.
13. The method according to claim 7, characterized in that The target device is an image forming apparatus, and the plurality of hardware modules to be verified include any one of an engine control module, a scanning control module, a laser scanning module, and a waste toner box module.
14. A hardware verification device, characterized in that: include: processor; Memory; and a computer program, wherein the computer program is stored in the memory, and the computer program comprises instructions, which, when executed by the processor, cause the processor to perform the method according to any one of claims 1 to 6.
15. An image forming apparatus, characterized in that: include: processor; Memory; and a computer program, wherein the computer program is stored in the memory, and the computer program comprises instructions, which, when executed by the processor, cause the processor to perform the method according to any one of claims 7 to 13.
16. A hardware verification system, characterized in that: include: The hardware verification device according to claim 14; The image forming device according to claim 15; Wherein, the hardware verification device is communicatively connected to the image forming device.