A memory access method, device, storage medium and program product

Abstract

The application discloses a memory access method and device, a storage medium and a program product, relates to the technical field of memory access, and comprises the following steps: monitoring memory access information of a target memory; the memory access information comprises a page fault address sequence during memory access, address distribution characteristics when an address translation failure event occurs in an address translation lookaside buffer, a cross-node access event and a virtual memory access frequency; corresponding target feature information is determined; the target feature information comprises spatial locality, heat density, access dispersion and imbalance data; a current memory access mode is determined based on the target feature information, and a target access strategy is determined from preset memory access strategies configured with different memory page table prefetch rules to access the memory. By quantifying the memory access feature information through the memory access information, determining the corresponding memory access mode, and executing the corresponding memory page table prefetch rule, the traversal delay of the multi-level page table can be reduced, the memory bandwidth can be fully utilized, and the memory access performance can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory access, and particularly relates to a memory access method, device, storage medium and program product. BACKGROUND

[0002] With the development of cloud computing and big data, the server memory capacity has jumped from GB level to TB level, which poses a severe challenge to the memory management mechanism of the Linux kernel. The traditional page table mechanism gradually loses its effectiveness in dealing with large-scale memory. The traversal path of the 5-level page table needs to pass through more levels of memory access, and each address translation consumes additional clock cycles, directly leading to a significant increase in memory access delay.

[0003] Meanwhile, the TB-level memory makes the coverage range of the TLB (Translation Lookaside Buffer, address translation backup buffer) relatively insufficient, and a large number of address translations cannot hit the TLB, forcing the page table traversal to be triggered, further aggravating the performance loss. However, the existing prefetch technology only supports fixed-depth single-level page table entry (PTE) prefetch, resulting in that in the non-continuous access scenario, most of the prefetch operations are invalid, wasting memory bandwidth. SUMMARY

[0004] The present application provides a memory access method, device, storage medium and program product, which quantifies memory access feature information through memory access information, determines the corresponding memory access mode, and executes the corresponding memory page table prefetch rule, solving the problem of memory bandwidth waste caused by single-level page table entry prefetch, reducing the traversal delay of multi-level page table, and fully utilizing the memory bandwidth to improve the memory access performance.

[0005] The present application provides a memory access method, comprising:

[0006] monitoring memory access information of a target memory; the memory access information includes a sequence of page fault addresses during memory access, address distribution characteristics of the address translation backup buffer when an address translation failure event occurs, cross-node access events and virtual memory access frequency;

[0007] determining target feature information corresponding to the memory access information; the target feature information includes spatial locality representing the strength of the continuity of the page fault addresses, heat density representing the high and low of the access frequency, access dispersion representing the concentration degree of the memory access, and imbalance data representing the proportion of remote access;

[0008] determining a current memory access mode of the target memory based on the target feature information;

[0009] The target access strategy corresponding to the current memory access mode is determined from the preset memory access strategies, and the target memory is accessed based on the target access strategy; different memory page table prefetch rules are configured in different preset memory access strategies.

[0010] The application further provides an electronic device, comprising a memory for storing a computer program, and a processor for executing the computer program to implement the steps of any of the memory access methods.

[0011] The application further provides a computer readable storage medium, which stores a computer program, wherein the computer program is executed by a processor to implement the steps of any of the memory access methods.

[0012] The application further provides a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the steps of any of the memory access methods.

[0013] The application can first monitor memory access information of the target memory; the memory access information comprises a sequence of page fault addresses during memory access, address distribution characteristics of an address translation buffer when an address translation failure event occurs, a cross-node access event, and a virtual memory access frequency; target feature information corresponding to the memory access information is determined; the target feature information comprises spatial locality representing a strength of continuity of the page fault addresses, heat density representing a level of the access frequency, access dispersion representing a degree of concentration of the memory access, and imbalance data representing a proportion of remote access; then, a current memory access mode of the target memory is determined based on the target feature information, and a target access strategy corresponding to the current memory access mode of the target memory is determined from preset memory access strategies configured with different memory page table prefetch rules, so as to access the target memory based on the target access strategy.

[0014] Through the application, memory access feature information comprising spatial locality, time heat density, access dispersion, and imbalance degree can be quantitatively obtained from memory access information of the target memory, and a corresponding memory access mode can be determined according to the memory access feature information, so as to access the target memory according to the corresponding memory page table prefetch rule. In this way, different memory page table prefetch modes are triggered according to different memory access modes, which can reduce the traversal delay of the multi-level page table, reduce the overhead of the address translation buffer, shorten the page fault path, avoid memory bandwidth waste caused by single-level page table prefetching, help to reduce the workload of subsequent memory access error correction, fully utilize the memory bandwidth, and improve the memory access performance. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. Obviously, the drawings described below are only some of the embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0016] Figure 1 A memory access method flow chart provided for the embodiments of the present application;

[0017] Figure 2 A memory access architecture diagram provided for the embodiments of the present application;

[0018] Figure 3 A memory access feature information calculation schematic diagram provided for the embodiments of the present application;

[0019] Figure 4 A memory access device structure schematic diagram provided for the embodiments of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be described clearly and completely in the following with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without any creative effort are within the protection scope of the present application.

[0021] It should be noted that, in the description of the present application, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the processes, methods, articles or devices comprising a series of elements not only include those elements, but also include other elements not explicitly listed or inherent to such processes, methods, articles or devices. The terms "first", "second" and the like in the present application are used to distinguish similar objects, not to describe a specific order or sequence.

[0022] With the leap of server memory capacity, the traversal path of the traditional page table mechanism needs to pass through more levels of memory access, and each address translation consumes additional clock cycles, which directly leads to a significant increase in memory access delay. At the same time, the TB-level memory makes the coverage range of the TLB relatively insufficient, further exacerbating performance loss. However, the existing prefetch technology only supports fixed-depth single-level page table item prefetching, while the present application quantifies memory access feature information through memory access information, determines the corresponding memory access mode, and executes the corresponding memory page table prefetch rule, which can reduce the traversal delay of multi-level page table, fully utilize the memory bandwidth and improve the memory access performance.

[0023] In order to enable the person skilled in the art to better understand the present application, the present application will be further described in detail below in combination with the drawings and specific embodiments.

[0024] Next, the present embodiment will be described in detail in combination with the execution flow of the memory access method, as shown in Figure 1 The present embodiment provides a memory access method, comprising:

[0025] Step S11, monitoring memory access information of the target memory; the memory access information comprises a page fault address sequence during memory access, address distribution characteristics of the address translation lookaside buffer when an address translation failure event occurs, a cross-node access event, and a virtual memory access frequency.

[0026] First of all, it needs to be pointed out that, as shown in Figure 2 The system architecture for memory access comprises a monitoring layer, an analysis layer, an execution layer, and a calibration layer, wherein the monitoring layer is responsible for collecting a page fault address sequence, a TLB Miss distribution (address translation lookaside buffer miss), a cross- NUMA (Non-Uniform Memory Access) node access event, a VMA (Virtual Memory Area) access frequency indicator, calculating spatial locality, temporal locality, access dispersion, and NUMA imbalance degree data; the analysis layer outputs a memory access mode label through four-dimensional data analysis of the monitoring layer, and generates an execution strategy according to the mode label; the execution layer issues an execution action according to the execution strategy, and dynamically adjusts a prefetch depth; the calibration layer reevaluates the label accuracy every preset time interval, and corrects a mode misjudgment. In this way, by constructing a dynamic labeling method based on memory access mode modeling, a collaborative optimization system of multi-level prefetching is established, the page table traversal path depth is optimized, a four-layer structure of “monitoring-analysis-execution-calibration” is adopted, a closed-loop control system is formed, and a breakthrough performance improvement scheme is provided for a TB-level memory system. It can be understood that the TLB is an SRAM (Static Random-Access Memory) cache on a processor chip, which stores “virtual page number→physical page frame” mapping items.

[0027] In the present embodiment, the memory access information of the target memory can be first monitored by using a preset monitoring layer. The memory access information comprises a page fault address sequence during memory access, address distribution characteristics of the address translation lookaside buffer when an address translation failure event occurs, a cross-node access event, and a virtual memory access frequency.

[0028] Step S12, determine the target feature information corresponding to the memory access information; the target feature information includes spatial locality representing the continuity of the page fault address, heat density representing the access frequency, access dispersion representing the memory access concentration, and imbalance data representing the remote access proportion.

[0029] In this embodiment, the target feature information corresponding to the memory access information can be determined. The target feature information includes spatial locality representing the continuity of the page fault address, heat density representing the access frequency, access dispersion representing the memory access concentration, and imbalance data representing the remote access proportion. That is, the embodiment can calculate spatial locality, temporal locality, access dispersion, and NUMA imbalance data by collecting page fault address sequence, TLB Miss distribution, cross- NUMA node access event, and VMA access frequency index.

[0030] Step S13, determine the current memory access mode of the target memory based on the target feature information.

[0031] In this embodiment, the current memory access mode of the target memory can be determined based on the target feature information. Specifically, the memory access mode includes a first memory access mode for continuous access, a second memory access mode for random access, a third memory access mode for accessing cold zone data, a fourth memory access mode for accessing hot zone data, a fifth memory access mode for intensive access, and a sixth memory access mode for sparse access; wherein the cold zone data is data with an access frequency satisfying a preset low frequency condition, and the hot zone data is data with an access frequency satisfying a preset high frequency condition. In this way, based on the four-dimensional quantization memory model of space-time-dispersion-NUMA, the six memory access modes are accurately identified by spatial variance, heat density, dispersion, and imbalance ratio, and the memory access label is generated, which helps to design a hierarchical prefetch mechanism driven by memory access mode and realize a multi-level memory collaborative management method.

[0032] In a specific embodiment, if the value corresponding to the spatial locality is less than a first preset threshold, the current memory access mode of the target memory is determined to be the first memory access mode; if the value corresponding to the spatial locality is greater than a second preset threshold, the current memory access mode of the target memory is determined to be the second memory access mode; wherein the second preset threshold is greater than the first preset threshold. Specifically, the adjacent addresses in the page fault address sequence can be determined, and the corresponding difference sequence can be determined according to the adjacent addresses, then the variance of the difference sequence is determined, and the variance is taken as the spatial locality. That is, as shown in Figure 3 the spatial locality, i.e. spatial variance When calculating the spatial locality, the input data is the virtual address sequence of the page fault interrupt, and the difference sequence of adjacent page fault addresses is first extracted:

[0033] ;

[0034] Then the variance of the difference sequence is calculated:

[0035] ;

[0036] wherein, represents the corresponding virtual address when the i-th page fault exception occurs; represents the difference between the adjacent two page fault addresses; n represents the number of adjacent page fault address differences participating in the calculation of the variance; represents the average value. And, the low variance indicates strong address continuity, and the high variance indicates strong address jump. Correspondingly, after receiving the four-dimensional data transmitted by the monitoring layer, the analysis layer first performs in-depth analysis on each index, wherein the spatial variance is a core quantitative index for measuring address continuity, and the numerical value is significantly negatively correlated with the continuity of memory access. For example: when σ2<5, it indicates that the memory access address presents extremely strong continuity in space, and in such a scenario, data is often accessed in the form of continuous blocks; and when σ2>50, it indicates that the address sequence presents violent jump, which belongs to a typical random access mode.

[0037] In another specific embodiment, the heat density of the target memory can be determined based on the virtual memory access frequency and the address distribution characteristics; if the heat density is less than a third preset threshold, it is determined that the current memory access mode of the target memory is a third memory access mode; if the heat density is greater than a fourth preset threshold, it is determined that the current memory access mode of the target memory is a fourth memory access mode; wherein the fourth preset threshold is greater than the third preset threshold. And when determining the heat density of the target memory, a preset sliding time window corresponding to the target memory can be determined, the memory access frequency in the preset sliding time window is determined based on the virtual memory access frequency, the initial heat density value is determined based on the memory access frequency and the preset sliding time window, and then the initial heat density value is adjusted based on the address distribution characteristics to obtain the heat density. That is, as shown in Figure 3 , when calculating the temporal locality, i.e. the heat density, the input data is the VMA access frequency: the number of accesses to a specific address range in a unit time window; the TLB Miss distribution: the marking of the high-frequency TLB Miss region. For example, in a 10ms sliding time window:

[0038] ;

[0039] And, the TLB Miss hotspot map can also be combined with heat density weighting in the embodiment. For example, the area with a TLB Miss rate > 30% is weighted by heat density x 1.5. The heat density can intuitively reflect the "hotness" characteristics of the memory region through the access frequency in the unit time window, so according to the calculation result, the high-density is used for hot region identification, and the low-density is used for cold region identification. For example, when the heat density > 60 times / ms, the region is marked as a hot region, and such a region is usually the core data area of the program; when the heat density < 10 times / ms, it is determined as a cold region, which is usually low-frequency access archived data or temporary cache.

[0040] In another specific embodiment, the access dispersion of the target memory can be determined based on the page fault address sequence; if the access dispersion is less than a fifth preset threshold, it is determined that the current memory access mode of the target memory is a fifth memory access mode; if the access dispersion is greater than a sixth preset threshold, it is determined that the current memory access mode of the target memory is a sixth memory access mode; wherein the sixth preset threshold is greater than the fifth preset threshold. Specifically, when determining the access dispersion of the target memory, the target address sequence corresponding to the page fault address sequence in the preset time period can be determined, and the number of page fault addresses corresponding to the target address sequence can be determined based on the target address sequence; wherein the addresses in the target address sequence are non-repeated page fault addresses; then the global memory access times in the preset time period are determined by using the performance monitoring device, and then the access dispersion of the target memory is determined based on the number of page fault addresses and the global memory access times. That is, as shown in Figure 3

[0041] ;

[0042] The access dispersion quantifies the dispersion degree of memory access, and high dispersion degree represents high dispersion of memory access, which belongs to sparse random access type; low dispersion degree represents concentrated memory access, which belongs to intensive sequential access. For example, when the dispersion degree > 0.8, it indicates that the address of each access is mostly a new address, which belongs to sparse access mode; when the dispersion degree < 0.2, the access is concentrated in a limited address range, which constitutes intensive access.

[0043] In another specific embodiment, the imbalance degree data of the target memory can also be determined based on the cross-node access event; if the imbalance degree data is greater than a seventh preset threshold, a target label for representing the prohibition of cross-node access is generated. Correspondingly, during the process of accessing the target memory based on the target access strategy, if the target label is detected, the corresponding memory access operation is performed based on the local target memory. That is, as shown in​Figure 3 As shown, when the input data is a cross- NUMA node access event corresponding to a remote access record, the corresponding NUMA imbalance degree can be determined to identify the local / remote access ratio and locate the optimization target node of memory binding. Among them:

[0044] ;

[0045] The NUMA imbalance ratio focuses on the cross-node access efficiency. For example, when the ratio is greater than 0.3, it means that more than 30% of memory access needs to be performed across NUMA nodes, which will cause significant delay overhead. At this time, the NUMA_BIND tag is forcibly added. And when subsequent memory access is performed, if it contains the NUMA_BIND tag, the local NUMA node is identified to set the memory policy to MPOL_BIND. In this way, by identifying the local / remote NUMA node ratio in memory access through the imbalance ratio, the optimization target node of memory binding is located, the delay caused by cross-node access is reduced, and the performance loss caused by the fact that the cross-node memory access delay of the TB-level memory system commonly using multi- NUMA node architecture is much higher than the local access can be accurately located and reduced.

[0046] And in the process of determining the current memory access mode of the target memory based on the target feature information, if the target memory corresponds to multiple memory access modes, the target access mode is determined as the current memory access mode according to a preset priority order; wherein the target access mode is the mode with the highest priority among the multiple memory access modes, and the preset priority order from high to low is: the fourth memory access mode, the first memory access mode, the fifth memory access mode, the second memory access mode, the third memory access mode, and the sixth memory access mode. That is, when performing memory access, the analysis layer strictly follows the priority rule of "hot zone mode>sequential mode>dense mode>random mode>cold zone mode> sparse mode". Specifically, this rule is based on the influence weight of different modes on system performance: the hot zone access frequency is the highest and the optimization benefit is the largest; the sequential mode and the dense mode have good predictability, low optimization cost and significant effect; the random mode has a large optimization difficulty and a relatively later priority; the cold zone and the sparse mode have less constraint on system performance, so they are placed at the end.

[0047] Step S14, determining the target access strategy corresponding to the current memory access mode from each preset memory access strategy, and accessing the target memory based on the target access strategy; wherein different memory page table prefetch rules are configured in different preset memory access strategies.

[0048] In the embodiment, the target access strategy corresponding to the current memory access mode can be determined from each preset memory access strategy configured with different memory page table prefetch rules, and the target memory is accessed based on the target access strategy. In addition, the preset memory access strategy corresponding to each memory access mode can also be constructed, that is, the analysis layer of the embodiment performs fine strategy synthesis based on mode determination, and each strategy is designed for the performance bottleneck of a specific access mode. Specifically, if the current memory access mode is the first memory access mode, the first preset number of continuous virtual addresses in the target memory are prefetched, and the physical pages in the target memory that meet the preset memory merging condition are determined, and the physical pages are merged. In the embodiment, the sequential mode adopts a strategy of deep prefetching future 8 pages and merging 2MB large pages, which reduces the number of subsequent page table traversals by using the spatial locality principle, and reduces the TLB invalidation probability by using the large page mechanism, that is, when the sequential mode is prefetched, the first 8 continuous virtual addresses are calculated, the page table entry is preloaded, and the continuous 512 4KB physical pages are scanned and replaced with 2MB large page table entries.

[0049] If the current memory access mode is the second memory access mode, the current memory page to be accessed is determined based on a random manner, and the memory page to be accessed is prefetched. In the embodiment, considering that the random mode is difficult to predict due to the access rule, a single-level freezing strategy is adopted to only prefetch the current page, and 4KB small pages are maintained to avoid memory waste.

[0050] If the current memory access mode is the third memory access mode, the memory page to be accessed that has been marked as cold data is determined, and the memory page to be accessed is added to the preset memory recycling list. In the embodiment, the cold mode turns off the prefetch function and keeps the swap open, and the memory page to be accessed is added to the recycling chain table as a cold page to preferentially recycle memory resources, so as to guarantee the memory supply of the key area,

[0051] If the current memory access mode is the fourth memory access mode, a memory page to be accessed currently marked as hot zone data is determined, a target address sequence of a memory page adjacent to the memory page to be accessed is determined, and corresponding memory pages are prefetched based on the target address sequence. That is, in the embodiment, the hot zone mode adopts a 128-page radius radiation prefetch, combined with local NUMA node locking, to ensure fast response of high-frequency access data, where the setting of the radiation prefetch radius is based on the hot zone data, which generally has a certain spatial diffusion characteristic. Specifically, when the hot zone mode is prefetched, a ±128-page virtual address sequence can be generated, a prefetch request can be submitted, and the local NUMA node can be identified to set the memory policy to MPOL_BIND. In this way, the system in the embodiment can locate the local NUMA node to which the current processor core belongs, and set the memory policy to MPOL_BIND, that is, through the memory policy interface, the memory allocation and access in this scenario are forced to be bound to the local NUMA node, and subsequent physical page allocation, data reading / writing in this scenario are all limited in the local node memory, and cross-node access is prohibited. This helps to reduce cross-node memory access delay, solve performance loss caused by NUMA imbalance, reduce multi-core performance reduction, and bind the local node to ensure that high-frequency access is all local access with low delay, maximize the optimization benefits of hot zones, and adapt to AI (Artificial Intelligence, Artificial Intelligence) training, cloud computing and other scenarios sensitive to memory response speed.

[0052] If the current memory access mode is the fifth memory access mode, the current memory page to be accessed is determined, other memory pages to be accessed are predicted based on the memory page to be accessed, a second target number of target memory pages are obtained, and the target memory pages are prefetched. In the embodiment, the dense mode calculates the memory pages in a target address chain, prefetches 64 memory pages in the future, and through 64-page chain prefetching, adapts to the centralized access characteristics and loads the subsequent page table entries in advance.

[0053] If the current memory access mode is the sixth memory access mode, the operation of performing memory page prefetching is prohibited. The embodiment considers that the sparsity mode has very low prefetching effectiveness, and directly closes the prefetching to avoid memory bandwidth waste. In this way, the analysis layer is used as a core hub connecting the monitoring layer and the execution layer, the original monitoring data is converted into executable strategies, and the accuracy and effectiveness of the entire memory management optimization are improved.

[0054] It can be understood that prefetching refers to a technology that, before a program actually accesses a part of memory such as a page table item or a physical page, the memory management system loads the memory data that may be accessed subsequently into a TLB cache or a specified memory area in advance according to the law of memory access mode, which helps to reduce the delay caused by data not being ready when actually accessed, such as TLB miss and page fault exception, and improves memory access efficiency.

[0055] And after accessing the target memory based on the target access strategy, the embodiment can further collect memory access data of the target memory based on a preset information collection interval; wherein the memory access data includes a memory prefetch hit rate, a memory bandwidth occupancy rate and an address translation success rate in a memory access process; and each preset memory access strategy is adjusted based on the memory access data. For example: the execution layer prefetch hit rate, the hardware memory bandwidth occupancy rate and the TLB hit rate are collected every 100 ms; if the prefetch hit rate is less than 20%, the prefetch depth is multiplied by 0.8; if the prefetch hit rate is greater than 70%, the prefetch depth is multiplied by 1.2; if the memory bandwidth is greater than 80%, all prefetches are paused for 10 ms; if the TLB miss rate is greater than 30%, the hot zone radius is multiplied by 1.5; and if the TLB miss rate is less than 10%, the hot zone radius is multiplied by 0.8. In this way, the calibration layer is used to monitor the strategy effect in real time, a closed-loop self-calibration mechanism is realized to dynamically adjust the parameters, the optimization system is ensured to continuously adapt to load changes, and strategy failure or resource waste is avoided.

[0056] Based on the above technical solution, the embodiment designs a memory page table access mechanism based on dynamic marking and multi-level cooperative prefetching, quantifies memory access characteristics including spatial continuity, time heat density, access dispersion, and NUMA imbalance degree, and generates six types of mode tags including sequential, random, hot zone, cold zone, sparse and dense. Then, the multi-level page table prefetch engine triggers different memory page table prefetch modes and memory allocation strategies according to different memory access modes: the sequential mode triggers five-level page table chain prefill and large page merging; the hot zone mode uses 128-page radius radiation prefetching and local NUMA binding; the sparse mode closes prefetching to prevent cache pollution; the calibration layer monitors the prefetch hit rate, memory bandwidth and TLB state in real time, dynamically adjusts the prefetch depth and hot zone radius, forms a "monitoring-analysis-execution-calibration" closed loop, and compared with the current fixed-depth single-level prefetching technology which cannot dynamically adjust according to the access mode, the embodiment can optimize the prefetch efficiency in real time, avoid resource waste and strategy failure, effectively reduce the multi-level page table traversal delay, TLB overhead and Page Fault path, and provide near-physical limit memory access performance for AI training, cloud computing, big data processing and other scenarios.

[0057] As shown in Figure 4 The embodiment of the application further provides a memory access device, which comprises:

[0058] The information detection module 11 is configured to monitor memory access information of the target memory; the memory access information includes a page fault address sequence during memory access, address distribution characteristics of the address translation buffer when an address translation failure event occurs, a cross-node access event and a virtual memory access frequency;

[0059] The feature determination module 12 is configured to determine target feature information corresponding to the memory access information, wherein the target feature information comprises spatial locality representing continuity of the page fault address, heat density representing access frequency, access dispersion representing memory access concentration, and imbalance degree data representing remote access proportion.

[0060] The mode determination module 13 is configured to determine a current memory access mode of the target memory based on the target feature information.

[0061] The memory access module 14 is configured to determine a target access strategy corresponding to the current memory access mode from the preset memory access strategies, and access the target memory based on the target access strategy, wherein different memory page table prefetch rules are configured in different preset memory access strategies.

[0062] The features of the embodiments of the memory access device can be referred to the related descriptions of the embodiments of the memory access method, which will not be repeated here.

[0063] Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment.

[0064] The embodiments of the present application also provide an electronic device, comprising a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above memory access method embodiments.

[0065] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to execute the steps in any of the above memory access method embodiments when running.

[0066] In an example embodiment, the above computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0067] The embodiments of the present application also provide a computer program product, which comprises a computer program, and the computer program is executed by a processor to implement the steps in any of the above memory access method embodiments.

[0068] The embodiment of the present application further provides another computer program product, comprising a nonvolatile computer readable storage medium, the nonvolatile computer readable storage medium stores a computer program, the computer program is executed by a processor to implement the steps in any of the above memory access method embodiments.

[0069] Those skilled in the art will further appreciate that the units and algorithm steps of the examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the above description has generally been stated in terms of the functional components and steps of the examples. Whether such functionality is implemented in hardware or software depends on the particular application and design constraints imposed on the overall system. Skilled persons can use various methods to implement the described functions for each particular application, but such implementation should not be considered beyond the scope of the present application.

[0070] The above provides a memory access method, device, storage medium and program product. The principles and implementation modes of the present application are described by applying specific examples. The above description of the examples is only applicable to help understand the method and core idea of the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A memory access method, characterized in that, include: Monitor memory access information of the target memory; The memory access information includes the page fault address sequence during memory access, the address distribution characteristics of the address translation backup buffer when an address translation failure event occurs, cross-node access events, and virtual memory access frequency. Determine the target feature information corresponding to the memory access information; The target feature information includes spatial locality, which characterizes the strength of the continuity of page fault addresses; thermal density, which characterizes the frequency of access; access dispersion, which characterizes the concentration of memory access; and imbalance data, which characterizes the proportion of remote accesses. The current memory access mode of the target memory is determined based on the target feature information; The target access strategy corresponding to the current memory access mode is determined from each preset memory access strategy, and the target memory is accessed based on the target access strategy; wherein, different preset memory access strategies are configured with different memory page table prefetch rules; Wherein, determining the target feature information corresponding to the memory access information includes: Determine the adjacent addresses in the page fault address sequence, and determine the corresponding difference sequence based on the adjacent addresses; Determine the variance of the difference sequence and use the variance as the spatial locality; Based on the virtual memory access frequency and the address distribution characteristics, the heat density of the target memory is determined; Based on the page fault address sequence, the access dispersion of the target memory is determined; Based on the cross-node access events, the imbalance data of the target memory is determined.

2. The memory access method according to claim 1, characterized in that, Before determining the target access policy corresponding to the current memory access mode from the preset memory access policies, the method further includes: Construct the preset memory access strategy corresponding to each memory access mode; the memory access modes include a first memory access mode for continuous access, a second memory access mode for random access, a third memory access mode for accessing cold zone data, a fourth memory access mode for accessing hot zone data, a fifth memory access mode for intensive access, and a sixth memory access mode for sparse access; wherein, the cold zone data is data whose access frequency meets the preset low frequency condition, and the hot zone data is data whose access frequency meets the preset high frequency condition.

3. The memory access method according to claim 2, characterized in that, Accessing the target memory based on the target access policy includes: If the current memory access mode is the first memory access mode, then a first preset number of consecutive virtual addresses in the target memory are prefetched, and physical pages in the target memory that meet the preset memory merging conditions are determined, and the physical pages are merged. If the current memory access mode is the second memory access mode, then the current memory page to be accessed is determined randomly, and the memory page to be accessed is prefetched. If the current memory access mode is the third memory access mode, then the memory page that has been marked as cold zone data is identified and added to the preset memory reclamation list; If the current memory access mode is the fourth memory access mode, then the memory page that has been marked as the hot zone data to be accessed is determined, and the target address sequence of memory pages adjacent to the memory page to be accessed is determined, and the corresponding memory pages are prefetched based on the target address sequence; If the current memory access mode is the fifth memory access mode, then the current memory page to be accessed is determined, other memory pages to be accessed are predicted based on the memory page to be accessed, a second target number of target memory pages are obtained, and the target memory pages are prefetched. If the current memory access mode is the sixth memory access mode, then the memory page prefetching operation is prohibited.

4. The memory access method according to claim 3, characterized in that, Determining the current memory access mode of the target memory based on the target feature information includes: If the value corresponding to the spatial locality is less than the first preset threshold, then the current memory access mode of the target memory is determined to be the first memory access mode. If the value corresponding to the spatial locality is greater than the second preset threshold, then the current memory access mode of the target memory is determined to be the second memory access mode; wherein, the second preset threshold is greater than the first preset threshold.

5. The memory access method according to claim 3, characterized in that, Determining the current memory access mode of the target memory based on the target feature information includes: Based on the virtual memory access frequency and the address distribution characteristics, the heat density of the target memory is determined; If the thermal density is less than the third preset threshold, then the current memory access mode of the target memory is determined to be the third memory access mode; If the thermal density is greater than the fourth preset threshold, then the current memory access mode of the target memory is determined to be the fourth memory access mode; wherein the fourth preset threshold is greater than the third preset threshold.

6. The memory access method according to claim 5, characterized in that, The step of determining the heat density of the target memory based on the virtual memory access frequency and the address distribution characteristics includes: Determine the preset sliding time window corresponding to the target memory, and determine the number of memory accesses within the preset sliding time window based on the virtual memory access frequency; The initial thermal density value is determined based on the number of memory accesses and the preset sliding time window. The initial thermal density value is adjusted based on the address distribution characteristics to obtain the thermal density.

7. The memory access method according to claim 3, characterized in that, Determining the current memory access mode of the target memory based on the target feature information includes: Based on the page fault address sequence, the access dispersion of the target memory is determined; If the access dispersion is less than the fifth preset threshold, then the current memory access mode of the target memory is determined to be the fifth memory access mode; If the access dispersion is greater than the sixth preset threshold, then the current memory access mode of the target memory is determined to be the sixth memory access mode; wherein the sixth preset threshold is greater than the fifth preset threshold.

8. The memory access method according to claim 7, characterized in that, Determining the access dispersion of the target memory based on the page fault address sequence includes: Determine the target address sequence corresponding to the page fault address sequence within a preset time period, and determine the corresponding number of page fault addresses based on the target address sequence; the addresses in the target address sequence are non-repeating page fault addresses; The number of global memory accesses within the preset time period is determined using performance monitoring equipment; The access dispersion of the target memory is determined based on the number of page fault addresses and the number of global memory accesses.

9. The memory access method according to claim 3, characterized in that, After determining the target feature information corresponding to the memory access information, the method further includes: Based on the cross-node access events, determine the imbalance data of the target memory; If the imbalance data is greater than the seventh preset threshold, a target label is generated to characterize the prohibition of cross-node access. Accordingly, the process of accessing the target memory based on the target access policy further includes: If the target tag is detected, a corresponding memory access operation is performed based on the target memory in the local memory.

10. The memory access method according to any one of claims 2 to 8, characterized in that, The process of determining the current memory access mode of the target memory based on the target feature information includes: If the target memory corresponds to multiple memory access modes, then the target access mode is determined as the current memory access mode according to a preset priority order; the target access mode is the mode with the highest priority among the multiple memory access modes. The preset priority order from high to low is as follows: the fourth memory access mode, the first memory access mode, the fifth memory access mode, the second memory access mode, the third memory access mode, and the sixth memory access mode.

11. The memory access method according to any one of claims 1 to 9, characterized in that, After accessing the target memory based on the target access policy, the process further includes: Memory access data of the target memory is collected based on a preset information collection interval; the memory access data includes memory prefetch hit rate, memory bandwidth utilization rate and address translation power during the memory access process; Adjust each of the preset memory access strategies based on the memory access data.

12. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for implementing the steps of the memory access method as described in any one of claims 1 to 11 when executing the computer program.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the memory access method as described in any one of claims 1 to 11.

14. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the memory access method as described in any one of claims 1 to 11.

Images