Core particle communication parameter optimization method, core particle and chip

Abstract

The invention provides a core particle communication parameter optimization method, a core particle and a chip, and the optimization method comprises the steps: carrying out the data transmission test through all transmitting ends of the core particle according to different preset phases; calculating a phase optimal value according to the test information of all the data sending tests, and optimizing the clock signal of the core particle according to the phase optimal value; based on the optimized clock signal, performing a data receiving test through each receiving end of the core particle according to different preset judgment levels; and calculating a corresponding judgment level optimal value according to a test result of the data receiving test of each receiving end, and optimizing the judgment level of the corresponding receiving end according to the judgment level optimal value. According to the core particle communication parameter optimization method, the core particle and the chip provided by the invention, the technical problem that parameters of a communication link between core particles are difficult to optimize can be solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a method for optimizing communication parameters of a die, a die and a chip. BACKGROUND

[0002] With the progress of chip design and packaging technology, die interconnection technology has become the focus of the industry because it can effectively reduce the cost, size of single chip design and improve manufacturing yield. As an emerging standard, UCIe supports PCIe 6.0, CXL 2.0 / 3.0 and custom protocols through protocol layers, and the adaptation layer and physical layer of the die implement efficient Die-to-Die data transmission to adapt to 2.5D / 3D advanced packaging. This technology replaces the limitations of traditional interconnection such as PCIe, provides transmission rate and bandwidth of the communication link between dies, and significantly improves the data transmission efficiency between dies.

[0003] In the UCIe physical layer, the increase in clock frequency leads to a decrease in timing margin and voltage margin, inter-module skew and difficulty in equalization adjustment, and the calibration of the communication parameters of the communication link becomes more difficult. The hardware-embedded calibration process may produce inaccurate parameters, and the protocol specification is difficult to flexibly adjust the algorithm, which reduces the performance and stability of the communication link between dies, and there is an urgent need for a flexible and reliable parameter optimization method to improve calibration accuracy. SUMMARY

[0004] The present application provides a method for optimizing communication parameters of a die, a die and a chip to solve the technical problem that the parameters of the communication link between dies are difficult to optimize.

[0005] The present application provides a method for optimizing communication parameters of a die, which is applied to a die, and the optimization method comprises:

[0006] According to the preset different phases, data transmission tests are performed through all the sending ends of the die; wherein the preset different phases are obtained by gradually adjusting the initial phase value of the die according to the preset phase step amount;

[0007] The optimal phase value is calculated according to the test information of all data transmission tests, and the clock signal of the die is optimized according to the optimal phase value;

[0008] Based on the optimized clock signal, data reception tests are performed through each receiving end of the die according to the preset different decision levels; wherein the preset different decision levels are obtained by gradually adjusting the preset minimum level and the preset maximum level of the die according to the preset level step amount;

[0009] According to the test result of the data receiving test of each receiving end, a corresponding decision level optimal value is calculated, and a decision level of the corresponding receiving end is optimized according to the decision level optimal value.

[0010] In an embodiment of the present application, the step of performing data sending tests through all the sending ends of the core grain according to the preset different phases comprises:

[0011] Starting from the initial phase value, the initial phase value of the core grain is adjusted step by step according to a preset negative phase offset direction and a preset phase code step size until one clock cycle is adjusted; data sending tests are performed through all the sending ends of the core grain according to the phase obtained after each adjustment.

[0012] Starting from the initial phase value, the initial phase value is adjusted step by step according to a preset positive phase offset direction and the phase code step size until one clock cycle is adjusted; data sending tests are performed through all the sending ends of the core grain according to the phase obtained after each adjustment.

[0013] In an embodiment of the present application, after the step of starting from the initial phase value, adjusting the initial phase value of the core grain step by step according to a preset negative phase offset direction and a preset phase code step size until one clock cycle is adjusted, the step further comprises:

[0014] The adjusted phase is adjusted step by step according to the phase code step size in a positive phase offset direction until the initial phase value is adjusted.

[0015] In an embodiment of the present application, after the step of starting from the initial phase value, adjusting the initial phase value step by step according to a preset positive phase offset direction and the phase code step size until one clock cycle is adjusted, the step further comprises:

[0016] The adjusted phase is adjusted step by step according to the phase code step size in a negative phase offset direction until the initial phase value is adjusted.

[0017] In an embodiment of the present application, the step of calculating a phase optimal value according to the test information of all the data sending tests and optimizing the clock signal of the core grain according to the phase optimal value comprises:

[0018] The test information is reserved for the phase passing the test.

[0019] The reserved phase is sorted to obtain a corresponding continuous sequence.

[0020] The phase optimal value is calculated according to the continuous sequence.

[0021] According to the phase optimal value, the clock signal of the core particle is optimized.

[0022] In an embodiment of the present application, the step of calculating the phase optimal value according to the continuous sequence comprises:

[0023] The difference between two adjacent phases in the continuous sequence is calculated, and the difference is compared with the phase code step amount;

[0024] The number of the difference greater than the phase code step amount is counted as the number of abnormal point positions;

[0025] According to the comparison result of the number of abnormal point positions and the preset threshold, the phase optimal value of the continuous sequence is found.

[0026] In an embodiment of the present application, the step of finding the phase optimal value of the continuous sequence according to the comparison result of the number of abnormal point positions and the preset threshold comprises:

[0027] It is judged whether the number of abnormal point positions is less than the preset threshold:

[0028] When the number of abnormal point positions is less than the preset threshold, the center value of the continuous sequence is found as the phase optimal value;

[0029] Otherwise, the continuous sequence is split into a plurality of sub-continuous sequences according to the abnormal point positions, and the sub-continuous sequence with the largest number of phases is selected as the target sub-continuous sequence; the center value of the target sub-continuous sequence is found as the phase optimal value.

[0030] In an embodiment of the present application, the step of performing data receiving test through each receiving end of the core particle according to the preset different decision levels based on the optimized clock signal comprises:

[0031] The decision levels of all receiving ends of the core particle are set to start from the preset minimum level, and the minimum level of all receiving ends of the core particle is adjusted step by step according to the preset level step amount until the preset maximum level is reached;

[0032] According to the decision level obtained by each adjustment and the optimized clock signal, data receiving test is performed through each receiving end of the core particle respectively, and the test result of data receiving test of each receiving end is obtained.

[0033] In an embodiment of the present application, the step of calculating the corresponding decision level optimal value according to the test result of data receiving test of each receiving end, and optimizing the decision level of the corresponding receiving end according to the decision level optimal value comprises:

[0034] For each receiving end:

[0035] retention test result is a decision level of test pass;

[0036] an average value of the maximum value and the minimum value of the decision level corresponding to the retention is calculated as an optimal value of the decision level of the receiving end;

[0037] the decision level of the receiving end is optimized according to the optimal value of the decision level.

[0038] The application further discloses a core particle, and the core particle uses the optimization method of the communication parameter of the core particle.

[0039] The application further discloses a chip, and the chip comprises the core particle.

[0040] The application has the following beneficial effects: dynamic calibration of UCIe physical layer communication parameters is realized through a software / firmware algorithm, time sequence margin compression under high-frequency clock, voltage margin reduction and multi-channel skew problems are effectively solved, and the optimal value of the phase based on phase scanning and calculation can eliminate problems caused by clock jitter; through full-range level scanning starting from a preset minimum level and independent decision level optimal value calculation of each receiving end, vertical direction noise tolerance can be maximized, and an eye diagram asymmetry problem caused by process deviation can be solved. BRIEF DESCRIPTION OF DRAWINGS

[0041] The drawings incorporated into the specification and forming a part thereof, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application. It is to be expressly understood, however, that the drawings are included herein for illustrative purposes only and that they are subject to interpretation, modification and / or change in light of this disclosure and of current art.

[0042] In the drawings:

[0043] Figure 1 A flow chart of an optimization method of a communication parameter of a core particle provided for an embodiment of the application;

[0044] Figure 2 A schematic diagram of a continuous sequence of phase tests provided in an embodiment of the application;

[0045] Figure 3 Another schematic diagram of a continuous sequence of phase tests provided in an embodiment of the application;

[0046] Figure 4 A schematic diagram of a decision level test provided in an embodiment of the application.

[0047] The reference signs are as follows:

[0048] 11, minimum index number; 12, maximum index number; 13, start index number; 14, end index number; 15, center index number; 21, preset level minimum value; 22, preset level maximum value; 23, level minimum value; 24, level maximum value; 25, decision level optimal value. DETAILED DESCRIPTION

[0049] Other advantages and benefits of the present application will become apparent to those skilled in the art upon consideration of the disclosure or can be learned by practice of the application. The application can be realized and achieved by means of the structures and combinations of features described in the description above and in the claims. The application can also be realized and achieved by means of other different specific embodiments, which are also protected by the scope of the claims.

[0050] It is to be understood that the drawings shown below are only schematic and that the actual implementation of the application can vary as a consequence of the preferences given to the elements, their shapes, dimensions and proportions, and the layout of the components shown in the drawings, which are only given by way of example.

[0051] In the following description, numerous specific details are discussed in order to provide a thorough understanding of the embodiments of the application. However, it will be apparent to one of ordinary skill in the art that the embodiments of the application can be practiced without these specific details. In other instances, well-known structures and devices are not described in exhaustive detail in order to avoid obscuring the embodiments of the application.

[0052] Referring to Figure 1 The application discloses a method for optimizing communication parameters of a core particle. The method can be applied to the core particle to optimize the communication parameters of a communication link between core particles. Before optimizing the communication link between core particles, basic parameters need to be configured, including setting a target transmission rate (including optional values such as 4G, 8G or 16G) and a target link width (i.e. the total number of channels). At the same time, the UCIe state machine is suspended in the MBTRAIN.DATATRAINCENTER2 state defined in its specification, which represents the equalization training phase for the center channel (this state machine is the inherent hardware logic of the UCIe protocol, and the present scheme only calls its suspension function).

[0053] In some embodiments, corelets can be divided into local corelets and remote corelets. The multiple transmitting ends of the local corelet are connected one-to-one with the multiple receiving ends of the remote corelet, forming multiple independent data transmission channels. The multiple receiving ends of the local corelet are connected one-to-one with the multiple transmitting ends of the remote corelet, forming multiple independent data reception channels. In the subsequent optimization process, the local corelet is used as an example and is represented as the corelet.

[0054] In some embodiments, the optimization method may include the following steps: Step S10, performing data transmission tests through all transmitting ends of the core particle according to preset different phases; wherein the preset different phases are obtained by gradually adjusting the initial phase value of the core particle according to the preset phase code step amount.

[0055] In some embodiments, step S10 may include the following steps: step S11, starting from the initial phase value, gradually adjusting the initial phase value of the core particle according to the preset negative phase offset direction and the preset phase code step amount until one clock cycle is adjusted; according to the phase obtained by each adjustment, performing data transmission tests through all sending ends of the core particle respectively.

[0056] In some embodiments, the initial phase value is adjusted in a preset negative phase offset direction (i.e., the direction of phase angle reduction) by a preset phase code step amount of (1 / MAX_PI)UI. MAX_PI represents the maximum division number of the phase interpolator; the number of adjustments can be MAX_PI; and UI represents the time used to transmit a single data. By adjusting MAX_PI times, a clock cycle is adjusted in the negative phase offset direction cumulatively. After each adjustment, a PRBS (pseudo-random binary sequence) test code stream is synchronously sent to the remote core through all transmitting ends of the core. The remote core monitors each data receiving channel in real time: if any data receiving channel has a data abnormal point (such as a bit error, timing misalignment, etc.), the test is judged to have failed at the current phase; if the data of all data receiving channels are normal, it is judged to have passed.

[0057] In some embodiments, the phase tolerance range on the left side of the clock cycle is systematically scanned by step-by-step left shifting a complete clock cycle. By utilizing a PRBS code stream to simulate high-load random data and forcing all transmitting channels to work in parallel, the weakest channel bottleneck in the link can be exposed. Through the remote anomaly feedback mechanism, the failure threshold of the phase offset can be accurately identified, providing data support for subsequent optimization.

[0058] In some embodiments, step S10 may further include the following steps: step S12, gradually adjusting the adjusted phase according to the phase code step amount in a preset positive phase offset direction until it is adjusted to an initial phase value.

[0059] In some embodiments, the current phase value is gradually increased by the phase code step size in the preset positive phase shift direction (phase angle increasing direction) until it returns to the initial phase value. This process does not trigger any data transmission test. Through the above process, the instantaneous voltage / current overshoot caused by the phase value jumping from the negative limit back to the initial value can be avoided, preventing signal ringing or power supply noise in high-frequency circuits; at the same time, a unified phase reference point can be established for subsequent positive shift tests, ensuring the consistency of test conditions in each stage.

[0060] In some embodiments, step S10 can further include the following step: step S13, starting from the initial phase value, gradually adjusting the initial phase value according to the phase code step size in the positive phase shift direction until one clock cycle is adjusted; and performing data transmission tests through all the transmitting ends of the core grain according to the phase obtained after each adjustment.

[0061] In some embodiments, the initial phase value is gradually adjusted by the same phase code step size in the preset positive phase shift direction (phase angle increasing direction), and the cumulative adjustment achieves a right shift of one clock cycle. After each adjustment, the transmitting ends of the core grain are started to synchronously transmit PRBS test code streams to the remote core grain. The remote core grain monitors each data receiving channel in real time: if any data receiving channel has abnormal data points (such as error codes, timing misplacement, etc.), it is determined that the test at the current phase is failed; if the data of all data receiving channels are normal, it is determined that the test is passed.

[0062] In some embodiments, by extending the scan to the right half of the clock cycle and merging it with the negative scan formed by the above process, the phase window of two consecutive clock cycles is completely covered. By shifting left and right by one clock cycle, potential timing conflicts (such as overlapping regions of data eye diagrams) across clock cycles can be captured, avoiding the blind area of traditional single-cycle calibration.

[0063] In some embodiments, step S10 can further include the following step: step S14, gradually adjusting the adjusted phase according to the phase code step size in the negative phase shift direction until it is adjusted to the initial phase value.

[0064] In some embodiments, the current phase value is gradually decreased by the same phase code step size in the preset negative phase shift direction (phase angle decreasing direction) until it returns to the initial phase value. No data transmission test is performed in this stage. Through the above process, the transient response problem of the driving circuit caused by the phase jumping from the positive limit back to zero can be avoided, maintaining signal integrity.

[0065] In some embodiments, by the combination strategy of left shift by one clock cycle and right shift by one clock cycle, the traditional single cycle calibration limit can be broken through, and the robustness to clock jitter and timing deviation can be significantly improved. Although the phase recovery operation does not participate in the performance test, the hardware transient risk is eliminated by the step reset, which is particularly important in high frequency (such as 16Gbps) scenarios. Each phase adjustment forces all data transmission channels to work synchronously, and combined with independent abnormality detection of the remote multi-receiving channel, the link bottleneck can be efficiently optimized.

[0066] In some embodiments, the optimization method can include the following steps: step S20, calculating the optimal phase value according to the test information of all data transmission tests, and optimizing the clock signal of the core grain according to the optimal phase value.

[0067] In some embodiments, step S20 can include: step S21, retaining the phase for which the test information is passed.

[0068] In some embodiments, by retaining only the phase for which the test information is passed (i.e., the remote core grain feedbacks that all data transmission channels have no abnormal points), and ignoring all phases for which the test is not passed, a phase set to be analyzed can be formed. By excluding phases with channel failures, it is ensured that subsequent analysis is based only on stable and available working phases; at the same time, invalid data interference can be avoided, and the phase interval within the actual fault tolerance capability of the link can be focused.

[0069] In some embodiments, step S20 can further include: step S22, sorting the retained phases to obtain a corresponding continuous sequence.

[0070] In some embodiments, the retained phases are sorted according to the number of adjustments to generate an ordered phase sequence. For the phases corresponding to the negative phase offset direction, the retained phases can be sorted in descending order of the number of adjustments. For the phases corresponding to the positive phase offset direction, the retained phases can be sorted in ascending order of the number of adjustments. At this time, the two sequences can be integrated to obtain a continuous sequence. The left side of the continuous sequence represents the phase when the number of adjustments in the negative phase offset direction is the largest, and the right side of the continuous sequence represents the phase when the number of adjustments in the positive phase offset direction is the largest.

[0071] In some embodiments, step S20 can further include: step S23, calculating the optimal phase value according to the continuous sequence.

[0072] In some embodiments, step S23 can include: step S231, calculating the difference between two adjacent phases in the continuous sequence, and comparing the difference with the phase code step size.

[0073] In some embodiments, a continuous sequence is traversed to calculate the difference between each two adjacent phases in the continuous sequence (e.g., the last term minus the previous term). Each difference is compared with the phase code step amount. When the difference between adjacent phases is greater than the phase code step amount, it indicates that a phase corresponding to a test failure exists. When the difference between adjacent phases is equal to the phase code step amount, it indicates that no phase corresponding to a test failure exists.

[0074] In some embodiments, step S23 may further include: step S232, counting the number of differences greater than the phase code step amount as the number of abnormal points.

[0075] In some embodiments, the number of adjacent phase code step values ​​greater than the phase code step value is accumulated and defined as the number of abnormal points. For example, if a continuous sequence has three values ​​with differences exceeding the phase code step value, the number of abnormal points is equal to 3. The number of abnormal points directly reflects the degree of fragmentation in the available phase interval; a higher value indicates poorer link timing fault tolerance.

[0076] In some embodiments, step S23 may further include: step S233, searching for the optimal phase value of the continuous sequence according to the comparison result of the number of abnormal points and a preset threshold.

[0077] In some embodiments, step S233 may include: determining the number of abnormal points and a preset threshold: when the number of abnormal points is less than the preset threshold, searching for the center value of the continuous sequence as the optimal phase value; otherwise, splitting the continuous sequence into multiple sub-continuous sequences according to the abnormal points, and screening out the sub-continuous sequence with the largest number of phases as the target sub-continuous sequence; searching for the center value of the target sub-continuous sequence as the optimal phase value.

[0078] In some embodiments, processing can be performed separately based on the comparison result of the number of outlier points with a preset threshold (e.g., 3). If the number of outlier points is less than or equal to the preset threshold, the central phase value of the continuous sequence is directly obtained as the optimal phase value. If the number of outlier points is greater than the preset threshold, the continuous sequence is split into multiple sub-continuous sequences based on the outlier points. The sub-continuous sequence containing the largest number of phase points is then selected as the target sub-sequence, and its central phase value is obtained as the optimal phase value.

[0079] See also Figure 2 and Figure 3 In some embodiments, the number of abnormal points ≤ a preset threshold is used as an example. The starting division number 13 of the phase that passed the test and the ending division number 14 of the phase that passed the test can be distributed on both sides of the minimum division number 11 or the maximum division number 12, or can be distributed at any position on the same side of the minimum division number 11 or the maximum division number 12. Figure 2 Continuous series can be displayed as bars,Figure 3 The displayed continuous sequence can be circular, starting from Figure 2 and Figure 3 It can be seen from the figure that the starting division number 13 is the starting point, the ending division number 14 is the end point, and the center division number 15 corresponding to the optimal phase value is located at the center of the two.

[0080] In some embodiments, step S20 may further include: step S24, optimizing the chiplet's clock signal based on the optimal phase value. Specifically, by writing the optimal phase value into the clock generator register, overwriting the initial phase value, dynamic calibration of the chiplet's transmitting clock phase can be achieved. Dynamically adjusting the clock phase based on measured data can compensate for timing offsets caused by process / voltage / temperature (PVT) variations.

[0081] In some embodiments, the optimization method may include the following steps: Step S30: Based on the optimized clock signal, a data reception test is performed on each receiving end of the chip according to different preset decision levels. The different preset decision levels are obtained by gradually adjusting the preset level minimum value of the chip according to the preset level step amount.

[0082] In some embodiments, step S30 may include the following steps: step S31, setting the decision level of all receiving ends of the core particle to start from a preset minimum level, and gradually adjusting the minimum level of all receiving ends of the core particle according to the preset level step amount until the preset maximum level is reached.

[0083] In some embodiments, the decision level of all data receiving terminals of the chiplet is uniformly set to a preset minimum level, such as 0, as the starting reference point for the decision level scan. This is achieved by configuring the reference voltage register of the internal comparator of the receiving terminal. This configuration ensures that all receiving terminals start the test from the same low-level baseline, eliminating differences in the initial hardware state.

[0084] In some embodiments, the preset level step size can be expressed as 1 / preset level maximum, where the preset level maximum refers to the maximum decision level that the receiving end can withstand. In this case, the decision levels of all receiving ends can be adjusted synchronously, with the cumulative number of adjustments being the maximum number, and the level step size can be increased with each adjustment. This step-by-step mechanism can avoid transient current overloads caused by level jumps and protect the receiving end comparator circuit. At the same time, all receiving ends always maintain the same decision level value, ensuring consistent test conditions. By adjusting the level operating range from 0 to the maximum value multiple times, the optimal decision point is captured without omission.

[0085] In some embodiments, step S30 can further include the following step: step S32, performing data receiving test through each receiving end of the die respectively according to the decision level obtained after each adjustment and the optimized clock signal, to obtain the test result of the data receiving test of each receiving end.

[0086] In some embodiments, according to the decision level obtained after each adjustment and the optimized clock signal, the far-end die can be controlled to continuously send the PRBS test code stream to all receiving ends of the die, and the data recovery state of each receiving end can be monitored independently. If ≥1 abnormal point (such as error code, data loss) occurs in a receiving end, the current decision level test result of the receiving end is marked as test failure. If all data of a receiving end is normally recovered, the current decision level test result of the receiving end is marked as test success. Finally, the test result under each decision level can be recorded for each receiving end respectively. By constructing a pass / fail state table under complete decision level scanning for each receiving end, the subsequent optimal level calculation can be supported.

[0087] In some embodiments, the optimization method can include the following step: step S40, calculating the optimal value of the decision level corresponding to each receiving end according to the test result of the data receiving test of the receiving end, and optimizing the decision level of the corresponding receiving end according to the optimal value of the decision level.

[0088] In some embodiments, step S40 can include the following step: step S41, for each receiving end: retaining the decision level with test success test result. Specifically, for each receiving end, all decision levels marked as test success test result can be extracted from the test result to generate the valid decision level set of the receiving end. If the data receiving of the receiving end is normal under a decision level (i.e. the PRBS code stream sent by the far-end die is completely and correctly recovered), the decision level is retained; otherwise, if there is an abnormal point, the decision level is excluded.

[0089] In some embodiments, step S40 can further include the following step: step S42, calculating the average value of the maximum value and the minimum value of the retained decision level as the optimal value of the decision level of the receiving end.

[0090] In some embodiments, the maximum value and the minimum value of the corresponding reserved decision level can be calculated for each receiving end, and the average value of the maximum value and the minimum value is the optimal decision level of the receiving end. The traditional fixed threshold method is prone to failure when the eye diagram is asymmetric. The optimal decision level calculated above is based on the measured pass interval, and automatically aligns the decision point to the position of the maximum vertical direction fault tolerance margin (i.e. the geometric center of the maximum value and the minimum value). For multiple receiving end cores, the eye diagram heights of the channels are inconsistent due to process deviation (e.g. the eye opening height of channel A is 0.4V, and the eye opening height of channel B is 0.3V). Independent calculation enables each receiving end to obtain an individual optimal level.

[0091] Referring to Figure 4 In some embodiments, the minimum value of the test pass level 23 can be distributed between the preset minimum level 21 and the preset maximum level 22, and the maximum value of the test pass level 24 can be distributed between the preset minimum level 21 and the preset maximum level 22. By calculating the average value of the minimum value of the test pass level 23 and the maximum value of the test pass level 24, the optimal decision level 25 can be obtained.

[0092] In some embodiments, step S40 can further include the following step: step S43, optimizing the decision level of the receiving end according to the optimal decision level. Specifically, by independently writing the calculated optimal decision level of each receiving end into the decision level register of the corresponding receiving end, the preset initial level can be overwritten, and the optimization of the full-link receiving end can be completed.

[0093] In some embodiments, after completing the first clock phase optimization and the receiving end decision level optimization, the UCIe link state machine can be restarted, and the optimization process can be re-executed. If the state machine still does not enter the Active state (i.e. the link stability standard required by the protocol is not met), the above process is continuously executed in a loop; the number of loops is not limited, and the state machine finally enters the Active state.

[0094] As can be seen, in the above scheme, the dynamic calibration of the UCIe physical layer communication parameters is realized by a software / firmware algorithm, effectively solving the problems of timing margin compression, voltage margin reduction and multi-channel skew under high-frequency clock. Based on the optimal phase value calculated by phase scanning and calculation, the problems caused by clock jitter can be eliminated. By full-range level scanning starting from the preset minimum level and independent decision level optimization calculation of each receiving end, the vertical direction noise tolerance can be maximized, and the problem of eye diagram asymmetry caused by process deviation can be solved.

[0095] The present invention also discloses a coreparticle. The aforementioned optimization method can be applied to the coreparticle to optimize the coreparticle's communication parameters. Coreparticles can be divided into local coreparticles and remote coreparticles. When the local coreparticle and the remote coreparticle are interconnected, the aforementioned optimization method can optimize the communication parameters of the communication link between the interconnected local coreparticle and the remote coreparticle.

[0096] The present invention also discloses a chip, which may include multiple interconnected core particles. The core particles may be the core particles described in the above embodiment. The chip may be divided into a local chip and a remote chip. When the local chip and the remote chip are interconnected, some core particles in the local chip may be interconnected with some core particles in the remote chip. The above optimization method may optimize the communication parameters of the communication link between the interconnected local chip and the remote chip.

[0097] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for optimizing communication parameters of a core particle, characterized in that: Applied to core particles, the optimization method includes: Performing a data transmission test through all transmitting ends of the chip according to different preset phases; wherein the different preset phases are obtained by gradually adjusting the initial phase value of the chip according to a preset phase code step amount; Calculating a phase optimal value according to test information of all data transmission tests, and optimizing a clock signal of the chiplet according to the phase optimal value; Based on the optimized clock signal, a data reception test is performed on each receiving end of the chiplet according to different preset decision levels; wherein the different preset decision levels are obtained by gradually adjusting the preset level step amount according to the preset level minimum value and the preset level maximum value of the chiplet; The corresponding optimal decision level value is calculated according to the test result of the data reception test of each receiving end, and the decision level of the corresponding receiving end is optimized according to the optimal decision level value.

2. The method for optimizing the communication parameters of a chip according to claim 1, characterized in that: The step of performing a data transmission test through all the transmitting ends of the chip according to the preset different phases includes: Starting from the initial phase value, the initial phase value of the chiplet is gradually adjusted according to a preset negative phase offset direction and a preset phase code step amount until one clock cycle is adjusted; and data transmission tests are performed through all transmitting ends of the chiplet according to the phase obtained by each adjustment; Starting from the initial phase value, the initial phase value is gradually adjusted according to the phase code step amount in the preset positive phase offset direction until one clock cycle is adjusted; according to the phase obtained by each adjustment, data transmission tests are performed through all sending ends of the core particle respectively.

3. The method for optimizing the communication parameters of a chip according to claim 2, characterized in that: After the step of gradually adjusting the initial phase value of the chip according to a preset negative phase offset direction and a preset phase code step amount starting from the initial phase value until one clock cycle is adjusted, the method further includes: According to the preset positive phase offset direction, the adjusted phase is gradually adjusted according to the phase code step amount until it is adjusted to the initial phase value.

4. The method for optimizing the communication parameters of a chip according to claim 2, wherein: After the step of gradually adjusting the initial phase value according to the phase code step amount starting from the initial phase value in a preset positive phase offset direction until adjusting for one clock cycle, the method further includes: The adjusted phase is gradually adjusted according to the phase code step amount in the negative phase offset direction until it is adjusted to the initial phase value.

5. The method for optimizing the communication parameters of a chip according to claim 1, characterized in that: The step of calculating the optimal phase value according to the test information of all data transmission tests and optimizing the clock signal of the chip according to the optimal phase value includes: The test information is retained as the phase where the test passed; Sort the retained phases to obtain the corresponding continuous sequence; Calculating an optimal phase value according to the continuous sequence; The clock signal of the chiplet is optimized according to the optimal phase value.

6. The method for optimizing the communication parameters of a chip according to claim 5, characterized in that: The step of calculating the optimal phase value according to the continuous sequence includes: Calculating a difference between two adjacent phases in the continuous sequence, and comparing the difference with the phase code step amount; Counting the number of the differences greater than the phase code step value as the number of abnormal points; According to the comparison result of the number of the abnormal points and the preset threshold, the optimal phase value of the continuous sequence is found.

7. The method for optimizing the communication parameters of a chip according to claim 6, characterized in that: The step of searching for the optimal phase value of the continuous sequence based on a comparison result of the number of abnormal points with a preset threshold comprises: Determine the number of abnormal points and the preset threshold: When the number of abnormal points is less than a preset threshold, finding the central value of the continuous sequence as the optimal phase value; Otherwise, the continuous sequence is split into multiple sub-continuous sequences according to the abnormal point position, and the sub-continuous sequence with the largest number of phases is screened out as the target sub-continuous sequence; the central value of the target sub-continuous sequence is found as the optimal phase value.

8. The method for optimizing the communication parameters of a chip according to claim 1, wherein: The step of performing a data reception test on each receiving end of the chiplet based on the optimized clock signal and according to different preset decision levels includes: Setting the decision levels of all receiving ends of the chiplet to start from a preset minimum level, and gradually adjusting the minimum levels of all receiving ends of the chiplet simultaneously according to a preset level step amount until the preset maximum level is reached; According to the decision level obtained by each adjustment and the optimized clock signal, a data reception test is performed on each receiving end of the chiplet to obtain a test result of the data reception test on each receiving end.

9. The method for optimizing the communication parameters of a chip according to claim 1, characterized in that: The step of calculating the corresponding optimal decision level value according to the test result of the data reception test of each receiving end, and optimizing the decision level of the corresponding receiving end according to the optimal decision level value includes: For each receiver: The test result is retained as the judgment level of the test passing; Calculate the average of the maximum and minimum values ​​of the corresponding retained decision levels as the optimal value of the decision level of the receiving end; The decision level of the receiving end is optimized according to the optimal value of the decision level.

10. A core particle, characterized in that The core particle applies the method for optimizing the communication parameters of the core particle according to any one of claims 1 to 9.

11. A chip, characterized in that: The chip comprises the core particle according to claim 10.

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