Staged activation of symbol-based envelope tracking switches

Abstract

The invention relates to staged activation of symbol-based envelope tracking switches. Aspects of the present disclosure relate to a voltage modulator with switch staged activation. The voltage modulator may receive supply voltages and provide a selected one of the supply voltages as an output voltage. The voltage modulator may include switches in parallel, wherein one of the switches in parallel is activated prior to the other switch in parallel by converting the output voltage between different supply voltages. The embodiment of the invention relates to symbol-based envelope tracking. Related systems and methods are disclosed.

Description

[0001] Cross Reference to Priority Application

[0002] Any and all applications identified in the Application Data Sheet as having a foreign or domestic priority filing date, including any priority applications of the present application, are hereby incorporated by reference under 37 CFR § 1.57. This application claims priority to U.S. Provisional Application No. 63 / 635,794, filed April 18, 2024, titled “Staged Activation of Symbol-Based Envelope Tracking Switch,” the content and subject matter of which are incorporated herein by reference in their entirety and for all purposes. TECHNICAL FIELD

[0003] Embodiments of the present disclosure relate to generating a bias voltage for a power amplifier, where the bias voltage tracks an envelope of a radio frequency signal. BACKGROUND

[0004] Radio systems can transmit and receive signals in the form of electromagnetic waves having frequencies in the range of about 30 kilohertz (kHz) to 300 gigahertz (GHz). Radio systems can be used for wireless communication, such as cellular communication and / or other wireless network communication.

[0005] Radio systems that transmit signals typically include a power amplifier for amplifying a radio frequency signal for transmission through one or more antennas. Power amplifiers can consume a significant amount of power in such systems. Power amplifiers with high power efficiency can be suitable for various applications. SUMMARY

[0006] The innovations described in this specification each have several aspects, no one of which is solely responsible for its desirable attributes. Without limiting the scope of the claims what we now describe will briefly describe some highlight features of the specification.

[0007] One aspect of the present disclosure is a system for staged activation of a symbol-based envelope tracking switch. The system includes a voltage modulator and a power amplifier. The voltage modulator is configured to receive a plurality of supply voltages and output a selected one of the plurality of supply voltages at an output node based on a symbol-based envelope tracking state. The voltage modulator includes a first switch, a second switch in parallel with the first switch, and a third switch. The first switch is configured to activate after the second switch is associated with a transition of the symbol-based envelope tracking state from a first state to a second state. The first switch and the second switch are configured to pass a first supply voltage to the output node in the second state. The third switch is configured to pass a second supply voltage to the output node in the first state. The power amplifier is electrically connected to the output node. The power amplifier is configured to amplify a radio frequency signal.

[0008] The first switch can occupy more physical area than the second switch.

[0009] The voltage modulator can include a fourth switch in parallel with the third switch. The third switch can be activated after the fourth switch in association with a transition of the symbol-based envelope tracking state from the second state to the first state.

[0010] The power amplifier can include a gallium nitride transistor.

[0011] The voltage at the output node can have a higher voltage level in the second state than in the first state. In the first state, the voltage at the output node can be greater than 0 volts. In the first state, the voltage at the output node can be at least one quarter of the voltage at the output node in the second state.

[0012] The first switch and the second switch can be field effect transistors.

[0013] The first switch can include a pair of sub-switches with magnetic field cancellation.

[0014] The voltage modulator can be configured to perform a turn-on-before-turn-off switching.

[0015] The voltage modulator can be configured to transition the voltage at the output node between a first supply voltage and a second supply voltage in less than 50 nanoseconds. A difference between the first supply voltage and the second supply voltage can be at least one quarter of the higher of the first supply voltage and the second supply voltage.

[0016] The voltage at the output node can track an envelope of the radio frequency signal on a symbol-by-symbol basis.

[0017] Another aspect of the disclosure is a method of voltage multiplexing with phased activation of switches. The method includes providing, in a first state, a first supply voltage of a plurality of supply voltages as an output voltage using a switch; activating a pair of parallel switches in association with a transition from the first state to a second state such that a second switch of the pair of parallel switches is activated before a first switch of the pair of parallel switches; and providing, in the second state, a second supply voltage of the plurality of supply voltages as the output voltage using the pair of parallel switches, wherein the first supply voltage and the second supply voltage are at different discrete non-zero voltage levels when provided as the output voltage.

[0018] The method can include biasing a power amplifier with the output voltage and amplifying a radio frequency signal using the power amplifier. The first state and the second state can be symbol-based envelope tracking states associated with a symbol of the radio frequency signal. The output voltage can track an envelope of the radio frequency signal on a symbol-by-symbol basis.

[0019] The activating can occur at a symbol boundary of the radio frequency signal amplified by a power amplifier that receives the output voltage.

[0020] The first switch can occupy more physical area than the second switch.

[0021] The method can include activating a second pair of parallel switches in association with transitioning from the second state to the first state, such that a fourth switch is activated before a third switch, where the second pair of parallel switches includes the third switch and the fourth switch.

[0022] Another aspect of the disclosure is a voltage modulator that activates switches in stages. The voltage modulator includes a first switch, a second switch in parallel with the first switch, and a third switch. The first switch is configured to activate after the second switch in association with transitioning from a first state to a second state. The first and second switches are configured to pass a first supply voltage to an output node in the second state. The third switch is configured to pass a second supply voltage to the output node in the first state. The voltage modulator is configured to receive a plurality of non-zero supply voltages including the first supply voltage and the second supply voltage.

[0023] The voltage modulator can be configured to perform a make-before-break switching. The first switch can occupy more physical area than the second switch.

[0024] The first switch can include a pair of sub-switches with magnetic field cancellation.

[0025] To summarize the disclosure, certain aspects, advantages, and novel features of the innovation are described herein. It is to be understood that not necessarily all such advantages can be achieved in all embodiments of the innovation. Thus, the innovation can be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as can be taught or suggested herein. BRIEF DESCRIPTION OF DRAWINGS

[0026] Embodiments of the disclosure will be described, by non-limiting example, with reference to the drawings.

[0027] Figure 1 is a waveform of a radio frequency (RF) signal and a symbol-by-symbol varying modulation bias voltage.

[0028] Figure 2 is a schematic block diagram of a multiple-input multiple-output (MIMO) radio system according to an embodiment.

[0029] Figure 3 is a schematic diagram of a radio transmitter channel with a dual-input bias voltage multiplexer for biasing an RF power amplifier.

[0030] Figure 4A is a schematic diagram of a dual-input single-output symbol-based envelope tracking (SBET) voltage modulator. Figure 4B 、 4C 、4D and 4E are waveforms ofFigure 4A The operation of the SBET voltage modulator is related to the diagram.

[0031] Figure 5A The figure shows a schematic diagram of a dual-input, single-output SBET voltage modulator with an RC snubber. Figure 5B 、 5C , 5D and 5E are related to Figure 5A The operation of the SBET voltage modulator is related to the diagram.

[0032] Figure 6A is a schematic diagram of a dual-input, single-output SBET voltage modulator with parallel switches and staged activation. Figure 6B 、 6C , 6D and 6E are Figure 6A The operation of the SBET voltage modulator is related to the diagram.

[0033] Figure 7 is a schematic diagram of the sub-switches of a switch and the associated bypass capacitors with magnetic field cancellation. DETAILED DESCRIPTION

[0034] The following detailed description of certain embodiments presents various descriptions of specific embodiments. However, the innovations described herein may be embodied in a variety of different ways, for example, as defined and encompassed by the claims. In this specification, reference is made to the accompanying drawings in which like reference numerals may represent identical or functionally similar elements. It should be understood that the elements shown in the drawings are not necessarily drawn to scale. Furthermore, it should be understood that certain embodiments may include more elements and / or a subset of the elements shown than shown in the figures. Furthermore, some embodiments may incorporate any suitable combination of features from two or more of the drawings. The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claims.

[0035] A rapidly growing use of power supplies is biasing radio frequency (RF) power amplifiers (PAs) in multiple-input, multiple-output (MIMO) cellular radios. Due to specifications supporting high-frequency transmission, these PAs can be configured as linear amplifiers rather than Class D or other switching amplifiers. Two or more supply voltages can be used to modulate the PA's bias voltage between two or more discrete voltage levels to track the RF envelope of the signal amplified by the PA on a symbol-by-symbol basis, thereby reducing and / or minimizing power consumption.

[0036] Aspects of the present disclosure relate to implementing clean, fast, rising and / or falling edge transitions at the output of a voltage modulator. The voltage modulator can be used for symbol based envelope tracking (SBET). The voltage modulator can include a pair of parallel switches with phased activation that provide fast transition times between discrete output voltage levels without generating excessive overshoot and / or power consumption. Associated with a transition between discrete output voltage levels, a smaller switch in the pair of parallel switches can activate before a larger switch in the pair of parallel switches. The transition can be associated with toggling a SBET state. The switches can include field effect transistors. For example, in certain applications, the switches can include enhancement mode metal oxide field effect transistors.

[0037] SBET envelope tracking

[0038] Figure 1 An example waveform is shown in which a PA bias voltage is modulated on a symbol by symbol basis to reduce power consumption. The PA bias voltage is modulated as a function of an RF waveform. This bias voltage modulation can reduce the power consumption of the PA. The heat dissipation can correspond to the difference between the RF waveform and the PA bias voltage. The PA bias voltage can be toggled between discrete voltage levels on a symbol by symbol basis. This technique can be referred to as symbol based envelope tracking (SBET). The PA bias voltage can track the root mean square symbol power of the RF signal in SBET.

[0039] In SBET, the PA transistor output terminal bias voltage (e.g., drain bias voltage) can only change at symbol boundaries, as shown in Figure 1 The bias voltage provided to the PA transistor output terminal (e.g., the drain of a PA field effect transistor) can have a generally constant voltage level for an entire symbol in SBET, while the envelope of the waveform has multiple peaks and valleys for the symbol. The PA transistor output terminal bias voltage can support the maximum peak power within a symbol. This can improve PA efficiency relative to using a fixed PA bias voltage. At the same time, SBET has lower implementation complexity and slower switching times compared to continuous envelope tracking.

[0040] In the case of mixed numerology carriers (e.g., in fifth generation new radio), the symbol length is shorter for higher numerologies. In this case, in certain cases, SBET can toggle at the symbol boundary of the highest numerology carrier. Alternatively, in certain other cases, SBET can toggle at the symbol boundary of the lowest numerology carrier. In either mixed numerology carrier case, the bias voltage provided by the SBET voltage modulator can only change at symbol boundaries, and the bias voltage is generally constant during each symbol.

[0041] Any suitable combination of the SBET features disclosed in one or more of U.S. Patent Publication No. 2024 / 0405725, U.S. Patent Publication No. 2025 / 0015769, or U.S. Patent Publication No. 2025 / 0015762 can be implemented in combination with the SBET features disclosed herein. The technical disclosures of U.S. Patent Publication No. 2024 / 0405725, U.S. Patent Publication No. 2025 / 0015769, and U.S. Patent Publication No. 2025 / 0015762 are all incorporated herein by reference in their entirety and for all purposes.

[0042] Radio system and transmitter channel

[0043] Figure 2 is a schematic block diagram of an example MIMO radio system 20 according to an embodiment. As shown, the MIMO radio system 20 includes a plurality of transmitter channels 22A, 22B, 22M, a plurality of power supplies 24A, 24N, and an RF and SBET control block 26. The transmitter channels 22A, 22B, 22M can be referred to as RF PA transmitter channels. The plurality of transmitter channels 22A, 22B, 22M can each include a PA 27, bypass capacitors 23A through 23N, a voltage multiplexer 28, and an antenna 29. A load capacitance 25 is also shown in the transmitter channel 22A. The voltage modulator circuit can include the bypass capacitors 23A, 23N and the voltage multiplexer 28. Any suitable positive integer M of transmitter channels can be implemented. In certain applications, there can be 8 to 128 transmitter channels. For example, in certain applications, there can be 32, 64, or 128 transmitter channels.

[0044] The voltage multiplexer 28 can implement the SBET biasing of the PA 27. The voltage multiplexer 28 can have two or more power supply voltage inputs and one output. The power supply voltage inputs of the voltage multiplexer 28 are configured to receive voltages generated from the respective power supplies 24A, 24N. As shown, the power supplies 24A, 24N can be contained in a power supply array. Any suitable positive integer N of power supplies can be implemented. For example, in certain applications, there can be 2 power supplies or 4 power supplies. The output of the voltage multiplexer 28 can be connected to the PA 27 to provide a bias voltage Vbias for the PA 27. The input bypass capacitors 23A and 23N can be placed proximate to the voltage multiplexer 28 to reduce and / or minimize parasitic inductance. Figure 2 The voltage multiplexer 28 can implement the SBET biasing of the PA 27. The voltage multiplexer 28 can have two or more power supply voltage inputs and one output. The power supply voltage inputs of the voltage multiplexer 28 are configured to receive voltages generated from the respective power supplies 24A, 24N. As shown, the power supplies 24A, 24N can be contained in a power supply array. Any suitable positive integer N of power supplies can be implemented. For example, in certain applications, there can be 2 power supplies or 4 power supplies. The output of the voltage multiplexer 28 can be connected to the PA 27 to provide a bias voltage Vbias for the PA 27. The input bypass capacitors 23A and 23N can be placed proximate to the voltage multiplexer 28 to reduce and / or minimize parasitic inductance.

[0045] Power supply voltages VDD1 to VDDn from power supplies 24A, 24N can be provided to two or more transmitter channels 22A, 22B, 22M. Power supplies 24A to 24N can be implemented as discrete voltage sources. Power supplies 24A to 24N can be implemented as voltage sources in series. Each of power supplies 24A to 24N can provide a non-zero power supply voltage.

[0046] RF and SBET control block 26 can generate an RF input signal (e.g., one of TX RF input 1 to TX RF input M) for PA 27, generate a second bias input signal (e.g., one of TX bias input 1 to TX bias input M) for PA 27, and generate one or more voltage multiplexer control signals (e.g., one of SBET control input 1 to SBET control input M) for each transmitter channel 22A to 22M. The one or more voltage multiplexer control signals can control switches of voltage multiplexer 28 to select a bias voltage Vbias that tracks an envelope of the RF signal. Each voltage multiplexer 28 can include a decoder to decode the one or more voltage multiplexer control signals in certain applications. The voltage level of bias voltage Vbias can be adjusted according to a sign boundary of the RF signal. Bias voltage Vbias can track the envelope of the RF signal on a symbol-by-symbol basis. In some cases, bias voltage Vbias can track the envelope of the RF signal for a group of symbols and / or each individual symbol. Bias voltage Vbias can be applied to an output (e.g., drain) of PA 27. The second bias input signal of PA 27 can be a bias signal for an input terminal (e.g., gate) of PA 27.

[0047] Power delivered from power supplies 24A, 24N can be limited by circuit breakers and / or fuses. Alternatively, voltage multiplexer 28 can incorporate electronic circuit breaker protection. In this case, voltage multiplexer 28 for each transmitter channel 22A to 22M can provide electronic circuit breaker protection.

[0048] PA 27 can amplify the RF input signal. PA 27 can be implemented by any suitable transistor. In certain applications, PA 27 can include a gallium nitride (GaN) field effect transistor. Antenna 29 can be coupled to an output of PA 27. Antenna 29 can transmit an output signal. Antennas 29 of transmitter channels 22A, 22B, 22M can perform beamforming in certain applications.

[0049] Figure 3is a schematic diagram of a transmitter channel 30 having a dual input bias voltage multiplexer 32 for biasing a PA 27. The transmitter channel 30 is configured to receive two different supply voltages VDD1 and VDD2. The voltage multiplexer 32 is configured to modulate a bias voltage Vbias by actuating switches 34A and 34B to selectively electrically connect input nodes at the supply voltages VDD1 and VDD2, respectively, to an output node that provides the bias voltage Vbias. The voltage multiplexer 32 can include a decoder 35 to control switching of the switches 34A and 34B to produce a bias voltage Vbias of discrete voltage levels. The decoder 35 can provide binary output signals to control the switches 34A and 34B. The decoder 35 can decode a control signal Control. In some applications, the decoder 35 can receive a ternary level input control signal to actuate the switches 34A and 34B, with a third level decoded to open both switches simultaneously. The control signal Control can be provided by a control block, such as Figure 2 RF and SBET control block 26 in FIG. 1.

[0050] Modulation of the PA bias voltage Vbias can significantly reduce power consumption. However, there are technical challenges to achieve a fast settling transition in the case where the output of the voltage multiplexer has a relatively small amount of overshoot. For example, a voltage modulator arranged to produce a SBET bias voltage can have a transition time of 10 nanoseconds (ns), and the voltage can step significantly (e.g., from approximately 25 volts (V) to approximately 50 V). This can result in a high slew rate. Staged activation of parallel switches in the SBET voltage modulator can enable a clean transition without significant overshoot or ringing.

[0051] Edge transition of SBET voltage modulator

[0052] It is desirable to achieve a clean, fast, rising edge and falling edge transition at the output of the SBET voltage modulator to preserve the integrity of the “0” symbol, which can be the first symbol after a rising edge or falling edge transition. A fast settling transition with minimal overshoot can also reduce and / or minimize one or more of device electrical overstress (EOS), electromagnetic interference (EMI), or power consumption.

[0053] The present disclosure provides a scheme for a staged metal oxide semiconductor field effect transistor (MOSFET) switch that can meet the relatively fast transition time specification (e.g., < 50 nanoseconds) of the SBET voltage modulator without generating excessive overshoot and / or power consumption.

[0054] Figure 4Ais an implementation schematic of a double-input single-output SBET voltage modulator 40. As shown, the SBET voltage modulator 40 includes a first field effect transistor 42 and a second field effect transistor 44. The field effect transistors 42 and 44 can respectively implement the switches 34A and 34B in Figure 3 . A first supply voltage VDD1 can be provided to the first field effect transistor 42. A second supply voltage VDD2 can be provided to the second field effect transistor 44. The supply voltages VDD1 and VDD2 can be respectively provided by the power supplies 24A and 24B.

[0055] Figure 4B , 4C , 4D and 4E are graphs related to the operation of the SBET voltage modulator 40 of Figure 4A . Figure 4B is a current graph of the voltage sources VDD1 and VDD2. Figure 4C is a gate voltage graph of the first field effect transistor 42. Figure 4D is a gate voltage graph of the second field effect transistor 44. Figure 4E is a bias voltage graph provided by the SBET voltage modulator 40 to the PA. Figure 4E indicates that the ringing causes the bias voltage of the PA to be almost twice the target bias voltage.

[0056] Using the SBET voltage modulator 40 of Figure 4A , a large voltage overshoot can occur at the switch output node SW, as well as a corresponding supply current transient of the supply voltages VDD1 and VDD2. These transients can be a result of energy storage in parasitic inductances, such as a first parasitic inductance LVDD1 and a second parasitic inductance LVDD2. An effective series inductance (ESL) of the load capacitance 25 can be designed to create a self-resonant impedance centered at the carrier frequency of the PA.

[0057] The first parasitic inductance LVDD1 and the second parasitic inductance LVDD2 can model the ESL typically present in the bypass capacitors of the supply voltages VDD1 and VDD2, respectively. Such bypass capacitors can correspond to the bypass capacitors 24A and 24N of Figure 2 and / or Figure 3 . The inductor LTline can model the distributed inductance of a quarter- wavelength frequency transmission line connecting the switch output node SW and the PA load. The power amplifier load is shown as the resistor R1 in Figure 4A . The PA load can be a PA, such as the PA 29 in Figure 3 .

[0058] Figure 5Ais a schematic diagram of SBET voltage modulator 50. SBET voltage modulator 50 is one solution for reducing and / or minimizing voltage overshoot and / or undershoot at switch output node SW. SBET voltage modulator 50 is similar to SBET voltage modulator 40 of Figure 4A , except that R-C buffer 52 is included in SBET voltage modulator 50. R-C buffer 52, which includes resistor R2 and capacitor C2, is placed in parallel at switch output node SW. The loss introduced by resistor R2 can suppress the effects of parasitic inductance in the system, resulting in smaller settling transients at switch output node SW when charging and discharging switch output node SW. Charging and discharging R-C buffer 52 can cause power current transients of voltage sources VDD1 and VDD2 to be larger than desired, which can result in unnecessary power consumption. R-C buffer 52 can take a relatively long time to discharge.

[0059] Figure 5B , 5C , 5D and 5E are graphs related to the operation of SBET voltage modulator 50 of Figure 5A . Figure 5B is a graph of current of voltage sources VDD1 and VDD2. Figure 5C is a graph of gate voltage of first field effect transistor 42. Figure 5D is a graph of gate voltage of second field effect transistor 44. Figure 5E is a graph of bias voltage provided by SBET voltage modulator 40 to PA. R-C buffer 52 can suppress the settling transients of the bias voltage provided to PA. This is reflected in the graph of Figure 5E . The power current transfer associated with switching the bias voltage PA between first power voltage VDD1 and second power voltage VDD2 can be higher than desired. The power current transients are shown in Figure 5B .

[0060] Phased activation of voltage modulator switches

[0061] To achieve ideal edge transitions with relatively small overshoot and relatively small power current transients, the switches of a voltage modulator can be implemented by field effect transistors in parallel with each other. The parallel field effect transistors can be turned on at different times to provide the desired edge characteristics to the bias voltage of a power amplifier. Such parallel switches can be implemented in a voltage modulator arranged to produce a SBET bias voltage, which can have transition times of 10s of ns, and the voltage can step significantly, by 10s of V or 20s of V, from one state to another.

[0062] Figure 6Ais a schematic diagram of an SBET voltage modulator 60 having switches implemented by parallel field effect transistors according to an embodiment. The SBET voltage modulator 60 is a technical solution that aims to achieve ideal edge transitions at the output of the SBET voltage modulator with relatively minimal overshoot and undershoot. The SBET voltage modulator 60 includes a first pair of field effect transistors 42 and 62 and a second pair of field effect transistors 44 and 46. The field effect transistors 42, 62, 44, and 64 can be metal oxide semiconductor field effect transistors (MOSFETs). The field effect transistors 42, 62, 44, and 64 can be enhancement mode MOSFETs. The field effect transistors 42, 62, 44, and 64 can be used as switches. The field effect transistors 62 and 64 are arranged in parallel with the field effect transistors 42 and 44, respectively. The field effect transistors 62 and 64 can be much smaller than the field effect transistors 42 and 44, respectively, resulting in the field effect transistors 62 and 64 having much larger on-resistances. The field effect transistor 42 can occupy more physical area than the field effect transistor 62. In some cases, the gate width of the field effect transistor 42 can be at least 4 times the gate width of the field effect transistor 62. In certain applications, the gate width of the field effect transistor 42 can be at least 8 times the gate width of the field effect transistor 62. The field effect transistor 44 can occupy more physical area than the field effect transistor 64. In some cases, the gate width of the field effect transistor 44 can be at least 4 times the gate width of the field effect transistor 64. In certain applications, the gate width of the field effect transistor 44 can be at least 8 times the gate width of the field effect transistor 64.

[0063] Figure 6B 、 6C , 6D and 6E are graphs related to the operation of the SBET voltage modulator 60 of Figure 6A . Figure 6B is a current graph of the voltage sources VDD1 and VDD2. Figure 6C is a gate voltage graph of the field effect transistors 42 and 62. Figure 6D is a gate voltage graph of the field effect transistors 44 and 46. Figure 6E is a bias voltage graph provided by the SBET voltage modulator 60 to the PA.

[0064] The SBET voltage modulator 60 includes phased activation of switches. The SBET voltage modulator 60 is configured to receive a plurality of supply voltages VDD1 and VDD2. The SBET voltage modulator 60 is configured to output a selected one of the supply voltages VDD1 and VDD2 at a switch output node SW based on a SBET state. The SBET state can correspond to a peak signal power of a sign of an RF signal amplified by a power amplifier. The peak power can be a peak root mean square (RMS) signal power. The SBET state can correspond to a peak complex power sign of an RF signal amplified by a power amplifier, where the RF signal includes a plurality of carriers.

[0065] Each of the supply voltages VDD1 and VDD2 is a non-zero voltage. The supply voltages VDD1 and VDD2 can differ from each other by at least 10 V. The voltage of the supply voltage VDD2 having the lower voltage can be at least one quarter of the voltage of the supply voltage VDD1 having the higher voltage level. In some such cases, the voltage of the supply voltage VDD2 having the lower voltage can be at least one half of the voltage of the supply voltage VDD1 having the higher voltage level.

[0066] In the SBET voltage modulator 60, a first switch (e.g., field effect transistor 42) is in parallel with a second switch (e.g., field effect transistor 62). The first switch (e.g., field effect transistor 42) is configured to turn on after the second switch (e.g., field effect transistor 62) associated with a sign-based envelope tracking state transition, e.g., as shown in Figure 6C The first switch (e.g., field effect transistor 42) and the second switch (e.g., field effect transistor 62) can pass the first supply voltage VDD1 when turned on. Figure 6E It is shown that, in an example application, the first supply voltage VDD1 can be 48 V. In the SBET voltage modulator 60, a third switch (e.g., field effect transistor 44) can pass the second supply voltage VDD2 when turned on. Figure 6E It is shown that, in an example application, the second supply voltage VDD2 can be 24 V.

[0067] At the instant of a rising edge transition on the switch output node SW, the field effect transistor 62 is boosted and the field effect transistors 44 and 64 are cut off. This corresponds to a rising bias voltage of Figure 6B first a gate voltage transition in Figure 6C and 6D Boosting a field effect transistor can refer to turning on the field effect transistor. Cutting off a field effect transistor refers to turning off the field effect transistor.

[0068] When enhancement transistor 62 is enhanced, field effect transistors 44 and 64 can still be enhanced. This can be referred to as a turn-on-before-turn-off switching scheme.

[0069] The switch output node SW voltage can then rise within a large portion of the transition band between power supply voltages VDD2 and VDD1. Field effect transistor 42 is then enhanced to complete the rising edge transition of switch output node SW with a relatively low or minimal settling error. Figure 6C The gate voltage of field effect transistor 42 is shown rising after the gate voltage of field effect transistor 62.

[0070] At the instant of the falling edge transition of the bias voltage, both field effect transistors 42 and 62 are turned off, and field effect transistor 64 is enhanced. This corresponds to Figure 6E a falling bias voltage, Figure 6C a falling gate voltage, and Figure 6D a rising gate voltage of field effect transistor 64.

[0071] Field effect transistor 64 can be enhanced while field effect transistors 42 and 62 are still enhanced. Field effect transistor 44 is enhanced after switch output node SW has transitioned to approximately the second power supply voltage VDD2, completing the falling edge transition with a low or minimal settling error. While the turn-on-before-turn-off switching scheme can result in a shoot-through current transient between power supply voltages VDD1 and VDD2, the resulting average power dissipation can not be significant, with only load capacitance 25 being charged or discharged, respectively, during the rising or falling edge transition.

[0072] The interval between enhancing field effect transistors 62 and 42 can be a fixed delay, or the interval can be a function of the voltage at switch output node SW. Similarly, the interval between enhancing field effect transistors 64 and 44 can be a fixed delay, or the interval can be a function of the voltage at switch output node SW.

[0073] Phased enhancement can involve splitting a top gate and bottom gate field effect transistor into two or more parallel devices, one of which can be much smaller than the other devices. Ringing and overshoot of the switch output can then be reduced and / or minimized by enhancing the smaller device and waiting for the switch output to rise or fall before enhancing the second device. Phased enhancement can also reduce and / or minimize power supply current spikes and power dissipation that are not directly related to changing the switch output voltage.

[0074] Segmented activation is an effective method to implement an SBET voltage modulator. Segmented activation of field effect transistor (e.g., MOSFET) switches can drive the switching output nodes of an SBET voltage modulator without significant ringing and overshoot. An SBET voltage modulator with segmented activation of field effect transistor (e.g., MOSFET) switches can be implemented as an integrated circuit.

[0075] Any switch of a voltage modulator disclosed herein can be segmented into a sub-switch with magnetic field cancellation. Magnetic field cancellation can be achieved by current loops that produce magnetic fields in opposite directions. A sub-switch can include a pair of switches contained in current loops with different bypass capacitors. The current loops can produce magnetic fields with opposite directions for magnetic field cancellation.

[0076] Figure 7 FIG. 42A is a schematic diagram of a pair of switches 42A, 42B with magnetic field cancellation and associated bypass capacitors 23A1, 23A2. A first current loop including a first switch 42A and a first bypass capacitor 23A1 can produce a first magnetic field in a first direction (e.g., into the plane of the page). A second current loop including a second switch 42B and a second bypass capacitor 23A2 can produce a second magnetic field in a second direction (e.g., out of the plane of the page), where the second direction is opposite to the first direction. The first and second magnetic fields are opposite magnetic fields that can cancel each other. For such cancellation, the first and second magnetic fields can have approximately the same magnitude and opposite directions. Magnetic field cancellation can be important even though such magnetic field cancellation can not completely cancel the first and second magnetic fields. Lower magnetic fields resulting from the cancellation of magnetic fields can reduce inductance.

[0077] Segmented activation of switches disclosed herein can be applied to switches of a voltage modulator implemented as common-drain switches. The switches of a voltage modulator can be implemented by common-drain switches, which can connect the output nodes of a voltage modulator to a supply voltage. The common-drain switches can be common-drain, back-to-back MOSFET switches. A smaller switch can be connected in parallel with a switch including a pair of common-drain switches, where the smaller switch can be activated before the switch including the pair of common-drain switches to implement segmented activation according to any of the principles and advantages disclosed herein. In some applications, the smaller switch can include a common-drain switch. In some cases, the smaller switch can include a switch connected in parallel with one of the common-drain switches.

[0078] While embodiments disclosed herein can be discussed with reference to field effect transistor switches or MOSFET switches, any other suitable switch can be alternatively or additionally implemented in accordance with any suitable principles and advantages disclosed herein. Such switches can include, but are not limited to, transistors, field effect transistors, complementary metal-oxide-semiconductor (CMOS) transistors, junction field effect transistors, integrated gate bipolar transistors, diode switches, microelectromechanical system switches, and the like.

[0079] While embodiments disclosed herein can be discussed with reference to SBET voltage modulators having 2 voltage sources, any suitable principles and advantages disclosed herein can be applied to SBCT voltage modulators having 3 or more voltage sources. As one example, any suitable principles and advantages disclosed herein can be applied to SBET voltage modulators that can selectively provide one of four non-zero supply voltages as an output voltage.

[0080] Conclusions

[0081] In the above embodiments, apparatuses for systems and / or SBET voltage modulators, voltage modulator systems, and methods are described in connection with specific embodiments. However, it should be understood that principles and advantages of the embodiments can be applied to any other system, apparatus, or method that requires a voltage modulator and / or envelope tracking disclosed herein. Moreover, any suitable principles and advantages disclosed herein can be implemented in systems and methods that include power amplifiers that amplify radio frequency signals for transmission through an antenna.

[0082] The principles and advantages described herein can be implemented in various devices. Examples of such devices can include, but are not limited to, communication infrastructure, such as wireless or wired communication infrastructure, consumer electronics, components of consumer electronics devices, electronic test equipment, vehicle electronics, industrial electronics, and the like. Electronic products can include, but are not limited to, base stations, such as cellular base stations, access points, repeaters, relays, wireless communication devices, mobile phones (e.g., smartphones), handheld computers, tablets, laptops, wearable computing devices, vehicle electronics systems, radios, wearable health monitoring devices, Internet of Things (IoT) devices, and the like. Moreover, devices can include unfinished products.

[0083] Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise," "comprising," "include," "including," and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of "including, but not limited to." Additionally, the words "coupled" or connected" or "coupling" or "connecting" as used in the specification refer to any connection or coupling, either direct or indirect, between or among two or more elements. Moreover, the use of "about" or "approximately" in connection with a recited numerical value means that the algebraic value of the number is "within" the numerical value, meaning, for example, that the actual value is within 10%, 5%, 1%, 0.5%, or 0.05% of the recited value, as appropriate. Furthermore, the use of the term "or" in the context of a recited list of items means that any of the items in the list can be present or omitted, i.e., the term "or" is used in the inclusive, not the exclusive, sense. Unless otherwise expressly specified, all numerical values provided herein are intended to include similar values within manufacturing tolerances thereof.

[0084] Also, unless specifically stated otherwise, or as can be clearly inferred from the specification, terms used throughout the description, and the claims, which can have different meanings under different contexts, take on the meanings consistent with those in the field of the technology to which the description pertains. Furthermore, conditional language, such as, among others, "can," "could," "might," "may," "e.g.," "for example," "such as," and the like, typically are intended to convey that a discussed feature, element, and / or act is not required, but is an example of an implementation.

[0085] The teachings provided herein can be applied to other systems, not necessarily the system described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments. The acts of the methods discussed herein can be performed in any order, as appropriate, unless otherwise specified and / or as can be indicated by the specification. Additionally, the acts of the methods discussed herein can be performed in serial, in parallel, or in any appropriate order.

[0086] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel methods and systems described herein can be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein can be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments are presented in a given arrangement, alternative embodiments can perform similar functions by using different components and / or circuit topologies, and can delete, move, add, subdivide, combine and / or modify some elements. Each of these elements can be implemented in various different ways as appropriate. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. The claims, and their equivalents, are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.

Claims

1. A system for symbol-based envelope tracking phased activation of switches, the system comprising: a voltage modulator configured to receive a plurality of supply voltages and output a selected one of the plurality of supply voltages at an output node based on a symbol-based envelope tracking state, the voltage modulator comprising: a first switch; a second switch in parallel with the first switch, wherein the first switch is configured to activate after the second switch is associated with a transition of the symbol-based envelope tracking state from a first state to a second state, and wherein the first switch and the second switch are configured to pass a first supply voltage to the output node in the second state; and a third switch configured to pass a second supply voltage to the output node in the first state; and a power amplifier electrically connected to the output node, the power amplifier configured to amplify a radio frequency signal.

2. The system of claim 1, wherein the first switch occupies more physical area than the second switch.

3. The system of claim 1, wherein the voltage modulator comprises a fourth switch in parallel with the third switch, wherein the third switch is configured to activate after the fourth switch is associated with a transition of the symbol-based envelope tracking state from the second state to the first state.

4. The system of claim 1, wherein the power amplifier comprises a gallium nitride transistor.

5. The system of claim 1, wherein a voltage at the output node has a higher voltage level in the second state than in the first state, wherein the voltage at the output node in the first state is greater than 0 volts, and wherein the voltage at the output node in the first state is at least one fourth of the voltage at the output node in the second state.

6. The system of claim 1, wherein the first switch and the second switch are field effect transistors.

7. The system of claim 1, wherein the first switch comprises a pair of sub-switches with magnetic field cancellation.

8. The system of claim 1, wherein the voltage modulator is configured to perform a turn-on-before-turn-off switching.

9. The system of claim 1, wherein the voltage modulator is configured to transition a voltage at the output node between the first supply voltage and the second supply voltage in less than 50 nanoseconds, and wherein a difference between the first supply voltage and the second supply voltage is at least one fourth of a higher one of the first supply voltage and the second supply voltage.

10. The system of claim 1, wherein the voltage at the output node tracks an envelope of the radio frequency signal from symbol to symbol.

11. A voltage multiplexing method of phased activation of switches, the method comprising: providing a first supply voltage of a plurality of supply voltages as an output voltage using a switch in a first state; activating a pair of parallel switches in association with a transition from the first state to a second state such that a second switch of the pair of parallel switches activates before a first switch of the pair of parallel switches; and providing a second supply voltage of the plurality of supply voltages as the output voltage using the second switch in the second state. using the pair of parallel switches in the second state provides a second supply voltage of the plurality of supply voltages as the output voltage, wherein the first supply voltage and the second supply voltage are at different discrete non-zero voltage levels when provided as the output voltage.

12. The method of claim 11, further comprising biasing a power amplifier with the output voltage and amplifying a radio frequency signal using the power amplifier.

13. The method of claim 12, wherein the first state and the second state are symbol-based envelope tracking states associated with a symbol of the radio frequency signal.

14. The method of claim 12, wherein the output voltage tracks an envelope of the radio frequency signal on a symbol-by-symbol basis.

15. The method of claim 11, wherein the activation occurs at a symbol boundary of a radio frequency signal amplified by a power amplifier that receives the output voltage.

16. The method of claim 11, wherein the first switch occupies more physical area than the second switch.

17. The method of claim 11, further comprising activating a second pair of parallel switches in association with transitioning from the second state to the first state such that a fourth switch is activated before a third switch, wherein the second pair of parallel switches includes the third switch and the fourth switch.

18. A voltage modulator that activates a switch in stages, the voltage modulator comprising: a first switch; a second switch in parallel with the first switch, wherein the first switch is configured to activate after the second switch in association with a transition from a first state to a second state, and wherein the first and second switches are configured to pass a first supply voltage to an output node in the second state; and a third switch configured to pass a second supply voltage to the output node in the first state, wherein the voltage modulator is configured to receive a plurality of non-zero supply voltages including the first supply voltage and the second supply voltage.

19. The voltage modulator of claim 18, wherein the voltage modulator is configured to perform a make-before-break switching, and wherein the first switch occupies more physical area than the second switch.

20. The voltage modulator of claim 18, wherein the first switch includes a pair of sub-switches with magnetic field cancellation.

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