Method of double BIOS (Basic Input / Output System) image processing mechanism
By utilizing a multi-interface and timer mechanism to detect and repair the BIOS image during the computer system's power-on self-test phase, the problem of inaccurate BIOS problem detection in existing technologies is solved, ensuring stable startup of the computer system.
Patent Information
- Application Number
- CN202410452216.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-16
- Publication Date
- 2025-10-24
AI Technical Summary
Existing dual BIOS imaging technology only performs BIOS boot checks through a single interface, which cannot accurately detect problems with the BIOS image, potentially causing the computer system to fail to boot normally.
During the power-on self-test phase, the baseboard management controller uses multiple interfaces (first hardware management interface, second hardware management interface, and third hardware management interface) to detect the BIOS image, including detecting the coordination of the start timer, end timer, and watchdog timer, and performing the BIOS repair program.
It enables more accurate detection of BIOS image problems and performs BIOS repair when anomalies are detected, ensuring that the computer system can start normally and reducing the risk of system crashes caused by BIOS failure.
Smart Images
Figure CN120832267A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of computer technology, and particularly relates to an electronic digital data processing method, in particular to a dual-BIOS image processing method. BACKGROUND
[0002] In a computer system with a single Basic Input / Output System (BIOS) image, the BIOS itself becomes a single point of failure. If the computer system is attacked maliciously, the BIOS image is damaged, or an error occurs during the BIOS upgrade, the computer system will not be able to start normally. Such a situation may require a complex recovery program and may cause data loss.
[0003] To solve the problem of a single BIOS image, a dual BIOS image technology is usually used. When the main BIOS image fails, the backup BIOS image can be used to replace it to provide a backup mechanism to reduce the risk of the computer system being unable to start due to a single BIOS failure.
[0004] Although the dual BIOS image technology solves the problem of a single BIOS image, the existing dual BIOS image technology only performs BIOS startup checks through a single interface, which cannot accurately check the problem of the BIOS image. SUMMARY
[0005] The main purpose of the present application is to provide a dual-BIOS image processing method that can perform BIOS startup checks through multiple interfaces.
[0006] To solve the above technical problems, the present application provides the following technical solutions:
[0007] A method of a dual-BIOS image processing mechanism, performed by a baseboard management controller of a computer system, the computer system storing a default BIOS image and a golden BIOS image, the method comprising: (A) after receiving a power-on signal, loading one of the default BIOS image and the golden BIOS image, and simultaneously starting a detection start timer set with a start timeout period and a detection end timer set with an end timeout period, the end timeout period being greater than the start timeout period; (B) determining whether a power-on self-test code is received via a first hardware management interface before the detection start timer expires, and when it is determined that the power-on self-test code is not received via the first hardware management interface before the detection start timer expires, performing a BIOS repair procedure; and (C) determining whether a falling edge signal or a rising edge signal is received via a second hardware management interface before the detection end timer expires, the second hardware management interface being different from the first hardware management interface, and when it is determined that the falling edge signal or the rising edge signal is not received via the second hardware management interface before the detection end timer expires, performing the BIOS repair procedure.
[0008] Preferably, in step (B), when it is determined that the power-on self-test code is received via the first hardware management interface before the detection start timer expires, step (D) is performed: (D) determining whether an enter-recovery-mode instruction is received via a third hardware management interface, the third hardware management interface being different from the first hardware management interface and the second hardware management interface, and when it is determined that the enter-recovery-mode instruction is received via the third hardware management interface, performing the BIOS repair procedure.
[0009] Preferably, in step (D), when it is determined that the enter-recovery-mode instruction is not received via the third hardware management interface, determining whether a watchdog timer set with a watchdog timeout period expires, the watchdog timeout period being greater than the start timeout period and less than the end timeout period, and when it is determined that the watchdog timer expires, performing the BIOS repair procedure.
[0010] Preferably, between step (A) and step (C), there is further included a step (E) of determining whether a first specific POST code is received via the first hardware management interface before the end of test timer expires, when it is determined that the first specific POST code is not received via the first hardware management interface before the end of test timer expires, step (C) is performed, when it is determined that the first specific POST code is received via the first hardware management interface before the end of test timer expires, step (F) is performed; (F) interrupting and suspending the end of test timer; (G) determining whether a second specific POST code is received via the first hardware management interface, when it is determined that the second specific POST code is not received via the first hardware management interface, step (G) is repeated until the second specific POST code is received, when it is determined that the second specific POST code is received via the first hardware management interface, step (H) is performed; and (H) resuming the end of test timer.
[0011] Preferably, in step (E), the first specific POST code is, for example, a code indicating entering a test mode, and in step (G), the second specific POST code is a code indicating ending the test mode.
[0012] Preferably, the BIOS repair procedure further includes a step (I) of determining whether the golden BIOS image has been loaded, when it is determined that the golden BIOS image has not been loaded, step (J) is performed; (J) switching from loading the default BIOS image to loading the golden BIOS image; and (K) triggering a reboot.
[0013] Preferably, before step (I), there is further included a step (L) of generating and storing a first system event log indicating a boot failure.
[0014] Preferably, between step (J) and (K), there is further included a step (M) of generating and storing a second system event log indicating that the golden BIOS image has been switched to.
[0015] Preferably, in step (I), when it is determined that the golden BIOS image has been loaded, step (N) is performed: (N) interrupting the boot, and generating and storing a baseboard management controller log.
[0016] The present invention has the effect of detecting the boot status through the first hardware management interface and the second hardware management interface by the baseboard management controller, and executing the BIOS repair program when the baseboard management controller finds an abnormality through the first hardware management interface or the second hardware management interface, thereby being able to more accurately detect problems with the BIOS image. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Other features and effects of the present invention will be clearly presented in the embodiments with reference to the accompanying drawings, in which:
[0018] Figure 1 is a block diagram illustrating a computer system for implementing a method for a dual BIOS image processing mechanism according to an embodiment of the present invention;
[0019] Figure 2 is a flow chart illustrating a boot check procedure of the embodiment of the method of the dual BIOS image processing mechanism of the present invention; and
[0020] Figure 3 The present invention is a flowchart illustrating a BIOS repair process of the dual BIOS image processing mechanism according to the embodiment of the present invention. DETAILED DESCRIPTION
[0021] Before the present invention is described in detail, it should be noted that similar elements are denoted by the same reference numerals in the following description.
[0022] See Figure 1 , illustrating a computer system 1 for implementing an embodiment of a method for a dual BIOS image processing mechanism of the present invention, comprising a memory 11, a central processing unit (CPU) 12, a baseboard management controller (BMC) 13, a first hardware management interface 17, a second hardware management interface 18, a third hardware management interface 19, and a system management bus (SMBus) 10. The memory 11 is electrically connected to the CPU 12 and the baseboard management controller 13. The system management bus 10 is electrically connected to the CPU 12, the baseboard management controller 13, the detection start timer, the watchdog timer, and the detection end timer. The computer system is, for example, but not limited to, a server or an embedded system.
[0023] The memory 11 is, for example, a non-volatile memory (NVM) storing a default BIOS image and a golden BIOS image.
[0024] The memory stores a detection start timer, a watchdog timer, and a detection end timer. The detection start timer is set with a start timeout, the watchdog timer is set with a watchdog timeout, and the detection end timer is set with an end timeout. The end timeout is greater than the start timeout, and the watchdog timeout is greater than the start timeout and less than the end timeout. It is to be noted that when a timer is started, if it is not reset or stopped before the timeout, the timer timeout is triggered.
[0025] In the embodiment, the detection start timer, the watchdog timer, and the detection end timer are implemented by software. The start timeout is, for example, 10 seconds, the watchdog timeout is, for example, 720 seconds, and the end timeout is, for example, 900 seconds. In other embodiments, the detection start timer, the watchdog timer, and the detection end timer can be implemented by hardware, without being limited thereto.
[0026] The first hardware management interface 17 is, for example, an enhanced serial peripheral interface (eSPI) or a low pin count (LPC) interface. The second hardware management interface 18 is, for example, a general purpose input / output (GPIO) interface. The third hardware management interface 19 is, for example, an intelligent platform management interface (IPMI).
[0027] The method of the dual-BIOS image processing mechanism is performed in a power-on self-test (POST) stage, and includes a power-on check program 2 and a BIOS repair program 3.
[0028] Referring to Figure 1 , 2 The power-on check program 2 of the embodiment of the method of the dual-BIOS image processing mechanism will be described below.
[0029] In step 201, after receiving a power on signal, the baseboard management controller 13 loads one of the pre-set BIOS image and the golden BIOS image, and starts the detection start timer and the detection end timer.
[0030] It is worth noting that in the present embodiment, the power on signal can come from a power management circuit, a remote tool, or other designated hardware, but is not limited thereto.
[0031] In step 202, the baseboard management controller 13 determines whether a power on self-test code is received via the first hardware management interface 17 before the detection start timer expires. When it is determined that the power on self-test code is not received via the first hardware management interface 17 before the detection start timer expires, the BIOS repair program 3 is performed; when it is determined that the power on self-test code is received via the first hardware management interface 17 before the detection start timer expires, step 203 is performed.
[0032] It is worth noting that a plurality of power on self-test codes are generated during the power on self-test process, which are used to indicate various stages of the hardware power on self-test process, i.e. each stage of the power on self-test corresponds to a power on self-test code, and the central processing unit 12 transmits the plurality of power on self-test codes via the first hardware management interface 17.
[0033] In step 203, the baseboard management controller 13 determines whether an enter recovery mode instruction is received via the third hardware management interface 19. When it is determined that the enter recovery mode instruction is received via the third hardware management interface 19, the BIOS repair program 3 is performed; when it is determined that the enter recovery mode instruction is not received via the third hardware management interface 19, step 204 is performed.
[0034] It is worth noting that when the power on self-test stage is performed, a BIOS code executed by the central processing unit 12 determines whether it needs to enter the recovery mode, and if so, transmits the enter recovery mode instruction to the baseboard management controller 13 via the third hardware management interface 19.
[0035] In step 204, the baseboard management controller 13 determines whether the watchdog timer expires. When it is determined that the watchdog timer expires, the BIOS repair program 3 is performed.
[0036] It is worth noting that the watchdog timer is often used in Fault Resilient Booting (FRB) level 2, and the watchdog timer can also be called FRB2 timer. When the POST stage is performed, the BIOS code executed by the central processor 12 can determine the start and stop time of the watchdog timer.
[0037] In step 201, the baseboard management controller 13 starts the detection end timer. In step 205, the baseboard management controller 13 determines whether a first specific POST code is received via the first hardware management interface 17 before the detection end timer expires. When it is determined that the first specific POST code is received via the first hardware management interface 17 before the detection end timer expires, step 206 is performed; otherwise, step 209 is performed.
[0038] In step 206, the baseboard management controller 13 stops and suspends the detection end timer.
[0039] In step 207, the baseboard management controller 13 determines whether a second specific POST code is received via the first hardware management interface 17. When it is determined that the second specific POST code is received via the first hardware management interface 17, step 208 is performed; otherwise, step 207 is repeated until the second specific POST code is received.
[0040] It is worth noting that in the embodiment, the first specific POST code is, for example, a code indicating entering a testing mode, and the second specific POST code is, for example, a code indicating ending the testing mode. That is, when the central processor 12 enters the testing mode, the first specific POST code is transmitted to the baseboard management controller 13, and the baseboard management controller 13 stops and suspends the detection end timer until the central processor 12 ends the testing mode. In other embodiments, the first specific POST code and the second specific POST code can be other POST codes, and are not limited thereto.
[0041] In step 208, the baseboard management controller 13 continues to start the detection end timer.
[0042] In step 209, the baseboard management controller 13 judges whether a falling edge signal or a rising edge signal is received via the second hardware management interface 18 before the detection end timer expires. When it is judged that the falling edge signal or the rising edge signal is not received via the second hardware management interface 18 before the detection end timer expires, the BIOS repair procedure 3 is performed.
[0043] When it is judged that the watchdog timer does not expire in step 204, and it is judged that the falling edge signal or the rising edge signal is received via the second hardware management interface 18 before the detection end timer expires in step 209, the power-on self-test stage is completed.
[0044] It is particularly noted that, in other embodiments, the power-on check procedure 2 can not include step 203 or / and step 204.
[0045] In the embodiment not including step 203, when it is judged that the power-on self-test code is received via the first hardware management interface 17 before the detection start timer expires in step 202, step 204 is performed.
[0046] In the embodiment not including step 204, when it is judged that the entering recovery mode instruction is not received via the third hardware management interface 19 in step 203, and it is judged that the falling edge signal or the rising edge signal is received via the second hardware management interface 18 before the detection end timer expires in step 209, the power-on self-test stage is completed.
[0047] In the embodiment not including step 203 and step 204, when it is judged that the power-on self-test code is received via the first hardware management interface 17 before the detection start timer expires in step 202, and it is judged that the falling edge signal or the rising edge signal is received via the second hardware management interface 18 before the detection end timer expires in step 209, the power-on self-test stage is completed.
[0048] Referring to Figure 1 , 3 , the embodiment of the method of the dual-BIOS image processing mechanism of the present application, the steps included in the BIOS repair procedure 3 will be described below.
[0049] In step 301, the baseboard management controller 13 generates and stores a first system event log (SEL) indicating a boot failure to the memory 11.
[0050] In step 302, the baseboard management controller 13 determines whether the golden BIOS image has been loaded. When it is determined that the golden BIOS image has been loaded, step 303 is performed; when it is determined that the golden BIOS image has not been loaded, step 304 is performed.
[0051] In step 303, the baseboard management controller 13 interrupts the boot and generates and stores a baseboard management controller journal log to the memory 11.
[0052] It is noted that the baseboard management controller journal log has a repair message, and the baseboard management controller 13 causes the computer system to stop at the current state and wait for a developer or repair personnel to detect.
[0053] In step 304, the baseboard management controller 13 switches from loading the preset BIOS image to loading the golden BIOS image.
[0054] In step 305, the baseboard management controller 13 generates and stores a second system event log indicating that the golden BIOS image has been switched to.
[0055] In step 306, the baseboard management controller 13 triggers the central processing unit 12 to perform a reboot.
[0056] In summary, the dual-BIOS image processing mechanism method of the present application can more accurately detect a problem in a BIOS image by the baseboard management controller 13 detecting a boot condition through the first, second, and third hardware management interfaces 17, 18, and 19, and performing the BIOS repair program 3 when the baseboard management controller 13 detects an abnormality through the first, second, or third hardware management interfaces 17, 18, or 19. In addition, the baseboard management controller 13 can interrupt and pause the end-of-detection timer when it is determined that a first specific boot self-detection code is received through the first hardware management interface 17 before the end-of-detection timer times out, so as to avoid the central processing unit 12 performing a specific action for too long (e.g., a test for too long), which can cause the baseboard management controller 13 to erroneously determine a BIOS image failure due to the end-of-detection timer timing out, thereby achieving the purpose of the present application.
[0057] The above is only an embodiment of the present application, and cannot limit the scope of the present application. Any simple equivalent change and modification made according to the scope and content of the present application is still within the scope of the present application.
Claims
1. A method for a dual BIOS image processing mechanism, performed during a power-on self-test (POST) phase by a baseboard management controller (BMC) of a computer system, wherein the computer system stores a default BIOS image and a golden BIOS image, wherein: The method comprises the following steps: (A) loading one of the preset BIOS image and the golden BIOS image after receiving a power-on signal, and simultaneously starting a detection start timer with a start timeout period and a detection end timer with an end timeout period, wherein the end timeout period is greater than the start timeout period; (B) determining whether a power-on self-test code is received via a first hardware management interface before the detection start timer expires, and performing a BIOS repair procedure when it is determined that the power-on self-test code is not received via the first hardware management interface before the detection start timer expires; and (C) determining whether a falling edge signal or a rising edge signal is received via a second hardware management interface before the detection end timer expires, wherein the second hardware management interface is different from the first hardware management interface, and performing the BIOS repair procedure when it is determined that the falling edge signal or the rising edge signal is not received via the second hardware management interface before the detection end timer expires.
2. The method of dual BIOS image handling mechanism according to claim 1, wherein, In step (B), when it is determined that the power-on self-test code is received via the first hardware management interface before the detection start timer expires, step (D) is performed: (D) determining whether an enter recovery mode instruction is received via a third hardware management interface, wherein the third hardware management interface is different from the first hardware management interface and the second hardware management interface, and performing the BIOS repair procedure when it is determined that the enter recovery mode instruction is received via the third hardware management interface.
3. The method of dual BIOS image handling mechanism according to claim 2, wherein, In step (D), when it is determined that the enter recovery mode instruction is not received via the third hardware management interface, determining whether a watchdog timer with a watchdog timeout period expires, wherein the watchdog timeout period is greater than the start timeout period and less than the end timeout period, and performing the BIOS repair procedure when it is determined that the watchdog timer expires.
4. The method of dual BIOS image handling mechanism according to claim 1, wherein, Between step (A) and step (C), the following step is further included: (E) determining whether a first specific power-on self-test code is received via the first hardware management interface before the detection end timer expires, and performing step (C) when it is determined that the first specific power-on self-test code is not received via the first hardware management interface before the detection end timer expires, and performing step (F) when it is determined that the first specific power-on self-test code is received via the first hardware management interface before the detection end timer expires; (F) interrupting and pausing the detection end timer; (G) determining whether a second specific POST code is received via the first hardware management interface, when it is determined that the second specific POST code is not received via the first hardware management interface, repeating step (G) until the second specific POST code is received, when it is determined that the second specific POST code is received via the first hardware management interface, proceeding to step (H); and (H) continuing to start the detection end timer.
5. The method of dual BIOS image handling mechanism according to claim 4, wherein, In step (E), the first specific POST code is, for example, a code indicating entry into a test mode, and in step (G), the second specific POST code is a code indicating exit from the test mode.
6. The method of dual BIOS image handling mechanism according to claim 1, wherein, The BIOS repair procedure comprises the following steps: (I) determining whether the golden BIOS image has been loaded, when it is determined that the golden BIOS image has not been loaded, proceeding to step (J); (J) switching from loading the preset BIOS image to loading the golden BIOS image; and (K) triggering a reboot.
7. The method of dual BIOS image handling mechanism according to claim 6, wherein, Before step (I), the following step is further included: (L) generating and storing a first system event log indicating a boot failure.
8. The method of dual BIOS image handling mechanism according to claim 6, wherein, Between steps (J) and (K), the following step is further included: (M) generating and storing a second system event log indicating that the golden BIOS image has been switched to.
9. The method of dual BIOS image handling mechanism according to claim 6, wherein, In step (I), when it is determined that the golden BIOS image has been loaded, step (N) is performed: (N) interrupting the boot, and generating and storing a baseboard management controller log.