Forward error correction synchronization method and forward error correction synchronization system capable of recovering forward error correction block synchronization

Abstract

A forward error correction (FEC) synchronization method includes establishing a link between a source terminal and a destination terminal, periodically transmitting a flag symbol from the source terminal to the destination terminal, identifying the flag symbol by the destination terminal after the flag symbol is received by the destination terminal, and synchronizing the identified flag symbol with the destination terminal. A plurality of symbols transmitted from the source terminal are collected to generate a plurality of Forward Error Correction (FEC) blocks received by the destination terminal, and the plurality of FEC blocks are synchronized between the source terminal and the destination terminal according to the flag symbol. The mark symbol contains a predefined pattern.

Description

TECHNICAL FIELD

[0001] The present application relates to a forward error correction synchronization method and system, and more particularly, to a forward error correction synchronization method and system for recovering forward error correction block synchronization. BACKGROUND

[0002] Forward error correction (FEC) is a mechanism for recovering erroneous packets on a link by padding additional parity symbols to the packets. In other words, an FEC code can be viewed as a special code word for detecting and correcting errors. With the redundant information sent by the transmitter, the receiver is able to detect certain errors from the received data. Because FEC techniques can resist errors and improve the robustness of signal communication, FEC techniques are widely used in various high-speed multimedia communications for correcting corrupted data.

[0003] However, when the receiving terminal (viewed as a receiver) does not detect the FEC enable sequence due to a large number of bit errors or severe channel interference, although the receiving terminal can maintain symbol synchronization, it can fail in FEC block synchronization because it does not know when the source (viewed as a transmitter) starts to send FEC enabled data.

[0004] Therefore, developing an FEC synchronization system capable of recovering FEC block synchronization in high-speed multimedia communications is an important design problem. SUMMARY

[0005] In one embodiment of the present application, a forward error correction (FEC) synchronization method is disclosed. The FEC synchronization method includes establishing a connection between a source terminal and a destination terminal; periodically transmitting a marker symbol from the source terminal to the destination terminal; identifying the marker symbol by the destination terminal after the marker symbol is received by the destination terminal; collecting a plurality of symbols transmitted from the source terminal to generate a plurality of forward error correction (FEC) blocks received by the destination terminal after the marker symbol is successfully identified; and synchronizing the plurality of FEC blocks between the source terminal and the destination terminal according to the marker symbol. The marker symbol includes a predefined pattern.

[0006] In another embodiment of the present application, a forward error correction (FEC) synchronization system is disclosed. The FEC synchronization system includes a source terminal and a destination terminal coupled to the source terminal. The source terminal includes an 8b / 10b encoder and an FEC encoder coupled to the 8b / 10b encoder. The destination terminal includes a 10b / 8b decoder and an FEC decoder coupled to the 10b / 8b decoder. After a coupling between the source terminal and the destination terminal is established, the source terminal periodically transmits a marker symbol to the destination terminal. The destination terminal identifies the marker symbol after the marker symbol is received by the destination terminal. The destination terminal collects a plurality of symbols transmitted from the source terminal after the marker symbol is successfully identified to generate a plurality of FEC blocks received by the destination terminal. The plurality of FEC blocks are synchronized between the source terminal and the destination terminal by the destination terminal based on the marker symbol. The marker symbol comprises a predefined pattern.

[0007] These and other objects of the present application will no doubt become obvious to one of ordinary skill in the art after reading the following detailed description of the preferred embodiment of the application, illustrated in the various drawing figures. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a block diagram of a forward error correction (FEC) synchronization system according to an embodiment of the present application.

[0009] Figure 2 Disclosed Figure 1 is a flowchart of a method for performing FEC synchronization in the FEC synchronization system.

[0010] Figure 3 Disclosed Figure 1 is a flowchart of a method for performing FEC synchronization in the FEC synchronization system. DETAILED DESCRIPTION

[0011] Figure 1FIG. 1 is a block diagram of a forward error correction (FEC) synchronization system 100 according to an embodiment of the present application. The FEC synchronization system 100 includes a source terminal 10 and a destination terminal 11. The destination terminal 11 is connected to the source terminal 10. The source terminal 10 can be regarded as a data transmitter, such as a graphics adapter. The destination terminal 11 can be regarded as a data receiver, such as a display device or monitor. To perform high-speed data communication between the source terminal 10 and the destination terminal 11, the source terminal 10 can initiate a link training phase at an appropriate link rate and an appropriate number of channels. The destination terminal 11 can be trained to perform clock recovery, channel equalization, and symbol lock functions (i.e., M symbol bit alignment). Thus, a link L between the source terminal 10 and the destination terminal 11 can correspond to a high-speed media channel link. The source terminal 10 includes an 8b / 10b encoder 10a and an FEC encoder 10b. The FEC encoder 10b is connected to the 8b / 10b encoder 10a. Here, the 8b / 10b encoder 10a is used to encode 8-bit data segments of a data stream DS1 into 10-bit symbols for direct current (DC) balance and bounded disparity. The FEC encoder 10b can be used to perform a linear encoding mechanism on a set of symbols using a generator matrix with parity information. The FEC encoder 10b can output a plurality of FEC blocks. However, the FEC synchronization system 100 is not limited to the 8b / 10b encoder 10a and the specific size of the FEC blocks. For example, each FEC block can include N symbols. Each symbol can include M symbol bits. N and M are positive integers. In addition, the destination terminal 11 can include a 10b / 8b decoder 11b and an FEC decoder 11a. The FEC decoder 11a is connected to the 10b / 8b decoder 11b. The FEC decoder 11a can be used to decode each FEC block. The 10b / 8b decoder 11b can be used to decode each symbol encoded by the 8b / 10b encoder 10a to generate a decoded data stream DS2. In the FEC synchronization system 100, after the link L between the source terminal 10 and the destination terminal 11 is established, the source terminal 10 can periodically transmit a marker symbol to the destination terminal 11. The destination terminal 11 can recognize the marker symbol after the marker symbol is received by the destination terminal 11. Then, the destination terminal 11 can collect a plurality of symbols transmitted from the source terminal 10 to generate a plurality of FEC blocks received by the destination terminal 11 after the marker symbol is successfully recognized. Here, the plurality of FEC blocks can be synchronized between the source terminal 10 and the destination terminal 11 according to the marker symbol. The marker symbol can include a predefined pattern. Details of the FEC synchronization system 100 performing FEC block synchronization are described below.

[0012] Figure 2 FIG. 2 is a diagram of data communication between the source terminal 10 and the destination terminal 11 in the FEC synchronization system 100. In the FEC synchronization system 100, the source terminal 10 can transmit a data stream DS1 to the destination terminal 11. The data stream DS1 can include a plurality of symbols. Each symbol can include a plurality of symbol bits. The source terminal 10 can encode the data stream DS1 using an 8b / 10b encoder 10a. The 8b / 10b encoder 10a can encode the data stream DS1 into a plurality of 10-bit symbols. The 8b / 10b encoder 10a can output the plurality of 10-bit symbols to an FEC encoder 10b. The FEC encoder 10b can encode the plurality of 10-bit symbols into a plurality of FEC blocks. The FEC encoder 10b can output the plurality of FEC blocks to the destination terminal 11. The destination terminal 11 can receive the plurality of FEC blocks from the source terminal 10. The destination terminal 11 can decode the plurality of FEC blocks using an FEC decoder 11a. The FEC decoder 11a can output a decoded data stream DS2. The destination terminal 11 can decode the plurality of 10-bit symbols using a 10b / 8b decoder 11b. The 10b / 8b decoder 11b can output the decoded data stream DS2. Figure 2 In FIG, the x-axis represents a timeline. After the FEC encoder 10b of the source terminal 10 is enabled, the source terminal 10 may transmit an FEC enabling sequence FEC_EN to the destination terminal 11. Then, after the FEC enabling sequence FEC_EN is generated, the source terminal 10 may transmit P FEC blocks (e.g., FEC blocks FEC0_0 to FEC0_255) to the destination terminal 10. P may be a positive integer, such as 256 or 512. Figure 2 In the example, the destination terminal 11 may receive a plurality of symbols transmitted from the source terminal 10 and then determine whether the received symbols can be detected as an FEC enabling sequence FEC_EN. Figure 2 In the first embodiment, the sequence UN_DET formed by the received symbols cannot be recognized as the FEC enable sequence FEC_EN due to multiple bit errors or severe channel interference. Therefore, since the FEC enable sequence FEC_EN cannot be detected or recognized by the destination terminal 11, synchronization of the P FEC blocks within the first duration fails. In other words, although FEC blocks FEC0_0 through FEC0_255 are transmitted from the source terminal 10 to the destination terminal 11, since the FEC enable sequence FEC_EN cannot be detected or recognized by the destination terminal 11, the FEC decoder 11a of the destination terminal 11 is not enabled. As a result, the destination terminal 11 processes FEC blocks FEC0_0 through FEC0_255 as "data symbols." It will be understood that the source terminal 10 can transmit multiple symbols to the destination terminal 11. The destination terminal 11 can still align the M symbol bits of each symbol to synchronize the multiple symbols received by the destination terminal 11. However, since the destination terminal 11 processes the FEC blocks FEC0_0 to FEC block FEC0_255 as “data symbols”, the FEC blocks FEC0_0 to FEC block FEC0_255 cannot be decoded by the FEC decoder 11 a during the first duration.

[0013] After the source terminal 10 generates the P FEC blocks FEC0 0 to FEC0 255 in the first time duration, the source terminal 10 can generate a marker symbol TG1. Thus, at the start time point of the second time duration, the source terminal 10 can transmit the marker symbol TG1 to the destination terminal 11. Then, after the marker symbol TG1 is transmitted from the source terminal 10 to the destination terminal 11, the source terminal 10 can transmit the P FEC blocks FEC1 0 to FEC1 255 to the destination terminal 11. As mentioned previously, the marker symbol TG1 contains a predefined pattern. Thus, after the destination terminal 11 obtains the predefined pattern, the destination terminal 11 can compare the predefined pattern with the marker symbol TG1 received by the destination terminal 11 to identify the marker symbol TG1. If the marker symbol TG1 is successfully identified by the destination terminal 11, it means that the start time point of the transmission of the P FEC blocks FEC1 0 to FEC1 255 from the source terminal 10 can be aligned by the destination terminal 11. Thus, although the destination terminal 11 loses synchronization of the P FEC blocks FEC0 0 to FEC0 255 in the first time duration, the destination terminal 11 can "recover" the synchronization of the P FEC blocks FEC1 0 to FEC1 255 in the second time duration according to the marker symbol TG1. After the P FEC blocks FEC1 0 to FEC1 255 are synchronized, the FEC decoder 11a of the destination terminal 11 can be enabled to decode the P FEC blocks FEC1 0 to FEC1 255. Likewise, after the source terminal 10 generates the P FEC blocks FEC1 0 to FEC1 255 in the second time duration, the source terminal 10 can generate a marker symbol TG2. The marker symbol TG1 and the marker symbol TG2 can be the same. In other words, the marker symbol TG1 can be generated periodically. The period of the marker symbol TG1 can be defined as the transmission time difference between the marker symbol TG1 and the marker symbol TG2, which is equal to the length of time of the transmission of the P FEC blocks FEC1 0 to FEC1 255. Likewise, if the marker symbol TG2 is successfully identified by the destination terminal 11, the subsequent FEC blocks following the marker symbol TG2 can also be synchronized by the destination terminal 11.

[0014] In the FEC synchronization system 100, any hardware or technical modification is within the scope of the present application. For example, when the source terminal 10 terminates the FEC encoder 10b, the source terminal 10 can transmit a FEC disable sequence to the destination terminal 11. Then, the destination terminal 11 can receive the FEC disable sequence. After the destination terminal 11 receives the FEC disable sequence, the destination terminal 11 can disable the FEC decoder 11a to decode at least one FEC block. In addition, the marker symbol TG1 or TG2 can include FEC parity marker (PM) information. The link L between the source terminal 10 and the destination terminal 11 can be a DisplayPort (DP) link or any high-speed media channel link. The 8b / 10b encoders 10a and 10b / 8b decoders 11b can be any pair of encoders and decoders for implementing DC balance and limited disparity. In addition, the marker symbol TG1 or TG2 can be any predefined symbol.

[0015] Figure 3 is a flowchart of a FEC synchronization method for performing the FEC synchronization system 100. The FEC synchronization method includes steps S301 to S305. Any technical or hardware modification is within the scope of the present application.

[0016] Step S301: Establishing a link L between the source terminal 10 and the destination terminal 11;

[0017] Step S302: The source terminal 10 periodically transmits a marker symbol TG1 to the destination terminal 11;

[0018] Step S303: After the destination terminal 11 receives the marker symbol TG1, the destination terminal 11 identifies the marker symbol TG1;

[0019] Step S304: Collecting a plurality of symbols transmitted by the source terminal 10 to generate a plurality of FEC blocks FEC1_0 to FEC1_255 received by the destination terminal 11 after successfully identifying the marker symbol TG1.

[0020] Step S305: Synchronizing the plurality of FEC blocks FEC1_0 to FEC1_255 between the source terminal 10 and the destination terminal 11 according to the marker symbol TG1.

[0021] The details of steps S301 to S305 have been explained previously. Therefore, they are omitted here. In the FEC synchronization system 100, periodic marker symbols are introduced for synchronizing the FEC blocks. Since the transmission time difference between two marker symbols is equal to the time length of transmitting P FEC blocks, the marker symbols can be used to align the start time point and the end time point of each P FEC block period. Therefore, although the FEC enable sequence is not detected by the destination terminal 11, the destination terminal 11 can still recover the FEC block synchronization between the source terminal 10 and the destination terminal 11 according to the marker symbols. As a result, the decoding error or the synchronization error of the incoming FEC blocks can be reduced.

[0022] In summary, the present disclosure discloses an FEC synchronization method and an FEC synchronization system. The FEC synchronization system can use periodic marker symbols to align the start time point and the end time point of each FEC block period. Therefore, when the FEC enable sequence is not detected by the destination terminal, the synchronization of the FEC blocks can be recovered. Since the synchronization of the FEC blocks can be recovered, the decoding error or the synchronization error of the incoming FEC blocks can be reduced.

[0023] Those skilled in the art will readily observe that numerous modifications and changes can be made to the devices and methods without departing from the teachings of the present disclosure. Accordingly, the above disclosure is intended to be illustrative only and not limiting.

Claims

1. A forward error correction (FEC) synchronization method, comprising: establishing a connection between a source terminal and a destination terminal; periodically transmitting a marker symbol from the source terminal to the destination terminal; identifying the marker symbol by the destination terminal after the marker symbol is received by the destination terminal; collecting a plurality of symbols transmitted from the source terminal to generate a plurality of forward error correction (FEC) blocks received by the destination terminal after the marker symbol is successfully identified; and synchronizing the plurality of FEC blocks between the source terminal and the destination terminal according to the marker symbol; wherein the marker symbol comprises a predefined pattern.

2. The method of claim 1, further comprising: decoding the plurality of FEC blocks by the destination terminal after the plurality of FEC blocks are synchronized.

3. The method of claim 1, wherein each of the FEC blocks comprises N symbols, each symbol comprises M symbol bits, and a period of the marker symbol is equal to P FEC blocks, N, M and P are positive integers.

4. The method of claim 3, further comprising: transmitting the plurality of symbols from the source terminal to the destination terminal; and aligning the M symbol bits of each symbol by the destination terminal to synchronize the plurality of symbols received by the destination terminal.

5. The method of claim 3, further comprising: transmitting the P FEC blocks from the source terminal to the destination terminal after transmitting the marker symbol from the source terminal to the destination terminal.

6. The method of claim 1, wherein identifying the marker symbol by the destination terminal after the marker symbol is received by the destination terminal comprises: obtaining the predefined pattern by the destination terminal; and comparing the predefined pattern with the marker symbol received by the destination terminal to identify the marker symbol.

7. The method of claim 1, further comprising: encoding a data stream by the source terminal using an 8b / 10b encoder to generate the plurality of symbols; wherein the connection corresponds to a high-speed media channel between the source terminal and the destination terminal.

8. The method of claim 1, further comprising: transmitting an FEC disable sequence from the source terminal to the destination terminal; terminating an FEC encoder of the source terminal; and disabling an FEC decoder of the destination terminal to decode the at least one FEC block by the destination terminal after the FEC disable sequence is received by the destination terminal.

9. The method of claim 1, further comprising: transmitting an FEC enable sequence from the source terminal to the destination terminal after an FEC encoder of the source terminal is enabled; and resuming synchronization of the plurality of FEC blocks between the source terminal and the destination terminal according to the marker symbol when the FEC enable sequence is not detected by the destination terminal.

10. The method of claim 1, wherein the marker symbol comprises a FEC parity marker (PM) information, and the connection is a display port (DP) connection between the source terminal and the destination terminal. ​ ​ ​ ​ ​ 11. A forward error correction (FEC) synchronization system, comprising: a source terminal, comprising: an 8b / 10b encoder; and an FEC encoder coupled to the 8b / 10b encoder; and a destination terminal coupled to the source terminal, the destination terminal comprising: a 10b / 8b decoder; and an FEC decoder coupled to the 10b / 8b decoder; wherein, upon establishment of a coupling between the source terminal and the destination terminal, the source terminal periodically transmits a marker symbol to the destination terminal, the destination terminal identifies the marker symbol upon receipt of the marker symbol by the destination terminal, the destination terminal collects a plurality of symbols transmitted from the source terminal upon successful identification of the marker symbol to generate a plurality of FEC blocks received by the destination terminal, the plurality of FEC blocks are synchronized between the source terminal and the destination terminal by the destination terminal based on the marker symbol, and the marker symbol comprises a predefined pattern.

12. The system of claim 11, wherein the FEC decoder decodes the plurality of FEC blocks by the destination terminal upon synchronization of the plurality of FEC blocks.

13. The system of claim 11, wherein each FEC block comprises N symbols, each symbol comprises M symbol bits, and a period of a marker symbol is equal to P FEC blocks, N, M, and P are positive integers.

14. The system of claim 13, wherein the source terminal transmits a plurality of symbols to the destination terminal, and the destination terminal aligns the M symbol bits of each symbol to synchronize the plurality of symbols received by the destination terminal.

15. The system of claim 13, wherein the source terminal transmits P FEC blocks to the destination terminal after transmitting a marker symbol from the source terminal to the destination terminal.

16. The system of claim 11, wherein the destination terminal obtains a predetermined pattern, and the destination terminal compares the predetermined pattern to a marker symbol received by the destination terminal to identify the marker symbol.

17. The system of claim 11, wherein the source terminal encodes a data stream using the 8b / 10b encoder to generate a plurality of symbols, the destination terminal decodes the plurality of symbols using the 10b / 8b decoder to generate a decoded data stream, and the coupling between the source terminal and the destination terminal corresponds to a high speed media channel.

18. The system of claim 11, wherein the source terminal transmits an FEC disable sequence to the destination terminal, the source terminal disables the FEC encoder, and the destination terminal disables the FEC decoder to decode at least one FEC block upon receipt of the FEC disable sequence.

19. The system of claim 11, wherein the source terminal transmits an FEC enable sequence to the destination terminal upon enabling the FEC encoder, and the destination terminal resumes synchronization of a plurality of FEC blocks between the source terminal and the destination terminal based on the marker symbol upon the destination terminal failing to detect the FEC enable sequence.

20. The system of claim 11, wherein the marker symbol contains FEC parity marker (PM) information, and the connection between the source terminal and the sink terminal is a DisplayPort (DP) connection.

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