Chip resource dynamic configuration method

Abstract

The invention relates to the technical field of chip resource management and scheduling, in particular to a chip resource dynamic configuration method, which comprises the following steps of: S1, detecting and acquiring a calculation event, a storage event and a communication event of a chip in a task processing process by an event sensor; s2, performing analysis and event demand prediction on the calculation event, the storage event and the communication event in the step 1 by an event analysis unit, and generating a resource configuration instruction; s3, according to the resource configuration instruction in the step S2, the chip resources are distributed in real time; and S4, after the chip resources are allocated in real time, the dynamic allocation of the chip resources is cancelled. The technical problems that in the prior art, due to the fact that the unit for allocating and adjusting the chip resources is large, the calculated amount and the data flow are sharply increased or decreased, and the chip resources cannot be configured more flexibly, efficiently and rapidly when resource requirements conflict occurs are solved.

Description

Technical Field

[0001] This invention relates to the field of chip resource management and scheduling technology, and more specifically, to a method for dynamic configuration of chip resources. Background Technology

[0002] In the field of modern electronic systems and chip technology, the rational allocation of chip resources is crucial. As the core driving force of various intelligent devices and computing systems, chips contain a variety of key resources, such as computing units, storage resources, and communication bandwidth. Effective resource allocation can maximize the performance potential of chips, ensuring they can provide services in an optimal state when running various complex tasks and applications, thereby improving the overall system's operating efficiency and response speed. Rational resource allocation helps balance the workload among different modules of the chip, avoiding some resources being excessively idle while others are overloaded, thus extending the chip's lifespan and reducing energy consumption. In the context of rapid technological development and explosive growth in data processing demands, optimizing chip resource allocation has profound significance.

[0003] In existing technologies, the commonly used chip resource allocation method is static configuration. During the chip design phase, the allocation of various resources is fixed. Based on predefined task models and expected operating scenarios, computing, storage, and other resources are allocated to different functional modules. This method largely maintains the resource allocation after chip manufacturing is complete. In addition, there is a dynamic configuration method based on simple rules. This method typically allocates chip resources according to task priority. When a high-priority task arrives, a certain amount of resources is allocated to it according to predetermined rules. This type of method often relies on a series of pre-defined logical rules to drive resource allocation and adjustment.

[0004] However, existing resource allocation methods have many flaws and limitations. Firstly, static allocation methods, once determined, are difficult to change. When faced with complex situations where task types and load intensities frequently change in actual operation, resource allocation is prone to severe disconnect from actual needs. This leads to some modules being under resource strain and unable to function properly, while others have significant idle resources, resulting in waste and hindering the full realization of the chip's overall performance advantages. Dynamic allocation methods based on simple rules, while offering some flexibility, often have relatively fixed and one-sided rules, making it difficult to cope with diverse and complex real-world application scenarios. When edge AI devices (smart cameras, AR glasses, etc.) run multimodal AI tasks (such as object detection, speech recognition, sensor fusion, etc.) in real time, their loads are characterized by sudden changes, heterogeneity, and conflicting resource demands. Existing chip resource allocation methods adjust resource allocation in large units, failing to provide more flexible, efficient, and rapid resource allocation when single tasks suddenly increase or decrease, or task combinations change, leading to sudden surges or drops in computational load and data flow, and conflicting resource demands. Summary of the Invention

[0005] The purpose of this application is to provide a method for dynamic configuration of chip resources, which solves the technical problems in the prior art, such as the large unit of chip resource allocation adjustment leading to a surge or drop in computing power and data traffic, and the inability to configure chip resources more flexibly, efficiently and quickly when resource demand conflicts exist.

[0006] To solve the above-mentioned technical problems, the solution adopted in this application is as follows:

[0007] A method for dynamic allocation of chip resources, the implementation process of which is as follows:

[0008] Step S1: The event sensor detects and acquires computational events, storage events, and communication events of the chip during task processing;

[0009] The computation events include three subcategories: multiply-accumulate instruction burst signals, instantaneous saturation / idle signals of NPU / DSP computing unit utilization, and specific operator activation signals; the storage events include three subcategories: cache miss storm signals, DRAM bank conflict signals, and specific data stream access pattern recognition signals; the communication events include two subcategories: NoC link congestion / idle signals and critical path delay exceeding threshold signals; the computation events, storage events, and communication events are referred to as the raw event stream.

[0010] Step S2: The event parsing unit parses the computation events, storage events, and communication events in Step 1 and predicts event requirements, and generates resource configuration instructions;

[0011] The event parsing unit consists of a state machine and a lookup table, and the event parsing unit is deployed in the NPU computing cluster, memory controller, and Noc node in the chip.

[0012] The event parsing unit identifies the resource scheduling demand pattern of the original event and predicts the resource demand of the original event based on the resource scheduling demand pattern; the resource scheduling demand pattern includes convolution calculation burst mode, matrix multiplication bottleneck mode, NoC congestion delay mode, DMA data flow optimization mode, high priority preemption mode, and task chain triggering mode.

[0013] Step S3: Allocate chip resources in real time according to the resource configuration instructions in step S2;

[0014] In this step, the chip's computing resources, storage resources, and communication resources are broken down into independent computing units, independent storage units, and independent communication units, and the chip resources are allocated and adjusted according to the resource configuration instructions in step S2.

[0015] Step S4: After real-time allocation of chip resources, cancel the dynamic allocation of chip resources.

[0016] In this step, the event parsing unit continuously monitors the real-time status of the original event stream. When the trigger condition for canceling dynamic allocation is detected, a cancel dynamic allocation instruction is generated and executed to release the chip resources allocated in step S3.

[0017] Preferably, the event parsing unit parses the original event stream and predicts event demand, and its implementation process is as follows:

[0018] Step S2.1: The WLU unit receives the raw event and performs spatiotemporal alignment and filtering on the raw event;

[0019] The WLU unit receives the raw event stream from step S1. The raw event stream is in 64-bit format and includes event type, intensity, timestamp, and spatial coordinates. After receiving the raw event streams from different parts of the chip, the WLU unit eliminates the chip's global clock offset based on the timestamp, achieving a synchronization accuracy of ±200ps. It also filters the raw event streams based on the spatial coordinates, only receiving raw events that match the location of the chip hardware resources directly managed by the current WLU unit. These raw events are called local events, and the WLU unit then outputs a local event stream with a unified time base.

[0020] Step S2.2: The event window caches local events from the most recent period;

[0021] A local event window is used to cache events within a recent period. The depth of the event window is determined by the maximum event rate and the window time. The event window is a hardware queue with storage capabilities.

[0022] Step S2.3: The WLU unit matches the cached local events with predefined pattern rules to identify the specific resource scheduling requirement pattern of the local events;

[0023] Step S2.4: Based on the resource scheduling requirement pattern of the local event in step S2.3, predict the resources required for the execution of the local event;

[0024] Step S2.5: Generate resource configuration instructions based on the resource requirements predicted in step S2.4;

[0025] Step S2.6: Distribute the resource configuration instructions to the local resource controller.

[0026] Preferably, the chip resources are allocated in real time according to the resource configuration instructions in step S2, and the implementation process is as follows:

[0027] Step S3.1: Decompose the chip's computing resources, storage resources, and communication resources;

[0028] Decompose computing resources into independent computing units; decompose storage resources into independent storage units; decompose communication resources into independent communication units;

[0029] Step S3.2: Dynamic allocation of chip resources;

[0030] Based on real-time event resource requirements and system status, the configuration of hardware resources is adjusted in real time by executing resource configuration commands.

[0031] Preferably, the dynamic allocation of chip resources is cancelled, and the implementation process is as follows:

[0032] Step S4.1: Cancel dynamic allocation trigger condition monitoring;

[0033] The conditions for revoking dynamic allocation include the end of a sudden instruction stream, a decrease in cache miss rate, completion of high-priority tasks, and relief of communication path congestion;

[0034] Step S4.2: Generate a command to cancel dynamic allocation;

[0035] Revoking dynamic allocation instructions includes revoking computing resource configuration instructions, revoking storage resource configuration instructions, and revoking communication resource configuration instructions.

[0036] Step S4.3: Execute the operation to cancel the dynamic allocation instruction;

[0037] After receiving the dynamic allocation cancellation instruction in step S4.2, the local resource controller executes the corresponding dynamic allocation cancellation operation.

[0038] Step S4.4: Chip resource status feedback.

[0039] After executing the command to revoke dynamic allocation, the local resource controller feeds back the current status of chip resources to the WLU unit in real time.

[0040] Preferably, chip resources are abstracted, and the implementation process is as follows:

[0041] Step S3.1.1: Decompose the computing resources in the chip into independent computing units with fine granularity;

[0042] Computing units can be used independently for startup, shutdown, and resource allocation. Through fine-grained decomposition, computing resources can be dynamically combined at runtime.

[0043] Step S3.1.2: Decompose the storage resources in the chip into independent storage units in a fine-grained manner;

[0044] The storage unit can independently perform storage tasks. Each storage unit is equipped with an independent priority control and bandwidth management module. The storage resources in the chip can be flexibly allocated in terms of priority and bandwidth according to different task requirements.

[0045] Step S3.1.3: Decompose the communication resources in the chip into independent communication units in a fine-grained manner;

[0046] Independent communication units can perform communication tasks independently. Each communication unit is provided with a dynamically configurable routing and bandwidth control module. The communication resources in the chip can dynamically adjust their connection weights and bandwidth allocation according to the communication requirements of different tasks.

[0047] Preferably, chip resources are dynamically allocated, and the implementation process is as follows:

[0048] Step S3.2.1: The local resource controller receives the resource configuration instruction;

[0049] The local resource controller receives the resource configuration instruction generated by the WLU unit in step S2, and performs chip resource adjustment and allocation actions according to the specific resource configuration instruction.

[0050] Step S3.2.2: Chip resource allocation and adjustment;

[0051] When the computing resources required for a computing event increase, a computing resource increase instruction is executed, and the local resource controller allocates computing units to the current computing event; when the computing resources required for a computing event decrease or become excessive, a computing resource decrease instruction is executed, and the local resource controller removes the computing units from the current task and allocates them to other computing events or sets them to an idle state.

[0052] When the storage resources required by a storage event increase, a storage bandwidth increase instruction is executed, and the local resource controller allocates storage units to the current storage event; when the storage resources required by a storage event decrease or become excessive, a storage bandwidth decrease instruction is executed, and the local resource controller allocates the storage units occupied by the current storage event to other storage events or releases them.

[0053] When the communication resources required for a communication event increase, an instruction to increase the bandwidth of the interconnect communication unit is executed, and the local resource controller increases the bandwidth of the interconnect communication unit for the current stored event; when the communication resources required for a communication event decrease, an instruction to decrease the bandwidth of the interconnect communication unit is executed, and the local resource controller decreases the bandwidth of the interconnect communication unit for the current communication event.

[0054] Preferably, the WLU unit performs pattern recognition on the cached local events, and its specific implementation process is as follows:

[0055] The WLU unit matches the event sequence in the event window with the predefined pattern rules; the parameters compared during the pattern matching process include event type, intensity, temporal relationship, and spatial relationship.

[0056] The predefined pattern rules include convolution calculation burst pattern rules, matrix multiplication bottleneck pattern rules, NoC congestion delay pattern rules, DMA data flow optimization pattern rules, high priority preemption pattern rules, and task chain triggering pattern rules.

[0057] The preferred method is to predict and output resource requirements, and its specific implementation process is as follows:

[0058] After a local event and pattern match is successful, the resource requirements of the local event are predicted and output according to the predefined resource prediction rules.

[0059] The predefined resource prediction rules include convolution calculation burst prediction rules, matrix multiplication bottleneck prediction rules, NoC congestion delay prediction rules, DMA data flow optimization prediction rules, high-priority preemption prediction rules, and task chain triggering prediction rules.

[0060] Preferably, the resource configuration instructions include computing resource configuration instructions, storage resource configuration instructions, and communication resource configuration instructions;

[0061] The computing resource configuration instructions are used to perform computing resource adjustment actions on the chip; the computing resource configuration instructions include computing resource increase instructions and computing resource decrease instructions;

[0062] The storage resource configuration instructions are used to perform storage resource adjustment actions on the chip; the storage resource configuration instructions include storage bandwidth increase instructions, storage bandwidth decrease instructions, storage cell access priority increase instructions, and storage cell access priority decrease instructions;

[0063] The communication resource configuration instructions are used to perform communication resource adjustment actions of the chip; the communication resource configuration instructions include instructions to increase the bandwidth of interconnect communication units, instructions to decrease the bandwidth of interconnect communication units, instructions to increase the priority of interconnect communication units, instructions to decrease the priority of interconnect communication units, and instructions to establish a high-priority data flow channel.

[0064] Preferably, the revocation of dynamic allocation instructions includes revocation of computing resource configuration instructions, revocation of storage resource configuration instructions, and revocation of communication resource configuration instructions;

[0065] The undo computing resource configuration instruction is used to execute the undo computing resource adjustment action of the chip; the undo computing resource configuration instruction includes an undo computing resource increase instruction and an undo computing resource decrease instruction;

[0066] The command to cancel storage resource configuration is used to cancel storage resource adjustment operations; the command to cancel storage resource configuration includes commands to cancel storage bandwidth increase, storage bandwidth decrease, storage unit access priority increase, and storage unit access priority decrease.

[0067] The command to cancel communication resource configuration is used to cancel communication resource adjustment operations; the command to cancel communication resource configuration includes canceling the command to increase the bandwidth of interconnected communication units, canceling the command to decrease the bandwidth of interconnected communication units, canceling the command to increase the priority of interconnected communication units, canceling the command to decrease the priority of interconnected communication units, and canceling the command to establish a high-priority data flow channel.

[0068] The technical solution of this application has at least the following advantages and beneficial effects:

[0069] 1. This invention addresses the characteristics of real-time multimodal AI tasks (such as object detection and speech recognition) running on edge AI devices, which exhibit bursty, heterogeneous, and conflicting resource demands. It discloses a dynamic chip resource allocation method. This invention captures event streams with physical location and timing information from the chip hardware layer, forming a "raw event stream" data stream reflecting the system's operating status. By directly utilizing the most recent and lowest-level hardware signals, it reduces latency in chip resource allocation and achieves finer-grained perception. This invention finely decomposes the chip's computing, storage, and communication resources into independent computing, storage, and communication units. These independent units can be combined to form larger data processing units when local event resource demands increase, and release excess data processing units when local event resource demands decrease or become excessive, allocating them to other events with greater resource demands. Therefore, when the computing and data processing load of edge AI devices exhibits sudden surges or drops, the chip can quickly and dynamically allocate its resources to solve the problems of bursty and heterogeneous loads.

[0070] 2. The chip dynamic configuration operation in this invention is designed to be short-time (microsecond to millisecond level). After the task load changes, the chip resources are quickly released or reallocated to avoid resource waste, reduce system power consumption, and maximize the utilization of chip resources. Attached Figure Description

[0071] Figure 1 This is a flowchart illustrating the overall process of the chip resource dynamic configuration method of the present invention.

[0072] Figure 2 This is a flowchart illustrating how the present invention parses the original event stream, predicts event requirements, and generates resource configuration instructions.

[0073] Figure 3 This is a flowchart of the process for canceling the dynamic allocation of chip resources according to the present invention. Detailed Implementation

[0074] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be briefly introduced below in conjunction with the accompanying drawings and descriptions of the embodiments or the prior art. Obviously, the following description of the structure of the accompanying drawings is only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the description of these embodiments is for the purpose of helping to understand the present invention, but does not constitute a limitation of the present invention.

[0075] It should be understood that although the terms first, second, etc., may be used herein to describe various modules, these modules should not be limited by these terms. These terms are only used to distinguish one module from another. For example, a first module may be referred to as a second module, and similarly, a second module may be referred to as a first module, without departing from the scope of the exemplary embodiments of the invention.

[0076] It should be understood that the term "and / or" that may appear in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, B exists alone, and A and B exist simultaneously. The term " / and" that may appear in this document describes another relationship between related objects, indicating that two relationships can exist. For example, A / and B can mean: A exists alone, and A and B exist alone. In addition, the character " / " that may appear in this document generally indicates that the related objects before and after it are in an "or" relationship.

[0077] Example:

[0078] Please refer to Figures 1-3 This invention provides a method for dynamic configuration of chip resources, which is applied to chips with the following resource architectures:

[0079] The underlying chip hardware includes the instruction pipeline, cache controller, NoC router, and task queue manager.

[0080] The instruction pipeline breaks down the instruction execution process into multiple consecutive steps; the cache controller manages data exchange between the cache and main memory; the NoC router is responsible for data transmission between the processor core and other modules in the chip system; and the task queue manager manages task scheduling and execution order.

[0081] The event sensor in this invention is a hardware logic module used to be deployed at the bottom layer of chip hardware to monitor and capture the occurrence of specific events in real time, and to pass the relevant information of these events to the subsequent analysis and decision-making modules, thereby realizing dynamic resource allocation.

[0082] In the instruction pipeline, event sensors are integrated at the arithmetic unit interface; in the cache controller, event sensors are integrated in the address mapping circuit and data exchange path; in the NoC router, event sensors are integrated in the NoC router's data buffer and routing decision circuit; in the task queue manager, event sensors are integrated in the scheduling control circuit and queue status detection point, collecting task scheduling-related events through read-only connections and then transmitting them to the WLU unit.

[0083] The internal structure of the chip hardware's underlying instruction pipeline, cache controller, NoC router, and task queue manager is existing technology. Therefore, the detailed internal circuit structure and principles of each resource module of the chip will not be described in detail in this invention.

[0084] Its implementation includes the following steps:

[0085] Step S1: The event sensor detects and acquires computational events, storage events, and communication events of the chip during task processing.

[0086] Specifically, computation events include three subcategories: multiply-accumulate instruction burst signals, instantaneous saturation / idle signals of NPU / DSP computing unit utilization, and specific operator activation signals; storage events include three subcategories: cache miss storm signals, DRAM bank conflict signals, and specific data stream access pattern recognition signals; and communication events include two subcategories: NoC link congestion / idle signals and critical path delay exceeding threshold signals. Computation events, storage events, and communication events are collectively referred to as the raw event stream.

[0087] Specifically, the raw event stream is acquired by embedding event sensors at the chip hardware level. The event sensors monitor the chip hardware level and capture computing events, storage events, and communication events when they occur.

[0088] Specifically, event sensors are deployed in the chip's instruction pipeline to monitor computational events such as burst signals of multiply-accumulate instructions, instantaneous saturation / idle signals of NPU / DSP computing unit utilization, and activation signals of specific operators; event sensors are deployed in the cache controller to monitor storage events such as cache miss storm signals, DRAM bank conflict signals, and identification signals of specific data stream access patterns; and event sensors are deployed in the NoC router to monitor communication events such as NoC link congestion / idle signals and critical path delay exceeding threshold signals.

[0089] It should be noted that the event sensor is a hardware logic module used to monitor and capture the occurrence of specific events in real time at the hardware level, and to pass the relevant information of these events to the subsequent analysis and decision-making modules. This is existing technology. The operation of the event sensor does not affect the normal function of the hardware unit. The main focus of this invention is a method for dynamically configuring the chip's computing, storage, and communication resources by using an event sensor to monitor and capture chip computational, storage, and communication events. The detailed working principle and hardware design method of the chip's underlying hardware will not be elaborated here, as those skilled in the art will understand.

[0090] Specifically, timestamps and spatial location information are added to each event to form a raw event stream with spatiotemporal characteristics.

[0091] Specifically, the detection source for computation events is the instruction pipeline, and the spatiotemporal encoding method is (x, y, t, intensity); the detection source for storage events is the cache controller, and the spatiotemporal encoding method is (bank_id, t); the detection source for communication events is the NoC router, and the spatiotemporal encoding method is (route coordinates, t).

[0092] Step S2: The event parsing unit parses the computation events, storage events, and communication events in Step 1 and predicts event requirements, and generates resource configuration instructions.

[0093] In this step, event parsing units are deployed in the NPU computing cluster, memory controller, and Noc nodes within the chip. Deploying event parsing units allows for rapid acquisition and parsing of the raw event stream from step S1, reducing communication latency and ensuring real-time parsing and decision-making. The event parsing unit is hereinafter referred to as the WLU unit.

[0094] It should be noted that the WLU unit consists of a state machine and a lookup table, and does not rely on complex processors or software algorithms, thereby ensuring low power consumption and high efficiency. State machines and lookup tables are existing technologies, and their design and working principles will not be elaborated here. In this invention, they are used for event flow parsing in chip resource allocation methods, which will be understood by those skilled in the art.

[0095] Specifically, in the NPU computing cluster, the WLU unit is deployed in the routing channel between computing arrays, connecting the local MAC unit and the adjacent L2 Bank; for the memory controller, the WLU unit is deployed next to the Bank arbitrator, connecting the local DRAM and the adjacent NoC node; for the NoC router, the WLU unit is deployed in the crossbar switch control module, connecting the local VC queue and the adjacent computing cluster.

[0096] Specifically, the WLU unit is used to identify the types of raw events and the corresponding resource scheduling demand patterns from the input raw event stream, and to generate resource configuration instructions based on these patterns.

[0097] It should be noted that the resource scheduling demand patterns are proposed based on the analysis of the types of original event streams and resource requirements, including convolution computation burst mode, matrix multiplication bottleneck mode, NoC congestion delay mode, DMA data stream optimization mode, high priority preemption mode, and task chain triggering mode.

[0098] Specifically, in step S2, the event parsing unit parses the computational events, stored events, and communication events from step 1 and performs event demand prediction according to the following steps:

[0099] Step S2.1: The WLU unit receives the raw event and performs spatiotemporal alignment and filtering on the raw event.

[0100] Specifically, the WLU unit receives the raw event stream from step S1. The raw event stream is in 64-bit format and includes event type, intensity, timestamp, and spatial coordinates. After receiving the raw event streams from different parts of the chip, the WLU unit eliminates the chip's global clock skew based on the timestamp, achieving a synchronization accuracy of ±200ps. It also filters the raw event streams based on the spatial coordinates, only receiving raw events that match the location of chip hardware resources directly managed by the current WLU unit. These raw events are called local events, and the WLU unit then outputs a local event stream with a unified time base.

[0101] More specifically, WLU units deployed in different parts of the chip filter relevant local events from the raw event stream based on their location and the resources they are responsible for. For example, a WLU unit deployed in an NPU computing cluster filters events related to the NPU computing cluster; a WLU unit deployed in a memory controller filters events related to the memory controller; and a WLU unit deployed in a NoC router filters local events related to the memory controller.

[0102] More specifically, if events in different domains of the chip use different clock domains, after the WLU unit filters out the times related to local resources, the WLU unit aligns these events using different clock domains according to the timestamps of the events, ensuring that the local event stream has a unified time base, which facilitates subsequent event parsing and demand prediction.

[0103] Step S2.2: The event window caches local events from the most recent period.

[0104] Specifically, an event window is used to cache local events within a recent period. The depth of the event window is determined by the maximum event rate and the window duration. The event window is a hardware queue with storage capabilities.

[0105] Specifically, the "recent period" is a sliding time window, the length of which is set according to the chip's operating characteristics and actual needs. As time goes on, the time window continuously moves forward, new events enter the time window, and the oldest events gradually move out of the window. More specifically, when the time window size is set to 10 milliseconds, at any given moment, the time window contains events that occurred within the past 10 milliseconds.

[0106] Step S2.3: The WLU unit matches the cached local events with predefined pattern rules to identify the specific resource scheduling requirement pattern of the local events.

[0107] Specifically, the WLU unit matches the event sequence in the event window against predefined pattern rules. The parameters compared during pattern matching include event type, intensity, temporal relationship, and spatial relationship.

[0108] Specifically, the predefined pattern rules include convolution computation burst pattern rules, matrix multiplication bottleneck pattern rules, NoC congestion delay pattern rules, DMA data flow optimization pattern rules, high priority preemption pattern rules, and task chain triggering pattern rules.

[0109] Step S2.4: Based on the resource scheduling requirement pattern of the local event in step S2.3, predict the resources required for the execution of the local event.

[0110] Specifically, after a local event and pattern match are successful, the resource requirements of that local event are predicted and output according to predefined resource prediction rules.

[0111] Specifically, the predefined resource prediction rules include convolution computation burst prediction rules, matrix multiplication bottleneck prediction rules, NoC congestion delay prediction rules, DMA data flow optimization prediction rules, high-priority preemption prediction rules, and task chain triggering prediction rules.

[0112] More specifically, when a local event matches a convolutional computation burst pattern, the convolutional computation burst prediction rule predicts that the number of MAC units in the NPU computation array needs to be increased, and at the same time, it predicts that the access priority of the relevant cache bank needs to be increased.

[0113] It should be noted that when the current task is to compute the convolutional layer of a convolutional neural network, this task requires a large number of matrix multiplications. The required computational cost is estimated based on the size of the input feature map, the size and number of convolutional kernels. Specifically, if the input feature map size is 28*28, the convolutional kernel size is 3*3, and there are 16 kernels, each MAC unit performs one multiplication-addition operation per cycle, and the task needs to be completed within 100 cycles, then 1204.8 MAC units are required. After rounding up, it is predicted that an additional 1205 MAC units are needed.

[0114] It should be noted that the resource prediction rules and prediction process in this invention are based on the existing XGBoost machine learning model. The XGBoost machine learning model integrates multiple learners, has high accuracy and stability, can process large-scale data, and can explore the relationship between specific task features and resource requirements. The specific data input and model training process are existing technologies and will not be described here.

[0115] More specifically, when a local event matches a matrix multiplication bottleneck pattern, the matrix multiplication bottleneck prediction rule predicts that the computing resources allocated to the task need to be reduced, and the bandwidth of the corresponding cache bank for the task also needs to be reduced.

[0116] More specifically, when a local event matches a NoC congestion delay pattern, the NoC congestion delay prediction rule predicts that additional NoC link bandwidth needs to be allocated for high-priority data streams, and predicts that the weights of cross-connects on that communication path need to be adjusted.

[0117] More specifically, when a local event matches the DMA data stream optimization mode, the bandwidth allocation of the DMA channel needs to be adjusted based on the DMA data stream optimization prediction rules. For continuous block access data streams, the bandwidth of the corresponding DMA channel is increased.

[0118] More specifically, when a local event matches a high-priority preemption pattern, the system predicts, based on high-priority preemption prediction rules, that computing resources need to be preempted quickly and that the access priority of storage resources related to the task needs to be increased.

[0119] More specifically, when a local event matches a task chain triggering pattern, the prediction rules based on the task chain triggering predict that computing resources need to be reserved for subsequent tasks, and the prediction also predicts that storage resource allocation needs to be adjusted.

[0120] Step S2.5: Generate resource configuration instructions based on the resource requirements predicted in step S2.4.

[0121] It should be noted that the specific resource configuration instructions will be described in detail in step S3, and will not be repeated here.

[0122] Step S2.6: Distribute the resource configuration instructions to the local resource controller.

[0123] Specifically, the resource configuration command in step S2.5 is sent to the local resource controller.

[0124] Step S3: Allocate chip resources in real time according to the resource configuration instructions in step S2.

[0125] In this invention, step S3 is implemented according to the following steps:

[0126] Step S3.1: Decompose the chip's computing resources, storage resources, and communication resources.

[0127] Specifically, the resource decomposition process in this invention breaks down chip hardware resources into finer-grained, more flexible, and configurable units. This chip resource decomposition process allows the chip to reconfigure and combine resources more flexibly, thereby better adapting to sudden task demands.

[0128] Step S3.2: Dynamic allocation of chip resources.

[0129] Specifically, dynamic chip resource allocation is the process of instantly adjusting hardware resource configurations by executing resource configuration commands based on real-time event task requirements and system status. Dynamic chip resource configuration is a dynamic, fine-grained resource management mechanism that enables rapid response to changes in task load by dynamically allocating chip resources, ensuring efficient resource utilization and smooth task execution.

[0130] In this invention, the decomposition of the chip's computing resources, storage resources, and communication resources in step S3.1 is implemented according to the following steps:

[0131] Step S3.1.1: Decompose the computing resources in the chip into independent computing units in a fine-grained manner.

[0132] Specifically, the computing units decomposed in step S3.1.1 can be used independently for startup, shutdown and resource allocation. Through fine-grained decomposition, computing resources can be dynamically combined at runtime.

[0133] More specifically, during the hardware design phase, the computing resources in the chip, including the NPU computing array, are designed as a combination of multiple independent MAC units. Each independent MAC unit has its own independent control logic and data path, and can independently execute computing tasks. Moreover, each MAC unit can be combined with another MAC unit to form a computing unit with greater computing power, thereby enabling flexible allocation of computing resources.

[0134] More specifically, when a task requires more computing power, multiple idle MAC units can be temporarily allocated to the computing array of that task. After the task is completed, these MAC units are released or reassigned to other tasks.

[0135] More specifically, the computing resources in the chip include each CPU core, NPU computing array, DSP processing module, etc.

[0136] Step S3.1.2: Decompose the storage resources in the chip into independent storage units in a fine-grained manner.

[0137] Specifically, the storage units disassembled in step S3.1.2 can independently perform storage tasks. Each storage unit is configured with an independent priority control and bandwidth management module. Thus, the storage resources in the chip can be flexibly allocated priority and bandwidth according to different task requirements.

[0138] More specifically, when a task frequently experiences cache misses, the priority of the cache bank corresponding to that task can be temporarily increased, or a portion of the storage area can be reallocated to other tasks.

[0139] More specifically, the storage resources in the chip include SRAM, DRAM controller channels, on-chip network buffers, etc.

[0140] Step S3.1.3: Decompose the communication resources in the chip into independent communication units in a fine-grained manner.

[0141] Specifically, the independent communication units separated in step S3.1.3 can independently perform communication tasks. Each communication unit is provided with a dynamically configurable routing and bandwidth control module. As a result, the communication resources in the chip can dynamically adjust their connection weights and bandwidth allocation according to the communication requirements of different tasks.

[0142] More specifically, when a task's communication path becomes congested, the bandwidth of that path can be temporarily adjusted, or the connection weights between communication units can be adjusted to establish a direct channel for high-priority data streams.

[0143] More specifically, the communication resources in the chip include the NoC routing path, crossbar switch connection, and DMA channel.

[0144] In this invention, step S3.2, dynamic allocation of chip resources, is implemented according to the following steps:

[0145] Step S3.2.1: The local resource controller receives the resource configuration instruction;

[0146] Specifically, the local resource controller receives the resource configuration instructions generated by the WLU unit in step S2. The local resource controller then performs chip resource adjustment and allocation actions based on these instructions. The local resource controller includes an NPU cluster controller, a Cache Bank controller, and a NoC router.

[0147] Specifically, resource configuration instructions include computing resource configuration instructions, storage resource configuration instructions, and communication resource configuration instructions;

[0148] More specifically, computing resource configuration instructions are used to execute computing resource adjustments on the chip. Upon receiving a computing resource configuration instruction, the local resource controller increases or decreases the computing units allocated to a specific task. Computing resource configuration instructions include computing resource increase instructions and computing resource decrease instructions.

[0149] More specifically, storage resource configuration instructions are used to execute storage resource adjustments on the chip. Upon receiving a storage resource configuration instruction, the local resource controller increases or decreases the storage bandwidth allocated to a specific task and raises or lowers the access priority of storage units for storage events. Storage resource configuration instructions include storage bandwidth increase instructions, storage bandwidth decrease instructions, storage unit access priority increase instructions, and storage unit access priority decrease instructions.

[0150] More specifically, communication resource configuration instructions are used to execute communication resource adjustments on the chip. Upon receiving the communication resource configuration instructions, the local resource controller adjusts the bandwidth allocation and priority of interconnect communication units, and establishes direct communication channels for high-priority data streams, bypassing congested general communication paths. Communication resource configuration instructions include instructions to increase interconnect communication unit bandwidth, decrease interconnect communication unit bandwidth, increase interconnect communication unit priority, decrease interconnect communication unit priority, and establish high-priority data stream channels.

[0151] Step S3.2.2: Chip resource allocation and adjustment.

[0152] Specifically, when the computing resources required for a computing event increase, a computing resource increase instruction is executed, and the local resource controller allocates computing units to the current computing event; when the computing resources required for a computing event decrease or become excessive, a computing resource decrease instruction is executed, and the local resource controller removes the computing units from the current task and allocates them to other computing events or sets them to an idle state.

[0153] More specifically, the computing units include the MAC unit in the NPU computing array and part of the ALU resources of a CPU core; the computing events that require changes in computing resources include burst convolution and burst filtering calculations.

[0154] Specifically, when the storage resources required by a storage event increase, a storage bandwidth increase instruction is executed, and the local resource controller allocates storage units to the current storage event; when the storage resources required by a storage event decrease or become excessive, a storage bandwidth decrease instruction is executed, and the local resource controller allocates the storage units occupied by the current storage event to other storage events or releases them; when the execution priority of a storage event increases, the local resource controller executes a storage unit access priority increase instruction to increase the storage unit access priority of that event; when the execution priority of a storage event decreases, the local resource controller executes a storage unit access priority decrease instruction to decrease the storage unit access priority of that event.

[0155] More specifically, the storage units include cache units, on-chip storage units, DRAM units, and network buffer units; storage events that change the required storage resources include cache miss events, DRAM access conflict events, data stream access mode change events, high-priority task storage demand events, on-chip network congestion mitigation events, and low storage resource utilization events.

[0156] Specifically, when the communication resources required for a communication event increase, an instruction to increase the bandwidth of the interconnect communication unit is executed, and the local resource controller increases the bandwidth of the interconnect communication unit for the current stored event; when the communication resources required for a communication event decrease, an instruction to decrease the bandwidth of the interconnect communication unit is executed, and the local resource controller decreases the bandwidth of the interconnect communication unit for the current communication event; when the execution priority of a certain communication event increases, an instruction to increase the priority of the interconnect communication unit is executed, and the local resource controller increases the priority of the interconnect communication unit for the current communication event; when the execution priority of a certain communication event decreases, an instruction to decrease the priority of the interconnect communication unit is executed, and the local resource controller decreases the priority of the interconnect communication unit for the current communication event.

[0157] More specifically, communication resources include on-chip network units, direct memory access units, DMA channels, and crossbar switch connection units; communication events that cause changes in required communication resources include NoC link congestion events, critical communication path delay events, surges in communication bandwidth demand events, DMA transfer queue congestion events, changes in inter-task communication priority events, and sudden increases in sensor data streams.

[0158] Step S4: After real-time allocation of chip resources, cancel the dynamic allocation of chip resources.

[0159] In this invention, the dynamic allocation operation of chip resources is designed to be short-lived (microseconds to milliseconds) to handle sudden loads. The purpose of canceling the dynamic allocation operation is to quickly release or reallocate chip resources after changes in task load, thereby avoiding resource waste and reducing system power consumption. The specific execution steps are as follows:

[0160] Step S4.1: Cancel dynamic allocation trigger condition monitoring.

[0161] Specifically, the WLU unit continuously monitors the raw event stream from the underlying hardware, including the real-time status of computation events, storage events, and communication events.

[0162] Specifically, the conditions for revoking dynamic allocation include the end of a sudden instruction stream, a decrease in cache miss rate, completion of high-priority tasks, and relief of communication path congestion.

[0163] Step S4.2: Generate a command to cancel dynamic allocation.

[0164] Specifically, revoking dynamic allocation instructions includes revoking computing resource configuration instructions, revoking storage resource configuration instructions, and revoking communication resource configuration instructions.

[0165] More specifically, the revoke computing resource configuration instruction is used to execute the chip's revocation of computing resource adjustments. Upon receiving the revoke computing resource configuration instruction, the local resource controller revoks the operation of adding or removing computing units allocated to a specific task. The revoke computing resource configuration instruction includes revoke computing resource addition instructions and revoke computing resource reduction instructions.

[0166] More specifically, the `Cancel Storage Resource Configuration` command is used to undo storage resource adjustment operations. Upon receiving a `Cancel Storage Resource Configuration` command, the local resource controller cancels the operation of increasing or decreasing the storage bandwidth allocated to a specific task. `Cancel Storage Resource Configuration` commands include commands to cancel storage bandwidth increases, decreases, increase storage unit access priority, and decrease storage unit access priority.

[0167] More specifically, the "Cancel Communication Resource Configuration" command is used to cancel communication resource adjustment operations. Upon receiving the command, the local resource controller cancels the bandwidth allocation and priority adjustments for interconnected communication units, and also cancels the operation of establishing direct communication channels for high-priority data streams. The "Cancel Communication Resource Configuration" command includes canceling instructions to increase interconnected communication unit bandwidth, decrease interconnected communication unit bandwidth, increase interconnected communication unit priority, decrease interconnected communication unit priority, and establish high-priority data stream channels.

[0168] Step S4.3: Execute the operation to cancel the dynamic allocation instruction.

[0169] Specifically, after receiving the revoke dynamic allocation instruction in step S4.2, the local resource controller executes the corresponding revoke dynamic allocation operation.

[0170] Specifically, when the computing resources required for a computing event decrease or become excessive, the instruction to increase computing resources is canceled; when the computing resources required for a computing event increase, the instruction to decrease computing resources is canceled.

[0171] Specifically, when the storage resources required for a storage event decrease or become excessive, the instruction to increase storage bandwidth is revoked; when the storage resources required for a storage event increase, the instruction to decrease storage bandwidth is revoked; when the execution priority of a storage event decreases, the local resource controller revoks the instruction to increase the access priority of a storage unit; when the execution priority of a storage event increases, the local resource controller revoks the instruction to decrease the access priority of a storage unit.

[0172] Specifically, when the communication resources required for a communication event decrease or become excessive, the instruction to cancel increasing the bandwidth of the interconnecting communication unit is executed; when the communication resources required for a communication event increase, the instruction to cancel decreasing the bandwidth of the interconnecting communication unit is executed; when the execution priority of a certain communication event decreases, the instruction to cancel increasing the priority of the interconnecting communication unit is executed; when the execution priority of a certain communication event increases, the instruction to cancel decreasing the priority of the interconnecting communication unit is executed.

[0173] Step S4.4: Chip resource status feedback

[0174] Specifically, after executing the revoking dynamic allocation instruction, the local resource controller feeds back the current status of the chip resources to the WLU unit in real time.

[0175] Finally, it should be noted that the above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for dynamic allocation of chip resources, characterized in that, The implementation process is as follows: Step S1: The event sensor detects and acquires computational events, storage events, and communication events of the chip during task processing; The computation events include three subcategories: multiply-accumulate instruction burst signals, instantaneous saturation / idle signals of NPU / DSP computing unit utilization, and specific operator activation signals; the storage events include three subcategories: cache miss storm signals, DRAM bank conflict signals, and specific data stream access pattern recognition signals; the communication events include two subcategories: NoC link congestion / idle signals and critical path delay exceeding threshold signals; the computation events, storage events, and communication events are referred to as the raw event stream. Step S2: The event parsing unit parses the computation events, storage events, and communication events in Step 1 and predicts event requirements, and generates resource configuration instructions; The event parsing unit consists of a state machine and a lookup table, and the event parsing unit is deployed in the NPU computing cluster, memory controller, and Noc node in the chip. The event parsing unit identifies the resource scheduling demand pattern of the original event and predicts the resource demand of the original event based on the resource scheduling demand pattern; the resource scheduling demand pattern includes convolution calculation burst mode, matrix multiplication bottleneck mode, NoC congestion delay mode, DMA data flow optimization mode, high priority preemption mode, and task chain triggering mode. Step S3: Allocate chip resources in real time according to the resource configuration instructions in step S2; In this step, the chip's computing resources, storage resources, and communication resources are broken down into independent computing units, independent storage units, and independent communication units, and the chip resources are allocated and adjusted according to the resource configuration instructions in step S2. Step S4: After real-time allocation of chip resources, cancel the dynamic allocation of chip resources. In this step, the event parsing unit continuously monitors the real-time status of the original event stream. When the trigger condition for canceling dynamic allocation is detected, a cancel dynamic allocation instruction is generated and executed to release the chip resources allocated in step S3.

2. The method for dynamic allocation of chip resources according to claim 1, characterized in that, The event parsing unit parses the raw event stream and predicts event demand. Its implementation process is as follows: Step S2.1: The WLU unit receives the raw event and performs spatiotemporal alignment and filtering on the raw event; The WLU unit receives the raw event stream from step S1. The raw event stream is in 64-bit format and includes event type, intensity, timestamp, and spatial coordinates. After receiving the raw event streams from different parts of the chip, the WLU unit eliminates the chip's global clock offset based on the timestamp, achieving a synchronization accuracy of ±200ps. It also filters the raw event streams based on the spatial coordinates, only receiving raw events that match the location of the chip hardware resources directly managed by the current WLU unit. These raw events are called local events, and the WLU unit then outputs a local event stream with a unified time base. Step S2.2: The event window caches local events from the most recent period; A local event window is used to cache events within a recent period. The depth of the event window is determined by the maximum event rate and the window time. The event window is a hardware queue with storage capabilities. Step S2.3: The WLU unit matches the cached local events with predefined pattern rules to identify the specific resource scheduling requirement pattern of the local events; Step S2.4: Based on the resource scheduling requirement pattern of the local event in step S2.3, predict the resources required for the execution of the local event; Step S2.5: Generate resource configuration instructions based on the resource requirements predicted in step S2.4; Step S2.6: Distribute the resource configuration instructions to the local resource controller.

3. The method for dynamic allocation of chip resources according to claim 1, characterized in that, According to the resource configuration instructions in step S2, chip resources are allocated in real time. The implementation process is as follows: Step S3.1: Decompose the chip's computing resources, storage resources, and communication resources; Decompose computing resources into independent computing units; decompose storage resources into independent storage units; decompose communication resources into independent communication units; Step S3.2: Dynamic allocation of chip resources; Based on real-time event resource requirements and system status, the configuration of hardware resources is adjusted in real time by executing resource configuration commands.

4. The method for dynamic allocation of chip resources according to claim 1, characterized in that, The process of revoking the dynamic allocation of chip resources is as follows: Step S4.1: Cancel dynamic allocation trigger condition monitoring; The conditions for revoking dynamic allocation include the end of a sudden instruction stream, a decrease in cache miss rate, completion of high-priority tasks, and relief of communication path congestion; Step S4.2: Generate a command to cancel dynamic allocation; Revoking dynamic allocation instructions includes revoking computing resource configuration instructions, revoking storage resource configuration instructions, and revoking communication resource configuration instructions. Step S4.3: Execute the operation to cancel the dynamic allocation instruction; After receiving the dynamic allocation cancellation instruction in step S4.2, the local resource controller executes the corresponding dynamic allocation cancellation operation. Step S4.4: Chip resource status feedback. After executing the command to revoke dynamic allocation, the local resource controller feeds back the current status of chip resources to the WLU unit in real time.

5. The method for dynamic allocation of chip resources according to claim 3, characterized in that, The process of abstracting chip resources is as follows: Step S3.1.1: Decompose the computing resources in the chip into independent computing units with fine granularity; Computing units can be used independently for startup, shutdown, and resource allocation. Through fine-grained decomposition, computing resources can be dynamically combined at runtime. Step S3.1.2: Decompose the storage resources in the chip into independent storage units in a fine-grained manner; The storage unit can independently perform storage tasks. Each storage unit is equipped with an independent priority control and bandwidth management module. The storage resources in the chip can be flexibly allocated in terms of priority and bandwidth according to different task requirements. Step S3.1.3: Decompose the communication resources in the chip into independent communication units in a fine-grained manner; Independent communication units can perform communication tasks independently. Each communication unit is provided with a dynamically configurable routing and bandwidth control module. The communication resources in the chip can dynamically adjust their connection weights and bandwidth allocation according to the communication requirements of different tasks.

6. The method for dynamic allocation of chip resources according to claim 3, characterized in that, The dynamic allocation of chip resources is implemented as follows: Step S3.2.1: The local resource controller receives the resource configuration instruction; The local resource controller receives the resource configuration instruction generated by the WLU unit in step S2, and performs chip resource adjustment and allocation actions according to the specific resource configuration instruction. Step S3.2.2: Chip resource allocation and adjustment; When the computing resources required for a computing event increase, a computing resource increase instruction is executed, and the local resource controller allocates computing units to the current computing event; when the computing resources required for a computing event decrease or become excessive, a computing resource decrease instruction is executed, and the local resource controller removes the computing units from the current task and allocates them to other computing events or sets them to an idle state. When the storage resources required by a storage event increase, a storage bandwidth increase instruction is executed, and the local resource controller allocates storage units to the current storage event; when the storage resources required by a storage event decrease or become excessive, a storage bandwidth decrease instruction is executed, and the local resource controller allocates the storage units occupied by the current storage event to other storage events or releases them. When the communication resources required for a communication event increase, an instruction to increase the bandwidth of the interconnect communication unit is executed, and the local resource controller increases the bandwidth of the interconnect communication unit for the current stored event; when the communication resources required for a communication event decrease, an instruction to decrease the bandwidth of the interconnect communication unit is executed, and the local resource controller decreases the bandwidth of the interconnect communication unit for the current communication event.

7. The method for dynamic allocation of chip resources according to claim 2, characterized in that, The WLU unit performs pattern recognition on cached local events, and its specific implementation process is as follows: The WLU unit matches the event sequence in the event window with the predefined pattern rules; the parameters compared during the pattern matching process include event type, intensity, temporal relationship, and spatial relationship. The predefined pattern rules include convolution calculation burst pattern rules, matrix multiplication bottleneck pattern rules, NoC congestion delay pattern rules, DMA data flow optimization pattern rules, high priority preemption pattern rules, and task chain triggering pattern rules.

8. The method for dynamic allocation of chip resources according to claim 2, characterized in that, The specific implementation process of predicting and outputting resource requirements is as follows: After a local event and pattern match is successful, the resource requirements of the local event are predicted and output according to the predefined resource prediction rules. The predefined resource prediction rules include convolution calculation burst prediction rules, matrix multiplication bottleneck prediction rules, NoC congestion delay prediction rules, DMA data flow optimization prediction rules, high-priority preemption prediction rules, and task chain triggering prediction rules.

9. A method for dynamic allocation of chip resources according to claim 2, characterized in that, The resource configuration instructions include computing resource configuration instructions, storage resource configuration instructions, and communication resource configuration instructions. The computing resource configuration instructions are used to perform computing resource adjustment actions on the chip; the computing resource configuration instructions include computing resource increase instructions and computing resource decrease instructions; The storage resource configuration instructions are used to perform storage resource adjustment actions on the chip; the storage resource configuration instructions include storage bandwidth increase instructions, storage bandwidth decrease instructions, storage cell access priority increase instructions, and storage cell access priority decrease instructions; The communication resource configuration instructions are used to perform communication resource adjustment actions of the chip; the communication resource configuration instructions include instructions to increase the bandwidth of interconnect communication units, instructions to decrease the bandwidth of interconnect communication units, instructions to increase the priority of interconnect communication units, instructions to decrease the priority of interconnect communication units, and instructions to establish a high-priority data flow channel.

10. A method for dynamic allocation of chip resources according to claim 4, characterized in that, The revocation dynamic allocation instruction includes the revocation of computing resource configuration instruction, the revocation of storage resource configuration instruction, and the revocation of communication resource configuration instruction; The command to cancel the configuration of computing resources is used to execute the action of canceling the adjustment of computing resources in the chip; The command to cancel computing resource configuration includes commands to cancel increasing computing resources and commands to cancel decreasing computing resources. The command to cancel storage resource configuration is used to cancel storage resource adjustment operations; the command to cancel storage resource configuration includes commands to cancel storage bandwidth increase, storage bandwidth decrease, storage unit access priority increase, and storage unit access priority decrease. The command to cancel communication resource configuration is used to cancel communication resource adjustment operations; the command to cancel communication resource configuration includes canceling the command to increase the bandwidth of interconnected communication units, canceling the command to decrease the bandwidth of interconnected communication units, canceling the command to increase the priority of interconnected communication units, canceling the command to decrease the priority of interconnected communication units, and canceling the command to establish a high-priority data flow channel.

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