Chip architecture exploration systems, methods, and storage media

Abstract

The application provides a chip architecture exploration system and method and a storage medium. The system comprises: a load and platform compatibility module configured to access an external simulation load tool and obtain configuration parameters of the simulation load tool; a use case management module configured to obtain input chip architecture exploration parameters, and generate an exploration use case corresponding to the chip architecture exploration parameters according to the configuration parameters; the use case management module is further configured to deploy and run the exploration use case, and obtain corresponding use case running data; and a result analysis module configured to perform data extraction and analysis according to preset chip performance indicators based on the use case running data, and output a chip architecture exploration result. The application is beneficial to quickly constructing a required exploration scene, saves redundant workload, and effectively improves chip architecture exploration efficiency.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a chip architecture exploration system, method and storage medium. Background Technology

[0002] In the field of chip design, chip architecture exploration is a crucial step in the chip design process. This step refers to the entire process of evaluating and optimizing chip architecture design schemes through a systematic approach. Its core objective is to quickly assess the PPA (Performance-Power-Area) metrics of different architecture schemes in the early stages of design, thereby reducing design risks after tape-out. In this step, designers need to use various simulation tools to simulate and confirm various parameters and configurations of the chip architecture in order to find the optimal combination, such as determining the size of each cache level to find the best balance between performance and area.

[0003] In this process, designers may face multiple configuration combinations of different architecture parameters. Traditional exploration methods generally include: manually configuring different simulation environments and running test cases one by one for each configuration combination; if a test case configuration fails, the test case needs to be manually restarted to ensure simulation coverage; after the simulation is completed, key information is collected in batches for each test case or using a simple script, and finally, the exploration results are analyzed using charts.

[0004] It can be seen that the existing methods have the following problems:

[0005] Poor compatibility between different simulation tools leads to high switching costs; an explosion of parameter combinations results in low efficiency and a high error rate in manual configuration.

[0006] The simulation results contain a massive amount of data, and the data analysis scripts vary widely, resulting in limited reusability. The excessive amount of data makes it impossible to effectively manage and reuse historical simulation data. There is a lack of a unified monitoring and management interface, and it is impossible to handle failed test cases in a timely manner.

[0007] Therefore, it is necessary to propose a new chip architecture exploration scheme to solve the above problems. Summary of the Invention

[0008] This invention provides a chip architecture exploration system, method, and storage medium, aiming to solve the technical problems of poor compatibility and lack of unified management in existing chip architecture exploration schemes.

[0009] To address the aforementioned technical problems, in a first aspect, the present invention provides a chip architecture exploration system, comprising:

[0010] The load and platform compatibility module is used to connect to external simulation load tools and obtain the configuration parameters of the simulation load tools.

[0011] The test case management module is used to obtain the input chip architecture exploration parameters and generate exploration test cases corresponding to the chip architecture exploration parameters according to the configuration parameters; the test case management module is also used to: deploy and run the exploration test cases and obtain the corresponding test case running data;

[0012] The results analysis module is used to extract and analyze data based on the test case running data according to preset chip performance indicators, and output the chip architecture exploration results.

[0013] Furthermore, the load and platform compatibility module is also used for:

[0014] Analyze the configuration parameters and extract the key parameters of the execution commands of the simulation load tool;

[0015] Based on the base class, a unified calling method for the key parameters of the simulation load tool is implemented, and the unified calling method is organized into selectable configuration list items.

[0016] Furthermore, the use case management module is also used for:

[0017] The chip architecture exploration parameters are obtained based on the configuration list, and the chip architecture exploration parameters are matched with the unified invocation method.

[0018] Furthermore, the use case management module is also used for:

[0019] Obtain the chip architecture exploration parameters, and determine the target structure for architecture exploration based on the chip architecture exploration parameters;

[0020] According to the format of the execution command corresponding to the simulation load tool, the architecture exploration target structure is traversed and combined to obtain multiple exploration use cases corresponding to the chip architecture exploration parameters.

[0021] Furthermore, the use case management module is also used for:

[0022] A simulation process is created to read and deploy all the exploration test cases that need to be run, and the exploration test cases are run in the corresponding simulation workload tool;

[0023] For each of the exploration use cases, a subprocess is created in the simulation process. The subprocess is used to invoke and execute commands and update use case information.

[0024] Upon completion of each exploration test case, the execution data of the test case corresponding to the exploration test case is aggregated through the subprocess, and the subprocess is terminated.

[0025] The simulation process terminates when all described exploratory use cases have finished running.

[0026] Furthermore, the use case management module is also used for:

[0027] The database sequentially stores the test case execution data obtained when the exploratory test case execution ends.

[0028] Furthermore, the result analysis module is also used for:

[0029] Obtain the preset chip performance indicators as input, and read the test case execution data from the database;

[0030] Based on the preset chip performance indicators, extract and analyze the corresponding key performance data from the test case running data;

[0031] The key performance data is visualized into performance charts, and these performance charts are output as the results of the chip architecture exploration.

[0032] Secondly, the present invention also provides a chip architecture exploration method, which is implemented based on the chip architecture exploration system described above, and includes the following steps:

[0033] The load and platform compatibility module connects to an external simulation load tool and obtains the configuration parameters of the simulation load tool.

[0034] The chip architecture exploration parameters are obtained from the test case management module, and exploration test cases corresponding to the chip architecture exploration parameters are generated according to the configuration parameters; the exploration test cases are deployed and run, and the corresponding test case execution data is obtained.

[0035] The results analysis module extracts and analyzes data based on the test case running data according to preset chip performance indicators, and outputs chip architecture exploration results.

[0036] Thirdly, the present invention also provides a computer device, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps in the chip architecture exploration method as described in any of the above embodiments.

[0037] Fourthly, the present invention also provides a storage medium storing a computer program, which, when executed by a processor, implements the steps in the chip architecture exploration method as described in any of the above embodiments.

[0038] The beneficial effects achieved by this invention are as follows: it proposes a chip architecture exploration system that adopts a configuration abstraction approach, is flexibly compatible with various simulation tools and workloads, supports batch generation and deployment of test cases, and can perform batch and automated analysis of test case results. This design facilitates the rapid construction of the required exploration scenarios and effectively improves the efficiency of chip architecture exploration. Secondly, the batch processing of test cases eliminates redundant workload and reduces the probability of errors. In addition, automated result analysis quickly compares test case performance and efficiently analyzes the architecture exploration results. Attached Figure Description

[0039] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0040] Figure 1 This is a schematic diagram of the chip architecture exploration system provided in an embodiment of the present invention;

[0041] Figure 2 This is a flowchart illustrating the steps of the chip architecture exploration method provided in this embodiment of the invention;

[0042] Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0044] Example 1

[0045] First, this embodiment of the invention provides a chip architecture exploration system 100, please refer to... Figure 1 , Figure 1 This is a schematic diagram of the chip architecture exploration system provided in an embodiment of the present invention. The chip architecture exploration system 100 includes:

[0046] The load and platform compatibility module 101 is used to connect to an external simulation load tool and obtain the configuration parameters of the simulation load tool;

[0047] The test case management module 102 is used to obtain the input chip architecture exploration parameters and generate exploration test cases corresponding to the chip architecture exploration parameters according to the configuration parameters; the test case management module is also used to: deploy and run the exploration test cases and obtain the corresponding test case running data;

[0048] The results analysis module 103 is used to extract and analyze data according to preset chip performance indicators based on the test case running data, and output the chip architecture exploration results.

[0049] Specifically, the load and platform compatibility module 101 is also used for:

[0050] Analyze the configuration parameters and extract the key parameters of the execution commands of the simulation load tool;

[0051] Based on the base class, a unified calling method for the key parameters of the simulation load tool is implemented, and the unified calling method is organized into selectable configuration list items.

[0052] Specifically, the load and platform compatibility module 101 uses object-oriented design to abstract the commands and parameters of different simulation load tools into a unified class interface. Any simulation load tool only needs to inherit the base class and implement specific calling methods to access and be compatible with the chip architecture exploration system 100, thereby improving the system's compatibility.

[0053] The simulation workload tools described in this embodiment of the invention include various existing simulation platforms and workload tools. A simulation platform refers to a professional tool or environment used for chip architecture simulation, which can simulate the chip's operating state, calculation process, etc., such as common EDA (Electronic Design Automation) tools used for chip design simulation, or dedicated simulation software developed for specific processor architectures. A workload tool refers to a tool used to generate the tasks or data required for chip operation. These tools can simulate various workloads that the chip may handle in actual applications, such as task flows or datasets in scenarios such as large-scale data computation and multi-task concurrent processing, in order to test the performance of the chip architecture under different load conditions.

[0054] It is understandable that, during the implementation process, since the simulation load tool is known, the execution commands of the simulation load tool can be specifically analyzed and processed based on the known information to obtain the key parameters. These parameters include, but are not limited to: the executable file path or execution command of the simulation platform, simulation parameters, architecture parameters, etc., and the executable file path and input parameters of the load tool.

[0055] The load and platform compatibility module 101 can also organize the unified calling method into selectable configuration list items. This design can help provide users with guidance on building exploration scenarios during the parameter input stage and improve execution efficiency.

[0056] The corresponding load and platform compatibility modules implement a unified invocation method based on the base class. The use case management module 102 is also used for:

[0057] The chip architecture exploration parameters are obtained based on the configuration list, and the chip architecture exploration parameters are matched with the unified invocation method.

[0058] The configuration list can be accessed through a graphical interface, such as input boxes and buttons. Matching user-inputted chip architecture exploration parameters with a unified calling method enables real-time mapping to specific simulation load tools upon input data.

[0059] Specifically, the use case management module 102 is also used for:

[0060] Obtain the chip architecture exploration parameters, and determine the target structure for architecture exploration based on the chip architecture exploration parameters;

[0061] According to the format of the execution command corresponding to the simulation load tool, the architecture exploration target structure is traversed and combined to obtain multiple exploration use cases corresponding to the chip architecture exploration parameters.

[0062] Based on the above functions, initially, the load and platform compatibility module 101 displays the available simulation load tools to the user; then, it selects the corresponding simulation load tool based on the user's input and displays the available configurations; then, it parses the input, calls the command generation method of the corresponding simulation load tool to generate the corresponding exploration test case command; finally, it saves the generated exploration test case for subsequent startup and deployment.

[0063] The process of generating exploratory test cases is a process of traversing and combining target results. For example, based on the input chip architecture exploration parameters, the L3 cache is explored. The L1 cache size is traversed to 32KB or 48KB, the L2 cache size to 256KB, 512KB, or 1024KB, and the L3 cache size to 1MB, 2MB, and 8MB, along with the option of whether the L2 cache is shared. In the test case management module 102, all possible structural combinations are traversed, quickly generating a total of 72 (2×2×3×3×2) exploratory test cases. During implementation, the relevant information of these test cases is saved in the system output path corresponding to the current exploration parameters. Furthermore, to facilitate test case management, the exploratory test case information under each chip architecture exploration parameter path should include the simulation process ID and a test case list. Each exploratory test case should include the test case name, terminal command, process ID, and timestamp.

[0064] In this embodiment of the invention, the execution of exploratory use cases is managed through an additional process. Specifically, the use case management module 102 is further used for:

[0065] A simulation process is created to read and deploy all the exploration test cases that need to be run, and the exploration test cases are run in the corresponding simulation workload tool;

[0066] For each of the exploration use cases, a subprocess is created in the simulation process. The subprocess is used to invoke and execute commands and update use case information.

[0067] Upon completion of each exploration test case, the execution data of the test case corresponding to the exploration test case is aggregated through the subprocess, and the subprocess is terminated.

[0068] The simulation process terminates when all described exploratory use cases have finished running.

[0069] Based on a process-oriented approach to exploratory test case management, the upper limit of simulation processes can be flexibly configured according to the platform's load status during implementation, or the upper limit of executable simulation processes can be dynamically calculated. Understandably, to improve simulation efficiency and reduce the dependence of simulation processes on platform processes, a multi-process approach can be used to start each exploratory test case for simulation. Furthermore, the simulation process and its sub-processes are independent of the simulation load tool, thus preventing the simulation process from being directly stopped after the tool process terminates.

[0070] The test case management module 102 can also be implemented based on a graphical interface. During the execution of the exploratory test cases, the exploratory test cases can be displayed in the monitoring panel through the monitoring window. The monitoring panel can also display the status of all test cases, including execution status, simulator name, process number, execution duration, and memory usage.

[0071] To facilitate efficient data management and analysis, the use case management module 102 is also used for:

[0072] The database sequentially stores the test case execution data obtained when the exploratory test case execution ends.

[0073] During implementation, the database stores all execution and running data of exploratory test cases through a historical information list. To facilitate quick retrieval, the historical information list is stored in JSON format in the default path of the chip architecture exploration parameters. Furthermore, the actual test case running data is stored in the form of a historical database and compressed and stored in units of time to reduce storage consumption.

[0074] The result analysis module 103 is also used for:

[0075] Obtain the preset chip performance indicators as input, and read the test case execution data from the database;

[0076] Based on the preset chip performance indicators, extract and analyze the corresponding key performance data from the test case running data;

[0077] The key performance data is visualized into performance charts, and these performance charts are output as the results of the chip architecture exploration.

[0078] The preset chip performance metrics are primarily obtained through user input. In projects involving batch chip architecture exploration, these preset metrics can also be automatically designed based on project objectives, thereby achieving intelligent analysis. The chart output method can intuitively display the current chip architecture exploration results and facilitate comparison of differences in data from different use cases.

[0079] The beneficial effects achieved by this invention are as follows: it proposes a chip architecture exploration system that adopts a configuration abstraction approach, is flexibly compatible with various simulation tools and workloads, supports batch generation and deployment of test cases, and can perform batch and automated analysis of test case results. This design facilitates the rapid construction of the required exploration scenarios and effectively improves the efficiency of chip architecture exploration. Secondly, the batch processing of test cases eliminates redundant workload and reduces the probability of errors. In addition, automated result analysis quickly compares test case performance and efficiently analyzes the architecture exploration results.

[0080] Example 2

[0081] This invention also provides a chip architecture exploration method, please refer to... Figure 2 , Figure 2 This is a flowchart illustrating the steps of a chip architecture exploration method provided in this embodiment of the invention. The chip architecture exploration method is implemented based on the chip architecture exploration system described in the above embodiment, and includes the following steps:

[0082] S201. Connect to an external simulation load tool based on the load and platform compatibility module, and obtain the configuration parameters of the simulation load tool;

[0083] S202. Obtain the input chip architecture exploration parameters based on the use case management module, generate exploration use cases corresponding to the chip architecture exploration parameters according to the configuration parameters, deploy and run the exploration use cases, and obtain the corresponding use case running data;

[0084] S203. The result analysis module extracts and analyzes data based on the test case running data according to preset chip performance indicators, and outputs the chip architecture exploration results.

[0085] Specifically, step S201 includes the following sub-steps:

[0086] S2011. Analyze the configuration parameters and extract the key parameters of the execution commands of the simulation load tool;

[0087] S2012. Implement a unified calling method for the key parameters of the simulation load tool based on the base class, and organize the unified calling method into selectable configuration list items.

[0088] Step S202 includes the following sub-steps:

[0089] S2021. Obtain the chip architecture exploration parameters and determine the architecture exploration target structure based on the chip architecture exploration parameters; wherein, the input chip architecture exploration parameters are obtained based on the configuration list, and the chip architecture exploration parameters are matched with the unified invocation method;

[0090] S2022. According to the format of the execution command corresponding to the simulation load tool, the architecture exploration target structure is traversed and combined to obtain multiple exploration use cases corresponding to the chip architecture exploration parameters;

[0091] S2023. Create a simulation process to read and deploy all the exploration test cases that need to be run, and run the exploration test cases in the corresponding simulation workload tool;

[0092] S2024. For each of the exploration use cases, a subprocess is created in the simulation process. The subprocess is used to call and execute commands and update use case information.

[0093] S2025. When each of the exploration test cases finishes running, the test case running data corresponding to the exploration test case is summarized by the subprocess, and the subprocess is terminated; wherein, the test case running data obtained when the exploration test case finishes running is stored sequentially in the database;

[0094] S2026. When all the described exploratory use cases have finished running, terminate the simulation process.

[0095] Step S203 includes the following sub-steps:

[0096] S2031. Obtain the preset chip performance indicators as input, and read the test case running data from the database;

[0097] S2032. Based on the preset chip performance indicators, extract and analyze the corresponding key performance data from the test case running data;

[0098] S2033. The key performance data is visualized into a performance chart, and the performance chart is output as the chip architecture exploration result.

[0099] The chip architecture exploration method described above can achieve the corresponding functions in the above embodiments based on the chip architecture exploration system described above, and can achieve the same technical effect. Referring to the description in the above embodiments, it will not be repeated here.

[0100] Example 3

[0101] This invention also provides a computer device, please refer to... Figure 3 , Figure 3 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a computer program stored in the memory 302 and executable on the processor 301.

[0102] The processor 301 calls the computer program stored in the memory 302 to execute the steps in the chip architecture exploration method provided in this embodiment of the invention. Please refer to... Figure 2 Specifically, it includes the following steps:

[0103] S201. Connect to an external simulation load tool based on the load and platform compatibility module, and obtain the configuration parameters of the simulation load tool;

[0104] S202. Obtain the input chip architecture exploration parameters based on the use case management module, generate exploration use cases corresponding to the chip architecture exploration parameters according to the configuration parameters, deploy and run the exploration use cases, and obtain the corresponding use case running data;

[0105] S203. The result analysis module extracts and analyzes data based on the test case running data according to preset chip performance indicators, and outputs the chip architecture exploration results.

[0106] Specifically, step S201 includes the following sub-steps:

[0107] S2011. Analyze the configuration parameters and extract the key parameters of the execution commands of the simulation load tool;

[0108] S2012. Implement a unified calling method for the key parameters of the simulation load tool based on the base class, and organize the unified calling method into selectable configuration list items.

[0109] Step S202 includes the following sub-steps:

[0110] S2021. Obtain the chip architecture exploration parameters and determine the architecture exploration target structure based on the chip architecture exploration parameters; wherein, the input chip architecture exploration parameters are obtained based on the configuration list, and the chip architecture exploration parameters are matched with the unified invocation method;

[0111] S2022. According to the format of the execution command corresponding to the simulation load tool, the architecture exploration target structure is traversed and combined to obtain multiple exploration use cases corresponding to the chip architecture exploration parameters;

[0112] S2023. Create a simulation process to read and deploy all the exploration test cases that need to be run, and run the exploration test cases in the corresponding simulation workload tool;

[0113] S2024. For each of the exploration use cases, a subprocess is created in the simulation process. The subprocess is used to call and execute commands and update use case information.

[0114] S2025. When each of the exploration test cases finishes running, the test case running data corresponding to the exploration test case is summarized by the subprocess, and the subprocess is terminated; wherein, the test case running data obtained when the exploration test case finishes running is stored sequentially in the database;

[0115] S2026. When all the described exploratory use cases have finished running, terminate the simulation process.

[0116] Step S203 includes the following sub-steps:

[0117] S2031. Obtain the preset chip performance indicators as input, and read the test case running data from the database;

[0118] S2032. Based on the preset chip performance indicators, extract and analyze the corresponding key performance data from the test case running data;

[0119] S2033. The key performance data is visualized into a performance chart, and the performance chart is output as the chip architecture exploration result.

[0120] The computer device 300 provided in this embodiment of the invention can implement the steps in the chip architecture exploration method as described in the above embodiments, and can achieve the same technical effect. Referring to the description in the above embodiments, it will not be repeated here.

[0121] Example 4

[0122] This invention also provides a storage medium storing a computer program. When the computer program is executed by a processor, it implements the various processes and steps in the chip architecture exploration method provided in this invention and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0123] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by hardware related to computer programs or instructions. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0124] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0125] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0126] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form under the guidance of the present invention without departing from the spirit and scope of the claims. All such changes are within the protection scope of the present invention.

Claims

1. A chip architecture exploration system, characterized by, The chip architecture exploration method comprises the following steps: A load and platform compatible module is used to access an external simulation load tool and obtain configuration parameters of the simulation load tool; A use case management module is used to obtain input chip architecture exploration parameters and generate exploration use cases corresponding to the chip architecture exploration parameters according to the configuration parameters; the use case management module is further used to deploy and run the exploration use cases and obtain corresponding use case running data; A result analysis module is used to extract and analyze data according to preset chip performance indicators based on the use case running data, and output chip architecture exploration results; The load and platform compatible module is further used to: analyze the configuration parameters and extract key parameters of an execution command of the simulation load tool; implement a unified calling method corresponding to the key parameters of the simulation load tool based on a base class, arrange the unified calling method as an entry of a selectable configuration list, and abstract commands and parameters of different simulation load tools into a unified class interface; The use case management module is further used to: obtain the input chip architecture exploration parameters based on the configuration list, and match the chip architecture exploration parameters with the unified calling method.

2. The chip architecture exploration system of claim 1, wherein, The use case management module is further used to: obtain the chip architecture exploration parameters and determine an architecture exploration target structure according to the chip architecture exploration parameters; perform traversal combination on the architecture exploration target structure according to a format of an execution command corresponding to the simulation load tool, and obtain a plurality of exploration use cases corresponding to the chip architecture exploration parameters.

3. The chip architecture exploration system of claim 1, wherein, The use case management module is further used to: create a simulation process to read and deploy all the exploration use cases that need to be run, and run the exploration use cases in the corresponding simulation load tool; for each exploration use case, create a sub-process in the simulation process, and the sub-process is used to call an execution command and update use case information; when each exploration use case ends running, aggregate the use case running data corresponding to the exploration use case through the sub-process, and end the sub-process; when all the exploration use cases end running, end the simulation process.

4. The chip architecture exploration system of claim 1, wherein, The use case management module is further used to: store the use case running data obtained when the exploration use cases end running in a database in sequence.

5. The chip architecture exploration system of claim 4, wherein, The result analysis module is further used to: obtain input preset chip performance indicators and read the use case running data from the database; extract and analyze corresponding key performance data from the use case running data according to the preset chip performance indicators; perform visual processing on the key performance data to obtain a performance chart, and output the performance chart as the chip architecture exploration results.

6. A chip architecture exploration method based on the chip architecture exploration system of any one of claims 1-5, characterized in that, The chip architecture exploration method comprises the following steps: A load and platform compatible module is used to access an external simulation load tool and obtain configuration parameters of the simulation load tool; A use case management module is used to obtain input chip architecture exploration parameters, generate exploration use cases corresponding to the chip architecture exploration parameters according to the configuration parameters, deploy and run the exploration use cases, and obtain corresponding use case running data; The result analysis module extracts and analyzes data according to preset chip performance indexes based on the use case running data, and outputs chip architecture exploration results; The load and platform compatibility module analyzes the configuration parameters and extracts key parameters of execution commands of the simulation load tool; A unified calling method corresponding to the key parameters of the simulation load tool is implemented based on a base class, the unified calling method is arranged as an entry of a selectable configuration list, and commands and parameters of different simulation load tools are abstracted as a unified class interface; The use case management module obtains the input chip architecture exploration parameters based on the configuration list, and matches the chip architecture exploration parameters with the unified calling method.

7. A computer device, comprising: Comprise: A memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of the chip architecture exploration method according to claim 6 when executing the computer program.

8. A storage medium, characterized by The storage medium stores a computer program, and the computer program is executed by the processor to implement the steps of the chip architecture exploration method according to claim 6.

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