Virtual quantum instruction set design method based on parameterized quantum gate

Abstract

The invention relates to the technical field of virtual quantum instruction sets, in particular to a virtual quantum instruction set design method based on parameterized quantum gates. The problems that when a current virtual instruction set expresses a quantum circuit, the number of basic gates is large, the comprehensive fidelity is low, and the calibration overhead is large are solved. According to the technical scheme, the method comprises the following steps: S1, designing interacting parameterized double quantum bit gates; s2, designing a parameter combination space of a virtual instruction set; s3, selecting different benchmark test lines; s4, decomposing different benchmark test circuits into basic gate circuits formed by different parameter combinations; s5, counting the results; s6, performing comprehensive analysis on a result; s7, selecting an instruction set of a single 2Q basic gate; and S8, designing an instruction set of a plurality of 2Q basic gates. The method has the beneficial effects that the number of basic gates after the quantum circuit is decomposed is reduced; the overall fidelity of the quantum circuit is improved; and the calibration overhead of the instruction set is reduced.

Description

Technical Field

[0001] This invention relates to the field of virtual quantum instruction set technology, and in particular to a design method for a virtual quantum instruction set based on parameterized quantum gates. Background Technology

[0002] Quantum computing is a computational method based on the principles of quantum mechanics, which uses qubits to process information. In quantum computing, qubits have special properties; they can exist simultaneously in a superposition of |0> and |1> states, and they also exhibit unique quantum characteristics such as entanglement. These properties enable quantum computers to process problems in parallel, thereby improving computational efficiency.

[0003] A quantum computer is a machine that runs quantum programs and quantum algorithms. Quantum computers use quantum gates to manipulate qubits to perform quantum computations. A quantum gate is a basic unit of operation used to perform specific operations on a qubit. Currently, quantum computing technology is in the so-called Noisy Intermediate-Scale Quantum (NISQ) era. Quantum computers have hardware limitations; they cannot execute complex quantum gates, but can only execute the quantum gates contained in their own native gate set, i.e., the instruction set of the quantum computer.

[0004] A quantum instruction set is a set of operational instructions composed of quantum gates, as described in the paper: Lin SF, Sussman S, Duckering C, et al. Let each quantum bit choose its basis gates[C] / / 2022 55th IEEE / ACM International Symposium on Microarchitecture(MICRO).IEEE,2022:1042-1058. Currently, complete quantum instruction sets contain both single-qubit gates (1Q gates) and two-qubit gates (2Q gates). Similar to the instruction set architecture in classical computers, quantum instruction sets define the basic operations that can be executed on current quantum computers. As described in the paper: Huang C, Wang T, Wu F, et al. Quantum instruction set design for performance[J]. Physical Review Letters,2023,130(7):070601., a quantum instruction set is an interface provided to software by quantum hardware vendors. For any advanced quantum circuit to be executed on a current quantum computer, the complex quantum gates contained in the advanced circuit must be equivalently converted into the quantum gates contained in the instruction set of the current quantum computer, i.e., the decomposition of the quantum circuit.

[0005] The set of quantum gates that can be executed on a real quantum computer is called the quantum computer's instruction set, while a virtual quantum instruction set is an abstract set of quantum gates that cannot currently be executed on a real quantum computer. Because current real quantum computer instruction set designs only contain a fixed number of basic quantum gates, decomposing advanced quantum circuits into instruction sets often results in a large number of quantum gates. Since all quantum gates on current quantum computers have an error rate, the more quantum gates there are, the more errors accumulate. Therefore, current quantum computer instruction set designs result in decomposed circuits with a large number of gates, high depth, and low overall fidelity. To address this problem, redesigning a set of efficient virtual quantum instruction sets is an urgent task, as these theoretically better-performing virtual quantum instruction sets can provide guidance for the future development of real quantum computer instruction sets.

[0006] Virtual quantum instruction sets (VQAs) provide an abstraction layer. Expressing quantum circuits using VQAs simply involves decomposing the quantum circuits into VQAs, without needing to consider whether these quantum gates can be directly executed on a real quantum computer. The design of VQAs aims to address the problems of high circuit depth, large number of gates, and low synthesis fidelity inherent in current real quantum computer instruction set designs. Research on VQAs theoretically improves the instruction set design of quantum computers and is of great significance for the design of instruction sets for future quantum computers.

[0007] Currently, virtual quantum instruction sets are composed of 2Q gates (non-I gates) and parameterized 1Q gates (U3 gates), as described in the paper: Peterson EC, Bishop LS, Javadi-Abhari A. Optimal synthesis into fixed xx interactions[J]. Quantum, 2022, 6: 696. Fixed 2Q gates (non-I gates) and parameterized 1Q gates (U3 gates) can form a complete set of quantum instructions that can represent all two-qubit operations. 2Q gates are also called basic gates. The design of virtual quantum instruction sets pays particular attention to 2Q gates because their error rate is much higher than that of 1Q gates. Therefore, current virtual quantum instruction set designs revolve around minimizing the number of 2Q basic gates in the decomposed circuit. In the design of virtual quantum instruction sets, the paper: Huang C, Wang T, Wu F, et al. Quantum instruction set design for performance[J]. Physical Review Letters, 2023, 130(7): 070601. proposes a new method for designing a quantum instruction set containing only one 2Q gate. By introducing the SQiSW gate (√iSWAP gate (square root of imaginary commutation gate)) to replace the traditional iSWAP gate, the compilation efficiency and fidelity of quantum computing are significantly improved. The paper: Wu A. Design the Quantum Instruction Set with the Cartan Coordinate Analysis Framework[J]. arXiv preprint arXiv:2410.04008, 2024. proposes a quantum instruction set design framework based on non-standard gates and continuous parameterized 2Q gates. Based on KAK decomposition and analysis of the Cartan coordinates of 2Q gates, analytical transformations can be performed between any 2Q gates.Paper: Lao L, Murali P, Martonosi M, et al. Designing calibration and expressivity-efficient instruction sets for quantum computing[C] / / 2021ACM / IEEE 48th Annual International Symposium on Computer Architecture (ISCA).IEEE,2021:846-859. This paper proposes an instruction set design scheme containing several 2Q gates. By optimizing the design of hardware parameterized gates, only 4-8 types of highly expressive two-qubit gates are used, which can achieve near-continuous gate family expressive power while reducing calibration time.

[0008] Although different quantum instruction set designs can reduce the number of basic gates after decomposition and improve the overall fidelity of the circuit compared to the current quantum computer instruction set design, these design methods also have the following problems:

[0009] (1) For a quantum instruction set design containing a single 2Q gate, all high-level circuits can only be decomposed into the 2Q gate and parameterized 1Q gates. Due to the complexity of the 2Q gate parameter space, an instruction set containing only one 2Q gate may not be able to minimize the number of basic gates after decomposition for most complex high-level gates. Furthermore, the 2Q basic gate has different error rates among different qubits, so it is impossible to guarantee that an instruction set using only one 2Q gate has stable fidelity.

[0010] (2) For quantum instruction set designs containing continuously parameterized 2Q gates, although it is possible to tailor a 2Q basic gate for each advanced quantum gate to be decomposed and minimize the number of basic gates after decomposition, the search space for parameterized decomposition of 2Q basic gates is extremely large during the decomposition process, which will require a great deal of computational resources. Furthermore, the calibration of 2Q gates is also a significant problem in continuously parameterized instruction set designs.

[0011] How to solve the above problems is the problem that this invention aims to solve. Summary of the Invention

[0012] The purpose of this invention is to provide a virtual quantum instruction set design method based on parameterized quantum gates. By designing a parameterized two-qubit gate with two parameters having XX+YY interaction as the basis, the number of basic gates required when decomposing a random 2Q gate with different discrete parameter combinations is tested. The basic gates corresponding to the best-performing parameter combinations are found as the instruction set, and the instruction set is partitioned to reduce the number of basic gates when the quantum circuit is decomposed into a quantum instruction set, thereby improving the fidelity of the quantum circuit.

[0013] A method for designing a virtual quantum instruction set based on parameterized quantum gates includes the following steps:

[0014] Step S1: Design a parameterized two-qubit gate with XX+YY interaction; the two-qubit gate is abbreviated as 2Q gate, and the single-qubit gate is abbreviated as 1Q gate. This parameterized quantum gate is designed as a virtual quantum instruction set scheme because the present invention aims to make the instruction set complete, that is, to be able to express all 2Q gate operations, and also to make the expression concise, that is, to be able to represent various complex operations with a small number of instructions. Because any random 2Q gate to be decomposed will contain at most three different interactions: XX, YY, and ZZ, if the ZZ interaction strength of a 2Q gate to be decomposed is 0, that is, it only contains the interaction between XX and YY, then by adjusting the size of its parameters, this 2Q gate or its equivalence class can be represented. This 2Q gate to be decomposed can be decomposed using only one basic gate and one 1Q gate. If the ZZ interaction strength of a 2Q gate to be decomposed is not 0, then by introducing an additional 1Q gate, the ZZ interaction of the gate can be equivalently transformed into a quantum gate with the interaction between XX and YY. Therefore, this invention considers such a virtual instruction set scheme with the interaction between XX and YY.

[0015] The parameterized 2Q gate with XX and YY interactions designed in this invention serves as the basis for a virtual instruction set. Not only are the instructions themselves concise, but they can also be expressed using fewer instructions when dealing with various complex quantum gates.

[0016] Step S2: Design of the virtual instruction set parameter combination space; A parameterized quantum gate contains parameters. For a parameterized two-qubit gate with XX+YY interaction, it has two parameters, each of which can take any value. The parameter space formed by these two parameters is infinite. Since the changes of the two parameters are periodic for the overall parameterized quantum gate, these two parameters can take values ​​within one period. Within one period, the two parameters are also infinite. By selecting 25 different values ​​at equal intervals within the period of each parameter, 25 × 25 = 625 different combinations can be formed, which can reflect the regularity of the parameter space while reducing the amount of computation, achieving two goals at once.

[0017] Step S3: Select different benchmark circuits; selecting different types of benchmark circuits allows for a more comprehensive evaluation of the performance of the virtual quantum instruction set in various computational tasks. Different circuit types correspond to different computational modes, gate structures, and compilation complexities, thus revealing the performance advantages and disadvantages of the instruction set in multiple dimensions. Using different benchmark circuits can simulate various quantum computing tasks, helping to evaluate the adaptability and versatility of the quantum instruction set from different perspectives.

[0018] Step S4: Decompose different benchmark circuits into basic gates composed of different parameter combinations. Selecting different types of benchmark circuits and decomposing them into basic gates with different parameter combinations is significant, as it allows for a more comprehensive evaluation and differentiation of the universality and expressive power of instruction sets composed of different parameter combinations in various computational tasks. First, different parameter combinations constitute different 2Q basic gates. These different 2Q basic gates, along with 1Q and U3 gates, all possess generality in their instruction sets, but they differ in terms of gate count, depth, and compilation difficulty in different types of circuits. Therefore, decomposing the same set of benchmark circuits into gates under these instruction sets reveals their differences. Second, different types of circuits have different requirements for instruction sets. By decomposing these different circuits separately, it becomes clear which instruction sets are naturally suited to certain types of tasks. Decomposition experiments of different circuits help differentiate the comprehensive expressive power of instruction sets, clarify their adaptability to different quantum computing tasks, and help select instruction sets that perform well across different circuits.

[0019] Step S5: Statistically analyze the decomposition results of all benchmark circuits. Systematically analyzing the decomposition results of all benchmark circuits has multiple and crucial benefits. Statistics provide a basis for quantitative evaluation. By statistically analyzing the decomposition results under different instruction sets, we can objectively measure the performance of each instruction set on different types of circuits and reveal the changing trends in its parameter space expression. Statistically analyzing the decomposition results of all benchmark circuits under instruction sets with different parameter combinations allows for a more intuitive view of the expressive power of instruction sets with different parameter combinations for different circuits, and also reveals the different patterns of parameter space variation on different circuits.

[0020] Step S6: Conduct a comprehensive analysis of the test results for all benchmark circuits. This involves a comprehensive analysis of the decomposition results of all benchmark test circuits under different parameter combinations of basic gate instruction sets. The significance of this analysis lies in going beyond mere data statistics to extract the performance patterns of instruction sets composed of different parameter combinations at a higher level. Comprehensive analysis can demonstrate the overall performance of different instruction sets with different parameter spaces on different test circuits. It allows for a clearer assessment of which instruction sets have superior overall performance. Comprehensive analysis can weigh the performance of different circuits and identify instruction sets that perform well across all tasks. Furthermore, comprehensive analysis integrates local test results into a visually comparable whole, enabling the selection of instruction sets with better overall performance.

[0021] Step S7: Instruction Set Selection for Individual 2Q Basic Gates; After comprehensive analysis of the instruction sets of basic gates composed of different parameter combinations, several instruction sets with strong expressive power are further selected, each of which is chosen as the instruction set for an individual 2Q basic gate. Comprehensive analysis reveals the expressive power of instruction sets composed of different 2Q basic gates under different tasks. Considering the expressive power after synthesis and the differences between basic gates corresponding to different parameter combinations, several basic gates corresponding to different parameter combinations are selected. These 2Q basic gates are each highly expressive and widely adaptable, and can be combined with 1Q gates and U3 gates to form instruction sets with individual 2Q basic gates, improving the efficiency and versatility of quantum computing. When dealing with various quantum computing tasks, this reduces the number of gates required for decomposition, lowers circuit depth, and reduces calibration overhead.

[0022] Step S8: Instruction Set Design for Multiple 2Q Basic Gates. Combining instruction sets of multiple highly expressive single 2Q basic gates into an instruction set containing multiple 2Q basic gates has significant advantages. This combination further enhances the expressive power of the entire instruction set. Different 2Q gates have different adaptability to different types of quantum operations. By integrating them into an instruction set, the compiler can select the most suitable underlying gate type based on the structural characteristics of the target operation during gate decomposition, thereby reducing the number of gates, shortening the circuit depth, and reducing error accumulation while ensuring equivalence. This multi-gate combination method enhances the instruction set's adaptability to diverse tasks. In real-world applications, quantum programs have vastly different structures, and different algorithms have different requirements for gate structures. This design concept is particularly suitable for building general-purpose quantum processors that support solving a wider range of practical problems. Combining multiple highly expressive 2Q basic gates not only further improves compilation quality and efficiency.

[0023] Step S1 is as follows:

[0024] The parameterized quantum gate is expressed as follows:

[0025]

[0026] In the formula: X represents a 1Q gate X gate, Y represents a 1Q gate Y gate, The tensor product is represented; this parameterized 2Q gate contains two parameters, θ and β, where the value of θ controls the strength of the XX interaction and the value of β controls the strength of the YY interaction; by adjusting the values ​​of θ and β, any 2Q quantum gate containing XX and YY interactions can be realized.

[0027] Step S2 is as follows:

[0028] Choosing the two parameters of the MPXY(θ,β) gate requires designing a parameter space, i.e., limiting the range of the two parameters θ and β. The parameter space for both θ and β is set to 25 values.

[0029] Where n∈[-12,-11,…,0,…,11,12];

[0030] Where n∈[-12,-11,…,0,…,11,12];

[0031] The parameter spaces for θ and β each start from -π / 2 and go up to π / 2, each containing 25 discrete values ​​with a step size of . Symmetrical distribution around 0; the specific values ​​of θ and β are as follows:

[0032] θ: -π / 2, -11π / 24,…,0,…,11π / 24,π / 2;

[0033] β: -π / 2, -11π / 24,…,0,…,11π / 24,π / 2;

[0034] There are 25 × 25 = 625 different combinations of parameters (θ, β).

[0035] The instruction set designed in this invention is a discrete parameter space instruction set, rather than an instruction set that allows θ and β to take arbitrary continuous parameter values. Although an instruction set design with continuous parameter values ​​can find an optimal parameter combination under the current instruction set for each 2Q gate to be decomposed, searching the continuous parameter space is extremely computationally expensive. Furthermore, if each 2Q gate to be decomposed corresponds to a basic gate, there will be many different basic gates in the decomposed circuit, making circuit calibration a huge problem. Therefore, this invention chooses an instruction set with a discrete parameter combination space and finds several optimal instruction sets within it.

[0036] Considering the periodicity of the interaction of the 2Q gates, we choose to let the two parameters θ and β range from -π / 2 to π / 2. We choose to take a value every π / 24, for a total of 25 values, because 25 values ​​for each parameter are sufficient to represent the pattern of the parameter space, and 24 is a number with a relatively large number of factors. Using 24 as the denominator for the parameters also makes it easy to obtain the simplest fraction, and the simplest fraction often reflects good performance.

[0037] Step S3 is as follows:

[0038] The benchmark circuits include the Quantum Volume (QV) circuit, the Quantum Fourier Transform (QFT) circuit, the Quantum Approximate Optimization Algorithm (QAOA) circuit, and the random circuit.

[0039] QV quantum circuitry is a full-stack benchmark proposed by IBM to evaluate the performance of quantum computers and test their accuracy and stability when processing complex computations.

[0040] QAOA quantum circuits are a type of quantum circuit used to solve combinatorial optimization problems. They are considered a potentially powerful tool for quantum computing in this field. QAOA circuits are also used to study the performance of real-world systems.

[0041] The QFT quantum circuit is a fundamental circuit in quantum computing, used to perform quantum Fourier transforms, and is crucial in many quantum algorithms;

[0042] Random circuits are randomly generated circuits of various types of quantum gates. If parameters are included, they are randomly generated. They can be used to test an algorithm's ability to handle various random situations.

[0043] Step S4 is as follows:

[0044] S41: Select the decomposition algorithm;

[0045] We choose a quantum circuit parameterization decomposition method based on the limited-memory Broyden–Fletcher–Goldfarb–Shanno algorithm (L-BFGS) numerical optimization search. This decomposition method searches for parameters multiple times to ensure that each 2Q gate to be decomposed has the minimum number of basic gates when the basic gates are fixed. This decomposition method ensures that the same circuit has the minimum number of basic gates when decomposed into basic gates with different parameter combinations. This decomposition method also guarantees the fairness of the subsequent instruction set selection.

[0046] S42: Decompose different lines;

[0047] The benchmark test circuit in step S3 is decomposed into a circuit composed of MPXY(θ,β) gates and parameterized 1Q gates U3 gates (a universal single-qubit gate with three parameters).

[0048] Step S5 specifically includes the following steps:

[0049] S51: Selection of comparison indicators;

[0050] For each decomposition, calculate the ratio of the number of 2Q basic gates in the decomposed circuit to the number of 2Q gates in the circuit before decomposition, when the basic gates are formed by the current parameter combination, denoted as K:

[0051]

[0052] Wherein, DN represents the number of 2Q basic gates in the decomposed circuit, and N represents the number of 2Q gates in the original circuit.

[0053] S52: Statistics of decomposition results;

[0054] The K values ​​of different benchmark test circuits were statistically analyzed for each circuit, which were decomposed into 25×25=625 different combinations of MPXY(θ,β) basic gates.

[0055] Step S6 specifically includes the following steps:

[0056] The test results of all benchmark circuits are comprehensively analyzed; the K values ​​of the basic gate corresponding to each parameter combination under different benchmark test circuits are added together for comprehensive evaluation.

[0057] Step S7 is as follows:

[0058] Six basic gates were selected based on parameter magnitude and symmetry. Specifically, considering both the magnitude of the synthesized K value and the differences between the basic gates corresponding to different parameter combinations, six basic gates were chosen for each parameter combination. These are:

[0059]

[0060] Each of these six basic gates can be combined with parameterized 1Q gates and U3 gates to form an instruction set containing a single 2Q basic gate.

[0061] Step S8 specifically includes the following steps:

[0062] The six different basic gates selected are combined to construct an instruction set containing multiple 2Q basic gates, with each quantum instruction set having at least two 2Q basic gates;

[0063] This invention designs instruction sets containing 2-6 quantum gates respectively:

[0064] G1 = {g1, g2}

[0065] G2 = {g1, g2, g3}

[0066] G3 = {g1, g2, g3, g4}

[0067] G4 = {g1, g2, g3, g4, g5}

[0068] G5 = {g1, g2, g3, g4, g5, g6}

[0069] G1-G5 are five sets of basic gates with different numbers of 2Q gates. Each of these five basic gate sets can be combined with parameterized 1Q gates and U3 gates to form an instruction set containing multiple 2Q basic gates.

[0070] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0071] (1) Reduce the number of basic gates after quantum circuit decomposition.

[0072] The virtual quantum instruction set designed and selected in this invention has clear technical characteristics: it specifies the form of 2Q basic gates during the instruction design stage, prioritizing the use of basic gates that can implement advanced gate functions with the fewest possible number. Based on this, the instruction set has strong expressive power at the logical level, significantly reducing the number of 2Q basic gates required for circuit decomposition of advanced logic gates. The technical effect of this feature is that the overall gate count of the circuit is significantly reduced, resulting in a simpler and more compact circuit structure. The resulting benefits are multifaceted, such as simplified circuits facilitating subsequent compilation and scheduling, shortening execution time, improving circuit execution efficiency, and reducing system resource consumption.

[0073] (2) Improve the overall fidelity of quantum circuits

[0074] The instruction set designed in this invention focuses on addressing the error rate of 2Q gates and the overall fidelity of quantum circuits. Specifically, its technical feature is that, while satisfying the expressive power of the quantum circuit, it decomposes the quantum circuit into instruction combinations with the fewest 2Q gates, thereby avoiding the introduction of redundant or complex gate structures during the decomposition process. This technical feature directly results in a significant reduction in the number of 2Q gates contained in the compiled instruction set. Because in current mainstream hardware, 2Q gates have lower fidelity and a higher error probability than 1Q gates, their number directly affects the accuracy of the overall circuit. Therefore, the beneficial effect of this instruction set is to improve the overall fidelity of the entire quantum circuit, reduce accumulated errors, and make the execution results more reliable.

[0075] (3) Reduce instruction set calibration overhead

[0076] Quantum gates require frequent calibration during implementation to ensure execution accuracy, and the calibration of 2Q gates is often particularly complex, involving multiple dimensions such as gate parameter fitting and noise modeling. The instruction set designed in this invention is characterized by: limiting the types of basic 2Q gates, employing finite discrete fixed-angle gates, and avoiding the use of continuously adjustable parameters or various gate types with significant structural differences. This technical approach results in fewer gate types required for calibration, increased standardization of the calibration process, and a significantly shorter debugging cycle. The resulting benefit is a significant reduction in the overall system calibration overhead, saving experimental time and costs, and improving operational consistency and maintainability. Attached Figure Description

[0077] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used together with the embodiments of the invention to explain the invention and do not constitute a limitation thereof.

[0078] Figure 1 This is a schematic diagram comparing the instruction set of the real quantum computer of this invention with the virtual instruction set: where, Figure 1 (a) is a schematic diagram of a CX gate; Figure 1 (b) to make Figure 1 (a) is a schematic diagram of the quantum circuit after the CX gate is decomposed into the instruction set of a real quantum computer. Figure 1 (c) to make Figure 1 (a) is a schematic diagram of the quantum circuit after the CX gate is decomposed into the virtual quantum instruction set.

[0079] Figure 2 This is a flowchart of a virtual quantum instruction set design method based on parameterized quantum gates according to the present invention.

[0080] Figure 3 This is a schematic diagram of the benchmark test results for the QV circuit of this invention.

[0081] Figure 4 This is a schematic diagram of the benchmark test results for the QFT circuit of this invention.

[0082] Figure 5 This is a schematic diagram of the benchmark test results for the QAOA circuit of this invention.

[0083] Figure 6 This is a schematic diagram of the benchmark test results for the random circuit of the present invention.

[0084] Figure 7 This is a schematic diagram of the results after integrating different benchmark test circuits according to the present invention.

[0085] Figure 8The SYC gate of this invention and A comparison diagram of doors: (wherein,) Figure 8 (a) is a schematic diagram of the original quantum circuit; Figure 8 (b) to make Figure 8 (a) is a schematic diagram of the original quantum circuit decomposed into a SYC gate;

[0086] Figure 8 (c) to make Figure 8 The original quantum circuit in (a) is decomposed into A schematic diagram of the quantum circuit behind the door.

[0087] Figure 9 For the CZ gate of this invention and A comparison diagram of doors: (wherein,) Figure 9 (a) is a schematic diagram of the original quantum circuit; Figure 9 (b) to make Figure 9 (a) is a schematic diagram of the original quantum circuit after being decomposed into CZ gates; Figure 9 (c) to make Figure 9 The original quantum circuit in (a) is decomposed into A schematic diagram of the quantum circuit behind the door. Detailed Implementation

[0088] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. Of course, the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0089] like Figure 1 As shown, Figure 1 (a) is a CX gate. Figure 1 (b) to make Figure 1 (a) The CX (controllable NOT gate) gate is decomposed into the quantum circuit of the instruction set of a real quantum computer, wherein the instruction set of the real quantum computer is a 2Q gate ECR (cross resonance gate) gate and a 1Q gate ID (unit gate), RZ (rotation Z gate), SX (square root of NOT gate) gate and X (NOT gate). Figure 1 (c) to make Figure 1 In (a), the CX gate is decomposed into a quantum circuit using a virtual quantum instruction set, which consists of 2Q-gate iSWAP (imaginary swapping gate) gates and 1Q-gate U3 (universal single-qubit gate) gates. Compared to the instruction set of a real quantum computer, the virtual quantum instruction set allows the same quantum circuit to be represented with different numbers of quantum gates.

[0090] Example 1

[0091] refer to Figure 2This invention provides a method for designing a virtual quantum instruction set based on parameterized quantum gates, comprising the following steps:

[0092] Step S1: Design a parameterized two-qubit gate with XX+YY interaction; the two-qubit gate is abbreviated as 2Q gate, and the single-qubit gate is abbreviated as 1Q gate. This parameterized quantum gate is designed as a virtual quantum instruction set scheme because the present invention aims to make the instruction set complete, that is, to be able to express all 2Q gate operations, and also to make the expression concise, that is, to be able to represent various complex operations with a small number of instructions. Because any random 2Q gate to be decomposed will contain at most three different interactions: XX, YY, and ZZ, if the ZZ interaction strength of a 2Q gate to be decomposed is 0, that is, it only contains the interaction between XX and YY, then by adjusting the size of its parameters, this 2Q gate or its equivalence class can be represented. This 2Q gate to be decomposed can be decomposed using only one basic gate and one 1Q gate. If the ZZ interaction strength of a 2Q gate to be decomposed is not 0, then by introducing an additional 1Q gate, the ZZ interaction of the gate can be equivalently transformed into a quantum gate with the interaction between XX and YY. Therefore, this invention considers such a virtual instruction set scheme with the interaction between XX and YY.

[0093] The parameterized 2Q gate with XX and YY interactions designed in this invention serves as the basis for a virtual instruction set. Not only are the instructions themselves concise, but they can also be expressed using fewer instructions when dealing with various complex quantum gates.

[0094] Step S2: Design of the virtual instruction set parameter combination space; A parameterized quantum gate contains parameters. For a parameterized two-qubit gate with XX+YY interaction, it has two parameters, each of which can take any value. The parameter space formed by these two parameters is infinite. Since the changes of the two parameters are periodic for the overall parameterized quantum gate, these two parameters can take values ​​within one period. Within one period, the two parameters are also infinite. By selecting 25 different values ​​at equal intervals within the period of each parameter, 25 × 25 = 625 different combinations can be formed, which can reflect the regularity of the parameter space while reducing the amount of computation, achieving two goals at once.

[0095] Step S3: Select different benchmark circuits; selecting different types of benchmark circuits allows for a more comprehensive evaluation of the performance of the virtual quantum instruction set in various computational tasks. Different circuit types correspond to different computational modes, gate structures, and compilation complexities, thus revealing the performance advantages and disadvantages of the instruction set in multiple dimensions. Using different benchmark circuits can simulate various quantum computing tasks, helping to evaluate the adaptability and versatility of the quantum instruction set from different perspectives.

[0096] Step S4: Decompose different benchmark circuits into basic gates composed of different parameter combinations. Selecting different types of benchmark circuits and decomposing them into basic gates with different parameter combinations is significant, as it allows for a more comprehensive evaluation and differentiation of the universality and expressive power of instruction sets composed of different parameter combinations in various computational tasks. First, different parameter combinations constitute different 2Q basic gates. These different 2Q basic gates, along with 1Q and U3 gates, all possess generality in their instruction sets, but they differ in terms of gate count, depth, and compilation difficulty in different types of circuits. Therefore, decomposing the same set of benchmark circuits into gates under these instruction sets reveals their differences. Second, different types of circuits have different requirements for instruction sets. By decomposing these different circuits separately, it becomes clear which instruction sets are naturally suited to certain types of tasks. Decomposition experiments of different circuits help differentiate the comprehensive expressive power of instruction sets, clarify their adaptability to different quantum computing tasks, and help select instruction sets that perform well across different circuits.

[0097] Step S5: Statistically analyze the decomposition results of all benchmark circuits. Systematically analyzing the decomposition results of all benchmark circuits has multiple and crucial benefits. Statistics provide a basis for quantitative evaluation. By statistically analyzing the decomposition results under different instruction sets, we can objectively measure the performance of each instruction set on different types of circuits and reveal the changing trends in its parameter space expression. Statistically analyzing the decomposition results of all benchmark circuits under instruction sets with different parameter combinations allows for a more intuitive view of the expressive power of instruction sets with different parameter combinations for different circuits, and also reveals the different patterns of parameter space variation on different circuits.

[0098] Step S6: Conduct a comprehensive analysis of the test results for all benchmark circuits. This involves a comprehensive analysis of the decomposition results of all benchmark test circuits under different parameter combinations of basic gate instruction sets. The significance of this analysis lies in going beyond mere data statistics to extract the performance patterns of instruction sets composed of different parameter combinations at a higher level. Comprehensive analysis can demonstrate the overall performance of different instruction sets with different parameter spaces on different test circuits. It allows for a clearer assessment of which instruction sets have superior overall performance. Comprehensive analysis can weigh the performance of different circuits and identify instruction sets that perform well across all tasks. Furthermore, comprehensive analysis integrates local test results into a visually comparable whole, enabling the selection of instruction sets with better overall performance.

[0099] Step S7: Instruction Set Selection for Individual 2Q Basic Gates; After comprehensive analysis of the instruction sets of basic gates composed of different parameter combinations, several instruction sets with strong expressive power are further selected, each of which is chosen as the instruction set for an individual 2Q basic gate. Comprehensive analysis reveals the expressive power of instruction sets composed of different 2Q basic gates under different tasks. Considering the expressive power after synthesis and the differences between basic gates corresponding to different parameter combinations, several basic gates corresponding to different parameter combinations are selected. These 2Q basic gates are each highly expressive and widely adaptable, and can be combined with 1Q gates and U3 gates to form instruction sets with individual 2Q basic gates, improving the efficiency and versatility of quantum computing. When dealing with various quantum computing tasks, this reduces the number of gates required for decomposition, lowers circuit depth, and reduces calibration overhead.

[0100] Step S8: Instruction Set Design for Multiple 2Q Basic Gates. Combining instruction sets of multiple highly expressive single 2Q basic gates into an instruction set containing multiple 2Q basic gates has significant advantages. This combination further enhances the expressive power of the entire instruction set. Different 2Q gates have different adaptability to different types of quantum operations. By integrating them into an instruction set, the compiler can select the most suitable underlying gate type based on the structural characteristics of the target operation during gate decomposition, thereby reducing the number of gates, shortening the circuit depth, and reducing error accumulation while ensuring equivalence. This multi-gate combination method enhances the instruction set's adaptability to diverse tasks. In real-world applications, quantum programs have vastly different structures, and different algorithms have different requirements for gate structures. This design concept is particularly suitable for building general-purpose quantum processors that support solving a wider range of practical problems. Combining multiple highly expressive 2Q basic gates not only further improves compilation quality and efficiency.

[0101] Step S1 is as follows:

[0102] The parameterized quantum gate is expressed as follows:

[0103]

[0104] In the formula: X represents a 1Q gate X gate, Y represents a 1Q gate Y gate, The tensor product is represented; this parameterized 2Q gate contains two parameters, θ and β, where the value of θ controls the strength of the XX interaction and the value of β controls the strength of the YY interaction; by adjusting the values ​​of θ and β, any 2Q quantum gate containing XX and YY interactions can be realized.

[0105] Step S2 is as follows:

[0106] Choosing the two parameters of the MPXY(θ,β) gate requires designing a parameter space, i.e., limiting the range of the two parameters θ and β. The parameter space for both θ and β is set to 25 values.

[0107] Where n∈[-12,-11,…,0,…,11,12];

[0108] Where n∈[-12,-11,…,0,…,11,12];

[0109] The parameter spaces for θ and β each start from -π / 2 and go up to π / 2, each containing 25 discrete values ​​with a step size of . Symmetrical distribution around 0; the specific values ​​of θ and β are as follows:

[0110] θ: -π / 2, -11π / 24,…,0,…,11π / 24,π / 2;

[0111] β: -π / 2, -11π / 24,…,0,…,11π / 24,π / 2;

[0112] There are 25 × 25 = 625 different combinations of parameters (θ, β).

[0113] The instruction set designed in this invention is a discrete parameter space instruction set, rather than an instruction set that allows θ and β to take arbitrary continuous parameter values. Although an instruction set design with continuous parameter values ​​can find an optimal parameter combination under the current instruction set for each 2Q gate to be decomposed, searching the continuous parameter space is extremely computationally expensive. Furthermore, if each 2Q gate to be decomposed corresponds to a basic gate, there will be many different basic gates in the decomposed circuit, making circuit calibration a huge problem. Therefore, this invention chooses an instruction set with a discrete parameter combination space and finds several optimal instruction sets within it.

[0114] Considering the periodicity of the interaction of the 2Q gates, we choose to let the two parameters θ and β range from -π / 2 to π / 2. We choose to take a value every π / 24, for a total of 25 values, because 25 values ​​for each parameter are sufficient to represent the pattern of the parameter space, and 24 is a number with a relatively large number of factors. Using 24 as the denominator for the parameters also makes it easy to obtain the simplest fraction, and the simplest fraction often reflects good performance.

[0115] Step S3 is as follows:

[0116] The benchmark circuits include the Quantum Volume (QV) circuit, the Quantum Fourier Transform (QFT) circuit, the Quantum Approximate Optimization Algorithm (QAOA) circuit, and the random circuit.

[0117] QV quantum circuitry is a full-stack benchmark proposed by IBM to evaluate the performance of quantum computers and test their accuracy and stability when processing complex computations.

[0118] QAOA quantum circuits are a type of quantum circuit used to solve combinatorial optimization problems. They are considered a potentially powerful tool for quantum computing in this field. QAOA circuits are also used to study the performance of real-world systems.

[0119] The QFT quantum circuit is a fundamental circuit in quantum computing, used to perform quantum Fourier transforms, and is crucial in many quantum algorithms;

[0120] Random circuits are randomly generated circuits of various types of quantum gates. If parameters are included, they are randomly generated. They can be used to test an algorithm's ability to handle various random situations.

[0121] The embodiments of the present invention use 20qubit QV circuits, QFT circuits, and QAOA circuits using a single-layer maximum cut problem, and conduct experiments using 10qubit random circuits.

[0122] Step S4 is as follows:

[0123] S41: Select the decomposition algorithm;

[0124] We choose a quantum circuit parameterization decomposition method based on the limited-memory Broyden–Fletcher–Goldfarb–Shanno algorithm (L-BFGS) numerical optimization search. This decomposition method searches for parameters multiple times to ensure that each 2Q gate to be decomposed has the minimum number of basic gates when the basic gates are fixed. This decomposition method ensures that the same circuit has the minimum number of basic gates when decomposed into basic gates with different parameter combinations. This decomposition method also guarantees the fairness of the subsequent instruction set selection.

[0125] S42: Decompose different lines;

[0126] The benchmark test circuit in step S3 is decomposed into a circuit composed of MPXY(θ,β) gates and parameterized 1Q gates and U3 gates.

[0127] In this embodiment, the benchmark test circuits are decomposed into 20qubit QV circuits, 20qubit QFT circuits, 20qubit QAOA circuits, and 10qubit random quantum circuits. Each benchmark test circuit is decomposed into circuits composed of 2Q basic gates and 1Q U3 gates corresponding to different parameter combinations.

[0128] Step S5 specifically includes the following steps:

[0129] S51: Selection of comparison indicators;

[0130] For each decomposition, calculate the ratio of the number of 2Q basic gates in the decomposed circuit to the number of 2Q gates in the circuit before decomposition, when the basic gates are formed by the current parameter combination, denoted as K:

[0131]

[0132] Wherein, DN represents the number of 2Q basic gates in the decomposed circuit, and N represents the number of 2Q gates in the original circuit.

[0133] S52: Statistics of decomposition results;

[0134] The K values ​​of different benchmark test circuits were statistically analyzed for each circuit, which were decomposed into 25×25=625 different combinations of MPXY(θ,β) basic gates.

[0135] like Figure 3 , Figure 4 , Figure 5 and Figure 6 As shown in the figure, the K values ​​of different lines decomposed into basic gates composed of different parameter combinations are shown in the figure, where the horizontal axis corresponds to the value of parameter θ and the vertical axis corresponds to the value of parameter β.

[0136] Step S6 specifically includes the following steps:

[0137] The test results of all benchmark circuits are comprehensively analyzed; the K values ​​of the basic gate corresponding to each parameter combination under different benchmark test circuits are added together for comprehensive evaluation.

[0138] like Figure 7 The figure shows the combined K-values ​​of different benchmark test circuits;

[0139] Step S7 is as follows:

[0140] Six basic gates were selected based on parameter magnitude and symmetry. Specifically, considering both the magnitude of the synthesized K value and the differences between the basic gates corresponding to different parameter combinations, six basic gates were chosen for each parameter combination. These are:

[0141]

[0142] like Figure 7 As shown, g1-g6 are the six 2Q basic gates that are finally selected. Each of these six basic gates can be combined with the parameterized 1Q gate U3 gate to form an instruction set containing a single 2Q basic gate.

[0143] Step S8 specifically includes the following steps:

[0144] The six different basic gates selected are combined to construct an instruction set containing multiple 2Q basic gates, with each quantum instruction set having at least two 2Q basic gates;

[0145] This invention designs instruction sets containing 2-6 quantum gates respectively:

[0146] G1 = {g1, g2}

[0147] G2 = {g1, g2, g3}

[0148] G3 = {g1, g2, g3, g4}

[0149] G4 = {g1, g2, g3, g4, g5}

[0150] G5 = {g1, g2, g3, g4, g5, g6}

[0151] G1-G5 are five sets of basic gates with different numbers of 2Q gates. Each of these five basic gate sets can be combined with parameterized 1Q gates and U3 gates to form an instruction set containing multiple 2Q basic gates.

[0152] Example 2

[0153] Building upon Example 1, an example of decomposing a quantum circuit into different instruction sets is given to demonstrate the effectiveness of the aforementioned instruction sets. For a randomly generated 4-qubit QV quantum circuit of depth 1, containing two random 2Q gates, such as... Figure 8 As shown in (a), it is now decomposed into two instruction sets: one consisting of 2Q-gate SYC (Sycamore gate) gates and parameterized 1Q-gate U3 gates, and the other consisting of the instruction set g1 proposed in this invention. As an instruction set consisting of 2Q gates and parameterized 1Q gates and U3 gates, compare which instruction set can represent the original quantum circuit with fewer basic gates.

[0154] All decomposition methods employ a quantum circuit parameterization decomposition method based on L-BFGS numerical optimization search to control variables and ensure that differences in results are solely due to the selection of different instruction sets. When SYC gates are used as the basic gates, the decomposed circuit will have 6 SYC gates, such as... Figure 8 As shown in (b). And when using If a door is used as the basic door, then the decomposed circuit will only have 4 lines. Door, like Figure 8 As shown in (c). Under the same decomposition method, each 2Q gate in the original quantum circuit requires an average of 3 SYC gates for decomposition, while only 2 are needed on average. Only one gate is needed. This demonstrates the advantage of the instruction set designed in this invention in terms of the number of gates after decomposition.

[0155] The comparison results are shown in Table 1:

[0156] Table 1 Comparison of gate counts for different instruction sets

[0157]

[0158]

[0159] For any quantum circuit, this invention can decompose the same quantum circuit using fewer basic gates while using the same decomposition method.

[0160] Example 3

[0161] Building upon Example 1, another example of decomposing a quantum circuit into different instruction sets is given to demonstrate the effectiveness of the aforementioned instruction sets. The same quantum circuit is decomposed into different quantum instruction sets using the same decomposition method, and the overall fidelity of the decomposed quantum circuits is compared. For example... Figure 9 As shown in (a), the original quantum circuit is a randomly generated two-qubit QV quantum circuit, which contains one random 2Q gate. It is now decomposed into two instruction sets: one consisting of a 2Q gate CZ (control Z gate) and a parameterized 1Q gate U3, and the other in instruction set g1 proposed in this invention. The instruction set consists of 2Q gates and parameterized 1Q gates / U3 gates. The decomposition method also uses the quantum circuit parameterization decomposition method based on L-BFGS numerical optimization search.

[0162] When CZ gates are used as the basic gates, the decomposed circuit will have 3 CZ gates, such as Figure 9 As shown in (b). And when using If a door is used as the basic door, then the decomposed circuit will only have two paths. Door, like Figure 9 As shown in (c). Assume the fidelity of all 1Q gates between q0 and q1 is 1, and the fidelity of the 2Q gates is 0.97. Then, decomposing the 2Q gates in the original circuit into instruction sets of CZ and U3 gates yields an overall fidelity of 0.97 × 0.97 × 0.97 ≈ 0.913. And decomposing this gate into the instruction set g1 proposed in this invention... For the U3 and U4 gates, the overall fidelity is 0.97 × 0.97 ≈ 0.941. This demonstrates the advantage of the instruction set designed in this invention in terms of overall fidelity.

[0163] The comparison results are shown in Table 2:

[0164] Table 2 Comparison of fidelity of different instruction sets

[0165]

[0166] For any quantum circuit, this invention can achieve higher overall fidelity of the decomposed quantum circuit when using the same decomposition method to decompose the same quantum circuit.

[0167] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for designing a virtual quantum instruction set based on parameterized quantum gates, characterized in that, Includes the following steps: Step S1: Design a parameterized two-qubit gate with XX+YY interaction; Step S2: Design of the virtual instruction set parameter combination space; Step S3: Select different benchmark test circuits; Step S4: Decompose different benchmark test circuits into basic gate circuits composed of different parameter combinations; Step S5: Statistically analyze the decomposition results of all benchmark test circuits; Step S6: Conduct a comprehensive analysis of the test results for all reference circuits; Step S7: Instruction set selection for a single 2Q basic gate; Step S8: Instruction set design for multiple 2Q basic gates.

2. The virtual quantum instruction set design method based on parameterized quantum gates according to claim 1, characterized in that, Step S1 specifically involves: The parameterized quantum gate is expressed as follows: In the formula: X represents a 1Q gate X gate, Y represents a 1Q gate Y gate, The tensor product is represented; this parameterized 2Q gate contains two parameters, θ and β, where the value of θ controls the strength of the XX interaction and the value of β controls the strength of the YY interaction; by adjusting the values ​​of θ and β, any 2Q quantum gate containing XX and YY interactions can be realized.

3. The virtual quantum instruction set design method based on parameterized quantum gates according to claim 2, characterized in that, Step S2 specifically involves: Choosing the two parameters of the MPXY(θ,β) gate requires designing a parameter space, i.e., limiting the range of the two parameters θ and β. The parameter space for both θ and β is set to 25 values. Where n∈[-12,-11,…,0,…,11,12]; Where n∈[-12,-11,…,0,…,11,12]; The parameter spaces for θ and β each start from -π / 2 and go up to π / 2, each containing 25 discrete values ​​with a step size of . Symmetrical distribution around 0; the specific values ​​of θ and β are as follows: θ: -π / 2, -11π / 24,…,0,…,11π / 24,π / 2; β：-π / 2，-11π / 24,…,0,…,11π / 24,π / 2； There are 25 × 25 = 625 different combinations of parameters (θ, β).

4. The method for designing a virtual quantum instruction set based on parameterized quantum gates according to claim 2, characterized in that, Step S3 specifically involves: The benchmark circuits include quantum volume (QV) circuits, quantum Fourier transform (QFT) circuits, quantum approximation optimization algorithm (QAQA) circuits, and random circuits.

5. The method for designing a virtual quantum instruction set based on parameterized quantum gates according to claim 4, characterized in that, Step S4 includes the following steps: S41: Select the decomposition algorithm; We select a quantum circuit parameterization decomposition method based on the quasi-Newton method L-BFGS numerical optimization search with limited memory. S42: Decompose different lines; The benchmark test circuit in step S3 is decomposed into a circuit composed of MPXY(θ,β) gates and parameterized 1Q gates and U3 gates.

6. The method for designing a virtual quantum instruction set based on parameterized quantum gates according to claim 1, characterized in that, Step S5 includes the following steps: S51: Selection of comparison indicators; For each decomposition, calculate the ratio of the number of 2Q basic gates in the decomposed circuit to the number of 2Q gates in the circuit before decomposition, when the basic gates are formed by the current parameter combination, denoted as K: Wherein, DN represents the number of 2Q basic gates in the decomposed circuit; N represents the number of 2Q gates in the circuit before decomposition. S52: Statistics of decomposition results; The K values ​​of different benchmark test circuits were statistically analyzed for each circuit, which were decomposed into 25×25=625 different combinations of MPXY(θ,β) basic gates.

7. The method for designing a virtual quantum instruction set based on parameterized quantum gates according to claim 1, characterized in that, Step S6 specifically involves: The test results of all benchmark circuits are comprehensively analyzed; the K values ​​of the basic gates corresponding to each parameter combination under different benchmark test circuits are added together for comprehensive evaluation.

8. The method for designing a virtual quantum instruction set based on parameterized quantum gates according to claim 1, characterized in that, Step S7 specifically involves: Six basic gates are selected based on parameter size and symmetry:

9. The method for designing a virtual quantum instruction set based on parameterized quantum gates according to claim 7, characterized in that, Step S8 specifically involves: The six different basic gates selected are combined to construct an instruction set containing multiple 2Q basic gates, with each quantum instruction set having at least two 2Q basic gates; G1 = {g1, g2} G2 = {g1, g2, g3} G3 = {g1, g2, g3, g4} G4 = {g1, g2, g3, g4, g5} G5 = {g1, g2, g3, g4, g5, g6} G1-G5 are five sets of basic gates with different numbers of 2Q gates. Each of these five basic gate sets can be combined with parameterized 1Q gates and U3 gates to form an instruction set containing multiple 2Q basic gates.

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