Shift register, gate drive circuit and display device

Abstract

The invention provides a shift register, a gate drive circuit and a display device, and belongs to the technical field of display. The shift register comprises a first input sub-circuit, a second input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit, at least one pull-down sub-circuit, at least one first auxiliary sub-circuit and at least one second auxiliary sub-circuit, the pull-down control sub-circuits are connected with the pull-down sub-circuits in a one-to-one correspondence manner, and connection nodes are pull-down nodes; a connection node among the first input sub-circuit, the second input sub-circuit and the output sub-circuit is a pull-up node; the first auxiliary sub-circuit is configured to pull down the potential of the pull-down node corresponding to the first auxiliary sub-circuit through the second scanning signal in response to the first input signal; and the second auxiliary sub-circuit is configured to pull down the potential of the pull-down node corresponding to the second auxiliary sub-circuit through the first scanning signal in response to the second input signal.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a shift register, a gate driving circuit, and a display device. Background Technology

[0002] With the continuous development of display technology, the development of displays in recent years has gradually shown a trend towards high integration and low cost. One very important technology is the mass production realization of GOA (Gate Driver on Array) technology. GOA technology integrates the gate switching circuit of TFT (Thin Film Transistor) onto the array substrate of the display panel to form a scanning drive for the display panel, thus eliminating the need for the gate driver integrated circuit. This not only reduces product costs in terms of both material costs and manufacturing processes, but also allows for a symmetrical and aesthetically pleasing design with narrow bezels. Furthermore, eliminating the gate-direction bonding process is beneficial for improving production capacity and yield. This gate switching circuit integrated onto the array substrate using GOA technology is also called a GOA circuit or a shift register circuit. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and provides a shift register, a gate driving circuit and a display device.

[0004] This disclosure provides a shift register, which includes: a first input sub-circuit, a second input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit, and at least one pull-down sub-circuit; the pull-down control sub-circuit and the pull-down sub-circuit are connected in a one-to-one correspondence, and the connection node is a pull-down node;

[0005] The first input sub-circuit is configured to precharge the pull-up node via a first scan signal in response to the first input signal;

[0006] The second input sub-circuit is configured to precharge the pull-up node via a second scan signal in response to a second input signal;

[0007] The output sub-circuit is configured to output the clock signal via a signal output in response to the potential of the pull-up node;

[0008] The pull-down control sub-circuit is configured to respond to a power supply voltage signal and control the potential of the corresponding pull-down node via the power supply voltage signal;

[0009] The pull-down sub-circuit is configured to, in response to the potential of the pull-up node, pull down the potential of the corresponding pull-down node by a non-operating level signal; wherein...

[0010] The shift register further includes at least one first auxiliary sub-circuit and at least one second auxiliary sub-circuit, wherein the first auxiliary sub-circuit and the second auxiliary sub-circuit are connected to the pull-down node in a one-to-one correspondence.

[0011] The first auxiliary sub-circuit is configured to, in response to the first input signal, pull down the potential of the corresponding pull-down node via the second scan signal;

[0012] The second auxiliary sub-circuit is configured to, in response to the second input signal, pull down the potential of the corresponding pull-down node via the first scan signal.

[0013] The first auxiliary sub-circuit includes a sixteenth transistor;

[0014] The first terminal of the sixteenth transistor is connected to the corresponding pull-down node, the second terminal is connected to the second scan signal terminal, and the control terminal is connected to the first input signal terminal.

[0015] The second auxiliary sub-circuit includes a fifteenth transistor;

[0016] The first terminal of the fifteenth transistor is connected to the corresponding pull-down node, the second terminal is connected to the first scan signal terminal, and the control terminal is connected to the second input signal terminal.

[0017] The shift register further includes a global reset sub-circuit, which, in response to a global reset signal, performs a global reset on the pull-up node and the signal output terminal through the non-working level signal.

[0018] The global reset sub-circuit includes a fourth transistor and a seventh transistor;

[0019] The first terminal of the fourth transistor is connected to the pull-up node, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the global reset signal terminal.

[0020] The first terminal of the seventh transistor is connected to the signal output terminal, the second terminal is connected to the non-operating level signal terminal, and the control terminal is connected to the global reset signal terminal.

[0021] The shift register further includes at least one first noise reduction sub-circuit; the first noise reduction sub-circuit is configured to reduce the noise of the output of the pull-up node by a non-working level signal under the control of the corresponding pull-down node.

[0022] The first noise reduction sub-circuit includes a tenth transistor;

[0023] The first terminal of the tenth transistor is connected to the pull-up node, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the corresponding pull-down node.

[0024] The shift register further includes at least one second noise reduction sub-circuit; the second noise reduction sub-circuit is configured to reduce the noise of the output of the signal output terminal by means of a non-working level signal under the control of the corresponding pull-down node.

[0025] The second noise reduction sub-circuit includes an eleventh transistor;

[0026] The first terminal of the eleventh transistor is connected to the signal output terminal, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the corresponding pull-down node.

[0027] The shift register further includes a cascaded sub-circuit configured to output a clock signal through the cascaded signal terminal in response to the potential of the pull-up node.

[0028] The cascaded sub-circuit includes a thirteenth transistor;

[0029] The first terminal of the thirteenth transistor is connected to the clock signal terminal, the second terminal is connected to the cascade signal terminal, and the control terminal is connected to the pull-up node.

[0030] The shift register further includes at least one third noise reduction sub-circuit; the third noise reduction sub-circuit is configured to reduce the noise of the output of the cascaded signal terminal by means of a non-working level signal under the control of the corresponding pull-down node.

[0031] The third noise reduction sub-circuit includes a twelfth transistor;

[0032] The first terminal of the twelfth transistor is connected to the cascaded signal terminal, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the corresponding pull-down node.

[0033] The first input sub-circuit includes a first transistor;

[0034] The first terminal of the first transistor is connected to the first scan signal terminal, the second terminal is connected to the pull-up node, and the control terminals are all connected to the first input signal terminal.

[0035] The second input sub-circuit includes a second transistor;

[0036] The first terminal of the second transistor is connected to the second scan signal terminal, the second terminal is connected to the pull-up node, and the control terminals are all connected to the second input signal terminal.

[0037] The output sub-circuit includes a third transistor and a storage capacitor;

[0038] The first terminal of the third transistor is connected to the clock signal terminal, the second terminal is connected to the signal output terminal and the second terminal of the storage capacitor, and the control terminal is connected to the first terminal of the pull-up node and the first terminal of the storage capacitor.

[0039] The pull-up control sub-circuit includes a fifth transistor;

[0040] The first and control terminals of the fifth transistor are connected to the power supply voltage terminal, and the second terminal is connected to the pull-down node.

[0041] The pull-down sub-circuit includes a sixth transistor;

[0042] The first terminal of the sixth transistor is connected to the pull-down node, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the pull-up node.

[0043] The pull-up control sub-circuit includes a fifth transistor and a ninth transistor;

[0044] The first terminal of the fifth transistor is connected to the first terminal of the ninth transistor, the control terminal of the ninth transistor, and the power supply voltage terminal, and the second terminal is connected to the pull-down node.

[0045] The pull-down sub-circuit includes a sixth transistor and an eighth transistor;

[0046] The first terminal of the sixth transistor is connected to the pull-down node, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the pull-up node;

[0047] The first terminal of the eighth transistor is connected to the control terminal of the fifth transistor and the first terminal of the ninth transistor, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the pull-up node.

[0048] This disclosure provides a gate driving circuit that includes a plurality of cascaded shift registers, wherein the shift registers are any of the shift registers described above.

[0049] This disclosure provides a display device that includes any of the gate driving circuits described above. Attached Figure Description

[0050] Figure 1 This is a circuit diagram of an exemplary shift register.

[0051] Figure 2 This is a circuit diagram of a shift register, representing a first example of an embodiment of this disclosure.

[0052] Figure 3 for Figure 2 Timing diagram of the forward scan of the shift register.

[0053] Figure 4 for Figure 2 Timing diagram of the shift register reverse scan.

[0054] Figure 5 This is a circuit diagram of a shift register, representing a second example of an embodiment of this disclosure.

[0055] Figure 6 This is a circuit diagram of a shift register, representing a third example of an embodiment of this disclosure.

[0056] Figure 7 This is a circuit diagram of a shift register, representing a fourth example of an embodiment of this disclosure.

[0057] Figure 8 This is a circuit diagram of a shift register, representing a fifth example of an embodiment of this disclosure. Detailed Implementation

[0058] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0059] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0060] It should be noted that the transistors used in the embodiments of this invention can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no distinction between them. In the embodiments of this invention, to distinguish the source and drain of the transistor, one of them is called the first terminal, the other is called the second terminal, and the gate is called the control terminal. Furthermore, transistors can be classified into N-type and P-type according to their characteristics. The following embodiments use N-type transistors for illustration. When using an N-type transistor, the first terminal is the source, the second terminal is the drain, and when the gate input is high, the source and drain are conducting; the opposite is true for P-type transistors. It is conceivable that using a P-type transistor is something that those skilled in the art can easily conceive of without creative effort, and therefore it is also within the scope of protection of the embodiments of this invention.

[0061] In this embodiment of the invention, since the transistor used is an N-type transistor, the working level signal in this embodiment of the invention refers to a high-level signal, and the non-working level signal is a low-level signal; the corresponding working level terminal is a high-level signal terminal, and the non-working level terminal is a low-level signal terminal VGL.

[0062] A typical display panel consists of multiple grid lines and multiple data lines. The grid lines and data lines intersect to define multiple pixel areas, each containing a pixel unit. The structure of the display panel is explained using the extension direction of the grid lines as the row direction and the extension direction of the data lines as the column direction as an example. When driving the display panel to display an image, grid scan signals are written to the grid lines row by row, and data voltage signals are simultaneously written to each data line, so that the pixel units in the display panel are lit row by row.

[0063] In this design, the gate scan signal is provided by the gate drive circuit, and the data voltage signal is provided by the source drive circuit. In related technologies, the gate drive circuit can be integrated into the gate drive chip, and the source drive circuit can be integrated into the source drive chip. Currently, in order to reduce the number of chips and achieve narrow bezels or bezel-less designs, a technology that integrates the gate drive circuit on the array substrate (Gate On Array; GOA) has been proposed. The gate drive circuit includes multiple cascaded shift registers integrated on the array substrate. Each shift register is connected to a gate line in a one-to-one correspondence and is used to provide the gate scan signal to the gate line connected to it.

[0064] To better understand how shift registers implement the output of the gate scan signal, the following explanation uses a specific example of a shift register unit.

[0065] Figure 1 Here is a circuit diagram of an exemplary shift register; such as Figure 1As shown, the shift register includes an input sub-circuit 1, an output sub-circuit 3, a pull-up reset sub-circuit 2, a global reset sub-circuit 6, two pull-down control sub-circuits 41 / 42, two pull-down sub-circuits 51 / 52, two first noise reduction sub-circuits 71 / 72, and two second noise reduction sub-circuits 81 / 82. For ease of description, the two pull-down control sub-circuits 41 and 52 are referred to as the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42, respectively, and the two pull-down sub-circuits 51 and 52, respectively. The first pull-down control sub-circuit 41 and the first pull-down circuit 51 are connected, and the connection node between them is called the first pull-down node PD1; the second pull-down control sub-circuit 42 and the second pull-down circuit 52 are connected, and the connection node between them is called the second pull-down node PD2.

[0066] Continue to refer to Figure 1 Input sub-circuit 1 is configured to respond to an input signal and precharge the pull-up node PU via the input signal. Output sub-circuit 3 is configured to output a clock signal through the signal output terminal G(N) in response to the potential of the pull-up node PU. Pull-up reset sub-circuit 2 is configured to reset the pull-up node PU via a low-level signal under the control of the pull-up reset signal. Global reset sub-circuit 6 is configured to reset the pull-up node PU and the signal output terminal G(N) via a low-level signal in response to a global reset signal. Output sub-circuit 3 is configured to output a clock signal through the signal output terminal G(N) in response to the potential of the pull-up node PU. First pull-down control sub-circuit 41 is configured to respond to a first power supply voltage signal and control the potential of the first pull-down node PD1 via the first power supply voltage signal. Second pull-down control sub-circuit 42 is configured to respond to a second power supply voltage signal and control the potential of the second pull-down node PD2 via the second power supply voltage signal. The first pull-down sub-circuit 51 is configured to respond to the potential of the pull-up node PU by pulling down the potential of the first pull-down node PD1 with a low-level signal. The second pull-down sub-circuit 52 is configured to respond to the potential of the pull-up node PU by pulling down the potential of the second pull-down node PD2 with a low-level signal. One of the two first noise reduction sub-circuits 71 responds to the potential of the first pull-down node PD1 by performing noise reduction on the output of the pull-up node PU with a low-level signal, and the other 72 responds to the potential of the second pull-down node PD2 by performing noise reduction on the output of the pull-up node PU with a low-level signal. One of the two second noise reduction sub-circuits 81 responds to the potential of the first pull-down node PD1 by performing noise reduction on the output of the signal output terminal G(N) with a low-level signal, and the other 82 responds to the potential of the second pull-down node PD2 by performing noise reduction on the output of the signal output terminal G(N) with a low-level signal.

[0067] Specifically, continuing with reference to 1, the input sub-circuit 1 includes a first transistor M1, the pull-up reset sub-circuit 2 includes a second transistor M2, the output sub-circuit 3 includes a third transistor M3 and a storage capacitor C1, the global reset sub-circuit 6 includes a fourth transistor M4 and a seventh transistor M7, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 both include a fifth transistor and a ninth transistor, the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 both include a sixth transistor and an eighth transistor, each first noise reduction sub-circuit includes a tenth transistor, and each second noise reduction sub-circuit includes an eleventh transistor. For ease of description, the fifth and ninth transistors in the first pull-down control sub-circuit 41 are represented by M5A and M9A, respectively; the fifth and ninth transistors in the second pull-down sub-circuit 52 are represented by M5B and M9B, respectively; the sixth and eighth transistors in the first pull-down sub-circuit 51 are represented by M6A and M8A, respectively; the sixth and eighth transistors in the second pull-down sub-circuit 52 are represented by M6B and M8B, respectively; the tenth transistors in the two first noise reduction sub-circuits are represented by M10A and M10B, respectively; and the eleventh transistors in the two second noise reduction sub-circuits are represented by M11A and M11B, respectively.

[0068] In this configuration, the source and gate of M1 are connected to the signal input terminal, and the drain of M1 is connected to the pull-up node PU. The source of M2 is connected to the pull-up node PU, the drain of M2 is connected to the low-level signal terminal VGL, and the gate of M2 is connected to the pull-up reset signal terminal. The source of M3 is connected to the clock signal terminal CLK, the drain of M3 is connected to the signal output terminal G(N), and the gate of M3 is connected to the pull-up node PU. The first terminal of C1 is connected to the pull-up node PU, and the second terminal of C1 is connected to the signal output terminal G(N). The source of M4 is connected to the pull-up node PU, the drain of M4 is connected to the low-level signal terminal VGL, and the gate of M4 is connected to the global reset signal terminal. The source of M7 is connected to the signal output terminal G(N), the drain of M7 is connected to the low-level signal terminal VGL, and the gate of M7 is connected to the global reset signal terminal. The source of M5A is connected to the first power supply voltage terminal VDDO, the drain of M5A is connected to the first pull-down node PD1, the gate of M5A is connected to the drain of M9A, and the source and gate of M9A are connected to the second power supply voltage terminal VDDE. The source of M5B is connected to the second power supply voltage terminal VDDE, the drain of M5B is connected to the second pull-down node PD2, the gate of M5B is connected to the drain of M9B, and the source and gate of M9B are connected to the second power supply voltage terminal VDDE. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M8A is connected to the drain of M9A and the gate of M5A, the drain of M8A is connected to the low-level signal terminal VGL, and the gate of M8A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU. The source of M8B is connected to the drain of M9B and the gate of M5B. The drain of M8B is connected to the low-level signal terminal VGL, and the gate of M8B is connected to the pull-up node PU. The source of M10A is connected to the pull-up node PU, the drain of M10A is connected to the low-level signal terminal VGL, and the gate of M10A is connected to the first pull-down node PD1. The source of M10B is connected to the pull-up node PU, the drain of M10B is connected to the low-level signal terminal VGL, and the gate of M10B is connected to the second pull-down node PD2. The source of M11A is connected to the signal output terminal G(N), the drain of M11A is connected to the low-level signal terminal VGL, and the gate of M11A is connected to the first pull-down node PD1. The source of M11B is connected to the signal output terminal G(N), the drain of M11B is connected to the low-level signal terminal VGL, and the gate of M11B is connected to the second pull-down node PD2.

[0069] It should be noted that the source of M1 may not be connected to its gate. For example, the source of M1 can be connected to the first signal terminal, the drain of M1 can be connected to the pull-up node PU, and the gate of M1 can be connected to the signal input terminal. In this case, a high-level signal is written to the signal input terminal, M1 is turned on, and the high-level signal written to the first signal terminal pre-charges the pull-up node PU. In this embodiment of the present disclosure, only the example of the source and gate of M1 being connected together is used for illustration. However, it should be understood that this does not constitute a limitation on the scope of protection of the embodiments of the present disclosure.

[0070] When the shift registers in the embodiments of this disclosure are applied to the gate drive circuit, except for the first-stage shift register, the signal input terminal of the Nth-stage shift register is connected to the signal output terminal G(N-1) of the (N-1)th-stage shift register; except for the last-stage shift register, the pull-up reset signal terminal of the Nth-stage shift register is connected to the signal output terminal G(N+1) of the (N+1)th-stage shift register. N≥2, and N is an integer. The inventors discovered that, as Figure 1 As shown, when the gate drive circuit is working, when G(N-1) is a high-level signal and the signals input to G(N+1) and the global reset signal are low-level signals, M1 is turned on and M2 is turned off, and the pull-up node PU begins charging. When the pull-up node PU is high, M6A / M6B / M8A / M8B are turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled low to ensure that the pull-up node PU remains high for normal output. However, when the pull-up node PU just begins charging, its potential has not yet risen to a high level, the first pull-down node PD1 and the second pull-down node PD2 are still high, and M10A / M10B are still on. The potential of the pull-up node PU is in a state of simultaneous charging and discharging. There is a competition relationship between the pull-up node PU, the first pull-down node PD1, and the second pull-down node PD2, affecting the charging of the pull-up node PU. Figure 1 As shown, if the pull-up node PU cannot compete with the potential of the first pull-down node PD1 and the second pull-down node PD2, the pull-up node PU will not be able to charge, and the shift register of this row will have no output, resulting in interlaced display.

[0071] To address the problems existing in the above-mentioned technical solutions, the present disclosure provides the following technical solutions. Before describing the technical solutions of the present disclosure, it should be noted that the following technical solutions are only examples where the number of pull-down control sub-circuit, pull-down sub-circuit, first noise reduction sub-circuit, second noise reduction sub-circuit, and third noise reduction sub-circuit is one or two. It should be understood that the number of pull-down control sub-circuit, pull-down sub-circuit, first noise reduction sub-circuit, second noise reduction sub-circuit, and third noise reduction sub-circuit in the shift register can be more, which will not be listed here.

[0072] The technical solutions of the embodiments of this disclosure will now be described in detail.

[0073] First example: Figure 2 This is a circuit diagram of a shift register according to a first example of an embodiment of this disclosure; as shown below. Figure 2 As shown, the shift register includes a first input sub-circuit 11, a second input sub-circuit 12, an output sub-circuit 3, two pull-down control sub-circuits 41 / 42, two pull-down sub-circuits 51 / 52, two first auxiliary sub-circuits, and two second auxiliary sub-circuits. For ease of description, the two pull-down control sub-circuits 41 / 42 are referred to as the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42, respectively, and the two pull-down sub-circuits 51 / 52 are referred to as the first pull-down circuit 51 and the second pull-down circuit 52, respectively. The first pull-down control sub-circuit 41 and the first pull-down circuit 51 are connected, and the connection node between them is called the first pull-down node PD1; the second pull-down control sub-circuit 42 and the second pull-down circuit 52 are connected, and the connection node between them is called the second pull-down node PD2.

[0074] for Figure 2The shift register in the circuit can achieve bidirectional scanning, i.e., forward scanning and reverse scanning. During forward scanning, the second input sub-circuit 12 acts as the pull-up reset sub-circuit 2; during reverse scanning, the first input sub-circuit 11 acts as the pull-up reset sub-circuit 2. The first input sub-circuit 11 is configured to pre-charge the pull-up node PU via the first scan signal in response to the first input signal. The second input sub-circuit 12 is configured to pre-charge the pull-up node PU via the second scan signal in response to the second input signal. The output sub-circuit 3 is configured to output the clock signal through the signal output terminal G(N) in response to the potential of the pull-up node PU. The first pull-down control sub-circuit 41 is configured to control the potential of the first pull-down node PD1 in response to the first power supply voltage signal. The second pull-down control sub-circuit 42 is configured to control the potential of the second pull-down node PD2 in response to the second power supply voltage signal. The first pull-down sub-circuit 51 is configured to pull down the potential of the first pull-down node PD1 via a low-level signal in response to the potential of the pull-up node PU. The second pull-down sub-circuit 52 is configured to pull down the potential of the second pull-down node PD2 via a low-level signal in response to the potential of the pull-up node PU. One of the two first auxiliary sub-circuits is configured to pull down the potential of the first pull-down node PD1 via a second scan signal in response to a first input signal during forward scanning; the other is configured to pull down the potential of the second pull-down node PD2 via a second scan signal in response to a first input signal. One of the two second auxiliary sub-circuits is configured to pull down the potential of the first pull-down node PD1 via a first scan signal in response to a second input signal during reverse scanning; the other is configured to pull down the potential of the second pull-down node PD2 via a first scan signal in response to a second input signal during reverse scanning.

[0075] In this embodiment, due to the addition of two first auxiliary sub-circuits and two second auxiliary sub-circuits, during forward scanning, the operation of the two first auxiliary sub-circuits can be controlled by the first input signal. Since the second scan signal is a low-level signal during forward scanning, the potentials of the first pull-down node PD1 and the second pull-down node PD2 can be pulled down by the second scan signal, thereby canceling the competition between the first pull-down node PD1 / second pull-down node PD2 and the pull-up node PU. Similarly, during reverse scanning, the operation of the two second auxiliary sub-circuits can be controlled by the second input signal. Since the first scan signal is a low-level signal during reverse scanning, the potentials of the first pull-down node PD1 and the second pull-down node PD2 can be pulled down by the first scan signal, thereby canceling the competition between the first pull-down node PD1 / second pull-down node PD2 and the pull-up node PU.

[0076] Continue to refer to Figure 2In this embodiment of the present disclosure, when the shift register is applied to the gate drive circuit, except for the first-stage shift register, the signal input terminal of the Nth-stage shift register is connected to the signal output terminal G(N-1) of the (N-1)th-stage shift register; except for the last-stage shift register, the pull-up reset signal terminal of the Nth-stage shift register is connected to the signal output terminal G(N+1) of the (N+1)th-stage shift register. N≥2, and N is an integer.

[0077] In some examples, continue to refer to Figure 2 The two first auxiliary sub-circuits have sixteenth transistors, denoted as M16A and M16B respectively. The source of M16A is connected to the first pull-down node PD1, the drain of M16A is connected to the second scan signal terminal VSD, and the gate of M16A is connected to the first input signal terminal. The source of M16B is connected to the second pull-down node PD2, the drain of M16B is connected to the second scan signal terminal VSD, and the gate of M16B is connected to the first input signal terminal.

[0078] Specifically, during forward scanning, the second scan signal written to the second scan signal terminal VSD is a low-level signal. When the first input signal is written to the first input signal terminal as a high-level signal, the first input sub-circuit 11 operates, pre-charging the pull-up node PU through the first scan signal. At the same time, since the first input signal is a high-level signal, M16A and M16B are turned on, and the potentials of the first pull-down node PD1 and the second pull-down node PD2 are pulled down through the low-level signal written to the second scan signal terminal VSD, thereby effectively avoiding the competition between the pull-up node PU and the first pull-down node PD1 / second pull-down node PD2.

[0079] In some examples, continue to refer to Figure 2 The two second auxiliary sub-circuits have fifteenth transistors, denoted as M15A and M15B respectively. The source of M15A is connected to the first pull-down node PD1, the drain of M15A is connected to the second scan signal terminal VSD, and the gate of M15A is connected to the first input signal terminal. The source of M15B is connected to the second pull-down node PD2, the drain of M15B is connected to the second scan signal terminal VSD, and the gate of M15B is connected to the first input signal terminal.

[0080] Specifically, during forward scanning, the second scan signal written to the first scan signal terminal VDS is a low-level signal. When the second input signal is written to the second input terminal as a high-level signal, the second input sub-circuit 12 operates, pre-charging the pull-up node PU through the second scan signal. At the same time, since the second input signal is a high-level signal, M15A and M15B are turned on, and the potentials of the first pull-down node PD1 and the second pull-down node PD2 are pulled down through the low-level signal written to the first scan signal terminal VDS, thereby effectively avoiding the competition between the pull-up node PU and the first pull-down node PD1 / second pull-down node PD2.

[0081] In some examples, continue to refer to Figure 2 The shift register also includes a global reset subcircuit 6. The global reset subcircuit 6 is configured to reset the pull-up node PU and the signal output terminal G(N) by a low-level signal in response to a global reset signal.

[0082] The global reset sub-circuit 6 includes a fourth transistor M4 and a seventh transistor M7. The source of M4 is connected to the pull-up node PU, the drain of M4 is connected to the low-level signal terminal VGL, and the gate of M4 is connected to the global reset signal terminal Total-Rest. The source of M7 is connected to the signal output terminal G(N), the drain of M7 is connected to the low-level signal terminal VGL, and the gate of M7 is connected to the global reset signal terminal Total-Rest.

[0083] Specifically, during the global reset phase, the global reset signal written to the global reset signal terminal Total-Rest is a high-level signal, and both the fourth transistor M4 and the seventh transistor M7 are turned on. At this time, the low-level signal written to the low-level signal terminal VGL resets the pull-up node PU through the fourth transistor M4 and resets the signal output terminal G(N) through the seventh transistor M7.

[0084] In some examples, continue to refer to Figure 2 The shift register also includes two first noise reduction sub-circuits and two second noise reduction sub-circuits. One of the two first noise reduction sub-circuits responds to the potential of the first pull-down node PD1 by using a low-level signal to reduce noise at the output of the pull-up node PU; the other responds to the potential of the second pull-down node PD2 by using a low-level signal to reduce noise at the output of the pull-up node PU. Similarly, one of the two second noise reduction sub-circuits responds to the potential of the first pull-down node PD1 by using a low-level signal to reduce noise at the output of the signal output terminal G(N); the other responds to the potential of the second pull-down node PD2 by using a low-level signal to reduce noise at the output of the signal output terminal G(N).

[0085] Each first noise reduction sub-circuit includes a tenth transistor, and each second noise reduction sub-circuit includes an eleventh transistor. The tenth transistors in the two first noise reduction sub-circuits are denoted as M10A and M10B, respectively; the eleventh transistors in the two second noise reduction sub-circuits are denoted as M11A and M11B, respectively. The source of M10A is connected to the pull-up node PU, the drain of M10A is connected to the low-level signal terminal VGL, and the gate of M10A is connected to the first pull-down node PD1. The source of M10B is connected to the pull-up node PU, the drain of M10B is connected to the low-level signal terminal VGL, and the gate of M10B is connected to the second pull-down node PD2. The source of M11A is connected to the signal output terminal G(N), the drain of M11A is connected to the low-level signal terminal VGL, and the gate of M11A is connected to the first pull-down node PD1. The source of M11B is connected to the signal output terminal G(N), the drain of M11B is connected to the low-level signal terminal VGL, and the gate of M11B is connected to the second pull-down node PD2.

[0086] Specifically, during the output noise reduction stage, when the potential of the first pull-down node PD1 is high, M10A and M11A are turned on, and the low-level signal written to the low-level signal terminal VGL pulls down the potential of the pull-up node PU and the signal output terminal G(N). When the potential of the second pull-down node PD2 is high, M10B and M11B are turned on, and the low-level signal written to the low-level signal terminal VGL pulls down the potential of the pull-up node PU and the signal output terminal G(N).

[0087] In some examples, the first input sub-circuit 11 includes a first transistor M1; the second input sub-circuit 12 includes a second transistor M2; wherein the source of M1 is connected to the first scan signal terminal VDS, the drain of M1 is connected to the pull-up node PU, and the gate of M1 is connected to the first signal input terminal. The source of M2 is connected to the second scan signal terminal VSD, the drain of M2 is connected to the pull-up node PU, and the gate of M2 is connected to the second signal input terminal.

[0088] Specifically, during the forward scan, in the input phase, the first input signal written to the first input signal terminal is a high-level signal, M1 is enabled, and the first scan signal written to the first scan signal terminal VDS is a high-level signal. At this time, the pull-up node PU is pre-charged through the first scan signal. In the pull-up reset phase, the second input signal written to the second input signal terminal is a high-level signal, M2 is enabled, and the second scan signal written to the second scan signal terminal VSD is a low-level signal. At this time, the pull-up node PU is discharged through the second scan signal, thereby resetting the pull-up node PU.

[0089] During reverse scanning, in the input phase, the second input signal written to the second input signal terminal is a high-level signal, M2 is enabled, and the second scan signal written to the second scan signal terminal VSD is a high-level signal. At this time, the pull-up node PU is pre-charged through the second scan signal. In the pull-up reset phase, the first input signal written to the first input signal terminal is a high-level signal, M1 is enabled, and the first scan signal written to the first scan signal terminal VDS is a low-level signal. At this time, the pull-up node PU is discharged through the first scan signal, thereby resetting the pull-up node PU.

[0090] In some examples, the output sub-circuit 3 includes a third transistor M3 and a storage capacitor C1; wherein, the source of M3 is connected to the clock signal terminal CLK, the drain of M3 is connected to the signal output terminal G(N), and the gate of M3 is connected to the pull-up node PU; the first end of C1 is connected to the pull-up node PU, and the second end of C1 is connected to the signal output terminal G(N).

[0091] Specifically, during the output phase, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M3 is fully turned on, and the clock signal written by the clock signal terminal CLK is a high-level signal during this phase. At this time, the signal output terminal G(N) outputs a high-level signal.

[0092] In some examples, both the first pull-down control subcircuit 41 and the second pull-down control subcircuit 42 include a fifth transistor and a ninth transistor. For ease of description, the fifth and ninth transistors in the first pull-down control subcircuit 41 are represented as M5A and M9A, respectively, and the fifth and ninth transistors in the second pull-down subcircuit 52 are represented as M5B and M9B, respectively. The source of M5A is connected to the first power supply voltage terminal VDDO, the drain of M5A is connected to the first pull-down node PD1, the gate of M5A is connected to the drain of M9A, and the source and gate of M9A are connected to the second power supply voltage terminal VDDE. The source of M5B is connected to the second power supply voltage terminal VDDE, the drain of M5B is connected to the second pull-down node PD2, the gate of M5B is connected to the drain of M9B, and the source and gate of M9B are connected to the second power supply voltage terminal VDDE.

[0093] Specifically, when the first power supply voltage terminal VDDO is written with the first power supply voltage, both M5A and M9A are turned on, and the potential of the first pull-down node PD1 is pulled high by the first power supply voltage, i.e., it is at a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, both MB5 and M9B are turned on, and the potential of the second pull-down node PD2 is pulled high by the second power supply voltage, i.e., it is at a high potential. It should be noted that the first power supply voltage and the second power supply voltage can be the same power supply voltage. In this embodiment of the disclosure, only the example of the first power supply voltage and the second power supply voltage being the same power supply voltage is described.

[0094] In some examples, both the first pull-down sub-circuit 51 and the second pull-down sub-circuit 52 include a sixth transistor and an eighth transistor. For ease of description, the sixth and eighth transistors in the first pull-down sub-circuit 51 are denoted as M6A and M8A, respectively, and the sixth and eighth transistors in the second pull-down sub-circuit 52 are denoted as M6B and M8B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M8A is connected to the drain of M9A and the gate of M5A, the drain of M8A is connected to the low-level signal terminal VGL, and the gate of M8A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU. The source of M8B is connected to the drain of M9B and the gate of M5B. The drain of M8B is connected to the low-level signal terminal VGL, and the gate of M8B is connected to the pull-up node PU.

[0095] Specifically, when the potential of the pull-up node PU is high, M6A / M6B / M8A / M8B are turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to low, ensuring that the pull-up node PU remains high for normal output.

[0096] To better understand the structure of the shift register in this embodiment, a detailed explanation will be provided in conjunction with the operation of the shift register.

[0097] For forward scan: Figure 3 for Figure 2 Timing diagram of the forward scan of the shift register; as shown Figure 3 As shown, the first scan signal written to the first scan signal terminal VDS is a continuous high-level signal, and the second scan signal written to the second scan signal terminal VSD is a continuous low-level signal.

[0098] Input phase: The first input signal written to the first input signal terminal is a high-level signal, the first scan signal written to the first scan signal terminal VDS is a high-level signal, and the second scan signal written to the second scan signal terminal VSD is a low-level signal. At this time, M1, M16A, and M16B are turned on, and the pull-up node PU is pre-charged through the first scan signal. Since M16A and M16B are turned on, the first pull-down node PD1 and the second pull-down node PD2 are pulled down to a low potential by the second scan signal, which can effectively avoid the potential competition between the pull-up node PU and the first pull-down node PD1 and the second pull-down node PD2.

[0099] Output Phase: Under the bootstrap effect of storage capacitor C1, the potential of pull-up node PU is further pulled high, transistor M3 is fully turned on, and the signal output terminal G(N) outputs the high potential of the clock signal written by the clock signal terminal CLK, that is, the signal output terminal G(N) outputs a high-level signal. At the same time, since the potential of pull-up node PU is high, M6A / M6B / M8A / M8B are turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled low, ensuring that pull-up node PU remains high.

[0100] Reset phase: The second input signal written to the second input signal terminal is a high-level signal, M2 is turned on, and the second scan signal written to the second scan signal terminal VSD is a low-level signal. At this time, the pull-up node PU is pulled down to a low level.

[0101] Output noise reduction stage: When the first power supply voltage VDDO is written with the first power supply voltage, both M5A and M9A are turned on. The potential of the first pull-down node PD1 is pulled high by the first power supply voltage, i.e., it is at a high potential. At this time, M10A and M11A are turned on, and the output of the pull-up node PU and the signal output terminal G(N) is pulled down by the low-level signal written by the low-level signal terminal VGL, so as to realize the output noise reduction of the pull-up node PU and the signal output terminal G(N). When the second power supply voltage VDDE is written with the second power supply voltage, both MB5 and M9B are turned on. The potential of the second pull-down node PD2 is pulled high by the second power supply voltage, i.e., it is at a high potential. At this time, M10B and M11B are turned on, and the output of the pull-up node PU and the signal output terminal G(N) is pulled down by the low-level signal written by the low-level signal terminal VGL, so as to realize the output noise reduction of the pull-up node PU and the signal output terminal G(N).

[0102] For reverse scan: Figure 4 for Figure 2 Timing diagram of the shift register reverse scan; as shown Figure 4 As shown, the second scan signal written by the second scan signal terminal VSD is a continuous high-level signal, and the first scan signal written by the first scan signal terminal VDS is a continuous low-level signal.

[0103] Input phase: The second input signal written to the second input signal terminal is a high-level signal, the second scan signal written to the second scan signal terminal VSD is a high-level signal, and the first scan signal written to the first scan signal terminal VDS is a low-level signal. At this time, M2, M15A and M15B are turned on, and the pull-up node PU is pre-charged through the first scan signal. Since M15A and M15B are turned on, the first pull-down node PD1 and the second pull-down node PD2 are pulled down to a low potential by the second scan signal, which can effectively avoid the potential competition between the pull-up node PU and the first pull-down node PD1 and the second pull-down node PD2.

[0104] Output Phase: Under the bootstrap effect of storage capacitor C1, the potential of pull-up node PU is further pulled high, transistor M3 is fully turned on, and the signal output terminal G(N) outputs the high potential of the clock signal written by the clock signal terminal CLK, that is, the signal output terminal G(N) outputs a high-level signal. At the same time, since the potential of pull-up node PU is high, M6A / M6B / M8A / M8B are turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled low, ensuring that pull-up node PU remains high.

[0105] Reset phase: The first input signal written to the first input signal terminal is a high-level signal, M1 is turned on, and the first scan signal written to the first scan signal terminal VDS is a low-level signal. At this time, the pull-up node PU is pulled down to a low level.

[0106] Output noise reduction stage: When the first power supply voltage VDDO is written with the first power supply voltage, both M5A and M9A are turned on. The potential of the first pull-down node PD1 is pulled high by the first power supply voltage, i.e., it is at a high potential. At this time, M10A and M11A are turned on, and the output of the pull-up node PU and the signal output terminal G(N) is pulled down by the low-level signal written by the low-level signal terminal VGL, so as to realize the output noise reduction of the pull-up node PU and the signal output terminal G(N). When the second power supply voltage VDDE is written with the second power supply voltage, both MB5 and M9B are turned on. The potential of the second pull-down node PD2 is pulled high by the second power supply voltage, i.e., it is at a high potential. At this time, M10B and M11B are turned on, and the output of the pull-up node PU and the signal output terminal G(N) is pulled down by the low-level signal written by the low-level signal terminal VGL, so as to realize the output noise reduction of the pull-up node PU and the signal output terminal G(N).

[0107] Second example: Figure 5 This is a circuit diagram of a shift register according to a second example of an embodiment of this disclosure; as shown below. Figure 5 As shown, the structure of the shift register in this example is roughly the same as that in the first example. The only difference is that the shift register in this example adds a cascaded sub-circuit to the shift register in the first example. The cascaded output sub-circuit 3 is configured to output the clock signal through the cascaded signal terminal in response to the potential of the pull-up node PU.

[0108] In some examples, the cascaded sub-circuit includes a thirteenth transistor M13, with the source of M13 connected to the clock signal terminal CLK, the drain of M13 connected to the cascaded signal terminal output_C(N), and the gate of M13 connected to the pull-up node PU.

[0109] Specifically, during the output phase, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M13 is fully turned on, and the clock signal written by the clock signal terminal CLK is a high-level signal during this phase. At this time, the cascade signal terminal output_C(N) outputs a high-level signal.

[0110] When the shift registers in the embodiments of this disclosure are applied to the gate drive circuit, except for the first-stage shift register, the signal input terminal of the Nth-stage shift register is connected to the cascaded signal terminal output_C(N-1) of the (N-1)th shift register; except for the last-stage shift register, the pull-up reset signal terminal of the Nth-stage shift register is connected to the cascaded signal terminal output_C(N+1) of the (N+1)th shift register. N≥2, and N is an integer.

[0111] In some examples, the shift register includes not only the structure described above, but also two third noise reduction sub-circuits. One of the third noise reduction sub-circuits is configured to pull down the output of the cascaded signal terminal by a low-level signal in response to the potential of the first pull-down node PD1. The other third noise reduction sub-circuit is configured to pull down the output of the cascaded signal terminal by a low-level signal in response to the potential of the second pull-down node PD2.

[0112] Among them, continue to refer to Figure 5 Both third noise reduction sub-circuits may include a twelfth transistor, denoted as M12A and M12B respectively; the source of M12A is connected to the cascaded signal terminal, the drain of M12A is connected to the low-level signal terminal VGL, and the gate of M12A is connected to the first pull-down node PD1. The source of M12B is connected to the cascaded signal terminal, the drain of M12B is connected to the low-level signal terminal VGL, and the gate of M12B is connected to the second pull-down node PD2.

[0113] Specifically, during the output noise reduction stage, when the first pull-down node PD1 is a high-level signal, M12A is turned on, and the low-level signal written to the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12A. When the second pull-down node PD2 is a high-level signal, M12B is turned on, and the low-level signal written to the low-level signal terminal VGL is output through the pull-down cascade signal terminal of M12B.

[0114] The other structures of the shift register in this example are the same as those in the first example, so they will not be repeated here.

[0115] The third example: Figure 6 This is a circuit diagram of a shift register according to a third example of an embodiment of this disclosure; as shown below. Figure 6As shown, the structure of the shift register in this example is roughly the same as that in the first example, except that the specific structures of the first pull-down control sub-circuit 41, the second pull-down control sub-circuit 42, the first pull-down sub-circuit 51, and the second pull-down sub-circuit 52 are different from those in the first example.

[0116] Specifically, in this example, the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 include a fifth transistor. For ease of description, the fifth transistors in the first pull-down control sub-circuit 41 and the second pull-down control sub-circuit 42 are represented by M5A and M5B, respectively. The gate and source of M5A are connected to the first power supply voltage terminal VDDO, and the drain of M5A is connected to the first pull-down node PD1. The gate and source of M5B are connected to the second power supply voltage terminal VDDE, and the drain of M5B is connected to the second pull-down node PD2.

[0117] Specifically, when the first power supply voltage terminal VDDO is written with the first power supply voltage, M5A is turned on, and the first pull-down node PD1 is at the potential of the first power supply voltage, i.e., a high potential. When the second power supply voltage terminal VDDE is written with the second power supply voltage, M5B is turned on, and the second pull-down node PD2 is at the potential of the second power supply voltage, i.e., a high potential.

[0118] In this example, both the first pull-down circuit 51 and the second pull-down circuit 52 include a sixth transistor. For ease of description, the sixth transistors in the first pull-down circuit 51 and the second pull-down circuit 52 are represented by M6A and M6B, respectively. The source of M6A is connected to the first pull-down node PD1, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU. The source of M6B is connected to the second pull-down node PD2, the drain of M6B is connected to the low-level signal terminal VGL, and the gate of M6B is connected to the pull-up node PU.

[0119] Specifically, when the potential of the pull-up node PU is high, M6A / M6B is turned on, and the first pull-down node PD1 and the second pull-down node PD2 are pulled to low level, ensuring that the pull-up node PU remains high and outputs normally.

[0120] The other structures of the shift register in this example are the same as those in the first example, so they will not be repeated here.

[0121] Fourth example: Figure 7 This is a circuit diagram of a shift register according to a fourth example of an embodiment of this disclosure; as shown below. Figure 7 As shown, the shift register includes a first input sub-circuit 11, a second input sub-circuit 12, a pull-down control sub-circuit 4, a pull-down sub-circuit 5, a first auxiliary sub-circuit, and a second auxiliary sub-circuit.

[0122] for Figure 7 The shift register in the circuit can achieve bidirectional scanning, i.e., forward scanning and reverse scanning. During forward scanning, the second input sub-circuit 12 acts as the pull-up reset sub-circuit 2, and during reverse scanning, the first input sub-circuit 11 acts as the pull-up reset sub-circuit 2. Specifically, the first input sub-circuit 11 is configured to pre-charge the pull-up node PU via the first scan signal in response to the first input signal. The second input sub-circuit 12 is configured to pre-charge the pull-up node PU via the second scan signal in response to the second input signal. The output sub-circuit 3 is configured to output the clock signal through the signal output terminal G(N) in response to the potential of the pull-up node PU. The pull-down control sub-circuit 4 is configured to control the potential of the pull-up node via the power supply voltage signal. The pull-down sub-circuit 5 is configured to pull down the potential of the pull-down node PD via a low-level signal in response to the potential of the pull-up node PU. The first auxiliary sub-circuit is configured to pull down the potential of the pull-down node PD via the second scan signal in response to the first input signal during forward scanning. The second auxiliary sub-circuit is configured to respond to the second input signal during reverse scanning by pulling down the potential of the node PD through the first scan signal.

[0123] In this embodiment, due to the addition of a first auxiliary sub-circuit and a second auxiliary sub-circuit, during forward scanning, the first auxiliary sub-circuit can be controlled to operate via the first input signal. Since the second scan signal is a low-level signal during forward scanning, the potential of the pull-down node PD can be pulled down via the second scan signal, thereby eliminating the competition between the pull-down node PD and the pull-up node PU. Similarly, during reverse scanning, the second auxiliary sub-circuit can be controlled to operate via the second input signal. Since the first scan signal is a low-level signal during reverse scanning, the potential of the pull-down node PD can be pulled down via the first scan signal, thereby eliminating the competition between the pull-down node PD and the pull-up node PU.

[0124] Continue to refer to Figure 7 In this embodiment of the present disclosure, when the shift register is applied to the gate drive circuit, except for the first-stage shift register, the signal input terminal of the Nth-stage shift register is connected to the signal output terminal G(N) of the (N-1)th-stage shift register; except for the last-stage shift register, the pull-up reset signal terminal of the Nth-stage shift register is connected to the signal output terminal G(N) of the (N+1)th-stage shift register. N≥2, and N is an integer.

[0125] In some examples, continue to refer to Figure 2 The first auxiliary sub-circuit contains the sixteenth transistor M16; wherein, the source of M16 is connected to the pull-down node PD, the drain of M16 is connected to the second scan signal terminal VSD, and the gate of M16 is connected to the first input signal terminal.

[0126] Specifically, during forward scanning, the second scan signal written to the second scan signal terminal VSD is a low-level signal. When the first input signal is written to the first input signal terminal as a high-level signal, the first input sub-circuit 11 operates, pre-charging the pull-up node PU through the first scan signal. At the same time, since the first input signal is a high-level signal, M16 is turned on, and the potential of the pull-down node PD is pulled down through the low-level signal written to the second scan signal terminal VSD, thereby effectively avoiding the competition between the pull-up node PU and the pull-down node PD.

[0127] In some examples, continue to refer to Figure 7 The fifteenth transistor M15 is in the second auxiliary sub-circuit; wherein, the source of M15 is connected to the pull-down node PD, the drain of M15 is connected to the second scan signal terminal VSD, and the gate of M15 is connected to the first input signal terminal.

[0128] Specifically, during forward scanning, the second scan signal written to the first scan signal terminal VDS is a low-level signal. When the second input signal is written to the second input terminal as a high-level signal, the second input sub-circuit 12 operates, pre-charging the pull-up node PU through the second scan signal. At the same time, since the second input signal is a high-level signal, M15 is turned on, and the potential of the pull-down node PD is pulled down through the low-level signal written to the first scan signal terminal VDS, thereby effectively avoiding the competition between the pull-up node PU and the pull-down node PD.

[0129] In some examples, continue to refer to Figure 7 The shift register also includes a global reset subcircuit 6. The global reset subcircuit 6 is configured to reset the pull-up node PU and the signal output terminal G(N) by a low-level signal in response to a global reset signal.

[0130] The global reset sub-circuit 6 includes a fourth transistor M4 and a seventh transistor M7. The source of M4 is connected to the pull-up node PU, the drain of M4 is connected to the low-level signal terminal VGL, and the gate of M4 is connected to the global reset signal terminal Total-Rest. The source of M7 is connected to the signal output terminal G(N), the drain of M7 is connected to the low-level signal terminal VGL, and the gate of M7 is connected to the global reset signal terminal Total-Rest.

[0131] Specifically, during the global reset phase, the global reset signal written to the global reset signal terminal Total-Rest is a high-level signal, and both the fourth transistor M4 and the seventh transistor M7 are turned on. At this time, the low-level signal written to the low-level signal terminal VGL resets the pull-up node PU through the fourth transistor M4 and resets the signal output terminal G(N) through the seventh transistor M7.

[0132] In some examples, continue to refer to Figure 2 The shift register also includes a first noise reduction sub-circuit and a second noise reduction sub-circuit. The first noise reduction sub-circuit responds to the potential of the pull-down node PD and reduces the noise of the output of the pull-up node PU by using a low-level signal. The second noise reduction sub-circuit responds to the potential of the pull-down node PD and reduces the noise of the output of the signal output terminal G(N) by using a low-level signal.

[0133] The first noise reduction sub-circuit includes a tenth transistor M10, and the second noise reduction sub-circuit includes an eleventh transistor M11. The source of M10 is connected to the pull-up node PU, the drain of M10 is connected to the low-level signal terminal VGL, and the gate of M10 is connected to the pull-down node PD. The source of M11 is connected to the signal output terminal G(N), the drain of M11 is connected to the low-level signal terminal VGL, and the gate of M11 is connected to the pull-down node PD.

[0134] Specifically, during the output noise reduction stage, when the potential of the first pull-down node PD1 is high, M10 and M11 are turned on, and the low-level signal written by the low-level signal terminal VGL pulls down the potential of the pull-up node PU and the signal output terminal G(N).

[0135] In some examples, the first input sub-circuit 11 includes a first transistor M1; the second input sub-circuit 12 includes a second transistor M2; wherein the source of M1 is connected to the first scan signal terminal VDS, the drain of M1 is connected to the pull-up node PU, and the gate of M1 is connected to the first signal input terminal. The source of M2 is connected to the second scan signal terminal VSD, the drain of M2 is connected to the pull-up node PU, and the gate of M2 is connected to the second signal input terminal.

[0136] Specifically, during the forward scan, in the input phase, the first input signal written to the first input signal terminal is a high-level signal, M1 is enabled, and the first scan signal written to the first scan signal terminal VDS is a high-level signal. At this time, the pull-up node PU is pre-charged through the first scan signal. In the pull-up reset phase, the second input signal written to the second input signal terminal is a high-level signal, M2 is enabled, and the second scan signal written to the second scan signal terminal VSD is a low-level signal. At this time, the pull-up node PU is discharged through the second scan signal, thereby resetting the pull-up node PU.

[0137] During reverse scanning, in the input phase, the second input signal written to the second input signal terminal is a high-level signal, M2 is enabled, and the second scan signal written to the second scan signal terminal VSD is a high-level signal. At this time, the pull-up node PU is pre-charged through the second scan signal. In the pull-up reset phase, the first input signal written to the first input signal terminal is a high-level signal, M1 is enabled, and the first scan signal written to the first scan signal terminal VDS is a low-level signal. At this time, the pull-up node PU is discharged through the first scan signal, thereby resetting the pull-up node PU.

[0138] In some examples, the output sub-circuit 3 includes a third transistor M3 and a storage capacitor C1; wherein, the source of M3 is connected to the clock signal terminal CLK, the drain of M3 is connected to the signal output terminal G(N), and the gate of M3 is connected to the pull-up node PU; the first end of C1 is connected to the pull-up node PU, and the second end of C1 is connected to the signal output terminal G(N).

[0139] Specifically, during the output phase, the potential of the pull-up node PU is pulled higher by the bootstrap of C1, M3 is fully turned on, and the clock signal written by the clock signal terminal CLK is a high-level signal during this phase. At this time, the signal output terminal G(N) outputs a high-level signal.

[0140] In some examples, the pull-down control subcircuit 4 includes a fifth transistor and a ninth transistor. The source of M5 is connected to the first power supply voltage terminal VDDO, the drain of M5 is connected to the pull-down node PD, the gate of M5 is connected to the drain of M9, and the source and gate of M9 are connected to the power supply voltage terminal GCH.

[0141] Specifically, when the power supply voltage signal is written to the power supply voltage terminal, both M5 and M9 are turned on, and the potential of the pull-down node PD is pulled high by the power supply voltage signal, that is, it is at a high potential.

[0142] In some instances, the pull-down sub-circuit 5 includes a sixth transistor and an eighth transistor. The source of M6 is connected to the pull-down node PD, the drain of M6 is connected to the low-level signal terminal VGL, and the gate of M6 is connected to the pull-up node PU. The source of M8 is connected to the drain of M9 and the gate of M5, the drain of M8 is connected to the low-level signal terminal VGL, and the gate of M8 is connected to the pull-up node PU.

[0143] Specifically, when the potential of the pull-up node PU is high, M6 / M8 is turned on, and the pull-down node PD is pulled low to ensure that the pull-up node PU remains high for normal output.

[0144] Fifth example: Figure 8 This is a circuit diagram of a shift register according to a fifth example of an embodiment of this disclosure; as follows: Figure 8As shown, the structure of the shift register in this example is roughly the same as that in the fourth example, except that the specific structures of the pull-down control sub-circuit 4 and pull-down sub-circuit 5 are different from those in the fourth example.

[0145] In some examples, specifically, in this example, the pull-down control sub-circuit 4 includes a fifth transistor M5; wherein the gate and source of M5 are connected to the power supply voltage terminal GCH, and the drain of M5 is connected to the pull-down node PD.

[0146] When a power supply voltage signal is written to the power supply voltage terminal, M5 is turned on, and the pull-down node PD is at the potential of the power supply voltage signal, i.e., a high potential.

[0147] In this example, the pull-down sub-circuit 5 includes a sixth transistor M6; wherein the source of M6 is connected to the pull-down node PD, the drain of M6A is connected to the low-level signal terminal VGL, and the gate of M6A is connected to the pull-up node PU.

[0148] Specifically, when the potential of the pull-up node PU is high, M6 is turned on, and the pull-down node PD is pulled low, ensuring that the pull-up node PU remains high for normal output.

[0149] The other structures of the shift register in this example are the same as those in the fourth example, so they will not be repeated here.

[0150] This disclosure also provides a gate driving circuit that includes a plurality of cascaded shift registers, wherein the shift registers can be any of the shift registers described above.

[0151] This disclosure provides a display device including the gate driving circuit described above.

[0152] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A shift register, comprising: A first input sub-circuit, a second input sub-circuit, an output sub-circuit, at least one pull-down control sub-circuit, and at least one pull-down circuit; The pull-down control sub-circuit is connected to the pull-down sub-circuit one by one, and the connection node is the pull-down node; The first input sub-circuit is configured to precharge the pull-up node via a first scan signal in response to the first input signal; The second input sub-circuit is configured to precharge the pull-up node via a second scan signal in response to a second input signal; The output sub-circuit is configured to output the clock signal via a signal output in response to the potential of the pull-up node; The pull-down control sub-circuit is configured to respond to a power supply voltage signal and control the potential of the corresponding pull-down node via the power supply voltage signal; The pull-down sub-circuit is configured to, in response to the potential of the pull-up node, pull down the potential of the corresponding pull-down node by a non-operating level signal; wherein... The shift register further includes at least one first auxiliary sub-circuit and at least one second auxiliary sub-circuit, wherein the first auxiliary sub-circuit and the second auxiliary sub-circuit are connected to the pull-down node in a one-to-one correspondence. The first auxiliary sub-circuit is configured to, in response to the first input signal, pull down the potential of the corresponding pull-down node via the second scan signal; The second auxiliary sub-circuit is configured to, in response to the second input signal, pull down the potential of the corresponding pull-down node via the first scan signal.

2. The shift register according to claim 1, wherein, The first auxiliary sub-circuit includes a sixteenth transistor; The first terminal of the sixteenth transistor is connected to the corresponding pull-down node, the second terminal is connected to the second scan signal terminal, and the control terminal is connected to the first input signal terminal.

3. The shift register according to claim 1, wherein, The second auxiliary sub-circuit includes a fifteenth transistor; The first terminal of the fifteenth transistor is connected to the corresponding pull-down node, the second terminal is connected to the first scan signal terminal, and the control terminal is connected to the second input signal terminal.

4. The shift register according to claim 1, wherein, It also includes a global reset sub-circuit, which, in response to a global reset signal, performs a global reset on the pull-up node and the signal output terminal through the non-working level signal.

5. The shift register according to claim 4, wherein, The global reset sub-circuit includes a fourth transistor and a seventh transistor; The first terminal of the fourth transistor is connected to the pull-up node, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the global reset signal terminal. The first terminal of the seventh transistor is connected to the signal output terminal, the second terminal is connected to the non-operating level signal terminal, and the control terminal is connected to the global reset signal terminal.

6. The shift register according to claim 1, wherein, It also includes at least one first noise reduction sub-circuit; the first noise reduction sub-circuit is configured to reduce the noise of the output of the pull-up node by a non-working level signal under the control of the corresponding pull-down node.

7. The shift register according to claim 6, wherein, The first noise reduction sub-circuit includes a tenth transistor; The first terminal of the tenth transistor is connected to the pull-up node, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the corresponding pull-down node.

8. The shift register according to claim 1, wherein, It also includes at least one second noise reduction sub-circuit; the second noise reduction sub-circuit is configured to reduce the noise of the output of the signal output terminal by means of a non-working level signal under the control of the corresponding pull-down node.

9. The shift register according to claim 8, wherein, The second noise reduction sub-circuit includes an eleventh transistor; The first terminal of the eleventh transistor is connected to the signal output terminal, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the corresponding pull-down node.

10. The shift register according to claim 1, wherein, It also includes cascaded sub-circuits configured to output a clock signal through the cascaded signal terminal in response to the potential of the pull-up node.

11. The shift register according to claim 10, wherein, The cascaded sub-circuit includes a thirteenth transistor; The first terminal of the thirteenth transistor is connected to the clock signal terminal, the second terminal is connected to the cascade signal terminal, and the control terminal is connected to the pull-up node.

12. The shift register according to claim 10, wherein, It also includes at least one third noise reduction sub-circuit; the third noise reduction sub-circuit is configured to reduce the noise of the output of the cascaded signal terminal by means of a non-working level signal under the control of the corresponding pull-down node.

13. The shift register according to claim 12, wherein, The third noise reduction sub-circuit includes a twelfth transistor; The first terminal of the twelfth transistor is connected to the cascaded signal terminal, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the corresponding pull-down node.

14. The shift register according to any one of claims 1-13, wherein, The first input sub-circuit includes a first transistor; The first terminal of the first transistor is connected to the first scan signal terminal, the second terminal is connected to the pull-up node, and the control terminals are all connected to the first input signal terminal.

15. The shift register according to any one of claims 1-13, wherein, The second input sub-circuit includes a second transistor; The first terminal of the second transistor is connected to the second scan signal terminal, the second terminal is connected to the pull-up node, and the control terminals are all connected to the second input signal terminal.

16. The shift register according to any one of claims 1-13, wherein, The output sub-circuit includes a third transistor and a storage capacitor; The first terminal of the third transistor is connected to the clock signal terminal, the second terminal is connected to the signal output terminal and the second terminal of the storage capacitor, and the control terminal is connected to the first terminal of the pull-up node and the first terminal of the storage capacitor.

17. The shift register according to any one of claims 1-13, wherein, The pull-up control sub-circuit includes a fifth transistor; The first and control terminals of the fifth transistor are connected to the power supply voltage terminal, and the second terminal is connected to the pull-down node.

18. The shift register according to any one of claims 1-13, wherein, The pull-down sub-circuit includes a sixth transistor; The first terminal of the sixth transistor is connected to the pull-down node, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the pull-up node.

19. The shift register according to any one of claims 1-13, wherein, The pull-up control sub-circuit includes a fifth transistor and a ninth transistor; The first terminal of the fifth transistor is connected to the first terminal of the ninth transistor, the control terminal of the ninth transistor, and the power supply voltage terminal, and the second terminal is connected to the pull-down node.

20. The shift register according to claim 19, wherein, The pull-down sub-circuit includes a sixth transistor and an eighth transistor; The first terminal of the sixth transistor is connected to the pull-down node, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the pull-up node; The first terminal of the eighth transistor is connected to the control terminal of the fifth transistor and the first terminal of the ninth transistor, the second terminal is connected to the non-working level signal terminal, and the control terminal is connected to the pull-up node.

21. A gate drive circuit comprising a plurality of cascaded shift registers, wherein the shift registers are any one of claims 1-20.

22. A display device comprising the gate driving circuit of claim 21.

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