Display panel and display driving method

Abstract

The application belongs to the technical field of display driving, and particularly relates to a display panel and a display driving method, the display panel comprising 2N rows of scanning lines and M columns of pixel columns, the pixel column comprising a data line, 2N rows of pixel units and N rows of control units; a 2n-1th row of pixel units and a 2nth row of pixel units are connected in series, one of the 2n-1th row of pixel units and the 2nth row of pixel units is connected with the data line, and the other is connected with an nth row of control units; wherein the nth row of control units are used for charging the pixel unit connected with the control unit by dividing the data voltage on the data line by a preset gray scale voltage in a normal display stage of a frame of picture, and are also used for charging the 2n-1th row of pixel units and the 2nth row of pixel units by the preset gray scale voltage in a black insertion stage of a frame of picture; the application solves the problem that the refresh rate is reduced when black insertion is implemented in the related art.

Description

Technical Field

[0001] This disclosure belongs to the field of display driver technology, specifically relating to a display panel and a display driving method. Background Technology

[0002] In the field of display technology, dynamic image clarity and viewing angle are core indicators for evaluating display performance. However, the liquid crystal molecules in liquid crystal displays have a response delay, which can easily cause ghosting in fast-moving images. To improve this problem, self-insertion black frame display technology has been proposed. Its core principle is to split the original frame into display frames and black frames. By integrating brightness in the time domain, the black frames are used to eliminate the visual persistence effect of the human eye, providing visual zeroing for the next frame, thereby improving the clarity of dynamic display.

[0003] Current self-insertion black display technology typically uses alternating output of display frames and black frames. However, this method results in a halving of the effective frames, which is equivalent to reducing the panel refresh rate and affecting the continuity of the image.

[0004] Therefore, how to achieve black insertion without reducing the panel refresh rate is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a display panel and a display driver method, which solves the problem that the refresh rate is reduced when black bars are inserted in the related technology.

[0006] In a first aspect, this application provides a display panel, the display panel including 2N rows of scan lines and M columns of pixels, the pixel column including: data lines, 2N rows of pixel units and N rows of control units; the (2n-1)th row of pixel units and the 2nth row of pixel units are connected in series, one of the pixel units of the (2n-1)th row of pixel units and the 2nth row of pixel units is connected to the data lines, and the other pixel unit is connected to the nth row of control units, and the other pixel unit and the nth row of control units are connected to the same scan line; wherein, the nth row of control units is used to charge the pixel units connected to the control unit by dividing the data voltage on the data lines by a preset grayscale voltage during the normal display stage of a frame, and is also used to charge the (2n-1)th row of pixel units and the 2nth row of pixel units simultaneously by the preset grayscale voltage during the black insertion stage of a frame, where N is a positive integer greater than 1, and n = [1, 2, 3, ..., N].

[0007] Optionally, the control terminal of the (2n-1)th row pixel unit is connected to the (2n-1)th row scan line, and the first end of the (2n-1)th row pixel unit is connected to the data line; the control terminal of the 2nth row pixel unit is connected to the 2nth row scan line, and the first end of the 2nth row pixel unit is connected to the second end of the (2n-1)th row pixel unit; the control terminal of the nth row control unit is connected to the 2nth row scan line, and the first end of the nth row control unit is connected to the second end of the 2nth row pixel unit, and the second end of the nth row control unit is connected to a preset voltage terminal.

[0008] Optionally, the control terminal of the (2n-1)th row pixel unit is connected to the (2n-1)th row scan line; the control terminal of the nth row control unit is connected to the (2n-1)th row scan line, the first terminal of the nth row control unit is connected to the second terminal of the (2n-1)th row pixel unit, and the second terminal of the nth row control unit is connected to a preset voltage terminal; the control terminal of the 2nth row pixel unit is connected to the 2nth row scan line, the first terminal of the 2nth row pixel unit is connected to the data line, and the second terminal of the 2nth row pixel unit is connected to the first terminal of the (2n-1)th row pixel unit.

[0009] Optionally, in the m-th pixel column, the pixel unit in the (2n-1)-th row is connected to the n-th row control unit; in the (m+1)-th pixel column, the pixel unit in the 2n-th row is connected to the n-th row control unit; or, in the m-th pixel column, the pixel unit in the 2n-th row is connected to the n-th row control unit; in the (m+1)-th pixel column, the pixel unit in the (2n-1)-th row is connected to the n-th row control unit.

[0010] Optionally, the pixel unit includes: a pixel transistor, wherein the control terminal of the pixel transistor serves as the control terminal of the pixel unit, the first terminal of the pixel transistor serves as the first terminal of the pixel unit, and the second terminal of the pixel transistor serves as the second terminal of the pixel unit; and a liquid crystal capacitor, wherein the upper plate of the liquid crystal capacitor is connected to the second terminal of the pixel transistor, and the lower plate of the liquid crystal capacitor is connected to a first common voltage terminal. The control unit includes: a control transistor, wherein the control terminal of the control transistor serves as the control terminal of the control unit, the first terminal of the control transistor serves as the first terminal of the control unit, and the second terminal of the control transistor serves as the second terminal of the control unit.

[0011] Optionally, for the pixel transistor connected to the control transistor, under the action of the gate drive signal on the scan line, the pixel transistor and the control transistor have an internal resistance ratio.

[0012] Optionally, the display panel further includes: a gate driving circuit; the gate driving circuit includes a black insertion control line, a frame start signal line, 2N cascaded driving circuit units, and a switching transistor; the control terminal of the switching transistor is connected to the black insertion control line, the first terminal of the switching transistor is connected to the frame start signal line, and the second terminal of the switching transistor is connected to a first-stage driving circuit unit or a second-stage driving circuit unit; wherein, during the black insertion stage, the black insertion control line controls the switching transistor to disconnect.

[0013] Secondly, this application provides a display driving method, which includes: during a normal display phase, controlling two adjacent rows of pixel units and a control unit to be in a conducting state, so that a preset grayscale voltage divides the data voltage on the data line and then charges the pixel units connected to the control unit; during a black insertion phase, controlling the pixel units connected to the data line to be in a disconnected state, while controlling the pixel units connected to the control unit and the control unit to be in a conducting state, so that the preset grayscale voltage charges the two adjacent rows of pixel units.

[0014] Optionally, during the normal display phase, after controlling two adjacent rows of pixel units and the control unit to be in a conducting state, the method further includes: driving the control unit to be in a disconnected state, controlling the pixel units connected to the data line to be in a conducting state, so that the data voltage on the data line charges the pixel units connected to the data line.

[0015] Optionally, when the display panel further includes a gate driving circuit, and the gate driving circuit includes a black insertion control line, a frame start signal line, 2N cascaded driving circuit units and a switching transistor, controlling the pixel unit connected to the data line to be in a disconnected state includes: controlling the switching transistor to be in a disconnected state through the black insertion control line, so that the first-stage driving circuit unit or the second-stage driving circuit unit disconnects from the frame start signal line, causing the odd-numbered driving circuit unit or the even-numbered driving circuit unit to stop outputting the gate driving signal.

[0016] The technical solution provided in this application has at least the following beneficial effects: 1. This application charges adjacent rows of pixel units in series, and during the normal display phase of a frame, the control unit divides the preset grayscale voltage to the data voltage on the data line and then charges the pixel units connected to the control unit. Then, the data voltage on the data line charges the pixel units connected to the data line, so that adjacent rows of pixel units have a difference in brightness. In space, the image is divided into two brightness levels and mixed to simulate an 8-domain effect, thereby improving the viewing angle of the panel.

[0017] 2. This application uses a control unit to charge the adjacent two rows of pixel units simultaneously with a preset grayscale voltage during the black insertion phase of a frame, so that both normal and black insertion frames can be displayed in a frame without reducing the refresh rate of the panel. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0019] Figure 1 The diagram shown is a structural schematic of the first type of display panel provided in this application embodiment.

[0020] Figure 2 The diagram shown is a structural schematic of a second type of display panel provided in an embodiment of this application.

[0021] Figure 3 The diagram shown is a structural schematic of a third type of display panel provided in an embodiment of this application.

[0022] Figure 4 The diagram shown is a circuit diagram of the first type of display panel provided in an embodiment of this application.

[0023] Figure 5 The diagram shown is a circuit diagram of a second type of display panel provided in an embodiment of this application.

[0024] Figure 6 The diagram shown is a circuit diagram of a third type of display panel provided in an embodiment of this application.

[0025] Figure 7 The diagram shown is a schematic diagram of a gate driving circuit provided in an embodiment of this application.

[0026] Figure 8 The diagram shown is a flowchart of a display driving method provided in an embodiment of this application.

[0027] Figure 9 The figure shown is a timing diagram of a normal display stage provided in an embodiment of this application.

[0028] Figure 10 The figure shown is a timing diagram of a black insertion stage provided in an embodiment of this application.

[0029] Figure 11 The figure shown is a timing diagram of a DLG mode provided in an embodiment of this application.

[0030] Explanation of reference numerals in the attached figures: 100. Display panel; 110. Scan line; 120. Pixel column; 121. Data line; 122. Pixel unit; 123. Control unit; 130. Gate drive circuit; X. Black insertion control line; STV. Frame start signal line; 131. Drive circuit unit; T0. Switching transistor; T1. First transistor; T2. Second transistor; T3. Third transistor; C1. First capacitor; C2. Second capacitor; C3. Third capacitor; C4. Fourth capacitor. Detailed Implementation

[0031] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0032] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0033] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0034] In a first aspect, this application provides a display panel, specifically including the following embodiments: Figure 1 The diagram shown is a structural schematic of the first type of display panel provided in this application embodiment; Figure 2 The diagram shown is a structural schematic of a second type of display panel provided in an embodiment of this application; as shown Figure 1 and Figure 2 As shown, the display panel 100 includes: 2N rows of scan lines 110 and M columns of pixels 120. Each column of pixels 120 includes one data line 121, 2N rows of pixel units 122, and N rows of control units 123. Figure 1 and Figure 2 Scan line 110 and data line 121 cross but are not connected. Figure 1 and Figure 2 In the table, G1, G2, G3, and G4 represent the first row scan line 110, the second row scan line 110, the third row scan line 110, and the fourth row scan line 110, respectively. S1, S2, S3, and S4 represent the first column data line 121, the second column data line 121, the third column data line 121, and the fourth column data line 121, respectively.

[0035] In one embodiment, the pixel units 122 in the (2n-1)th row and the pixel units 122 in the 2nth row are connected in series. One pixel unit 122 in the (2n-1)th row and the pixel unit 122 in the 2nth row are connected to the data line 121, and the other pixel unit 122 is connected to the control unit 123 in the nth row. The other pixel unit 122 and the control unit 123 in the nth row are connected to the same scan line 110. That is, two adjacent rows of pixel units 122 in the vertical direction are connected in series, the data line 121 is electrically connected to one of the pixel units 122, and the control unit 123 is electrically connected to the other pixel unit 122. Specifically, this includes the following two cases: (1) such as Figure 1 As shown, the control terminal of the (2n-1)th row pixel unit 122 is connected to the (2n-1)th row scan line 110, and the first end of the (2n-1)th row pixel unit 122 is connected to the data line 121; the control terminal of the 2nth row pixel unit 122 is connected to the 2nth row scan line 110, and the first end of the 2nth row pixel unit 122 is connected to the second end of the (2n-1)th row pixel unit 122; the control terminal of the nth row control unit 123 is connected to the 2nth row scan line 110, the first end of the nth row control unit 123 is connected to the second end of the 2nth row pixel unit 122, and the second end of the nth row control unit 123 is connected to the preset voltage terminal. Taking n=1 as an example: the control terminal of the first row pixel unit 122 is connected to the first scan line 110, the first end of the first row pixel unit 122 is connected to the first column data line 121, the second end of the first row pixel unit 122 is connected to the first end of the second row pixel unit 122, the second end of the second row pixel unit 122 is connected to the first end of the control unit 123, the control terminal of the second pixel unit 122 is connected to the second row scan line 110, the control terminal of the control unit 123 is connected to the second row scan line 110, and the second end of the control unit 123 is connected to the preset voltage terminal.

[0036] (2) For example Figure 2As shown, the control terminal of the (2n-1)th row pixel unit 122 is connected to the (2n-1)th row scan line 110; the control terminal of the nth row control unit 123 is connected to the (2n-1)th row scan line 110, the first terminal of the nth row control unit 123 is connected to the second terminal of the (2n-1)th row pixel unit 122, and the second terminal of the nth row control unit 123 is connected to the preset voltage terminal; the control terminal of the 2nth row pixel unit 122 is connected to the 2nth row scan line 110, the first terminal of the 2nth row pixel unit 122 is connected to the data line 121, and the second terminal of the 2nth row pixel unit 122 is connected to the first terminal of the (2n-1)th row pixel unit 122. Taking n=1 as an example: the control terminal of the first row pixel unit 122 is connected to the first scan line 110, the first end of the first row pixel unit 122 is connected to the second end of the second row pixel unit 122, the second end of the first row pixel unit 122 is connected to the first end of the control unit 123, the control terminal of the second row pixel unit 122 is connected to the second scan line 110, and the first end of the second row pixel unit 122 is connected to the data line 121.

[0037] exist Figure 1 and Figure 2 In the embodiment shown, the nth row control unit 123 is used to charge another pixel unit 122 by dividing the data voltage on the data line 121 with a preset gray level voltage during the normal display phase, and is also used to charge the 2n-1th row pixel unit 122 and the 2nth row pixel unit 122 simultaneously with a preset gray level voltage during the black insertion phase; where N is a positive integer greater than 1, n=[1,2,3,…,N], and the preset gray level voltage is 0 gray level voltage.

[0038] It should be noted that the control unit 123 in this embodiment has a voltage divider function during the normal display phase and a function of providing a 0 grayscale voltage during the black level insertion phase; the specific control process is as follows: (1) During the normal display phase, first charge another pixel unit 122 connected to the control unit 123, then charge another pixel unit 122 connected to the data line 121; Figure 1Taking the first row of pixel units 122 and the second row of pixel units 122 as an example: First, the data voltage corresponding to the second row of pixel units 122 is output on the first column of data lines 121. At the same time, the first row of scan lines 110 and the second row of scan lines 110 simultaneously turn on the first row of pixel units 122, the second row of pixel units 122 and the control unit 123. At this time, the control unit 123 divides the data voltage on the data line 121 by a preset grayscale voltage and then charges the second row of pixel units 122. At this time, the charging voltage is less than the data voltage. For example, the data voltage of the second row of pixel units 122 is a grayscale voltage of 100, and the actual charging voltage after being divided by the control unit 123 is a grayscale voltage of 80. Then, the second row of scan lines 110 is turned off, causing the second row of pixel units 122 and control unit 123 to turn off simultaneously. At this time, the first row of scan lines 110 is still turned on, so that the data voltage corresponding to the first row of pixel units 122 output on the data line 121 charges the first row of pixel units 122. Similarly, other interconnected pixel units 122 in this embodiment are also charged in this manner, thereby achieving the technical effect of a wide viewing angle.

[0039] (2) During the black pixel insertion phase, the pixel unit 122 connected to the data line 121 is turned off, and the control unit 123 and the pixel unit 122 connected to the control unit 123 are turned on, so that the control unit 123 charges the two pixel units 122 connected in series simultaneously through the preset grayscale voltage, thereby achieving black pixel insertion; continue with Figure 1 Taking the first row of pixel units 122 and the second row of pixel units 122 as an example: First, the first row of scan lines 110 is closed and the second row of scan lines 110 is open, so that the data voltage on the data line 121 cannot charge the first row of pixel units 122 and the second row of pixel units 122; at the same time, since the second row of scan lines 110 is open, the open control unit 123 charges the second row of pixel units 122 through the 0 grayscale voltage, and the 0 grayscale voltage then charges the first row of pixel units 122 through the open second row of pixel units 122, thereby realizing black insertion of the display screen.

[0040] In this embodiment, both the normal display phase and the black-insertion phase belong to one frame of display. That is to say, in one frame of display, the first half of the frame can display the normal image, and the second half of the frame can display the black-insertion image. This allows for a wide viewing angle when displaying the normal image, and does not affect the refresh rate when displaying the black-insertion image.

[0041] In summary, the display panel 100 provided in this application has at least the following beneficial effects: 1. This application charges two adjacent rows of pixel units 122 in series, and during the normal display phase of a frame, the control unit 123 divides the data voltage on the data line using a preset grayscale voltage and then charges the pixel units 122 connected to the control unit 123. Then, the data voltage on the data line 121 charges the pixel units 122 connected to the data line 121, so that the two adjacent rows of pixel units 122 have a difference in brightness. This spatially splits the image into two brightness levels and mixes them to simulate an 8-domain effect, thereby improving the viewing angle of the panel.

[0042] 2. This application uses the control unit 123 to charge the adjacent two rows of pixel units 122 simultaneously with the preset grayscale voltage during the black insertion stage of a frame, so that both normal and black insertion frames can be displayed in a frame, thus without reducing the refresh rate of the panel.

[0043] Figure 3 The diagram shown is a structural schematic of a third type of display panel provided in an embodiment of this application; as shown Figure 3 As shown, in the m-th pixel column 120, the pixel unit 122 in the (2n-1)-th row is connected to the control unit 123 in the n-th row; in the m+1-th pixel column 120, the pixel unit 122 in the 2n-th row is connected to the control unit 123 in the n-th row. That is, in the first pixel column 120, the first row pixel unit 122 is connected to the control unit 123, and the second row pixel unit 122 is connected to the data line 121; in the second pixel column 120, the first row pixel unit 122 is connected to the data line 121, and the second row pixel unit 122 is connected to the control unit 123; m=[1, 2, 3, ..., M].

[0044] Conversely, in another embodiment: in the m-th pixel column 120, the 2n-th row pixel unit 122 and the n-th row control unit 123, and in the m+1-th pixel column 120, the 2n-1-th row pixel unit 122 and the n-th row control unit 123.

[0045] This embodiment arranges the pixel architecture in a scattered manner to avoid the problem of faint bright and dark lines appearing in odd pixel rows, thereby improving the uniformity of the displayed image.

[0046] In one embodiment, the pixel unit 122 includes a pixel transistor and a liquid crystal capacitor; the control terminal of the pixel transistor serves as the control terminal of the pixel unit 122, the first terminal of the pixel transistor serves as the first terminal of the pixel unit 122, and the second terminal of the pixel transistor serves as the second terminal of the pixel unit 122; the upper plate of the liquid crystal capacitor is connected to the second terminal of the pixel transistor, and the lower plate of the liquid crystal capacitor is connected to the first common voltage terminal.

[0047] In one embodiment, the control unit 123 includes: a control transistor, wherein the control terminal of the control transistor serves as the control terminal of the control unit 123, the first terminal of the control transistor serves as the first terminal of the control unit 123, and the second terminal of the control transistor serves as the second terminal of the control unit 123.

[0048] Figure 4 The diagram shown is a circuit diagram of the first type of display panel provided in this application embodiment. Figure 5 The diagram shown is a circuit diagram of a second type of display panel provided in an embodiment of this application. Figure 6 The diagram shown is a circuit diagram of a third type of display panel provided in an embodiment of this application; wherein, Figure 4 The circuit diagram and Figure 1 Corresponding to the structural diagram, Figure 5 The circuit diagram and Figure 2 Corresponding to the structural diagram, Figure 6 The circuit diagram and Figure 3 The structural diagram corresponds to this.

[0049] In another embodiment, such as Figure 4 , Figure 5 and Figure 6 As shown, the pixel unit 122 also includes a storage capacitor. The upper plate of the storage capacitor is connected to the second terminal of the pixel transistor, and the lower plate of the storage capacitor is connected to the second common voltage terminal. The second common voltage terminal and the first common voltage terminal can be the same voltage terminal or different voltage terminals.

[0050] It should be noted that, in order to clearly distinguish the correspondence between the pixel transistors, liquid crystal capacitors, and storage capacitors in different rows of pixel units 122, the following will be used here: Figure 4 , Figure 5 and Figure 6 The pixel transistors, control transistors, storage capacitors, and liquid crystal capacitors are redefined as follows: the pixel transistor connected to data line 121 is defined as the first transistor T1; the pixel transistor connected to control unit 123 is defined as the second transistor T2; the control transistor is defined as the third transistor T3; the liquid crystal capacitor and storage capacitor connected to the first transistor T1 are defined as the first capacitor C1 and the second capacitor C2, respectively; and the liquid crystal capacitor and storage capacitor connected to the second transistor T2 are defined as the third capacitor C3 and the fourth capacitor C4, respectively. Additionally, Figure 4 , Figure 5 and Figure 6 In this context, Vcom is defined as the first common voltage terminal, AVcom is defined as the second common voltage terminal, and DVcom is defined as the preset voltage terminal.

[0051] In one embodiment, for the pixel transistor connected to the control transistor, under the action of the gate drive signal on scan line 110, the pixel transistor and the control transistor have an internal resistance ratio; that is, the pixel transistor and the control transistor have different turn-on voltages, and under the action of the gate drive signal, both the control transistor and the pixel transistor connected to the control transistor are in a partially turned-on state, thus having a certain internal resistance ratio; optionally, the internal resistance ratio of the pixel transistor to the control transistor can be 1:4, or it can be set according to the actual application scenario. In addition, the pixel transistor connected to the data line 121 is in a fully turned-on state under the action of the gate drive signal, and its internal resistance can be ignored.

[0052] Figure 7 The diagram shown is a schematic representation of a gate driving circuit according to an embodiment of this application; the display panel 100 of this embodiment also includes a gate driving circuit 130, as shown... Figure 7 As shown, the gate drive circuit 130 includes: a black insertion control line X, a frame start signal line STV, 2N cascaded drive circuit units 131, and a switching transistor T0.

[0053] Specifically, the control terminal of the switching transistor T0 is connected to the black insertion control line X, the first terminal of the switching transistor T0 is connected to the frame start signal line STV, and the second terminal of the switching transistor T0 is connected to the first-stage driving circuit unit or the second-stage driving circuit unit.

[0054] In one embodiment, during the normal display phase, the black insertion control line X controls the switch transistor T0 to close, so that the first-stage driving circuit unit 131 is electrically connected to the frame start signal line STV, and the second-stage driving circuit unit 131 is also electrically connected to the frame start signal line STV; during the black insertion phase, the black insertion control line X controls the switch transistor T0 to open, so that either the first-stage driving circuit unit 131 or the second-stage driving circuit unit 131 is disconnected from the frame start signal line STV, thereby preventing the voltage on the data line 121 from charging the pixel units 122 in the even-numbered rows or odd-numbered rows during the black insertion phase.

[0055] In one embodiment, the gate driving circuit 130 further includes multiple clock signal lines, and each driving circuit unit 131 is electrically connected to one clock signal line, so that the driving circuit unit 131 generates a gate driving signal according to the clock signal on the clock signal line.

[0056] Secondly, this application provides a display driving method applied to the display panel shown in the above embodiments, specifically including the following embodiments: Figure 8 The diagram shown is a flowchart illustrating a display driving method provided in an embodiment of this application; as follows: Figure 8As shown, the specific steps include: Step S100: During the normal display phase, control the adjacent two rows of pixel units and the control unit to be in the conducting state, so that the preset gray level voltage divides the data voltage on the data line and then charges the pixel unit connected to the control unit.

[0057] Step S200: During the black insertion stage, the pixel unit connected to the data line is in a disconnected state, while the pixel unit connected to the control unit and the control unit are in a conducting state, and the adjacent two rows of pixel units are charged by a preset grayscale voltage.

[0058] In one embodiment, during the normal display phase, after controlling two adjacent rows of pixel units 122 and the control unit to be in a conducting state, the method further includes: driving the control unit 123 to be in a disconnected state, controlling the pixel unit 122 connected to the data line 121 to be in a conducting state, so that the data voltage on the data line 121 charges the pixel unit 122 connected to the data line 121.

[0059] In one embodiment, when the display panel 100 further includes a gate driving circuit 130, the gate driving circuit 130 includes a black insertion control line X, a frame start signal line STV, 2N cascaded driving circuit units 131 and a switching transistor T0, controlling the pixel unit 122 connected to the data line 121 to be in an open state includes: controlling the switching transistor T0 to be in an open state through the black insertion control line X, so that the first-level driving circuit unit 131 or the second-level driving circuit unit 131 disconnects from the frame start signal line STV, causing the odd-numbered driving circuit unit 131 or the even-numbered driving circuit unit 131 to stop outputting the gate driving signal.

[0060] It should be noted that, Figure 9 The figure shown is a timing diagram of a normal display stage provided in an embodiment of this application. Figure 10 The diagram shown is a timing illustration of a black insertion stage provided in an embodiment of this application; wherein, Figure 9 and Figure 10 They are respectively Figure 5 The corresponding work sequence; here, combined with Figure 9 and Figure 10 right Figure 5 The driving method of the display panel 100 shown is explained below: (1) During the normal display phase, data line 121 needs to charge the third capacitor C3 and the fourth capacitor C4, which must pass through the first transistor T1 and the second transistor T2. If the first capacitor C1 and the second capacitor C2 are charged first, and then the third capacitor C3 and the fourth capacitor C4 are charged, then the voltage of the first capacitor C1 and the second capacitor C2 will be overwritten by the charging voltage of the third capacitor C3 and the fourth capacitor C4. Therefore, data line 121 can only charge the third capacitor C3 and the fourth capacitor C4 first. In order to keep the first capacitor C1 and the second capacitor C2 in the correct position after charging, the first row scan line G1 should control the second transistor T2 and the third transistor T3 to turn off first. As for turning them on, the first row scan line G1 can be turned on first or simultaneously with the second row scan line G2. For the sake of simplification of the front-end driver, the high-level time of the first row scan line G1 and the second row scan line G2 is the same, so the first row scan line G1 can be turned on first. Figure 9 As shown, in the first scan line G1, the second transistor T2 is not fully turned on, and the third transistor T3 is weakly turned on. The fourth capacitor C4, the third capacitor C3, the second capacitor C2, and the first capacitor C1 are charged through the preset voltage terminal DVcom. After one line of time, in... Figure 9At time t3, the second scan line G2 turns on the first transistor T1, and the voltage on the first line of data is Vcom, which is close to the preset voltage terminal DVcom, and it is also in the pre-charging stage. At time t4, the first line of grayscale voltage officially arrives, and the first capacitor C1, the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 begin to charge. The left side of the third transistor T3 will be the grayscale voltage, and the right side of the third transistor T3 will be the preset voltage terminal DVcom. The channel resistance of the third transistor T3 is relatively large when it is weakly turned on, and a certain current will still flow through it. Then, the first scan line G1 turns off the second transistor T2 and the third transistor T3 at time t6, and the first line of charging ends. (t6 to t7 is because there is a delay in the switching of signals such as the first scan line G1 of all the displays. Before turning them off, the Sn voltage must be kept constant. t4 to t7 is the time for a whole line, but the actual charging time t4 to t6 is less than a line. Therefore, the time from t6 to t7 is the time to prevent incorrect charging.) The second row has already been pre-charged with the earliest Vcom voltage, and then the first row voltage has been pre-charged. At time t7, when the second row grayscale voltage arrives on Sn, it charges the first capacitor C1 and the second capacitor C2, covering the grayscale voltage of the first row, and simultaneously pre-charges the next two rows. It should be noted that the number of rows pre-charged corresponds to the number of rows where the gate drive signal Gn is high. After charging is complete, the second row scan line G2 is turned off. The charging process for other rows is similar, and will not be elaborated here. The frame start signal line STV outputs the frame start signal. Only when the frame start signal line STV outputs a high level can the first row scan line G1 and the second row scan line G2 rise in voltage and turn on. Then, G3 must be during the high level time of the first row scan line G1, and G4 must be during the high level time of the second row scan line G2. Odd rows transmit the next row, even rows transmit the next row, and so on.

[0061] (2) During the black insertion phase, a switching transistor T0 is added to the path from the frame start signal line STV to the second-stage drive circuit unit 131 (wherein, the first-stage drive circuit unit 131 is always directly connected to the frame start signal line STV). When the black insertion control line X outputs a high level, the frame start signal line can simultaneously start the first row scan line G1 and the second row scan line G2. When the black insertion control line X outputs a low level, the frame start signal line can only start the first row scan line G1. For example, when the black insertion time is 1:1 with the display time, the first row scan line G1 is started with the frame start control line X outputting a low level. Figure 9 When progressive scan display is normally enabled, the black control line X outputs a high level. If the display is FHD and the total number of lines per frame is 1100, then when progressive scan displays up to line 550, the black control line X outputs a low level, the frame start signal line STV is enabled again, and then the first scan line G1 is enabled, while the second scan line G2 is disabled. Figure 9 As shown, since the preset voltage terminal DVcom corresponds to the DC voltage of the black screen, there is no issue of switching the voltage between different lines when inserting black screen; the entire first line scan line G1 is at a high level. Figure 10 From t2 to t4, the time is for charging. There is no pre-charging or anti-mischarging issue. Even if the third transistor T3 is not fully turned on, the time is long enough for the first transistor T1 to be completely turned off and the second transistor T2 to be partially turned on. The first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 will eventually be charged to the black screen voltage output by the preset voltage terminal DVcom. The first two lines are inserted into black simultaneously, and the next lines are inserted into black in the same way until the next frame is recharged, and the cycle repeats.

[0062] This embodiment also supports DLG (Dual Line Gate) displays, such as... Figure 11 As shown, the first row of scan lines G1 and the second row of scan lines G2 are simultaneously turned on and off to achieve refresh rate multiplication display; optionally, in DLG mode, when performing black insertion and normal display, respectively, they are paired with Figure 9 and Figure 10 The driver timing is sufficient, so I won't go into details here.

[0063] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0064] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0065] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A display panel, the display panel comprising 2N rows of scan lines and M columns of pixels, characterized in that, The pixel column includes: Data cable, 2N rows of pixel units, and N rows of control units; The pixel units in rows 2n-1 and 2n are connected in series. One pixel unit in row 2n-1 and row 2n is connected to the data line, and the other pixel unit is connected to the control unit in row n. The other pixel unit and the control unit in row n are connected to the same scan line. The control terminal of the pixel unit in row 2n-1 is connected to the scan line in row 2n-1, and the first end of the pixel unit in row 2n-1 is connected to the data line. The control terminal of the pixel unit in row 2n is connected to the scan line in row 2n, and the first end of the pixel unit in row 2n is connected to the second end of the pixel unit in row 2n-1. The control terminal of the control unit in row n is connected to the scan line in row 2n, and the first end of the control unit in row n is connected to the second end of the pixel unit in row 2n. The second end of the control unit in row n is connected to a preset voltage terminal. The nth row control unit is used to charge the pixel unit connected to the control unit by dividing the data voltage on the data line by a preset grayscale voltage during the normal display stage of a frame. It is also used to charge the pixel unit in the 2n-1th row and the pixel unit in the 2nth row simultaneously by the preset grayscale voltage during the black insertion stage of a frame. N is a positive integer greater than 1, and n = [1, 2, 3, ..., N].

2. A display panel, the display panel comprising 2N rows of scan lines and M columns of pixels, characterized in that, The pixel column includes: Data cable, 2N rows of pixel units, and N rows of control units; The pixel units in rows 2n-1 and 2n are connected in series. One pixel unit in row 2n-1 and row 2n is connected to the data line, and the other pixel unit is connected to the control unit in row n. The other pixel unit and the control unit in row n are connected to the same scan line. The control terminal of row 2n-1 is connected to the scan line in row 2n-1. The control terminal of the control unit in row n is connected to the scan line in row 2n-1. The first terminal of the control unit in row n is connected to the second terminal of row 2n-1, and the second terminal of the control unit in row n is connected to a preset voltage terminal. The control terminal of row 2n is connected to the scan line in row 2n. The first terminal of row 2n is connected to the data line, and the second terminal of row 2n is connected to the first terminal of row 2n-1. The nth row control unit is used to charge the pixel unit connected to the control unit by dividing the data voltage on the data line by a preset grayscale voltage during the normal display stage of a frame. It is also used to charge the pixel unit in the 2n-1th row and the pixel unit in the 2nth row simultaneously by the preset grayscale voltage during the black insertion stage of a frame. N is a positive integer greater than 1, and n = [1, 2, 3, ..., N].

3. The display panel according to claim 1 or 2, characterized in that, In the m-th pixel column, the pixel unit in the (2n-1)-th row is connected to the n-th row control unit; in the m+1-th pixel column, the pixel unit in the 2n-th row is connected to the n-th row control unit. Alternatively, in the m-th pixel column, the pixel unit in the 2n-th row is connected to the n-th row control unit; in the m+1-th pixel column, the pixel unit in the 2n-1-th row is connected to the n-th row control unit.

4. The display panel according to claim 1 or 2, characterized in that, The pixel unit includes: A pixel transistor, wherein the control terminal of the pixel transistor serves as the control terminal of the pixel unit, the first terminal of the pixel transistor serves as the first terminal of the pixel unit, and the second terminal of the pixel transistor serves as the second terminal of the pixel unit; A liquid crystal capacitor, wherein the upper plate of the liquid crystal capacitor is connected to the second terminal of the pixel transistor, and the lower plate of the liquid crystal capacitor is connected to the first common voltage terminal. The control unit includes: A control transistor, wherein the control terminal of the control transistor serves as the control terminal of the control unit, the first terminal of the control transistor serves as the first terminal of the control unit, and the second terminal of the control transistor serves as the second terminal of the control unit.

5. The display panel according to claim 4, characterized in that, For the pixel transistor connected to the control transistor, under the action of the gate drive signal on the scan line, the pixel transistor and the control transistor have an internal resistance ratio.

6. The display panel according to claim 1 or 2, characterized in that, The display panel further includes: a gate driving circuit; the gate driving circuit includes a black insertion control line, a frame start signal line, 2N cascaded driving circuit units, and a switching transistor; The control terminal of the switching transistor is connected to the black insertion control line, the first terminal of the switching transistor is connected to the frame start signal line, and the second terminal of the switching transistor is connected to the first-stage driving circuit unit or the second-stage driving circuit unit. During the black insertion phase, the black insertion control line controls the switching transistor to disconnect.

7. A display driving method, characterized in that, Applied to the display panel according to any one of claims 1-6, the display driving method includes: During the normal display phase, the adjacent two rows of pixel units and the control unit are controlled to be in the conducting state, so that the preset gray level voltage divides the data voltage on the data line and then charges the pixel unit connected to the control unit. During the black insertion phase, the pixel units connected to the data line are in a disconnected state, while the pixel units connected to the control unit and the control unit are in a conducting state, and the adjacent two rows of pixel units are charged by the preset grayscale voltage.

8. The display driving method according to claim 7, characterized in that, During the normal display phase, after controlling two adjacent rows of pixel units and the control unit to be in the on state, the method further includes: The control unit is driven to be in the off state, and the pixel unit connected to the data line is controlled to be in the on state, so that the data voltage on the data line charges the pixel unit connected to the data line.

9. The display driving method according to claim 7, characterized in that, When the display panel further includes a gate driving circuit; and the gate driving circuit includes a black insertion control line, a frame start signal line, 2N cascaded driving circuit units, and a switching transistor, controlling the pixel units connected to the data lines to be in an open state includes: The black-insertion control line controls the switching transistor to be in the off state, causing the first-stage driving circuit unit or the second-stage driving circuit unit to disconnect from the frame start signal line, thereby causing the odd-numbered driving circuit unit or the even-numbered driving circuit unit to stop outputting the gate driving signal.

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