Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel. The array substrate comprises a substrate body, an active layer and a plurality of conducting layers, the active layer and the conducting layers are arranged on one side of the substrate body in a stacked mode, at least one pixel circuit is formed by the active layer and the conducting layers, and each pixel circuit comprises a first capacitor, a second capacitor and a driving transistor; wherein the multiple conductive layers comprise at least two scanning lines, and the scanning lines extend in the first direction; the pixel circuit comprises a first-type transistor and a second-type transistor, and in the second direction, the orthographic projection of the first capacitor on the substrate, the orthographic projection of the second capacitor on the substrate and the orthographic projection of the driving transistor on the substrate are located between the orthographic projections of any two scanning lines connected with the first-type transistor and the second-type transistor respectively on the substrate; the first capacitor and the second capacitor are arranged along a second direction; wherein the second direction intersects with the first direction. According to the technical scheme, the use performance of the display panel is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to an array substrate and a display panel. Background Technology

[0002] Organic light-emitting diode (OLED) and flat panel display devices based on light-emitting diode (LED) technologies are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display panels needs improvement. Summary of the Invention

[0004] This invention provides an array substrate and a display panel to improve the performance of the display panel.

[0005] According to one aspect of the present invention, an array substrate is provided, the array substrate comprising:

[0006] Substrate;

[0007] An active layer and multiple conductive layers are stacked on one side of the substrate, and the active layer and the multiple conductive layers form at least one pixel circuit, the pixel circuit including a first capacitor, a second capacitor and a driving transistor;

[0008] The multilayer conductive layer includes at least two scan lines extending along a first direction; the pixel circuit includes a first type of transistor and a second type of transistor, and along a second direction, the orthographic projection of the first capacitor on the substrate, the orthographic projection of the second capacitor on the substrate, and the orthographic projection of the driving transistor on the substrate are located between the orthographic projections of any two scan lines that respectively connect the first type of transistor and the second type of transistor on the substrate, and the first capacitor and the second capacitor are arranged along the second direction; wherein the second direction intersects the first direction.

[0009] According to another aspect of the present invention, an array substrate is provided, the array substrate comprising:

[0010] Substrate;

[0011] A first conductive layer, a third conductive layer, and a fourth conductive layer are stacked sequentially along the direction away from the substrate;

[0012] The first scan line is located in the fourth conductive layer;

[0013] The third scan line is located between the first conductive layer and the fourth conductive layer;

[0014] The fourth scan line is located in the first conductive layer, the third conductive layer, and the fourth conductive layer;

[0015] The first scan line, the third scan line, and the fourth scan line are projected onto the substrate in a first direction and are spaced apart in a second direction. The first direction and the second direction intersect.

[0016] According to another aspect of the present invention, a display panel is provided, the display panel including the array substrate described in any embodiment of the present invention.

[0017] The technical solution of this invention provides that the pixel circuit of the array substrate includes a first capacitor, a second capacitor, and a driving transistor. Along a second direction, the orthographic projection of the first capacitor, the orthographic projection of the second capacitor, and the orthographic projection of the driving transistor on the substrate are located between the orthographic projections of any two scan lines that are respectively connected to a first type of transistor and a second type of transistor on the substrate. The first capacitor and the second capacitor are arranged along the second direction, such that the two scan lines that are respectively connected to the first type of transistor and the second type of transistor are separated by the first capacitor, the driving transistor, and the second capacitor. This reduces the crosstalk between the two scan lines that are respectively connected to the first type of transistor and the second type of transistor, which is beneficial to improving the reliability of the signal transmitted on the scan line and improving the performance of the display panel.

[0018] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of an array substrate provided in an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention;

[0022] Figure 3 yes Figure 1 A sectional view along the a1-a2 direction;

[0023] Figure 4 This is a schematic diagram of another array substrate structure provided in an embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram of another array substrate provided in an embodiment of the present invention;

[0025] Figure 6 yes Figure 5 A sectional view along the b1-b2 direction;

[0026] Figure 7 This is a schematic diagram of another array substrate provided in an embodiment of the present invention;

[0027] Figure 8 yes Figure 7 A schematic diagram along the e1-e2 direction;

[0028] Figure 9 This is a schematic diagram of another array substrate provided in an embodiment of the present invention;

[0029] Figure 10 This is a schematic diagram of the structure of an array substrate provided in an embodiment of the present invention;

[0030] Figure 11 This is a schematic diagram of another array substrate provided in an embodiment of the present invention;

[0031] Figure 12 yes Figure 11 A sectional view along the f1-f2 direction;

[0032] Figure 13 yes Figure 11 A sectional view along the f3-f4 direction;

[0033] Figure 14 This is a schematic diagram of another array substrate provided in an embodiment of the present invention;

[0034] Figure 15 yes Figure 14 A sectional view along the h1-h2 direction;

[0035] Figure 16 This is a schematic diagram of another array substrate provided in an embodiment of the present invention;

[0036] Figure 17 This is a timing diagram of a pixel circuit provided in an embodiment of the present invention;

[0037] Figure 18 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0038] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0039] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0040] As mentioned in the background section, existing display panels suffer from performance issues that require improvement. The inventors discovered that this problem arises because display panels include pixel circuits, which generate drive current to power the light-emitting devices within the panel. Pixel circuits include thin-film transistors (TFTs). Polysilicon transistors (PSTs) offer advantages such as stable characteristics, high mobility, and mature manufacturing processes. Oxide transistors (OTSs) offer advantages such as low leakage current and high uniformity. Therefore, in related technologies, some transistors in the pixel circuit utilize polysilicon transistors, while others utilize OTSs. However, the close spacing between the scan lines of OTSs and polysilicon transistors in the display panels of these technologies leads to significant crosstalk, resulting in poor performance.

[0041] To address the aforementioned technical problems, embodiments of the present invention provide an array substrate. Figure 1 This is a schematic diagram of an array substrate provided in an embodiment of the present invention, for reference. Figure 1 The array substrate includes:

[0042] Substrate 110;

[0043] An active layer 120 and multiple conductive layers are stacked on one side of a substrate 110. The active layer 120 and the multiple conductive layers form at least one pixel circuit 210. The pixel circuit 210 includes a first capacitor C1, a second capacitor C2, and a driving transistor T1.

[0044] The multilayer conductive layer includes at least two scan lines Scan, which extend along the first direction X. The pixel circuit 210 includes a first type transistor T01 and a second type transistor T02. Along the second direction Y, the orthographic projection of the first capacitor C1 on the substrate 110, the orthographic projection of the second capacitor C2 on the substrate 110, and the orthographic projection of the driving transistor T1 on the substrate 110 are located between the orthographic projections of any two scan lines Scan that connect the first type transistor T01 and the second type transistor T02 on the substrate 110, and the first capacitor C1 and the second capacitor C2 are arranged along the second direction Y. The second direction Y intersects the first direction X.

[0045] The substrate 110 has the functions of support, protection and buffer. The substrate 110 can be a flexible substrate, such as a polyimide (PI) substrate, or a rigid substrate, such as a glass substrate. No limitation is made here.

[0046] The pixel circuit 210 can generate a driving current to drive the light-emitting devices in the display panel formed by the array substrate to emit light. For example, Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention, such as... Figure 2 As shown, the pixel circuit 210 includes a first capacitor C1, a second capacitor C2, and a driving transistor T1. The driving transistor T1 can generate a driving current to drive the light-emitting device to emit light. The first capacitor C1 and the second capacitor C2 have a coupling effect and can couple and transmit voltage.

[0047] The first type transistor T01 and the second type transistor T02 are of different types. For example, one of the first type transistor T01 and the second type transistor T02 may be an N-type transistor and the other may be a P-type transistor. This is not a limitation here.

[0048] Specifically, by setting the orthographic projections of the first capacitor C1, the second capacitor C2, and the driving transistor T1 on the substrate 110 along the second direction Y, respectively, between the orthographic projections of any two scan lines Scan connected to the first type transistor T01 and the second type transistor T02 on the substrate 110, and arranging the first capacitor C1 and the second capacitor C2 along the second direction Y, the two scan lines Scan connected to the first type transistor T01 and the second type transistor T02 are separated by the first capacitor C1, the driving transistor T1, and the second capacitor C2. That is, the interval between the two scan lines Scan connected to the first type transistor T01 and the second type transistor T02 is large, which reduces the crosstalk between the two scan lines Scan connected to the first type transistor T01 and the second type transistor T02. This is beneficial to improving the reliability of the signal transmitted on the scan lines Scan and improving the performance of the display panel.

[0049] In this embodiment, the pixel circuit of the array substrate includes a first capacitor, a second capacitor, and a driving transistor. Along the second direction, the orthographic projection of the first capacitor, the orthographic projection of the second capacitor, and the orthographic projection of the driving transistor on the substrate are located between the orthographic projections of any two scan lines that are respectively connected to the first type transistor and the second type transistor on the substrate. The first capacitor and the second capacitor are arranged along the second direction, such that the two scan lines that are respectively connected to the first type transistor and the second type transistor are separated by the first capacitor, the driving transistor, and the second capacitor. This reduces the crosstalk between the two scan lines that are respectively connected to the first type transistor and the second type transistor, which helps to improve the reliability of the signal transmitted on the scan line and improves the performance of the display panel.

[0050] Based on the above technical solutions, alternatively, the following can be referenced: Figure 1 At least two scan lines include a first scan line S1 and a second scan line S2;

[0051] The pixel circuit 210 also includes a data writing transistor T2 and a threshold compensation transistor T3;

[0052] The first scan line S1 is connected to the gate T21 of the data writing transistor T2, and the second scan line S2 is connected to the gate of the threshold compensation transistor T3.

[0053] Along the second direction Y, the orthographic projection of the first capacitor C1 on the substrate 110, the orthographic projection of the second capacitor C2 on the substrate 110, and the orthographic projection of the driving transistor T1 on the substrate 110 are located between the orthographic projection of the first scan line S1 on the substrate 110 and the orthographic projection of the second scan line S2 on the substrate 110.

[0054] Threshold compensation transistor T3 is a first type transistor T01, and data writing transistor T2 is a second type transistor T02;

[0055] The first type transistor T01 and the second type transistor T02 have different channel types.

[0056] Optionally, one of the first type transistor T01 and the second type transistor T02 is an N-type transistor and the other is a P-type transistor.

[0057] Among them, such as Figure 2 As shown, the data writing transistor T2 can be connected to the data line Data. When the data writing transistor T2 is turned on, it transmits the data voltage on the data line Data, allowing the driving transistor T1 to generate a driving current based on the data voltage. When the threshold compensation transistor T3 is turned on, it can transmit a voltage related to the threshold voltage of the driving transistor T1 to the gate of the driving transistor T1. The gate-source voltage difference of the driving transistor T1 is related to its threshold voltage, and the driving current generated by the driving transistor T1 is related to the gate-source voltage difference minus its threshold voltage. This makes the driving current generated by the driving transistor T1 independent of its threshold voltage, avoiding the influence of threshold voltage fluctuations on the driving current.

[0058] Specifically, by setting the orthographic projections of the first capacitor C1, the second capacitor C2, and the driving transistor T1 on the substrate 110 along the second direction Y to be located between the orthographic projections of the first scan line S1 and the second scan line S2 on the substrate 110, the spacing between the orthographic projections of the first scan line S1 and the second scan line S2 on the substrate 110 is made larger, which can reduce crosstalk between the signals on the first scan line S1 and the second scan line S2.

[0059] Based on the above technical solutions, Figure 3 yes Figure 1 A sectional view along the a1-a2 direction, optionally, refer to Figure 1 and Figure 3 The active layer 120 includes a first active layer 121 and a second active layer 122, and the multilayer conductive layer includes a first conductive layer M1, a second conductive layer M2 and a third conductive layer M3.

[0060] The second active layer 122 is located on one side of the substrate 110, the first conductive layer M1 is located on the side of the second active layer 122 away from the substrate 110, the second conductive layer M2 is located on the side of the first conductive layer M1 away from the substrate 110, the first active layer 121 is located on the side of the second conductive layer M2 away from the substrate 110, and the third conductive layer M3 is located on the side of the first active layer 121 away from the substrate 110.

[0061] The array substrate also includes a fourth conductive layer M4 located on the side of the third conductive layer M3 facing away from the substrate 110, with at least a portion of the scan lines located on the fourth conductive layer M4. For example, the first scan line S1 connected to the second type transistor T02 and the second scan line S2 connected to the first type transistor T01 are located on the fourth conductive layer M4. For example, the gate T21 of the second type transistor T02 is located on the first conductive layer M1. For example, the second gate T12 of the driving transistor T1 and the gate of the first type transistor T01 (the third gate T31 of the threshold compensation transistor T3) are located on the third conductive layer M3.

[0062] Optionally, the second active layer 122 is made of a different material than the first active layer 121. This facilitates the formation of different types of first-type transistors T01 and second-type transistors T02.

[0063] Optionally, the first active layer 121 comprises an oxide semiconductor material, and the second active layer 122 comprises a polysilicon semiconductor material. For example, the first active layer 121 comprises the active region of a first-type transistor T01, and the second active layer 122 comprises the active region of a second-type transistor T02. That is, the first-type transistor T01 is an oxide transistor, and the second-type transistor T02 is a polysilicon transistor. For example, the first-type transistor T01 is an N-type transistor, and the second-type transistor T02 is a P-type transistor.

[0064] Optionally, refer to Figure 1 The projection of the first capacitor C1 onto the substrate 110 overlaps with the projection of the driving transistor T1 onto the substrate 110. This reduces the space occupied by the first capacitor C1 and the driving transistor T1, which is beneficial for achieving a higher pixel density in the display panel formed by the array substrate.

[0065] The projections of the first capacitor C1 onto the substrate 110 are spaced apart from the projections of the second capacitor C2 onto the substrate 110. This ensures that the first capacitor C1 and the second capacitor C2 are insulated from each other, preventing interference between them.

[0066] Optionally, refer to Figure 1 and Figure 3 The first capacitor C1 includes a first plate C11 and a second plate C12, and the second capacitor C2 includes a third plate C21 and a fourth plate C22.

[0067] The first electrode plate C11 and the third electrode plate C21 are located in the first conductive layer M1, and the second electrode plate C12 and the fourth electrode plate C22 are located in the second conductive layer M2.

[0068] The orthographic projection of the first electrode C11 onto the substrate 110 at least partially overlaps with the orthographic projection of the second electrode C12 onto the substrate 110, and the orthographic projection of the third electrode C21 onto the substrate 110 at least partially overlaps with the orthographic projection of the fourth electrode C22 onto the substrate 110.

[0069] Specifically, by setting the first electrode C11 and the third electrode C21 to be located on the first conductive layer M1, the second electrode C12 and the fourth electrode C22 to be located on the second conductive layer M2, and at least a portion of the scan lines to be located on the fourth conductive layer M4, the conductive structures on the first conductive layer M1 and the second conductive layer M2 are not excessive. This helps to reduce the space occupied in the first direction X and the second direction Y, which is beneficial for achieving a higher pixel density. Furthermore, it can reduce crosstalk between the scan lines and the first capacitor C1 and the second capacitor C2.

[0070] Figure 4 This is a schematic diagram of another array substrate structure provided in an embodiment of the present invention. Optionally, refer to... Figure 4 The array substrate also includes: a first connection line L1 located in the fourth conductive layer M4, the first connection line L1 being connected between the first electrode of the driving transistor T1 and the fourth electrode plate C22;

[0071] The first connection line L1 is connected to the first electrode of the driving transistor T1 through the sixth via V6, and the first connection line L1 is connected to the fourth electrode plate C22 through the seventh via V7.

[0072] The first terminal of the driving transistor T1 is either the source or the drain, which is not limited here. A first connection line L1 is provided to connect the first terminal of the driving transistor T1 to the fourth plate C22, thereby connecting the driving transistor T1 to the second capacitor C2. The sixth via V6 and the seventh via V7 are filled with conductive material.

[0073] Based on the above technical solutions, optionally, refer to Figure 3 and Figure 4 The first active layer 121 includes a first active region 1211, and the second active layer 122 includes a second active region 1221.

[0074] The pixel circuit 210 includes a data writing transistor T2 and a threshold compensation transistor T3. The channel region of the data writing transistor T2 is located in the second active region 1221, and the gate T21 of the data writing transistor T2 is located in the first conductive layer M1.

[0075] The gate T21 of the data writing transistor T2 extends along the second direction Y;

[0076] The first terminal T22, the channel region T23, and the second terminal T24 of the data writing transistor T2 are arranged sequentially along the first direction X.

[0077] The gate of the threshold compensation transistor T3 is located at least in the third conductive layer M3, and the gate of the threshold compensation transistor T3 extends along the first direction X. The channel region of the threshold compensation transistor T3 is located in the first active region 1211. The first gate T11 of the driving transistor T1 is located in the second conductive layer M2, the second gate T12 of the driving transistor T1 is located in the third conductive layer M3, and the channel region of the driving transistor T1 is located in the first active region 1211. The first terminal T22 of the data writing transistor T2 is the source, and the second terminal T24 of the data writing transistor T2 is the drain; alternatively, the first terminal T22 of the data writing transistor T2 is the drain, and the second terminal T24 of the data writing transistor T2 is the source. The material of the second active layer 122 includes polysilicon semiconductor, and the data writing transistor T2 is a polysilicon transistor, for example, a P-type transistor. The material of the first active layer 121 includes oxide semiconductor, and the threshold compensation transistor T3 is an oxide transistor, for example, an N-type transistor.

[0078] Specifically, the first electrode T22, the channel region T23, and the second electrode T24 of the data writing transistor T2 are arranged sequentially along the first direction X, making the data writing transistor T2 laterally positioned. Therefore, when the first capacitor C1 and the second capacitor C2 are arranged along the second direction Y, the laterally positioned data writing transistor T2 can reduce the space in the second direction Y, achieving rational use of space and improving the pixel density of the display panel formed by the array substrate.

[0079] The gate (third gate T31) of the threshold compensation transistor T3 extends along the first direction X, that is, it is in the same direction as the extension of the second scan line S2 connected to the threshold compensation transistor T3, which can reduce the space occupied by the threshold compensation transistor T3 in the first direction X and the second direction Y.

[0080] Optionally, such as Figure 4 As shown, the second electrode C12 is reused as the first gate T11. This reduces the space required for the driving transistor T1, which is beneficial for achieving a thinner and lighter design of the array substrate.

[0081] Optionally, such as Figure 4 As shown, the orthogonal projection of the first electrode C11 onto the substrate 110 overlaps the orthogonal projection of the second electrode C12 onto the substrate 110. This results in a smaller area for the first electrode C11, which in turn leads to a smaller area for the first gate electrode T11.

[0082] Optionally, such as Figure 4As shown, the orthogonal projection of the first gate T11 onto the substrate 110 covers the orthogonal projection of the second gate T12 onto the substrate 110. This results in a smaller area for the second gate T12, preventing the driving transistor T1 from becoming too large and avoiding crosstalk between the driving transistor T1 and the scan lines, thus further improving the performance of the display panel.

[0083] Optionally, the channel region of the threshold compensation transistor T3 is located on one side of the channel region of the driving transistor T1 and within the same second active region 1221. The orthogonal projections of the channel region T23 of the data writing transistor T2 and the channel region of the driving transistor T1 onto the substrate 110 are separated by the orthogonal projection of the second capacitor C2 onto the substrate. This ensures that no other transistors exist between the threshold compensation transistor T3, the data writing transistor T2, and the driving transistor T1, minimizing the length of the connection traces from the threshold compensation transistor T3 and the data writing transistor T2 to the driving transistor T1. This also minimizes the loss of data signals and threshold compensation signals transmitted to the driving transistor T1, thereby improving the driving accuracy of the pixel circuit.

[0084] Based on the above technical solutions, optionally, such as Figure 3 As shown, the multilayer conductive layer also includes a fourth conductive layer M4 located on the side of the third conductive layer M3 away from the substrate 110.

[0085] At least two scan lines Scan include a first scan line S1 and a second scan line S2; the first scan line S1 is located in the fourth conductive layer M4.

[0086] The first scan line S1 is connected to the gate T21 of the data writing transistor T2 through a first via V1. The first via V1 is filled with a conductive material. In this way, the first scan line S1 is connected to the gate T21 of the data writing transistor T2, so that the scan signal on the first scan line S1 can control the turning on or off of the data writing transistor T2.

[0087] Optionally, the sheet resistance of the fourth conductive layer M4 is less than the sheet resistance of at least one of the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3. Thus, the lower sheet resistance of the scan lines located on the fourth conductive layer M4 helps reduce signal loss on the scan lines, allowing for more accurate control of the corresponding transistors' on / off states, further improving the performance of the display panel.

[0088] Figure 5 This is a schematic diagram of another array substrate provided in an embodiment of the present invention. Figure 6 yes Figure 5 A sectional view along the b1-b2 direction, optionally, as follows: Figure 5 and Figure 6 As shown, the array substrate also includes:

[0089] The first connection part A1 is connected between the first electrode T22 and the third electrode C21 of the data writing transistor T2;

[0090] The data cable (Data) extends along the second direction (Y).

[0091] The second connection part A2 is connected between the data line Data and the second terminal T24 of the data writing transistor T2;

[0092] The first connecting part A1 is located in the fourth conductive layer M4;

[0093] The first connection part A1 is connected to the first electrode T22 of the data writing transistor T2 through the second via V2, and the first connection part A1 is connected to the third electrode plate C21 through the third via V3.

[0094] The second connecting part A2 is located in the fourth conductive layer M4;

[0095] The second connection part A2 is connected to the data line Data through the fourth via V4, and the second connection part A2 is connected to the second terminal T24 of the data writing transistor T2 through the fifth via V5.

[0096] The second via V2, third via V3, fourth via V4, and fifth via V5 are filled with conductive material. This connects the data writing transistor T2 to the data line Data. It also connects the data writing transistor T2 to the second capacitor C2, allowing the data writing transistor T2 to transmit the data voltage on the data line Data to the third plate C21, and the second capacitor C2 to couple the data voltage to the driving transistor T1.

[0097] Based on the above technical solutions, optionally, such as Figure 3 As shown, the multilayer conductive layer also includes a fourth conductive layer M4 located on the side of the third conductive layer M3 away from the substrate 110.

[0098] The second scan line S2 is located in the fourth conductive layer M4;

[0099] The sheet resistance of the material of the fourth conductive layer M4 is lower than that of at least one of the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3. Thus, the sheet resistance of the first scan line S1 and the second scan line S2 located on the fourth conductive layer M4 is relatively low, which helps to reduce signal loss on the first scan line S1 and the second scan line S2, allowing for more accurate control of the corresponding transistors' on / off states, and further improving the performance of the display panel.

[0100] Optionally, such as Figure 4 or Figure 5 As shown, the gate of the threshold compensation transistor T3 includes a third gate T31 located in the third conductive layer M3; the third gate T31 extends along the first direction X.

[0101] The second scan line S2 is connected to the third gate T31 through an eighth via V8. The eighth via V8 is filled with a conductive material. This connects the second scan line S2 to the gate of the threshold compensation transistor T3, allowing the scan signal on the second scan line S2 to control the threshold compensation transistor T3 to turn on or off.

[0102] Optionally, such as Figure 4 or Figure 5 As shown, the orthographic projection of the third gate T31 onto the substrate 110 overlaps with the orthographic projection of the first active region 1211 onto the substrate 110. That is, the channel of the threshold compensation transistor T3 overlaps with the third gate T31.

[0103] The orthographic projection of the third gate T31 onto the substrate 110 at least partially overlaps with the orthographic projection of the second scan line S2 onto the substrate 110. This reduces the space occupied by the third gate T31 and the second scan line S2, which is beneficial for achieving a high pixel density in the display panel formed by the array substrate.

[0104] Optionally, such as Figure 4 or Figure 5 As shown, the length of the orthogonal projection of the third gate T31 onto the substrate 110 in the first direction X is less than the length of the orthogonal projection of the second scan line S2 onto the substrate 110 in the first direction X. This reduces the space occupied by the third gate T31 and avoids interference from other signals. Furthermore, it prevents the third gate T31 from forming additional transistors with other active regions.

[0105] Figure 7 This is a schematic diagram of another array substrate provided in an embodiment of the present invention. Figure 8 yes Figure 7 A schematic diagram along the e1-e2 direction, optionally, as follows: Figure 7 and Figure 8 As shown, the array substrate also includes:

[0106] The third connection part A3 is connected between the first electrode of the threshold compensation transistor T3 and the second electrode plate C12; the second electrode of the threshold compensation transistor T3 is connected to the first electrode of the driving transistor T1.

[0107] The fourth connection part A4 is connected between the second gate T12 and the second electrode of the driving transistor T1;

[0108] The third connecting part A3 is located in the fourth conductive layer M4;

[0109] The fourth connection part A4 is located in the fourth conductive layer;

[0110] The third connection part A3 is connected to the second electrode plate C12 through the ninth via V9, and the third connection part A3 is connected to the first electrode of the threshold compensation transistor T3 through the tenth via V10.

[0111] The fourth connection part A4 is connected to the second gate T12 through the eleventh via V11, and the fourth connection part A4 is connected to the second terminal of the driving transistor T1 through the twelfth via V12.

[0112] In this configuration, the first electrode of the driving transistor T1 is the source, and the second electrode of the driving transistor T1 is the drain, or the first electrode of the driving transistor T1 is the drain, and the second electrode of the driving transistor T1 is the source; this is not limited to either. The first electrode of the threshold compensation transistor T3 is the source, and the second electrode of the threshold compensation transistor T3 is the drain, or the first electrode of the threshold compensation transistor T3 is the drain, and the second electrode of the threshold compensation transistor T3 is the source; this is not limited to either. The ninth via V9, the tenth via V10, the eleventh via V11, and the twelfth via V12 are filled with conductive material.

[0113] Specifically, by providing the fourth connection portion A4, the second gate T12 of the driving transistor T1 can be connected to other devices through the third connection portion A3. By providing the third connection portion A3, the threshold compensation transistor T3 is connected to the second plate C12, that is, connected to the second gate T12 of the driving transistor T1, so that the threshold compensation transistor T3 can transmit the voltage related to the threshold voltage of the driving transistor T1 to the second gate T12.

[0114] Figure 9 This is a schematic diagram of another array substrate provided in an embodiment of the present invention. Optionally, refer to... Figure 9 The threshold compensation transistor T3 also includes a fourth gate T32.

[0115] The fourth gate T32 is located in the second conductive layer M2, and the orthogonal projections of the fourth gate T32 and the second gate T31 on the substrate 110 overlap. This allows the threshold compensation transistor T3 to form a dual-gate transistor, which helps reduce leakage current.

[0116] Based on the above technical solutions, Figure 10 This is a schematic diagram of an array substrate provided in an embodiment of the present invention. Optionally, as shown... Figure 10 As shown, the first active region 1211 includes a first active part G1, a second active part G2, a third active part G3 and a fourth active part G4 connected in sequence.

[0117] The first active part G1 and the third active part G3 extend along the first direction X, and the second active part G2 and the fourth active part G4 extend along the second direction Y.

[0118] The first active part G1 includes the channel region of the driving transistor T1, and the fourth active part G4 includes the channel region of the threshold compensation transistor T3.

[0119] The orthographic projection of the third gate T31 onto the substrate 110 overlaps with the orthographic projection of the fourth active part G4 onto the substrate 110; the orthographic projection of the third gate T31 onto the substrate 110 is spaced apart from the orthographic projection of the second active part G2 onto the substrate.

[0120] In this way, the formation of the driving transistor T1 and the threshold compensation transistor T3 can be guaranteed, and the formation of an additional transistor in the second active part G2 can be avoided.

[0121] Optionally, such as Figure 10 As shown, the first boundary D1 of the orthogonal projection of the third gate T31 onto the substrate 110, the orthogonal projection of the fourth active part G4 onto the substrate 110, the second boundary D2 of the orthogonal projection of the third gate T31 onto the substrate 110, and the orthogonal projection of the second active part G2 onto the substrate 110 are arranged sequentially along the first direction X.

[0122] Among them, the first boundary D1 is opposite to the second boundary D2.

[0123] In this way, the third gate T31 can be prevented from overlapping with the second active part G2, thus preventing the second active part G2 from forming an additional transistor.

[0124] Optionally, the first active region 1211 is a single-piece structure. This facilitates a reduction in the fabrication process.

[0125] It should be noted that, in order to clearly illustrate the third gate T31, Figure 10 The second scan line S2 is not shown in the diagram.

[0126] Optionally, such as Figure 10 As shown, the second active region 1221 includes a fifth active part G5 and a sixth active part G6 connected to each other. The fifth active part G5 extends along the first direction X, and the sixth active part G6 extends along the second direction Y.

[0127] The channel region of the data writing transistor T2 is located in the fifth active part G5, and the gate T21 of the data writing transistor T2 overlaps with the orthographic projection of the fifth active part G5.

[0128] The pixel circuit 210 also includes a second reset transistor T4, the channel region of which is located in the sixth active region G6. This facilitates the formation of the data writing transistor T2 and the second reset transistor T4. The second reset transistor T4 can reset the third plate C21 of the second capacitor C2, facilitating subsequent data writing to the third plate C21. The material of the second active layer 122 includes polysilicon semiconductor, and the second reset transistor T4 is a polysilicon transistor, for example, a P-type transistor.

[0129] Optionally, such as Figure 7 As shown, at least two scan lines include a third scan line S3; the third scan line S3 includes a first sub-line S31 located in the first conductive layer M1 and a second sub-line S32 located in the fourth conductive layer M4;

[0130] The orthographic projection of the third scan line S3 on the substrate 110 overlaps with the orthographic projection of the sixth active part G6 on the substrate 110.

[0131] Specifically, the orthographic projection of the third scan line S3 on the substrate 110 overlaps with the orthographic projection of the sixth active part G6 on the substrate 110, thereby forming the gate of the second reset transistor T4. The third scan line S3 includes a first sub-line S31 located in the first conductive layer M1 and a second sub-line S32 located in the fourth conductive layer M4. The sheet resistance of the material of the fourth conductive layer M4 is low, which can reduce the impedance of the third scan line S3 and reduce signal loss on the third scan line S3. Furthermore, it is beneficial to increase the trace area, thereby reducing impedance and avoiding significant signal loss on the third scan line S3.

[0132] Optionally, the second active region 1221 is a single-piece structure. This facilitates a reduction in the fabrication process.

[0133] Optionally, such as Figure 7 As shown, the array substrate also includes:

[0134] The second reset signal line Vini is located in the fourth conductive layer M4 and extends along the first direction X. The second reset signal line Vini is connected to the second terminal of the second reset transistor T4. In the second direction Y, the orthogonal projections of the second reset signal line Vini, the third scan line S3, and the first scan line S1 on the substrate 110 are arranged sequentially. The distance between the orthogonal projection of the first scan line S1 on the substrate 110 and the orthogonal projection of the driving transistor T1 on the substrate 110 is smaller than the distance between the orthogonal projection of the third scan line S3 on the substrate 110 and the orthogonal projection of the driving transistor T1 on the substrate 110, and smaller than the distance between the orthogonal projection of the second reset signal line Vini on the substrate 110 and the orthogonal projection of the driving transistor T1 on the substrate 110. The first terminal of the second reset transistor T4 is connected to the first terminal of the data writing transistor T2.

[0135] In this configuration, the first electrode of the second reset transistor T4 is the source, and the second electrode is the drain; alternatively, the first electrode of the second reset transistor T4 is the drain, and the second electrode is the source. This is not a limitation. The second reset signal line Vini can transmit the second reset voltage. When the second reset transistor T4 is turned on, the second reset voltage on the second reset signal line Vini can be transmitted to the third plate C21 of the second capacitor C2, resetting the voltage on the third plate C21 of the second capacitor C2.

[0136] Specifically, along the second direction Y, the distance between the orthographic projection of the first scan line S1 on the substrate 110 and the orthographic projection of the driving transistor T1 on the substrate 110 is smaller than the distance between the orthographic projection of the third scan line S3 on the substrate 110 and the orthographic projection of the driving transistor T1 on the substrate 110, and smaller than the distance between the orthographic projection of the second reset signal line Vini on the substrate 110 and the orthographic projection of the driving transistor T1 on the substrate 110. This makes the first scan line S1 closest to the driving transistor T1 among the first scan line S1, the third scan line S3, and the second reset signal line Vini. This also makes the data writing transistor T2 connected to the first scan line S1 closer to the driving transistor T1, which facilitates the data writing transistor T2 to transmit data voltage to the driving transistor T1 or the second capacitor C2.

[0137] Optionally, the second reset signal line Vini is connected to the second terminal of the second reset transistor T4 through the twenty-seventh via V27. The twenty-seventh via V27 is filled with conductive material, so that the second reset signal line Vini is connected to the second terminal of the second reset transistor T4.

[0138] Based on the above technical solutions, optionally, such as Figure 7 As shown, the second active layer 122 also includes a third active region 1222. In the first direction X, the third active region 1222 and the second active region 1221 are arranged at intervals, and the third active region 1221 extends along the second direction Y.

[0139] The pixel circuit 210 also includes a first light-emitting control transistor T5;

[0140] The channel region of the first light-emitting control transistor T5 is located in the third active region 1222;

[0141] The orthographic projection of the third scan line S3 onto the substrate 110 overlaps with the orthographic projection of the third active region 1222 onto the substrate 110.

[0142] The material of the second active layer 122 includes polycrystalline silicon semiconductor, and the first light-emitting control transistor T5 is a polycrystalline silicon transistor, such as a P-type transistor.

[0143] Specifically, in the first direction X, the third active region 1222 and the second active region 1221 are arranged at intervals, and the third active region 1221 extends along the second direction Y. That is, the arrangement direction of the third active region 1222 and the second active region 1221 is different from the extension direction of the third active region 1221, which can ensure the rationality of space utilization and is conducive to improving the pixel density of the display panel formed by the array substrate.

[0144] The orthographic projection of the third scan line S3 onto the substrate 110 overlaps with the orthographic projection of the third active region 1222 onto the substrate 110, thereby forming the gate of the first light-emitting control transistor T5. Furthermore, the first light-emitting control transistor T5 and the second reset transistor T4 share the third scan line S3, which can reduce the number of scan lines and is beneficial to improving the pixel density of the display panel formed by the array substrate.

[0145] Optionally, the first sub-line S31 can be multiplexed as the gate of the second reset transistor T4 and the first light-emitting control transistor T5. This reduces the space occupied by the conductive structure, facilitating a thinner and lighter design of the array substrate, or increasing the pixel density of the display panel formed by the array substrate.

[0146] Figure 11 This is a schematic diagram of another array substrate provided in an embodiment of the present invention. Optionally, as shown... Figure 11 As shown, the array substrate also includes:

[0147] The second connection line L2 is connected between the second terminal of the driving transistor T1 and the first terminal of the first light-emitting control transistor T5;

[0148] The third connection line L3 is connected between the second terminal of the first light-emitting control transistor T5 and the first plate C11. This connects the second terminal of the driving transistor T1 to the first terminal of the first light-emitting control transistor T5, and the second terminal of the first light-emitting control transistor T5 to the first plate C11. The second terminal of the first light-emitting control transistor T5 can be connected to the first terminal of the light-emitting device OLED, and the second terminal of the OLED can be connected to the second power line VSS. This allows the first light-emitting control transistor T5 to conduct, transmitting a driving current to the light-emitting device OLED, causing it to emit light. One of the first and second terminals of the first light-emitting control transistor T5 is the source, and the other is the drain. The light-emitting device OLED can be an organic light-emitting diode, with the first terminal being the anode and the second terminal being the cathode, or vice versa; no limitation is made here.

[0149] Figure 12 yes Figure 11A sectional view along the f1-f2 direction, optionally, as follows: Figure 11 and Figure 12 As shown, the array substrate also includes:

[0150] The fifth connecting part A5 and the sixth connecting part A6 are connected. The fifth connecting part A5 is connected to the first end of the third connecting line L3 and to the second electrode of the first light-emitting control transistor T5. The sixth connecting part A6 is connected between the second end of the third connecting line L3 and the first electrode plate C11. In this way, the third connecting line L3 connects the second electrode of the first light-emitting control transistor T5 to the first electrode plate C11.

[0151] Optionally, such as Figure 11 and Figure 12 As shown, the second connecting line L2, the fifth connecting part A5, and the sixth connecting part A6 are located in the fourth conductive layer M4;

[0152] The multilayer conductive layer also includes a fifth conductive layer M5 located on the side of the fourth conductive layer M4 away from the substrate;

[0153] The third connecting line L3 is located in the fifth conductive layer M5;

[0154] The second connection line L2 is connected to the second terminal of the driving transistor T1 through the thirteenth via V13, and the second connection line L2 is connected to the second terminal of the first light-emitting control transistor T5 through the fourteenth via V14.

[0155] The fifth connection part A5 is connected to the first end of the third connection line L3 through the fifteenth via V15, and the fifth connection part A5 is connected to the second electrode of the first light-emitting control transistor T5 through the sixteenth via V16.

[0156] The sixth connection part A6 is connected to the second end of the third connection line L3 through the seventeenth via V17, and the sixth connection part is connected to the first electrode plate C11 through the eighteenth via V18. The thirteenth via V13, fourteenth via V14, fifteenth via V15, sixteenth via V16, seventeenth via V17, and eighteenth via V18 are filled with conductive material. In this way, the second electrode of the driving transistor T1 can be connected to the first electrode of the first light-emitting control transistor T5, and the second electrode of the first light-emitting control transistor T5 can be connected to the first electrode plate C11.

[0157] Based on the above technical solutions, optionally, refer to Figure 2 and Figure 7 The pixel circuit also includes a second light-emitting control transistor T6 and a first reset transistor T7;

[0158] The second active layer 122 includes a fourth active region 1223, and the channel region of the second light-emitting control transistor T6 is located in the fourth active region 1223.

[0159] The first active layer 121 includes a fifth active region 1212, and the channel region of the first reset transistor T7 is located in the fifth active region 1212. Therefore, the channel type of the second light-emitting control transistor T6 is different from the channel type of the first reset transistor T7. The material of the second active layer 122 includes polysilicon semiconductor, and the second light-emitting control transistor T6 is a polysilicon transistor, such as a P-type transistor. The material of the first active layer 121 includes oxide semiconductor, and the first reset transistor T7 is an oxide transistor, such as an N-type transistor.

[0160] The first reset transistor T7 can be connected to the first electrode of the OLED. When the first reset transistor T7 is turned on, it transmits a first reset voltage to the first electrode of the OLED to reset the first electrode of the OLED. The second light-emitting control transistor T6 can be connected between the power line VDD and the driving transistor T1 to control whether the first power supply voltage on the power line VDD is transmitted to the driving transistor T1.

[0161] In one implementation, alternatively, such as Figure 7 As shown, in the second direction Y, the orthogonal projections of the fourth active region 1223 and the fifth active region 1212 located in the same pixel circuit 210 onto the substrate 110 are located on different sides of the orthogonal projections of the first capacitor C1 and the second capacitor C2 onto the substrate 110.

[0162] In the first direction X, the fourth active region 1223 and the fifth active region 1212 in the adjacent pixel circuit 210 are arranged sequentially on the substrate 110 by their orthogonal projections.

[0163] In other words, the fourth active region 1223 and the fifth active region 1212 adjacent along the first direction X correspond to different pixel circuits 210, that is, the second light-emitting control transistor T6 and the first reset transistor T7 adjacent along the first direction X are located in different pixel circuits 210.

[0164] Optionally, such as Figure 7 As shown, the fourth active region 1223 and the fifth active region 1212 extend along the second direction Y. In this way, the extension direction of the fourth active region 1223 and the fifth active region 1212 is different from the arrangement direction of the first capacitor C1 and the second capacitor C2, which can achieve more rational use of space.

[0165] Optionally, such as Figure 7 and Figure 11 As shown, the array substrate also includes:

[0166] The power line VDD is located on the fifth conductive layer M5 on the side of the fourth conductive layer M4 away from the substrate, and extends along the second direction Y.

[0167] The fourth connection line L4 is connected between the first terminal of the second light-emitting control transistor T6 and the first terminal of the driving transistor T1;

[0168] The seventh connection part A7 is connected between the power line VDD and the second electrode of the second light-emitting control transistor T6.

[0169] Wherein, the first electrode of the second light-emitting control transistor T6 is the source, and the second electrode of the second light-emitting control transistor T6 is the drain, or the first electrode of the second light-emitting control transistor T6 is the drain, and the second electrode of the second light-emitting control transistor T6 is the source.

[0170] The power supply line VDD can provide a first power supply voltage. When the second light-emitting control transistor T6 is turned on, the first power supply voltage on the power supply line VDD can be transmitted to the first terminal of the driving transistor T1.

[0171] By providing the fourth connection line L4, the first terminal of the second light-emitting control transistor T6 is connected to the first terminal of the driving transistor T1. By providing the seventh connection part A7, the power supply line VDD is connected to the second terminal of the second light-emitting control transistor T6.

[0172] Figure 13 yes Figure 11 A sectional view along the f3-f4 direction, optionally, as follows: Figure 13 and Figure 11 As shown, the fourth connecting line L4 and the seventh connecting part A7 are located in the fourth conductive layer M4;

[0173] The fourth connection line L4 is connected to the first terminal of the second light-emitting control transistor T6 through the nineteenth via V19, and the fourth connection line L4 is connected to the first terminal of the driving transistor T1 through the twentieth via V20.

[0174] The seventh connection part A7 is connected to the power line VDD through the twenty-first via V21, and the seventh connection part A7 is connected to the second terminal of the second light-emitting control transistor T6 through the twenty-second via V22.

[0175] The nineteenth via V19, the twentieth via V20, the twenty-first via V21, and the twenty-second via V22 are filled with conductive material, so that the fourth connecting line L4 connects the first terminal of the second light-emitting control transistor T6 to the first terminal of the driving transistor T1, and the seventh connecting part A7 connects the power line VDD to the second terminal of the second light-emitting control transistor T6.

[0176] Optionally, such as Figure 7 As shown, the array substrate also includes: a first connection line L1, which is connected between the first electrode of the driving transistor T1 and the fourth electrode plate C22;

[0177] The first connection line L1 is connected to the first terminal of the driving transistor T1 through the sixth via V6;

[0178] The sixth via V6 is reused as the twentieth via V20. This saves space and facilitates increasing the pixel density of the display panel formed by the array substrate.

[0179] Optionally, such as Figure 7 , Figure 11 and 13 As shown, at least two scan lines include a fourth scan line S4. The fourth scan line S4 includes a third sub-line S41 located in the first conductive layer M1, a fourth sub-line S42 located in the third conductive layer M3, and a fifth sub-line S43 located in the fourth conductive layer M4, which are interconnected. The third sub-line S41, the fourth sub-line S42, and the fifth sub-line S43 are connected by vias.

[0180] The orthographic projection of the fourth scan line S4 onto the substrate 110 overlaps with the orthographic projection of the channel region of the second light-emitting control transistor T6 in the m-th row pixel circuit 210 onto the substrate 110; where m is a positive integer, and each row of pixel circuits is arranged along the first direction;

[0181] The orthographic projection of the fourth scan line S4 onto the substrate 110 overlaps with the orthographic projection of the channel region of the first reset transistor T7 in the (m+1)th row pixel circuit 210 onto the substrate 110.

[0182] Optionally, at least two scan lines further include a first scan line S1, a second scan line S2, and a third scan line S3. The first scan line S1 is connected to the gate of the data writing transistor T2 of the pixel circuit 210, the second scan line S2 is connected to the gate of the threshold compensation transistor T3 of the pixel circuit 210, and the third scan line S3 is used to drive the second reset transistor T4. The first scan line S1 is located on the side of the third scan line S3 closer to the driving transistor T1, and the second scan line S2 is located on the side of the fourth scan line S4 closer to the driving transistor T1. This ensures that the data writing transistor T2 connected to the first scan line S1 and the threshold compensation transistor T3 connected to the second scan line S2 are closest to the driving transistor T1, thereby improving signal transmission accuracy. Furthermore, the first scan line S1 and the second scan line S2 are spaced far apart, preventing signal crosstalk.

[0183] Specifically, in the first direction X, the orthogonal projections of the fourth active region 1223 and the fifth active region 1212 in adjacent pixel circuits 210 in the second direction Y are arranged sequentially on the substrate 110. That is, the fourth active region 1223 and the fifth active region 1212 adjacent in the first direction X correspond to different pixel circuits 210. That is, the second light-emitting control transistor T6 and the first reset transistor T7, which share a fourth scan line S4, are located in different pixel circuits 210.

[0184] In the same pixel circuit 210, the scan signal on the fourth scan line S4 connected to the second light-emitting control transistor T6 is delayed by one line time relative to the scan signal on the fourth scan line S4 connected to the first reset transistor T7. This allows the first reset transistor T7 to first transmit a first reset voltage to the first electrode of the OLED, resetting the first electrode of the OLED, before the second light-emitting control transistor T6 turns on, driving transistor T1 to generate a driving current and driving the OLED to emit light. The line time can be determined based on the refresh rate of the display panel; for example, the reciprocal of the refresh rate of the display panel divided by the total number of rows in the pixel circuit of the display panel gives one line time.

[0185] In this way, the scan lines can be shared, and the pixel circuit 210 can be guaranteed to work normally.

[0186] The fourth scan line S4 includes a third sub-line S41 located in the first conductive layer M1, a fourth sub-line S42 located in the third conductive layer M3, and a fifth sub-line S43 located in the fourth conductive layer M4, which are interconnected. That is, the three sub-lines of the fourth scan line S4 are arranged sequentially along the thickness direction Z of the display panel, resulting in a larger trace area for the fourth scan line S4. This reduces impedance and voltage drop, improving signal transmission reliability and reducing space requirements in the first direction X and the second direction Y. Furthermore, the sub-lines of different layers of the fourth scan line S4 can overlap with different active layers to form different types of transistors. For example, the portion of the third sub-line S41 overlapping with the fourth active region 1222 can serve as the gate of the second light-emitting control transistor T6, facilitating its formation. Similarly, the portion of the fourth sub-line S42 overlapping with the fifth active region 1212 can serve as the gate of the first reset transistor T7, facilitating its formation.

[0187] Optionally, a portion of the fourth scan line is multiplexed as the gate of the second light-emitting control transistor T6 and the first reset transistor T7. This facilitates a thinner and lighter array substrate design. For example, the first reset transistor T7 is an N-type transistor, and the fourth sub-line S42 is multiplexed as the gate of the first reset transistor T7. The second light-emitting control transistor T6 is a P-type transistor, and the third sub-line S41 is multiplexed as the gate of the second light-emitting control transistor T6.

[0188] Based on the above technical solutions, optionally, such as Figure 7 or Figure 11 As shown, the fourth conductive layer M4 also includes a first reset signal line Vref and a second reset signal line Vini extending along the first direction X.

[0189] In the same pixel circuit 210 located in the m-th row, the orthogonal projections of the first light-emitting control transistor T5, the second reset transistor T4, the first capacitor C1, the second capacitor C2, and the driving transistor T1 on the substrate 110 are located between the orthogonal projections of the first reset signal line Vref corresponding to the (m+1)-th row pixel circuit 210 and the second reset signal line Vini corresponding to the m-th row pixel circuit 210 on the substrate 110; where m is a positive integer, and each row of pixel circuits 210 is arranged along the first direction X;

[0190] In the second direction Y, the orthogonal projection of the first reset signal line Vref on the substrate 110 is located near the orthogonal projection of the fourth scan line S4 on the substrate 110, close to the orthogonal projection of the driving transistor T1 on the substrate 110, and the second scan line S2 is located on the side of the first reset signal line Vref near the driving transistor T1.

[0191] In this way, the fourth scan line S4 can isolate the first reset signal line Vref and the second reset signal line Vini, avoiding signal crosstalk, and further ensuring that the threshold compensation transistor T3 connected to the second scan line S2 is as close as possible to the driving transistor T1.

[0192] Optionally, the first reset signal line Vref is connected to the first terminal of the first reset transistor T7; the second terminal of the first reset transistor T7 is connected to the second terminal of the first light-emitting control transistor T5. Wherein, the first terminal of the first reset transistor T7 is the source, and the second terminal of the first reset transistor T7 is the drain, or the first terminal of the first reset transistor T7 is the drain, and the second terminal of the first reset transistor T7 is the source.

[0193] Optionally, the orthographic projections of the first electrode C11 onto the substrate 110, the orthographic projections of the first reset signal line Vref onto the substrate 110, and the orthographic projections of the fourth scan line S4 onto the substrate 110 are arranged sequentially along the second direction Y. This makes the distance between the fourth scan line S4 and the first reset signal line Vref relatively close, facilitating the transmission of the first reset voltage from the first reset signal line Vref to the first reset transistor T7.

[0194] Optionally, such as Figure 7 or Figure 11 As shown, the distance between the orthogonal projection of the fourth scan line S4 onto the substrate 110 and the orthogonal projection of the driving transistor T1 onto the substrate 110 is greater than the distance between the orthogonal projection of the first reset signal line Vref onto the substrate 110 and the orthogonal projection of the driving transistor T1 onto the substrate 110. That is, along the second direction Y, the orthogonal projection of the first reset signal line Vref onto the substrate 110 is located between the orthogonal projection of the driving transistor T1 onto the substrate 110 and the orthogonal projection of the fourth scan line S4 onto the substrate 110.

[0195] In another implementation, Figure 14This is a schematic diagram of another array substrate provided in an embodiment of the present invention. Optionally, refer to... Figure 14 The pixel circuit 210 also includes a second light-emitting control transistor T6 and a first reset transistor T7;

[0196] The second active layer 122 includes a fourth active region 1223, and the channel region of the second light-emitting control transistor T6 is located in the fourth active region 1223.

[0197] The first active layer 121 includes a fifth active region 1212, and the channel region of the first reset transistor T7 is located in the fifth active region 1212.

[0198] In the second direction Y, the orthogonal projections of the fourth active region 1223 and the fifth active region 1212 located in the same pixel circuit 210 onto the substrate 110 are located on the same side of the orthogonal projection of the first capacitor C1 away from the second capacitor C2 onto the substrate 110.

[0199] In the first direction X, the orthographic projections of the fourth active region 1223 and the fifth active region 1212 in the same pixel circuit 210 onto the substrate 110 are arranged sequentially.

[0200] In other words, the fourth active region 1223 and the fifth active region 1212 adjacent along the first direction X correspond to the same pixel circuit 210, that is, the second light-emitting control transistor T6 and the first reset transistor T7 adjacent along the first direction X are located in the same pixel circuit 210.

[0201] Optionally, refer to Figure 14 The fourth active region 1223 and the fifth active region 1212 both extend along the second direction. In this way, the extension direction of the fourth active region 1223 and the fifth active region 1212 is different from the arrangement direction of the first capacitor C1 and the second capacitor C2, which can achieve more rational use of space.

[0202] Based on the above technical solutions, optionally, refer to Figure 14 At least two scan lines include a fourth scan line S4, which includes a third sub-line S41 located in the first conductive layer M1, a fourth sub-line S42 located in the third conductive layer M3, and a fifth sub-line S43 located in the fourth conductive layer M4.

[0203] The orthographic projection of the fourth scan line S4 onto the substrate 110 overlaps with the orthographic projection of the channel region of the second light-emitting control transistor T6 and the channel region of the first reset transistor T7 in the m-th row pixel circuit 210 onto the substrate 110; where m is a positive integer, and each row of pixel circuits 210 is arranged along the first direction X.

[0204] This allows the second light-emitting control transistor T6 and the first reset transistor T7, both located in the same pixel circuit 210, to share a fourth scan line S4, facilitating an increase in the pixel density of the display panel formed by the array substrate. In this case, the signals on the fourth scan line S4 connected to the second light-emitting control transistor T6 in the same pixel circuit 210 are the same as those on the fourth scan line S4 connected to the first reset transistor T7.

[0205] Optionally, refer to Figure 14 The fourth conductive layer M4 also includes a first reset signal line Vref and a second reset signal line Vini extending along the first direction X.

[0206] Within the same pixel circuit 210, the orthogonal projections of the first light-emitting control transistor T5, the second reset transistor T4, the first capacitor C1, the second capacitor C2, and the driving transistor T1 onto the substrate 110 lie between the orthogonal projections of the first reset signal line Vref and the second reset signal line Vini onto the substrate 110. This results in a larger spacing between the first reset signal line Vref and the second reset signal line Vini, avoiding signal crosstalk.

[0207] Optionally, refer to Figure 14 In the second direction Y, the orthogonal projection of the first reset signal line Vref on the substrate 110 is located away from the orthogonal projection of the fourth scan line S4 on the substrate 110.

[0208] Optionally, the array substrate further includes a fifth connection line L5, which is connected between the second electrode of the first reset transistor T7 and the first electrode plate C11;

[0209] The fifth connection line L5 extends along the second direction Y. The orthographic projection of the fifth connection line L5 onto the substrate 110 overlaps with the orthographic projection of the second scan line S2 onto the substrate 110. This connects the second electrode of the first reset transistor T7 to the first plate C11 of the first capacitor C1. Furthermore, the overlap between the orthographic projection of the fifth connection line L5 onto the substrate 110 and the orthographic projection of the second scan line S2 onto the substrate 110 reduces the space occupied by the fifth connection line L5.

[0210] Figure 15 yes Figure 14 A sectional view along the h1-h2 direction, optionally, refer to Figure 14 and Figure 15 The first reset signal line Vref is located on the fourth conductive layer M4, and the fifth connecting line L5 is located on the same layer as the first electrode plate C11. This facilitates the connection between the fifth connecting line L5 and the first electrode plate C11, reducing the number of vias.

[0211] Optionally, refer to Figure 14 and Figure 15 The first reset signal line Vref is connected to the first terminal of the first reset transistor T7 through the twenty-third via V23. This connects the first reset signal line Vref to the first terminal of the first reset transistor T7.

[0212] Optionally, refer to Figure 14 and Figure 15 The array substrate also includes:

[0213] The eighth connection part A8 is connected between the first end of the fifth connection line L5 and the second electrode of the first reset transistor T7; the second end of the fifth connection line L5 is connected to the first electrode plate C11. Thus, the first end of the fifth connection line L5 is connected to the second electrode of the first reset transistor T7.

[0214] Optionally, refer to Figure 14 and Figure 15 The eighth connection part A8 is connected to the first end of the fifth connection line L5 through the twenty-fifth via V25, and the eighth connection part A8 is connected to the second terminal of the first reset transistor T7 through the twenty-sixth via V26.

[0215] The eighth connection part A8 is located in the fourth conductive layer M4.

[0216] In this way, the eighth connection part A8 connects the first end of the fifth connection line L5 to the second terminal of the first reset transistor T7.

[0217] Based on the above technical solutions, optionally, such as Figure 11 As shown, the array substrate also includes a fifth conductive layer M5 located on the side of the fourth conductive layer M4 away from the fourth conductive layer M4, and the fifth conductive layer M5 includes a data line Data and a power line VDD extending along the second direction Y.

[0218] At least a portion of the orthogonal projection of the power line VDD onto the substrate 110 is located between the orthogonal projection of the data line Data onto the substrate 110 and the orthogonal projection of the first gate T11 onto the substrate 110.

[0219] At least a portion of the orthogonal projection of the power line VDD onto the substrate 110 is located between the orthogonal projection of the data line Data onto the substrate 110 and the orthogonal projection of the second gate T12 onto the substrate 110.

[0220] This allows the power line VDD to shield the gates (first gate T11 and second gate T12) of the driving transistor T1 from the data line Data, preventing the data line Data from interfering with the voltage of the gates (first gate T11 and second gate T12) of the driving transistor T1. Furthermore, it allows for a more compact layout design of the array substrate, enabling efficient use of space and facilitating higher pixel density in the display panel formed by the array substrate.

[0221] Optionally, such as Figure 11 As shown, the orthogonal projection of the power line VDD onto the substrate 110 covers at least a portion of the orthogonal projection of the first active region 1211 onto the substrate 110.

[0222] Optionally, such as Figure 11 As shown, the orthogonal projection of the power line VDD onto the substrate 110 covers the orthogonal projection of the first capacitor C1 onto the substrate 110. This reduces the space occupied by the power line VDD and the pixel circuit 210 in the first direction X and the second direction Y, facilitating an increase in the pixel density of the display panel formed by the array substrate.

[0223] This invention also provides an array substrate. Figure 16 This is a schematic diagram of another array substrate provided in an embodiment of the present invention, for reference. Figure 16 The array substrate includes:

[0224] Substrate 110;

[0225] A first conductive layer M1, a third conductive layer M3, and a fourth conductive layer M4 are stacked sequentially along a direction away from the substrate 110.

[0226] The first scan line S1 is located in the fourth conductive layer M4;

[0227] The third scan line S3 is located between the first conductive layer M1 and the fourth conductive layer M4;

[0228] The fourth scan line S4 is located in the first conductive layer M1, the third conductive layer M3 and the fourth conductive layer M4;

[0229] The first scan line S1, the third scan line S3 and the fourth scan line S4 are projected onto the substrate 110 along the first direction X and are spaced apart along the second direction Y. The first direction X and the second direction Y are intersected.

[0230] Specifically, by setting the orthogonal projections of the first scan line S1, the third scan line S3, and the fourth scan line S4 on the substrate 110 to be spaced along the second direction Y, signal crosstalk between different scan lines can be avoided, which is beneficial to improving the performance of the display panel formed by the array substrate. Furthermore, the sheet resistance of the fourth conductive layer M4 can be less than the sheet resistance of at least one of the first conductive layer M1, the second conductive layer M2, and the third conductive layer M3. Since at least a portion of the first scan line S1, the third scan line S3, and the fourth scan line S4 are located in the fourth conductive layer M4, the sheet resistance of the first scan line S1, the third scan line S3, and the fourth scan line S4 is relatively small, resulting in a smaller voltage drop loss. This helps reduce signal loss on the scan lines and allows for more accurate control of the corresponding transistors' on / off states, further improving the performance of the display panel.

[0231] Furthermore, the third scan line S3 is located between the first conductive layer M1 and the fourth conductive layer M4, while the fourth scan line S4 is located between the first conductive layer M1, the third conductive layer M3, and the fourth conductive layer M4. This enhances the signal transmission capability of the third and fourth scan lines S3 and S4, helps reduce wiring resistance and power consumption, and improves driving stability, allowing for more accurate control of the corresponding transistors' on / off states. Moreover, the sub-lines of different layers of the fourth scan line S4 can overlap with different active layers, thereby forming different types of transistors.

[0232] Optionally, such as Figure 16 As shown, the third scan line S3 includes a first sub-line S31 located in the first conductive layer M1 and a second sub-line S32 located in the fourth conductive layer M4;

[0233] The fourth scan line S4 includes a third sub-line S41 located in the first conductive layer M1, a fourth sub-line S42 located in the third conductive layer M3, and a fifth sub-line S43 located in the fourth conductive layer M4.

[0234] It should be noted that, Figure 16 The first sub-line S31 and the second sub-line S32 are stacked together. The specific positional relationship between the first sub-line S31 and the second sub-line S32 can be found in the reference. Figure 12 Similarly, the specific positional relationships of the third sub-line S41, the fourth sub-line S42, and the fifth sub-line S43 can be found by referring to... Figure 13 .

[0235] Optionally, such as Figure 2 and Figure 7 As shown, the array substrate also includes:

[0236] An active layer 120 is stacked on one side of the substrate 110. The active layer 120 and the multilayer conductive layers form at least one pixel circuit 210. The pixel circuit 210 includes a first capacitor C1, a second capacitor C2 and a driving transistor T1.

[0237] The array substrate also includes:

[0238] The second scan line S2 is located in the second conductive layer M2, which is located on the side of the first conductive layer M1 away from the substrate 110.

[0239] Along the second direction Y, the orthographic projection of the first capacitor C1 on the substrate 110, the orthographic projection of the second capacitor C2 on the substrate 110, and the orthographic projection of the driving transistor T1 on the substrate 110 are located between the orthographic projection of the first scan line S1 on the substrate 110 and the orthographic projection of the second scan line S2 on the substrate 110.

[0240] The pixel circuit 210 also includes a data writing transistor T2, a threshold compensation transistor T3, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a first reset transistor T7, and a second reset transistor T4. The first scan line S1 is connected to the gate of the data writing transistor T2, the second scan line S2 is connected to the gate of the threshold compensation transistor T3, the third scan line S3 is connected to the gate of the first reset transistor T7 and the gate of the second light-emitting control transistor T6, and the fourth scan line S4 is connected to the gate of the second reset transistor T4 and the gate of the first light-emitting control transistor T5.

[0241] Specifically, along the second direction Y, the orthographic projections of the first capacitor C1 on the substrate 110, the second capacitor C2 on the substrate 110, and the driving transistor T1 on the substrate 110 are located between the orthographic projections of the first scan line S1 on the substrate 110 and the second scan line S2 on the substrate 110. This can separate the first scan line S1 and the second scan line S2, avoiding crosstalk between the signals on the first scan line S1 and the signals on the second scan line S2.

[0242] Optionally, such as Figure 2 and Figure 7 As shown, the third scan line S3 is used to drive the second reset transistor T4 of the pixel circuit 210. The first scan line S1 is located on the side of the third scan line S3 close to the driving transistor T1, and the second scan line S2 is located on the side of the fourth scan line S4 close to the driving transistor T1.

[0243] Figure 17 This is a timing diagram of a pixel circuit provided in an embodiment of the present invention, such as... Figure 2 and Figure 7 As shown, the operation of the pixel circuit includes the following stages. The following explanation uses the example of the scanning signal on the fourth scan line S4 connected to the first reset transistor T7 being the same as the scanning signal on the fourth scan line S4 connected to the second light-emitting control transistor T6 to illustrate the operation of the pixel circuit.

[0244] In the first stage t1, the first scan signal Sn1 on the first scan line S1 is high, and the data writing transistor T2 is not turned on. The second scan signal Sn2 on the second scan line S2 is high, and the threshold compensation transistor T3 is turned on. The third scan signal Sn3 on the third scan line S3 is low, and the second reset transistor T4 and the first light-emitting control transistor T5 are turned on. The fourth scan signal Sn4 on the fourth scan line S4 is high, and the first reset transistor T7 is turned on. The first reset transistor T7 transmits the first reset voltage on the first reset signal line Vref to the first electrode of the light-emitting device OLED, resetting the first electrode of the light-emitting device OLED. The second reset transistor T4 transmits the second reset voltage on the second reset signal line Vini to the first terminal (third plate C21) of the second capacitor C2, resetting the first terminal of the second capacitor C2. The first light-emitting control transistor T5 transmits the first reset voltage to the second electrode of the driving transistor T1, resetting the second electrode of the driving transistor T1. The threshold compensation transistor T3 transmits the voltage of the first terminal of the driving transistor T1 to the gate of the driving transistor T1. The voltage of the gate of the driving transistor T1 is the voltage provided by the power supply line VDD, so that a voltage difference is formed between the gate of the driving transistor T1 and the second terminal of the driving transistor T1. The gate of the driving transistor T1 discharges until it is the sum of the first reset voltage and the threshold voltage of the driving transistor T1.

[0245] In the second stage t2, the first scan signal Sn1 on the first scan line S1 is low, and the data writing transistor T2 is turned on. The second scan signal Sn2 on the second scan line S2 is high, and the threshold compensation transistor T3 is turned on. The third scan signal Sn3 on the third scan line S3 is high, and the second reset transistor T4 and the first light-emitting control transistor T5 are not turned on. The fourth scan signal Sn4 on the fourth scan line S4 is high, and the first reset transistor T7 is turned on. The first reset transistor T7 transmits the first reset voltage on the first reset signal line Vref to the first electrode of the light-emitting device OLED, resetting the first electrode of the light-emitting device OLED. The data writing transistor T2 transmits the data voltage to the first terminal of the second capacitor C2, and the second capacitor C2 couples the data voltage to the first electrode of the driving transistor T1. The threshold compensation transistor T3 transmits the voltage related to the data voltage to the gate of the driving transistor T1. This makes the voltage at the gate of the driving transistor T1 a voltage related to the data voltage and the threshold voltage of the driving transistor T1.

[0246] In the third stage t3, the first scan signal Sn1 on the first scan line S1 is low, and the data writing transistor T2 is turned on. The second scan signal Sn2 on the second scan line S2 is low, and the threshold compensation transistor T3 is not turned on. The third scan signal Sn3 on the third scan line S3 is high, and the second reset transistor T4 and the first light-emitting control transistor T5 are not turned on. The fourth scan signal Sn4 on the fourth scan line S4 is high, and the first reset transistor T7 is turned on. The first reset transistor T7 transmits the first reset voltage on the first reset signal line Vref to the first electrode of the light-emitting device OLED, resetting the first electrode of the light-emitting device OLED.

[0247] In the fourth stage t4, the first scan signal Sn1 on the first scan line S1 is high, and the data writing transistor T2 is not turned on. The second scan signal Sn2 on the second scan line S2 is low, and the threshold compensation transistor T3 is not turned on. The third scan signal Sn3 on the third scan line S3 is low, and the first light-emitting control transistor T5 is turned on. The fourth scan signal Sn4 on the fourth scan line S4 is low, the first reset transistor T7 is not turned on, and the second light-emitting control transistor T6 is turned on. This causes the driving transistor T1 to generate a driving current, driving the OLED to emit light.

[0248] Optionally, such as Figure 2 and Figure 7 As shown, the orthographic projection of the first capacitor C1 onto the substrate 110 overlaps with the orthographic projection of the driving transistor T1 onto the substrate 110.

[0249] The orthographic projection of the first capacitor C1 onto the substrate 110 does not overlap with the orthographic projection of the second capacitor C2 onto the substrate 110. This reduces the space occupied by the first capacitor C1 and the driving transistor T1, which is beneficial for achieving a higher pixel density in the display panel formed by the array substrate. Furthermore, it ensures that the first capacitor C1 and the second capacitor C2 are insulated, preventing interference between them.

[0250] Based on the above technical solutions, optionally, refer to Figure 3 and Figure 4 The active layer 120 includes a first active layer 121 and a second active layer 122. The second active layer 122 is located on one side of the substrate 110. The first conductive layer M1 is located on the side of the second active layer 122 away from the substrate 110. The second conductive layer M2 is located on the side of the first conductive layer M1 away from the substrate 110. The first active layer 121 is located on the side of the second conductive layer M2 away from the substrate 110. The third conductive layer M3 is located on the side of the first active layer 121 away from the substrate 110.

[0251] The first active layer 121 includes a first active region 1211, and the second active layer 122 includes a second active region 1221;

[0252] The channel region of the data writing transistor T2 is located in the second active region 1221, and the gate of the data writing transistor T2 is located in the first conductive layer M1.

[0253] The gate of the data writing transistor T2 extends along the second direction Y;

[0254] The first terminal, the channel region, and the second terminal of the data writing transistor T2 are arranged sequentially along the first direction X.

[0255] The gate of the threshold compensation transistor T3 is located at least in the third conductive layer, and the gate of the threshold compensation transistor T3 extends along the first direction X. The channel region of the threshold compensation transistor T3 is located in the first active region 1211. The first gate T11 of the driving transistor T1 is located in the second conductive layer M2, the second gate T12 of the driving transistor T1 is located in the third conductive layer M3, and the channel region of the driving transistor T1 is located in the first active region 1211.

[0256] Optionally, such as Figure 4 As shown, the first capacitor C1 includes a first plate C11 and a second plate C12, and the second plate C12 is multiplexed as the first gate T11.

[0257] Optionally, such as Figure 4 As shown, the orthographic projection of the first electrode C11 onto the substrate 110 covers the orthographic projection of the second electrode C21 onto the substrate 110.

[0258] Optionally, such as Figure 4 As shown, the orthogonal projection of the first gate T11 onto the substrate 110 covers the orthogonal projection of the second gate onto the substrate.

[0259] The beneficial effects of the array substrate in this embodiment and Figure 4 The beneficial effects of the array substrate shown are the same, and will not be repeated here.

[0260] Based on the above technical solution, optionally, the first active region 1211 includes a first active part G1, a second active part G2, a third active part G3 and a fourth active part G4 connected in sequence.

[0261] The first active part G1 and the third active part G3 extend along the first direction X, and the second active part G2 and the fourth active part G4 extend along the second direction Y.

[0262] The first active part G1 includes the channel region of the driving transistor T1, and the fourth active part G4 includes the channel region of the threshold compensation transistor T3.

[0263] The threshold compensation transistor T3 has a gate including a third gate T31 located in the third conductive layer M3; the orthographic projection of the third gate T31 on the substrate 110 overlaps with the orthographic projection of the fourth active part G4 on the substrate 110; the orthographic projection of the third gate T31 on the substrate 110 is spaced apart from the orthographic projection of the second active part G2 on the substrate 110.

[0264] Optionally, the first boundary D1 of the orthogonal projection of the third gate T31 onto the substrate 110, the orthogonal projection of the fourth active portion G4 onto the substrate 110, the second boundary D2 of the orthogonal projection of the third gate T31 onto the substrate 110, and the orthogonal projection of the second active portion G2 onto the substrate 110 are arranged sequentially along the first direction X.

[0265] Optionally, the first active region 1211 is an integral structure.

[0266] The beneficial effects of the array substrate in this embodiment and Figure 10 The beneficial effects of the array substrate shown are the same, and will not be repeated here.

[0267] This invention also provides a display panel. Figure 18 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention, for reference. Figure 18 The display panel 100 includes the array substrate 101 provided in any embodiment of the present invention. The display panel 100 may also include an OLED (Light Emitting Device). The pixel circuit 210 in the array substrate 101 is connected to the OLED and drives the OLED to emit light. Since the display panel 100 includes the array substrate 101 provided in any embodiment of the present invention, it possesses the same beneficial effects as the array substrate provided in any embodiment of the present invention, which will not be elaborated further here. The display panel can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, or digital photo frame.

[0268] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. An array substrate, characterized in that, include: Substrate; An active layer and multiple conductive layers are stacked on one side of the substrate, and the active layer and the multiple conductive layers form at least one pixel circuit, the pixel circuit including a first capacitor, a second capacitor and a driving transistor; The multilayer conductive layer includes at least two scan lines extending along a first direction; the pixel circuit includes a first type of transistor and a second type of transistor, and along a second direction, the orthographic projection of the first capacitor on the substrate, the orthographic projection of the second capacitor on the substrate, and the orthographic projection of the driving transistor on the substrate are located between the orthographic projections of any two scan lines that respectively connect the first type of transistor and the second type of transistor on the substrate, and the first capacitor and the second capacitor are arranged along the second direction; wherein the second direction intersects the first direction.

2. The array substrate according to claim 1, characterized in that, The at least two scan lines include a first scan line and a second scan line; The pixel circuit also includes a data writing transistor and a threshold compensation transistor; The first scan line is connected to the gate of the data writing transistor, and the second scan line is connected to the gate of the threshold compensation transistor; Along the second direction, the orthographic projection of the first capacitor on the substrate, the orthographic projection of the second capacitor on the substrate, and the orthographic projection of the driving transistor on the substrate are located between the orthographic projection of the first scan line on the substrate and the orthographic projection of the second scan line on the substrate. The threshold compensation transistor is a first type of transistor, and the data writing transistor is a second type of transistor; The first type of transistor has a different channel type than the second type of transistor; Preferably, one of the first type of transistor and the second type of transistor is an N-type transistor and the other is a P-type transistor.

3. The array substrate according to claim 1, characterized in that, The active layer includes a first active layer and a second active layer, and the multilayer conductive layer includes a first conductive layer, a second conductive layer and a third conductive layer; The second active layer is located on one side of the substrate, the first conductive layer is located on the side of the second active layer away from the substrate, the second conductive layer is located on the side of the first conductive layer away from the substrate, the first active layer is located on the side of the second conductive layer away from the substrate, and the third conductive layer is located on the side of the first active layer away from the substrate. The array substrate further includes a fourth conductive layer located on the side of the third conductive layer opposite to the substrate, and at least a portion of the scan lines are located in the fourth conductive layer; Preferably, the second active layer is made of a different material than the first active layer; Preferably, the first active layer comprises an oxide semiconductor material, and the second active layer comprises a polycrystalline silicon semiconductor material; Preferably, the orthographic projection of the first capacitor onto the substrate overlaps with the orthographic projection of the driving transistor onto the substrate; The orthographic projection of the first capacitor onto the substrate is spaced apart from the orthographic projection of the second capacitor onto the substrate; Preferably, the first capacitor includes a first plate and a second plate, and the second capacitor includes a third plate and a fourth plate; The first electrode plate and the third electrode plate are located in the first conductive layer, and the second electrode plate and the fourth electrode plate are located in the second conductive layer; The orthographic projection of the first electrode plate onto the substrate at least partially overlaps with the orthographic projection of the second electrode plate onto the substrate, and the orthographic projection of the third electrode plate onto the substrate at least partially overlaps with the orthographic projection of the fourth electrode plate onto the substrate. Preferably, the array substrate further includes: a first connection line located in the fourth conductive layer, the first connection line being connected between the first electrode of the driving transistor and the fourth electrode plate; The first connecting line is connected to the first electrode of the driving transistor through the sixth via, and the first connecting line is connected to the fourth electrode plate through the seventh via.

4. The array substrate according to claim 3, characterized in that, The first active layer includes a first active region, and the second active layer includes a second active region; The pixel circuit includes a data writing transistor and a threshold compensation transistor. The channel region of the data writing transistor is located in the second active region, and the gate of the data writing transistor is located in the first conductive layer. The gate of the data writing transistor extends along the second direction; The first electrode of the data writing transistor, the channel region of the data writing transistor, and the second electrode of the data writing transistor are arranged sequentially along the first direction; The gate of the threshold compensation transistor is located at least in the third conductive layer and extends along the first direction; the channel region of the threshold compensation transistor is located in the first active region. The first gate of the driving transistor is located in the second conductive layer, the second gate of the driving transistor is located in the third conductive layer, and the channel region of the driving transistor is located in the first active region. Preferably, the second electrode plate is reused as the first gate. Preferably, the orthographic projection of the first electrode plate onto the substrate covers the orthographic projection of the second electrode plate onto the substrate; Preferably, the orthogonal projection of the first gate onto the substrate covers the orthogonal projection of the second gate onto the substrate.

5. The array substrate according to claim 3, characterized in that, The multilayer conductive layer further includes a fourth conductive layer located on the side of the third conductive layer away from the substrate; The at least two scan lines include a first scan line and a second scan line; the first scan line is located in the fourth conductive layer; The first scan line is connected to the gate of the data writing transistor through the first via; Preferably, the sheet resistance of the fourth conductive layer is less than the sheet resistance of at least one of the first conductive layer, the second conductive layer, and the third conductive layer; Preferably, the array substrate further includes: The first connection portion is connected between the first electrode of the data writing transistor and the third electrode plate; The data cable extends along the second direction; The second connection portion is connected between the data line and the second electrode of the data writing transistor; The first connection portion is located in the fourth conductive layer; The first connection portion is connected to the first electrode of the data writing transistor through a second via, and the first connection portion is connected to the third electrode plate through a third via. The second connection portion is located in the fourth conductive layer; The second connection portion is connected to the data line through the fourth via, and the second connection portion is connected to the second terminal of the data writing transistor through the fifth via.

6. The array substrate according to claim 4, characterized in that, The at least two scan lines include a first scan line and a second scan line; The multilayer conductive layer further includes a fourth conductive layer located on the side of the third conductive layer away from the substrate; The second scan line is located in the fourth conductive layer; The sheet resistance of the material of the fourth conductive layer is less than the sheet resistance of at least one of the first conductive layer, the second conductive layer and the third conductive layer; Preferably, the gate of the threshold compensation transistor includes a third gate located in the third conductive layer; The third gate extends along the first direction; The second scan line is connected to the third gate via an eighth via; Preferably, the orthographic projection of the third gate onto the substrate overlaps with the orthographic projection of the first active region onto the substrate; The orthogonal projection of the third gate onto the substrate at least partially overlaps with the orthogonal projection of the second scan line onto the substrate; Preferably, the length of the orthogonal projection of the third gate onto the substrate in the first direction is less than the length of the orthogonal projection of the second scan line onto the substrate in the first direction; Preferably, the array substrate further includes: The third connection portion is connected between the first electrode of the threshold compensation transistor and the second electrode plate; the second electrode of the threshold compensation transistor is connected to the first electrode of the driving transistor. The fourth connection portion is connected between the second gate and the second electrode of the driving transistor; The third connection portion is located in the fourth conductive layer; The fourth connection portion is located in the fourth conductive layer; The third connection portion is connected to the second electrode plate through the ninth via, and the third connection portion is connected to the first electrode of the threshold compensation transistor through the tenth via; The fourth connection portion is connected to the second gate through the eleventh via, and the fourth connection portion is connected to the second electrode of the driving transistor through the twelfth via; Preferably, the gate of the threshold compensation transistor further includes a fourth gate; The fourth gate is located in the second conductive layer, and the orthographic projection of the fourth gate and the second gate on the substrate overlaps.

7. The array substrate according to claim 6, characterized in that, The first active region includes a first active section, a second active section, a third active section, and a fourth active section connected in sequence; The first active portion and the third active portion extend along the first direction, and the second active portion and the fourth active portion extend along the second direction; The first active portion includes the channel region of the driving transistor, and the fourth active portion includes the channel region of the threshold compensation transistor; The orthographic projection of the third gate onto the substrate overlaps with the orthographic projection of the fourth active portion onto the substrate; The orthographic projection of the third gate onto the substrate is spaced apart from the orthographic projection of the second active portion onto the substrate. Preferably, the first boundary of the orthographic projection of the third gate onto the substrate, the orthographic projection of the fourth active portion onto the substrate, the second boundary of the orthographic projection of the third gate onto the substrate, and the orthographic projection of the second active portion onto the substrate are arranged sequentially along the first direction; Preferably, the first active region is an integral structure.

8. The array substrate according to claim 4, characterized in that, The second active region includes a fifth active portion and a sixth active portion connected to each other, wherein the fifth active portion extends along the first direction and the sixth active portion extends along the second direction; The channel region of the data writing transistor is located in the fifth active region, and the gate of the data writing transistor overlaps with the orthographic projection of the fifth active region. The pixel circuit further includes a second reset transistor, the channel region of which is located in the sixth active portion; Preferably, the at least two scan lines include a third scan line; the third scan line includes a first sub-line located in the first conductive layer and a second sub-line located in the fourth conductive layer; The orthographic projection of the third scan line on the substrate overlaps with the orthographic projection of the sixth active part on the substrate; Preferably, the second active region is an integral structure; The array substrate further includes: The second reset signal line is located in the fourth conductive layer and extends along the first direction. The second reset signal line is connected to the second terminal of the second reset transistor. In the second direction, the orthogonal projections of the second reset signal line, the third scan line, and the first scan line on the substrate are arranged sequentially. The distance between the orthogonal projection of the first scan line on the substrate and the orthogonal projection of the driving transistor on the substrate is smaller than the distance between the orthogonal projection of the third scan line on the substrate and the orthogonal projection of the driving transistor on the substrate, and smaller than the distance between the orthogonal projection of the second reset signal line on the substrate and the orthogonal projection of the driving transistor on the substrate. The first terminal of the second reset transistor is connected to the first terminal of the data write transistor; Preferably, the second reset signal line is connected to the second terminal of the second reset transistor through the twenty-seventh via.

9. The array substrate according to claim 8, characterized in that, The second active layer further includes a third active region, which is arranged at intervals from the second active region in the first direction, and the third active region extends along the second direction; The pixel circuit also includes a first light-emitting control transistor; The channel region of the first light-emitting control transistor is located in the third active region; The orthographic projection of the third scan line onto the substrate overlaps with the orthographic projection of the third active region onto the substrate; Preferably, the first sub-line is multiplexed as the gate of the second reset transistor and the first light-emitting control transistor; Preferably, the array substrate further includes: The second connection line is connected between the second terminal of the driving transistor and the first terminal of the first light-emitting control transistor; The third connecting line is connected between the second electrode of the first light-emitting control transistor and the first electrode plate; Preferably, the array substrate further includes: The fifth connection part and the sixth connection part are provided. The fifth connection part is connected to the first end of the third connection line and connected to the second electrode of the first light-emitting control transistor. The sixth connection part is connected between the second end of the third connection line and the first electrode plate. Preferably, the second connecting line, the fifth connecting portion, and the sixth connecting portion are located in the fourth conductive layer; The multilayer conductive layer further includes a fifth conductive layer located on the side of the fourth conductive layer away from the substrate; The third connecting line is located in the fifth conductive layer; The second connection line is connected to the second terminal of the driving transistor through the thirteenth via, and the second connection line is connected to the second terminal of the first light-emitting control transistor through the fourteenth via; The fifth connection part is connected to the first end of the third connection line through the fifteenth via, and the fifth connection part is connected to the second electrode of the first light-emitting control transistor through the sixteenth via; The sixth connecting part is connected to the second end of the third connecting line through the seventeenth through hole, and the sixth connecting part is connected to the first electrode plate through the eighteenth through hole.

10. The array substrate according to claim 3, characterized in that, The pixel circuit also includes a second light-emitting control transistor and a first reset transistor; The second active layer includes a fourth active region, and the channel region of the second light-emitting control transistor is located in the fourth active region; The first active layer includes a fifth active region, and the channel region of the first reset transistor is located in the fifth active region; Preferably, in the second direction, the orthogonal projections of the fourth active region and the fifth active region located in the same pixel circuit on the substrate are located on different sides of the orthogonal projections of the first capacitor and the second capacitor on the substrate; In the first direction, the orthogonal projections of the fourth active region and the fifth active region in the adjacent pixel circuits in the second direction are arranged sequentially on the substrate; Preferably, the fourth active region and the fifth active region extend along the second direction.

11. The array substrate according to claim 10, characterized in that, The array substrate further includes: The power line is located on the fifth conductive layer on the side of the fourth conductive layer opposite to the substrate, and extends along the second direction; The fourth connection line is connected between the first electrode of the second light-emitting control transistor and the first electrode of the driving transistor; The seventh connection part is connected between the power line and the second electrode of the second light-emitting control transistor; Preferably, the fourth connecting line and the seventh connecting portion are located in the fourth conductive layer; The fourth connection line is connected to the first terminal of the second light-emitting control transistor through the nineteenth via, and the fourth connection line is connected to the first terminal of the driving transistor through the twentieth via; The seventh connection part is connected to the power line through the twenty-first via, and the seventh connection part is connected to the second electrode of the second light-emitting control transistor through the twenty-second via; Preferably, the array substrate further includes: a first connecting line, the first connecting line being connected between the first electrode of the driving transistor and the fourth electrode plate; The first connection line is connected to the first electrode of the driving transistor through the sixth via; The sixth via is reused as the twentieth via.

12. The array substrate according to claim 11, characterized in that, The at least two scan lines include a fourth scan line, the fourth scan line being a third sub-line located in the first conductive layer, a fourth sub-line located in the third conductive layer, and a fifth sub-line located in the fourth conductive layer, the third sub-line, the fourth sub-line, and the fifth sub-line being connected by vias; The projection of the fourth scan line onto the substrate overlaps with the projection of the channel region of the second light-emitting control transistor in the m-th row pixel circuit onto the substrate; where m is a positive integer, and each row of pixel circuits is arranged along the first direction; The projection of the fourth scan line onto the substrate overlaps with the projection of the channel region of the first reset transistor in the (m+1)th row pixel circuit onto the substrate. Preferably, the at least two scan lines further include a first scan line, a second scan line, and a third scan line. The first scan line is connected to the gate of the data write transistor of the pixel circuit, the second scan line is connected to the gate of the threshold compensation transistor of the pixel circuit, and the third scan line is used to drive the second reset transistor of the pixel circuit. The first scan line is located on the side of the third scan line closer to the driving transistor, and the second scan line is located on the side of the fourth scan line closer to the driving transistor. Preferably, a portion of the fourth scan line is multiplexed as the gate of the second light-emitting control transistor and the first reset transistor.

13. The array substrate according to claim 12, characterized in that, The fourth conductive layer further includes the first reset signal line and the second reset signal line extending along the first direction. In the same pixel circuit located in the m-th row, the orthogonal projections of the first light-emitting control transistor, the second reset transistor, the first capacitor, the second capacitor, and the driving transistor on the substrate are located between the orthogonal projections of the first reset signal line corresponding to the (m+1)-th row pixel circuit and the second reset signal line corresponding to the m-th row pixel circuit on the substrate; where m is a positive integer, and each row of pixel circuits is arranged along a first direction; In the second direction, the orthogonal projection of the first reset signal line on the substrate is located on the side of the orthogonal projection of the fourth scan line on the substrate that is close to the orthogonal projection of the driving transistor on the substrate, and the second scan line is located on the side of the first reset signal line that is close to the driving transistor. Preferably, the first reset signal line is connected to the first terminal of the first reset transistor; the second terminal of the first reset transistor is connected to the second terminal of the first light-emitting control transistor. Preferably, the orthographic projections of the first electrode plate on the substrate, the first reset signal line on the substrate, and the fourth scan line on the substrate are arranged sequentially along the second direction; preferably, the distance between the orthographic projection of the fourth scan line on the substrate and the orthographic projection of the driving transistor on the substrate is greater than the distance between the orthographic projection of the first reset signal line on the substrate and the orthographic projection of the driving transistor on the substrate.

14. The array substrate according to claim 3, characterized in that, The pixel circuit also includes a second light-emitting control transistor and a first reset transistor; The second active layer includes a fourth active region, and the channel region of the second light-emitting control transistor is located in the fourth active region; The first active layer includes a fifth active region, and the channel region of the first reset transistor is located in the fifth active region; In the second direction, the orthogonal projections of the fourth active region and the fifth active region located in the same pixel circuit on the substrate are located on the same side of the orthogonal projection of the first capacitor away from the second capacitor on the substrate; In the first direction, the orthographic projections of the fourth active region and the fifth active region in the same pixel circuit on the substrate are arranged sequentially. Preferably, both the fourth active region and the fifth active region extend along the second direction.

15. The array substrate according to claim 14, characterized in that, The at least two scan lines include a first scan line and a second scan line; The at least two scan lines also include a fourth scan line, which includes a third sub-line located in the first conductive layer, a fourth sub-line located in the third conductive layer, and a fifth sub-line located in the fourth conductive layer; The projection of the fourth scan line onto the substrate overlaps with the projection of the channel regions of the second light-emitting control transistor and the first reset transistor onto the substrate in the m-th row of pixel circuits; where m is a positive integer, and each row of pixel circuits is arranged along the first direction. Preferably, the fourth conductive layer further includes a first reset signal line and a second reset signal line extending along the first direction; the pixel circuit further includes a first light-emitting control transistor and a second reset transistor; Located in the same pixel circuit, the orthogonal projections of the first light-emitting control transistor, the second reset transistor, the first capacitor, the second capacitor, and the driving transistor on the substrate are located between the orthogonal projections of the first reset signal line and the second reset signal line on the substrate; Preferably, in the second direction, the orthogonal projection of the first reset signal line on the substrate is located on the side of the orthogonal projection of the fourth scan line on the substrate that is away from the orthogonal projection of the driving transistor on the substrate; Preferably, the array substrate further includes a fifth connection line connected between the second electrode of the first reset transistor and the first electrode plate; The fifth connecting line extends along the second direction, and the orthographic projection of the fifth connecting line on the substrate overlaps with the orthographic projection of the second scanning line on the substrate. Preferably, the first reset signal line is located in the fourth conductive layer, and the fifth connecting line is disposed in the same layer as the first electrode plate; Preferably, the first reset signal line is connected to the first terminal of the first reset transistor through the twenty-third via; Preferably, the array substrate further includes: The eighth connection part is connected between the first end of the fifth connection line and the second electrode of the first reset transistor; the second end of the fifth connection line is connected to the first electrode plate; Preferably, the eighth connection portion is connected to the first end of the fifth connection line through the twenty-fifth via, and the eighth connection portion is connected to the second terminal of the first reset transistor through the twenty-sixth via; The eighth connection portion is located in the fourth conductive layer.

16. The array substrate according to claim 4, characterized in that, The array substrate further includes a fifth conductive layer located on the side of the fourth conductive layer opposite to the fourth conductive layer, wherein the fifth conductive layer includes data lines and power lines extending along the second direction; At least a portion of the power line in the orthographic projection of the substrate is located between the data line in the orthographic projection of the first gate in the orthographic projection of the substrate. At least a portion of the power line in the orthographic projection of the substrate is located between the data line in the orthographic projection of the substrate and the second gate in the orthographic projection of the substrate. Preferably, the orthographic projection of the power line onto the substrate covers at least a portion of the orthographic projection of the first active region onto the substrate; Preferably, the orthogonal projection of the power line onto the substrate covers the orthogonal projection of the first capacitor onto the substrate.

17. An array substrate, characterized in that, include: Substrate; A first conductive layer, a third conductive layer, and a fourth conductive layer are stacked sequentially along the direction away from the substrate; The first scan line is located in the fourth conductive layer; The third scan line is located between the first conductive layer and the fourth conductive layer; The fourth scan line is located in the first conductive layer, the third conductive layer, and the fourth conductive layer; The first scan line, the third scan line, and the fourth scan line are projected onto the substrate in a first direction and are spaced apart in a second direction. The first direction and the second direction intersect.

18. The array substrate according to claim 17, characterized in that, Also includes: An active layer is stacked on one side of the substrate, and the active layer and multiple conductive layers form at least one pixel circuit, the pixel circuit including a first capacitor, a second capacitor and a driving transistor; The array substrate further includes: The second scan line is located in the second conductive layer, which is located on the side of the first conductive layer away from the substrate. Along the second direction, the orthographic projection of the first capacitor on the substrate, the orthographic projection of the second capacitor on the substrate, and the orthographic projection of the driving transistor on the substrate are located between the orthographic projection of the first scan line on the substrate and the orthographic projection of the second scan line on the substrate. The pixel circuit further includes a data writing transistor, a threshold compensation transistor, a first light-emitting control transistor, a second light-emitting control transistor, a first reset transistor, and a second reset transistor. The first scan line is connected to the gate of the data writing transistor, the second scan line is connected to the gate of the threshold compensation transistor, the third scan line is connected to the gate of the first reset transistor and the gate of the second light-emitting control transistor, and the fourth scan line is connected to the gate of the second reset transistor and the gate of the first light-emitting control transistor. Preferably, the third scan line is used to drive the second reset transistor of the pixel circuit, the first scan line is located on the side of the third scan line closer to the driving transistor, and the second scan line is located on the side of the fourth scan line closer to the driving transistor; Preferably, the orthographic projection of the first capacitor onto the substrate overlaps with the orthographic projection of the driving transistor onto the substrate; The orthographic projection of the first capacitor onto the substrate does not overlap with the orthographic projection of the second capacitor onto the substrate.

19. The array substrate according to claim 18, characterized in that, The active layer includes a first active layer and a second active layer. The second active layer is located on one side of the substrate. The first conductive layer is located on the side of the second active layer away from the substrate. The second conductive layer is located on the side of the first conductive layer away from the substrate. The first active layer is located on the side of the second conductive layer away from the substrate. The third conductive layer is located on the side of the first active layer away from the substrate. The first active layer includes a first active region, and the second active layer includes a second active region; The channel region of the data writing transistor is located in the second active region, and the gate of the data writing transistor is located in the first conductive layer. The gate of the data writing transistor extends along the second direction; The first electrode of the data writing transistor, the channel region of the data writing transistor, and the second electrode of the data writing transistor are arranged sequentially along the first direction; The gate of the threshold compensation transistor is located at least in the third conductive layer and extends along the first direction; the channel region of the threshold compensation transistor is located in the first active region. The first gate of the driving transistor is located in the second conductive layer, the second gate of the driving transistor is located in the third conductive layer, and the channel region of the driving transistor is located in the first active region. Preferably, the first capacitor includes a first plate and a second plate, and the second plate is reused as the first gate. Preferably, the orthographic projection of the first electrode plate onto the substrate covers the orthographic projection of the second electrode plate onto the substrate; Preferably, the orthogonal projection of the first gate onto the substrate covers the orthogonal projection of the second gate onto the substrate.

20. The array substrate according to claim 19, characterized in that, The first active region includes a first active section, a second active section, a third active section, and a fourth active section connected in sequence; The first active portion and the third active portion extend along the first direction, and the second active portion and the fourth active portion extend along the second direction; The first active portion includes the channel region of the driving transistor, and the fourth active portion includes the channel region of the threshold compensation transistor; The threshold compensation transistor includes a third gate located in the third conductive layer; The orthographic projection of the third gate onto the substrate overlaps with the orthographic projection of the fourth active portion onto the substrate; The orthographic projection of the third gate onto the substrate is spaced apart from the orthographic projection of the second active portion onto the substrate. Preferably, the first boundary of the orthographic projection of the third gate onto the substrate, the orthographic projection of the fourth active portion onto the substrate, the second boundary of the orthographic projection of the third gate onto the substrate, and the orthographic projection of the second active portion onto the substrate are arranged sequentially along the first direction; Preferably, the first active region is an integral structure.

21. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-20.

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