Array substrate, display panel and display device

Abstract

The invention discloses an array substrate, a display panel and a display device. The array substrate comprises a plurality of data line groups; the binding pin groups comprise a plurality of first binding pins which are electrically connected with the data lines in the data line group one by one; the plurality of test circuits are in one-to-one correspondence with the plurality of binding pin groups, one ends, close to the binding pin groups, of the test circuits are connected with the plurality of corresponding first binding pins, and the test circuits are provided with a plurality of fractures in one-to-one correspondence with the plurality of first binding pins; one end, far away from the binding pin group, of the test circuit is connected with at least one test pad pair; in the first direction, two test circuits at two ends of the plurality of test circuits are respectively connected with a test pad pair, and the test pad pair connected with the two test circuits at the two ends is not overlapped with areas at two sides of the plurality of binding pin groups; and the test pad pair corresponding to at least one test circuit in the plurality of test circuits is symmetrical about the center line of the plurality of first binding pins connected with the at least one test circuit.

Description

Technical Field

[0001] This invention relates to the field of testing technology, and in particular to an array substrate, a display panel, and a display device. Background Technology

[0002] The manufacturing process of LCD panels typically includes multiple inspection procedures. One very important inspection procedure is to test the cut LCD cells (also known as a lamp test) to confirm whether there are any defects in the LCD cells.

[0003] The lamp-on test includes the first lamp-on test (denoted as CT1). The first lamp-on test transmits the test signal to the data cable through the data cable test pad to detect whether there is a display defect in the LCD panel.

[0004] If the bezel of the LCD panel is narrow, the pads used in the CT1 stage can only be placed between two adjacent data driving circuits. When the number of data driving circuits contained in the display panel is odd, the problem of false alarm blocks being displayed poorly often occurs, resulting in reduced detection efficiency.

[0005] Therefore, how to reduce the false alarm rate of poor block display in the CT1 stage has become an urgent technical problem to be solved. Summary of the Invention

[0006] This invention provides an array substrate, a display panel, and a display device to solve the technical problem of high false alarm rate of CT1 stage block display failure in the prior art.

[0007] In a first aspect, to solve the above-mentioned technical problems, embodiments of the present invention provide an array substrate, comprising:

[0008] Multiple data cable sets;

[0009] Multiple bonding pin groups, wherein each bonding pin group includes multiple first bonding pins that are electrically connected to each data line in the data line group;

[0010] Multiple test lines are provided, each corresponding to one of the multiple bonding pin groups. The end of each test line near the multiple first bonding pins is connected to the multiple first bonding pins. The end of each test line near the multiple first bonding pins has multiple breaks that correspond one-to-one with the multiple bonding pins, and the multiple breaks are arranged along a first direction, which is the arrangement direction of the multiple bonding pin groups.

[0011] Multiple test pad pairs are provided, with one end of the test line away from the multiple first bonding pins connected to at least one test pad pair; in the first direction, each of the two test lines at both ends of the multiple test lines is connected to a test pad pair, and the test pad pairs connected to the two test lines at both ends do not overlap with the areas on both sides of the multiple bonding pin groups; the test pad pairs corresponding to at least one of the multiple test lines are symmetrically arranged about the center line of the multiple first bonding pins connected to the at least one test line; wherein, the center line is perpendicular to the first direction.

[0012] In one possible implementation, each of the test lines is connected to a pair of test pads;

[0013] Each of the test pads is located on the side of the bonding pin group corresponding to the connected test line away from the plurality of data line groups;

[0014] Each of the test pad pairs contains test pad pairs that are symmetrical about the center line of the multiple first bonding pins corresponding to the connected test lines.

[0015] In one possible implementation, the number of the plurality of bonded pin groups is odd, and only one of the plurality of test lines connects to two test pad pairs, while the remaining test lines connect to one test pad pair.

[0016] The two test pads connected to the test line are symmetrical about the center line of the plurality of first bonding pins connected to the test line.

[0017] In the first direction, the plurality of test pads are distributed in pairs within the partial gaps of the plurality of bonding pin groups.

[0018] One possible implementation is that the bonding pin group corresponding to the two test pad pairs is the bonding pin group closest to either end of the plurality of bonding pin groups.

[0019] In one possible implementation, each of the two test lines at both ends of the plurality of test lines is connected to a pair of test pads, and each of the remaining test lines is connected to two pairs of test pads.

[0020] Two test pads connected to the same test line are symmetrically positioned about the center line of the corresponding multiple first-bonded pins.

[0021] One possible implementation of the test circuit includes:

[0022] Multiple first connecting segments are connected one-to-one with the multiple first bonding pins, and the first connecting segments have the breaks; the multiple first connecting segments are located in the area enclosed by the bonding pins in the bonding pin group;

[0023] The second connecting segment has one end connected to the end of each of the first connecting segments away from the first bonding pin, and the other end connected to the corresponding test pad.

[0024] In one possible implementation, the second connecting segment includes:

[0025] The first sub-segment, the second sub-segment, and the third sub-segment are connected in sequence, wherein the width of the second sub-segment is smaller than the width of the first sub-segment and the third sub-segment;

[0026] The bonding pin group also includes a plurality of second bonding pins, wherein the second sub-segment is located between two adjacent second bonding pins, and the extension direction of the second sub-segment is the same as the extension direction of the adjacent second bonding pin.

[0027] In one possible implementation, the plurality of first connecting segments are divided into a plurality of first odd-numbered connecting segments and a plurality of first even-numbered connecting segments; one end of the first odd-numbered connecting segment is connected to a first pin of the data line connecting the odd-numbered column, and one end of the first even-numbered connecting segment is connected to a first pin of the data line connecting the even-numbered column.

[0028] The second connecting segment includes: a second odd-numbered connecting segment and a second even-numbered connecting segment; one end of the second odd-numbered connecting segment is connected to the end of each of the first odd-numbered connecting segments away from the first binding pin; one end of the second even-numbered connecting segment is connected to the end of each of the first even-numbered connecting segments away from the first binding pin.

[0029] One possible implementation of the test pad pair includes:

[0030] The odd-numbered test pad is connected to the second odd-numbered connecting line segment;

[0031] The even-numbered test pad is connected to the second even-numbered connecting line segment.

[0032] One possible implementation also includes:

[0033] First diode and second diode;

[0034] The positive terminals of the first diode and the second diode are electrically connected to the odd-numbered test pad and the even-numbered test pad, respectively, and the negative terminals of the first diode and the second diode are grounded.

[0035] In one possible implementation, the array substrate further includes a gate layer and an indium tin oxide layer;

[0036] The test pad pair includes:

[0037] First metal layer;

[0038] An insulating layer is located on one side of the first metal layer; the insulating layer has a plurality of through holes penetrating the metal layer;

[0039] The second metal layer is located on the side of the insulating layer away from the first metal layer, and the second metal layer is connected to the first metal layer through the via; one of the first metal layer and the second metal layer is disposed in the same layer as the gate layer, and the other is disposed in the same layer as the indium tin oxide layer.

[0040] In one possible implementation, the gate layer is a molybdenum-aluminum-molybdenum structure.

[0041] In a second aspect, embodiments of the present invention provide a display panel, including an array substrate as described in the first aspect.

[0042] Thirdly, embodiments of the present invention provide a display device, including a display panel as described in the second aspect. Attached Figure Description

[0043] Figure 1 This is a schematic diagram showing the location of the data line test pad in a liquid crystal display panel of a related technology.

[0044] Figure 2 This is a schematic diagram of the structure of an array substrate provided in an embodiment of the present invention;

[0045] Figure 3 This is a schematic diagram of another array substrate provided in an embodiment of the present invention;

[0046] Figure 4 This is a schematic diagram of another array substrate provided in an embodiment of the present invention;

[0047] Figure 5 Provided for embodiments of the present invention Figure 4 A schematic diagram of the structure corresponding to the first lighting test;

[0048] Figure 6 and Figure 7 This is a schematic diagram of another array substrate provided in an embodiment of the present invention;

[0049] Figure 8 A schematic diagram of a test circuit provided in an embodiment of the present invention;

[0050] Figure 9 This is a schematic diagram of the structure of a second connecting line segment provided in an embodiment of the present invention;

[0051] Figure 10 This is a schematic diagram of another test circuit provided in an embodiment of the present invention;

[0052] Figure 11 This is a schematic diagram of another array substrate provided in an embodiment of the present invention;

[0053] Figure 12 This is a schematic diagram of a test pad pair provided in an embodiment of the present invention.

[0054] Figure label:

[0055] Data cable group 1, data cable 11, bonding pin group 2, first bonding pin 21, second bonding pin 22, test circuit 3, test pad pair 4, odd test pad 41, even test pad 42, data drive circuit 5, pixel area AA, peripheral area BB, first direction X, break K, first connecting line segment 31, second connecting line segment 32, first sub-line segment 321, second sub-line segment 322, third sub-line segment 323, first odd connecting line segment 311, first even connecting line segment 312, second odd connecting line segment 32a, second even connecting line segment 32b, first diode 6, second diode 7, first metal layer 211, insulating layer 212, second metal layer 213, through hole H. Detailed Implementation

[0056] This invention provides an array substrate, a display panel, and a display device to solve the technical problem of high false alarm rate of CT1 stage block display failure in the prior art.

[0057] It should be understood that the specific structural and functional details disclosed in the embodiments of the present invention are merely representative and are intended to describe exemplary embodiments of this application. However, this application can be implemented in many alternative forms and should not be construed as being limited solely to the embodiments set forth herein.

[0058] In the description of this application, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.

[0059] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0060] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural. It should also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, units, and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.

[0061] In this invention, the term "and / or" is merely a description of the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following associated objects have an "or" relationship.

[0062] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described below in conjunction with the accompanying drawings and embodiments. However, the exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms describing position and direction in the present invention are illustrative based on the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of the present invention. The accompanying drawings of the present invention are for illustrative purposes only and do not represent actual proportions.

[0063] It should be noted that specific details are set forth in the following description to provide a full understanding of the invention. However, the invention can be practiced in many ways other than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below. The following description is a preferred embodiment for carrying out the present application; however, the description is for the purpose of illustrating the general principles of the application and is not intended to limit the scope of the application. The scope of protection of this application shall be determined by the appended claims.

[0064] Please see Figure 1 This diagram illustrates the location of data line test pads in a liquid crystal display panel (LCD) of the related technology. The LCD panel includes multiple data driving circuits 5 and test pad pairs 4 corresponding to the data driving circuits 5, as well as test lines 3 that electrically connect the output terminals of the data driving circuits 5 (not shown) to the test pad pairs 4 during the CT1 phase. Multiple output terminals of the data driving circuits 5 are electrically connected to a group of data lines 1. The data test pad pairs 4 include odd-numbered test pads 41 and even-numbered test pads 42. During the CT1 phase, odd-numbered test pads 41 are electrically connected to all odd-numbered columns of data lines 11 connected to the corresponding data driving circuits 5, and even-numbered test pads 42 are electrically connected to all even-numbered columns of data lines 11 connected to the corresponding data driving circuits 5.

[0065] Because some display products have narrow bezels, there is no space on both sides of multiple data driver circuits 5 to place the data test pads 4; they can only be placed between two adjacent data driver circuits 5. For example... Figure 1 The liquid crystal display panel shown includes 5 data driving circuits 5. Figure 1 The two adjacent data driving circuits 5 at the right end are prone to block display defects at the corresponding boundary position in the pixel area AA, resulting in uneven display of the liquid crystal display panel.

[0066] The inventor discovered: leading to Figure 1 The reason why block display defects easily occur at the corresponding boundary position of the two adjacent data driving circuits 5 on the right end in pixel area AA is that the voltage difference between the first data line 11 electrically connected in the first data driving circuit 5 on the right and the last data line 11 electrically connected in the second data driving circuit 5 on the right is too large. That is, in the same data driving circuit 5, the test voltage on the data line 11 closest to the corresponding test pad pair 4 is low (denoted as VT). L The test voltage on data line 11, which is furthest from the corresponding test pad 4, is high (denoted as VT). H ),like Figure 1 The number of data driving circuits 5 contained in the central LCD panel is odd. The test voltage on the first data line 11 electrically connected to the first data driving circuit 5 on the right is VT. HThe test voltage on the last data line 11 electrically connected in the second data drive circuit 5 on the right is VT. L , while VT H -VT L If the value is too large, it will cause block display defects at the boundary position of the two data driving circuits 5 on the right side of the pixel area AA during the CT1 stage. However, after the CT1 stage is completed, the electrical connection between the test line 3 used in the CT1 stage and the corresponding pin of the data line 11 that is electrically connected to the data driving circuit 5 will be cut off, so that the data line 11 is disconnected from the corresponding test pad pair 4, and the data lines 11 that are electrically connected to the same data driving circuit 5 will not be electrically connected. At this time, Figure 1 The two adjacent data drive circuits 5 at the right end of the middle will not exhibit block display defects at the corresponding boundary position of pixel area AA. In other words, the block display defects detected in the CT1 stage are not caused by the quality problem of the display panel, but by the CT1 test circuit 3. This is called a false defect. However, during testing, it will be mistakenly judged as a real defect, thus discarding display panels without quality problems, reducing product yield, and causing relevant personnel to spend a lot of time finding the cause of the defect, resulting in low testing efficiency in the CT1 stage.

[0067] To address the aforementioned problems, embodiments of the present invention provide an array substrate, a display panel, and a display device, which will be described in detail below with reference to the accompanying drawings.

[0068] Please see Figure 2 This is a schematic diagram of an array substrate provided in an embodiment of the present invention. The array substrate includes:

[0069] Multiple data cable groups 1;

[0070] Multiple bonding pin groups 2, each including multiple first bonding pins 21 electrically connected to the data lines 11 in the data line group 1; bonding pin groups 2 and Figure 1 The data drive circuit 5 shown is bonded;

[0071] Multiple test lines 3 correspond one-to-one with multiple bonding pin groups 2. The end of the test line 3 near the multiple first bonding pins 21 is connected to the multiple first bonding pins 21. The end of the test line 3 near the multiple first bonding pins 21 has multiple breaks K corresponding one-to-one with the multiple bonding pins, and the multiple breaks K are arranged along the first direction X, which is the arrangement direction of the multiple bonding pin groups 2.

[0072] Multiple test pad pairs 4, and one end of the test line 3 away from the multiple first binding pins 21 is connected to at least one test pad pair 4; in the first direction X, each of the two test lines 3 at both ends of the multiple test lines 3 is connected to a test pad pair 4, and the test pad pair 4 connected to the two test lines 3 at both ends does not overlap with the areas on both sides of the multiple binding pin groups 2; the test pad pair 4 corresponding to at least one test line 3 of the multiple test lines 3 is symmetrically arranged about the center line of the multiple first binding pins 21 connected to at least one test line 3; wherein, the center line is perpendicular to the first direction X.

[0073] The array substrate has a pixel area AA and a peripheral area BB surrounding the pixel area AA. Multiple data line groups 1 are located in the pixel area AA, and multiple bonding pin groups 2, multiple test lines 3 and multiple test pad pairs 4 are located in the peripheral area BB.

[0074] Regardless of whether the array substrate includes an odd or even number of bonded pin groups 2, a test pad pair 4 can be set for each pin group. The test pad pairs 4 corresponding to multiple bonded pin groups 2 are located on the side of the multiple bonded pin groups 2 away from the multiple data line groups 1, such as... Figure 3 The diagram shows another array substrate structure provided by an embodiment of the present invention. Each test pad pair 4 includes a test pad that is symmetrical about the center line of multiple first binding pins 21 corresponding to the test line 3. The center line is perpendicular to the first direction X. This makes the voltage drop from the test pad in the test pad pair 4 to the first binding pins 21 at both ends of the multiple first binding pins 21 approximately the same (i.e., the voltage drop difference between the first binding pins 21 at both ends is less than a preset value, which is the voltage difference between two adjacent gray levels, so it can be considered the same). Correspondingly, the voltage applied to the data line 11 electrically connected to the first binding pins 21 at both ends of the multiple first binding pins 21 group 2 is also approximately the same. Therefore, there will be no uneven brightness at the boundary position corresponding to pixel area AA of any two adjacent binding pin groups 2, and there will be no block defects, thereby effectively improving the display effect.

[0075] In the multiple bonding pin groups 2, except for the bonding pin groups 2 at both ends which can only correspond to one test pad pair 4, at least one of the other bonding pin groups 2 can correspond to two test point pairs.

[0076] like Figure 2 The test pad pair 4 shown is connected to the plurality of first binding pins 21 of the second binding pin group 2 on the left. There are two test pad pairs 4, which are symmetrical about the center line of the plurality of first binding pins 21 in the second binding pin group 2 on the left.

[0077] Please see Figure 4This is a schematic diagram of another array substrate provided in an embodiment of the present invention. The number of multiple bonding pin groups 2 is odd. Among the multiple test lines 3, only one test line 3 is connected to two test pad pairs 4, and the remaining test lines 3 are connected to one test pad pair 4.

[0078] Two test pad pairs 4 connected by a test line 3 are symmetrical about the center line of the plurality of first bonded pins 21 connected by a test line 3;

[0079] In the first direction X, multiple test pads 4 are distributed in pairs in the partial gaps of multiple bonded pin groups 2.

[0080] by Figure 4 For example, when the array substrate includes an odd number of (e.g.) Figure 4 The diagram shows 5) pin groups 2. Assume that each pin group 2 corresponds to a data line group 1 containing n data lines 11. Figure 4 The two binding pin groups 2 on the left side of the middle are located at the intersection of data line 11n and data line 11n+1 in pixel area AA, which allows... Figure 4 In the second left-hand binding pin group 2, there are two corresponding test pad pairs 4. The corresponding test line 3 is connected to these two test pad pairs 4 and distributed on both sides of the second left-hand binding pin group 2. During the first lamp-lighting test, the test voltage applied to each test pad pair 4 is the same, and all breaks K in the test line 3 are connected (e.g., ...). Figure 5 The image shown is provided by an embodiment of the present invention. Figure 4 (Structural diagram corresponding to the first lighting test), due to Figure 5 The second binding pin group 2 from the left corresponds to two test pad pairs 4, and the two test pad pairs 4 are distributed on both sides of the second binding pin group 2 from the left. This makes the test pad pair 4 on the left side of the second binding pin group 2 the closest to the (n+1)th data line 11, while the test pad pair 4 on the side corresponding to the first binding pin group 2 from the left is the closest to the nth data line 11. Therefore, even if there is a voltage drop in the test line 3, the voltage drop on the nth data line 11 and the (n+1)th data line 11 is the same, so there will be no brightness unevenness at the junction of the nth data line 11 and the (n+1)th data line 11. Similarly, for the other two binding pin groups 2, where two test pad pairs 4 are set between adjacent binding pin groups 2, there will be no brightness unevenness at the junction of the pixel area AA. Please continue to see Figure 5There is no test pad pair 4 between the third and fourth binding pin groups 2. The 3nth data line 11 is furthest from the test pad pair 4 corresponding to the third binding pin group 2 on the left. However, the 3n+1th data line 11 is also furthest from the test pad pair 4 corresponding to the fourth binding pin group 2 on the left. Therefore, even if there is a voltage drop in the corresponding test line 3, the voltage drop is consistent, which makes the test voltage applied to the 3nth data line 11 and the 3n+1th data line 11 consistent. This prevents uneven brightness between the 3nth data line 11 and the 3n+1th data line 11, thus effectively preventing false defects caused by the test line 3 and improving test efficiency.

[0081] In the embodiments provided by the present invention, when the number of multiple bonding pin groups 2 is odd, and only one test line 3 of the multiple test lines 3 connects two test pad pairs 4, while the other test lines 3 connect one test pad pair 4; by making the two test pad pairs 4 connected by one test line 3 symmetrical about the center line of the multiple first bonding pins 21 connected by one test line 3; and by distributing the multiple test pad pairs 4 in pairs in the first direction X in the partial gaps of the multiple bonding pin groups 2, it is possible to effectively prevent false defects caused by the test lines 3 and improve test efficiency.

[0082] like Figure 4 or Figure 5 As shown, the bonding pin group 2 connecting the two test pad pairs 4 is the bonding pin group 2 closest to any one of the two ends of the plurality of bonding pin groups 2. For example... Figure 4 The nearest binding pin group 2 to the left end is the second binding pin group 2 from the left, and the nearest binding pin group 2 to the right end is the second binding pin group 2 from the right. This can be seen as follows: Figure 4 The image shows two test pad pairs 4 configured for the second bonding pin group 2 on the left. Alternatively, two test pad pairs 4 can be configured for the second bonding pin group 2 on the right.

[0083] In the embodiments provided by the present invention, by setting the bonding pin group 2 corresponding to the two test pad pairs 4 to the bonding pin group 2 closest to any one of the bonding pin groups 2 at both ends of the plurality of bonding pin groups 2, the array substrate can be modified with minimal changes to prevent false defects during the first lamp test, and the width of the peripheral area BB will not be increased in the direction perpendicular to the first direction X, thus achieving a narrow bezel design.

[0084] Please see Figure 6 and Figure 7 This is a schematic diagram of another array substrate provided in an embodiment of the present invention. Each of the two test lines 3 at both ends of the plurality of test lines 3 is connected to a test pad pair 4, and each of the remaining test lines 3 is connected to two test pad pairs 4.

[0085] Two test pads 4 connected to the same test line 3 are symmetrically arranged about the center line of the corresponding multiple first binding pins 21.

[0086] When the number of multiple bonded pin groups 2 is odd, such as Figure 6 As shown, by connecting two test point pairs to each of the remaining test lines 3 outside the two ends of the multiple test lines 3, and symmetrically setting the two test point pairs connected to the same test line 3 about the center of the corresponding multiple first binding pins 21, two test pad pairs 4 can be set in the gap of the multiple binding pin groups 2, and the two test pad pairs 4 located in the gap are connected to the corresponding two adjacent test lines 3, thereby preventing false defects from appearing at the corresponding boundary position of the two adjacent binding pin groups 2 in the pixel area AA.

[0087] When the number of multiple bonded pin groups 2 is even, such as Figure 7 As shown, the two test pads 4 located in the gap can also be connected to the two adjacent test lines 3, thereby preventing false defects from appearing at the corresponding boundary positions of the two adjacent bonded pin groups 2 in the pixel area AA.

[0088] In the embodiments provided by the present invention, by connecting two test point pairs to each of the remaining test lines 3 outside the two ends of the multiple test lines 3, and symmetrically arranging the two test point pairs connected to the same test line 3 about the center of the corresponding multiple first binding pins 21, two test pad pairs 4 can be set in the gaps of multiple binding pin groups 2, and the two test pad pairs 4 located in the gaps are connected to the corresponding two adjacent test lines 3, thereby preventing false defects from appearing at the corresponding boundary positions of two adjacent binding pin groups 2 in the pixel area AA. Moreover, this method is not limited by whether the number of binding pin groups 2 is odd or even, and can adapt to various numbers of binding pin groups 2, with a wide range of applications.

[0089] Please see Figure 8 This is a schematic diagram of a test circuit provided in an embodiment of the present invention. Test circuit 3 includes:

[0090] Multiple first connecting segments 31 are connected one-to-one with multiple first binding pins 21, and the first connecting segments 31 have a break point K; the multiple first connecting segments 31 are located in the area enclosed by the binding pins in the binding pin group 2;

[0091] The second connecting segment 32 has one end connected to the end of the first bonding pin 21 away from the break point K of each first connecting segment 31, and the other end connected to the corresponding test pad pair 4.

[0092] The extension direction of the first connecting segment 31 is the same as the extension direction of the first bonding pin 21, and the extension direction of the second connecting segment 32 is the same as the arrangement direction of the plurality of first bonding pins 21.

[0093] During the first lighting test, the first connecting line segment 31 has no break K. The test pad transmits test voltage to the data line 11 in the data line group 1 that is connected to multiple first connecting line segments 31 in four directions to detect whether there is a defect in the pixel area AA. After the first lighting test is completed, the test line 3 is no longer needed. The multiple first connecting line segments 31 are cut along the extension direction of multiple first binding pins 21 to form a break K on the first connecting line segment 31, thereby preventing the test line 3 from connecting the data line 11 in the data line group 1.

[0094] In the embodiments provided by the present invention, by setting the test line 3 as multiple first connection segments 31 connected one-to-one with multiple first binding pins 21, and placing the multiple first connection segments 31 in the area enclosed by the binding pins in the binding pin group 2, most of the test line 3 can be located in the area where the binding pin group 2 is located, saving wiring space; and by connecting the multiple first connection segments 31 and the test pad pair 4 with the second connection segment 32, test signals can be provided to the multiple data lines 11 connected to the multiple first connection segments 31 through the test pad pair 4 during the first lamp-lighting test; after the first lamp-lighting test is completed, the electrical connection between the first binding pins 21 and the test line 3 is disconnected by the break point K on the first connection segment 31, so that after the data driver chip is subsequently bound to the binding pin group 2, the data driver chip can provide data signals to the data lines 11.

[0095] Please see Figure 9 This is a schematic diagram of the structure of a second connecting line segment provided in an embodiment of the present invention. The second connecting line segment 32 includes:

[0096] The first sub-segment 321, the second sub-segment 322, and the third sub-segment 323 are connected in sequence. The width W1 of the second sub-segment 322 is smaller than the width W2 of the first sub-segment 321 and the third sub-segment 323.

[0097] The bonding pin group 2 also includes a plurality of second bonding pins 22, and a second sub-segment 322 is located between two adjacent second bonding pins 22, and the extension direction of the second sub-segment 322 is the same as the extension direction of the adjacent second bonding pin 22.

[0098] In the embodiments provided by the present invention, by dividing the second connecting line segment 32 into second sub-line segments 322 connected in sequence, and making the line width of the second sub-line segment 322 located between two adjacent second binding pins 22 smaller than the line width of the first sub-line segment 321 and the second sub-line segment 322, it can be ensured that the second sub-line segment 322 does not overlap with the two adjacent second binding pins 22, thereby preventing the second sub-line segment 322 from short-circuiting with the second binding pin 22.

[0099] Please see Figure 10 This is a schematic diagram of another test circuit provided in an embodiment of the present invention.

[0100] Multiple first connecting segments 31 are divided into multiple first odd-numbered connecting segments 311 and multiple first even-numbered connecting segments 312; one end of the first odd-numbered connecting segment 311 is connected to the first pin of the connecting odd-numbered column data line 11, and one end of the first even-numbered connecting segment 312 is connected to the first pin of the connecting even-numbered column data line 11.

[0101] The second connecting segment 32 includes: a second odd-numbered connecting segment 32a and a second even-numbered connecting segment 32b; one end of the second odd-numbered connecting segment 32a is connected to the end of each first odd-numbered connecting segment 311 away from the first binding pin 21; one end of the second even-numbered connecting segment 32b is connected to the end of each first even-numbered connecting segment 312 away from the first binding pin 21.

[0102] Test pad pair 4, including:

[0103] Odd-numbered test pad 41 is connected to the second odd-numbered connecting line segment 32a;

[0104] The even-numbered test pad 42 is connected to the second even-numbered connecting line segment 32b.

[0105] In the embodiments provided by the present invention, by connecting the first odd-numbered connecting segment 311 of the odd-numbered data lines 11 electrically connected in the same test line 3 to the odd-numbered test pad 41 through the second odd-numbered connecting segment 32a, and connecting the first even-numbered connecting segment 312 of the even-numbered data lines 11 electrically connected to the even-numbered test pad 42 through the second even-numbered connecting segment 32b, different test voltages can be provided to the odd-numbered data lines 11 and the even-numbered data lines 11 through the technical test pad and the even-numbered test pad 42, or time-division testing can be performed, thereby enabling timely detection of defects in the odd-numbered data lines 11 and the even-numbered data lines 11.

[0106] Please see Figure 11 This is a schematic diagram of another array substrate provided in an embodiment of the present invention. The array substrate further includes:

[0107] First diode 6 and second diode 7;

[0108] The positive terminals of the first diode 6 and the second diode 7 are electrically connected to the odd-numbered test pad 41 and the even-numbered test pad 42, respectively, and the negative terminals of the first diode 6 and the second diode 7 are grounded to GND.

[0109] In the embodiments provided by the present invention, by setting a first diode 6 and a second diode 7, and making the positive terminals of the first diode 6 and the second diode 7 electrically connected to the odd-numbered test pad 41 and the even-numbered test pad 42 respectively, and the negative terminals of the first diode 6 and the second diode 7 grounded to GND, the first diode 6 and the second diode 7 can form an anti-static structure, thereby preventing the odd-numbered test pad 41 and the even-numbered test pad 42 from being burned by static electricity.

[0110] Please see Figure 12 This is a schematic diagram of a test pad pair provided in an embodiment of the present invention. The array substrate further includes a gate layer (not shown) and an indium tin oxide layer (not shown).

[0111] Test pad pair 4, including:

[0112] First metal layer 211;

[0113] An insulating layer 212 is located on one side of the first metal layer 211; the insulating layer 212 has a plurality of through holes H penetrating the metal layer;

[0114] The second metal layer 213 is located on the side of the insulating layer 212 away from the first metal layer 211, and the second metal layer 213 is connected to the first metal layer 211 through a via H; one of the first metal layer 211 and the second metal layer 213 is disposed in the same layer as the gate layer, and the other is disposed in the same layer as the indium tin oxide layer. The odd-numbered test pads 41 and even-numbered test pads 42 have the above structure.

[0115] For example, the first metal layer 211 can be disposed in the same layer as the gate layer, and the second metal layer 213 can be disposed in the same layer as the indium tin oxide layer; or, the first metal layer 211 can be disposed in the same layer as the indium tin oxide layer, and the second metal layer 213 can be disposed in the same layer as the gate layer.

[0116] In some embodiments, the gate layer may be a molybdenum-aluminum-molybdenum structure.

[0117] In the embodiments provided by the present invention, the test pad pair 4 is configured as the first metal layer 211;

[0118] An insulating layer 212 is located on one side of the first metal layer 211; the insulating layer 212 has multiple through holes H penetrating the metal layer; a second metal layer 213 is located on the side of the insulating layer 212 away from the first metal layer 211, and the second metal layer 213 is connected to the first metal layer 211 through through holes H; one of the first metal layer 211 and the second metal layer 213 is disposed in the same layer as the gate layer, and the other is disposed in the same layer as the indium tin oxide layer, which can utilize the existing film layers in the array substrate to form test pad pair 4 and improve the conductivity of test pad pair 4.

[0119] Based on the same inventive concept, embodiments of the present invention provide a display panel, which includes an array substrate as described above.

[0120] Based on the same inventive concept, embodiments of the present invention provide a display device, which includes a display panel as shown above.

[0121] The display device can be a liquid crystal display, liquid crystal screen, liquid crystal television, or other display devices, or a mobile device such as a mobile phone, tablet computer, or laptop.

[0122] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0123] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. An array substrate, characterized in that, include: Multiple data cable sets; Multiple bonding pin groups, wherein each bonding pin group includes multiple first bonding pins that are electrically connected to each data line in the data line group; Multiple test lines are provided, each corresponding to one of the multiple bonding pin groups. The end of each test line near the multiple first bonding pins is connected to the multiple first bonding pins. The end of each test line near the multiple first bonding pins has multiple breaks that correspond one-to-one with the multiple bonding pins, and the multiple breaks are arranged along a first direction, which is the arrangement direction of the multiple bonding pin groups. Multiple test pad pairs are provided, with one end of the test line away from the multiple first bonding pins connected to at least one test pad pair; in the first direction, each of the two test lines at both ends of the multiple test lines is connected to a test pad pair, and the test pad pairs connected to the two test lines at both ends do not overlap with the areas on both sides of the multiple bonding pin groups; the test pad pairs corresponding to at least one of the multiple test lines are symmetrically arranged about the center line of the multiple first bonding pins connected to the at least one test line; wherein, the center line is perpendicular to the first direction.

2. The array substrate as described in claim 1, characterized in that, Each of the test lines is connected to a pair of test pads; Each of the test pads is located on the side of the bonding pin group corresponding to the connected test line away from the plurality of data line groups; Each of the test pad pairs contains test pad pairs that are symmetrical about the center line of the multiple first bonding pins corresponding to the connected test lines.

3. The array substrate as described in claim 1, characterized in that, The number of the plurality of bonded pin groups is odd, and only one of the plurality of test lines connects two test pad pairs, while the other test lines connect one test pad pair. The two test pads connected to the test line are symmetrical about the center line of the plurality of first bonding pins connected to the test line. In the first direction, the plurality of test pads are distributed in pairs within the partial gaps of the plurality of bonding pin groups.

4. The array substrate as described in claim 3, characterized in that, The bonding pin group corresponding to the two test pad pairs is the bonding pin group that is closest to either end of the plurality of bonding pin groups.

5. The array substrate as described in claim 1, characterized in that, Each of the two test lines at both ends of the plurality of test lines is connected to a pair of test pads, and each of the remaining test lines is connected to two pairs of test pads. Two test pads connected to the same test line are symmetrically positioned about the center line of the corresponding multiple first-bonded pins.

6. The array substrate according to any one of claims 1-5, characterized in that, The test circuit includes: Multiple first connecting segments are connected one-to-one with the multiple first bonding pins, and the first connecting segments have the breaks; the multiple first connecting segments are located in the area enclosed by the bonding pins in the bonding pin group; The second connecting segment has one end connected to the end of each of the first connecting segments away from the first bonding pin, and the other end connected to the corresponding test pad.

7. The array substrate as described in claim 6, characterized in that, The second connecting segment includes: The first sub-segment, the second sub-segment, and the third sub-segment are connected in sequence, wherein the width of the second sub-segment is smaller than the width of the first sub-segment and the third sub-segment; The bonding pin group also includes a plurality of second bonding pins, wherein the second sub-segment is located between two adjacent second bonding pins, and the extension direction of the second sub-segment is the same as the extension direction of the adjacent second bonding pin.

8. The array substrate as described in claim 6, characterized in that, The plurality of first connecting segments are divided into a plurality of first odd-numbered connecting segments and a plurality of first even-numbered connecting segments; one end of the first odd-numbered connecting segment is connected to the first pin of the data line connecting the odd-numbered column, and one end of the first even-numbered connecting segment is connected to the first pin of the data line connecting the even-numbered column. The second connecting segment includes: a second odd-numbered connecting segment and a second even-numbered connecting segment; one end of the second odd-numbered connecting segment is connected to the end of each of the first odd-numbered connecting segments away from the first binding pin; one end of the second even-numbered connecting segment is connected to the end of each of the first even-numbered connecting segments away from the first binding pin.

9. The array substrate as described in claim 8, characterized in that, The test pad pair includes: The odd-numbered test pad is connected to the second odd-numbered connecting line segment; The even-numbered test pad is connected to the second even-numbered connecting line segment.

10. The array substrate as claimed in claim 9, characterized in that, Also includes: First diode and second diode; The positive terminals of the first diode and the second diode are electrically connected to the odd-numbered test pad and the even-numbered test pad, respectively, and the negative terminals of the first diode and the second diode are grounded.

11. The array substrate according to any one of claims 1-5, characterized in that, The array substrate further includes a gate layer and an indium tin oxide layer; The test pad pair includes: First metal layer; An insulating layer is located on one side of the first metal layer; the insulating layer has a plurality of through holes penetrating the metal layer; The second metal layer is located on the side of the insulating layer away from the first metal layer, and the second metal layer is connected to the first metal layer through the via; one of the first metal layer and the second metal layer is disposed in the same layer as the gate layer, and the other is disposed in the same layer as the indium tin oxide layer.

12. The array substrate as claimed in claim 11, characterized in that, The gate layer has a molybdenum-aluminum-molybdenum structure.

13. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-12.

14. A display device, characterized in that, Includes the display panel as described in claim 13.

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